Semiconductor device and method for manufacturing a semiconductor device

Abstract

According to the present invention, a front surface electrode (14) forms an ohmic contact with a semiconductor substrate (8) by the intermediary of a contact structure which is composed of a TiSix film (11), a TiN film (12) and a metal plug (13). The TiSix film (11) is directly deposited by sputtering so as to extend from a lateral wall of a contact hole (9a) (a lateral surface of an interlayer insulating film (9)) along the inner wall of a source contact trench (8a). An end part of the TiSix film (11) ends on the lateral surface of the interlayer insulating film (9). The TiSix film (11) has a uniform thickness from the lateral wall of the contact hole (9a) to the lateral wall of the source contact trench (8a). The TiN film (12) is provided along the surface of the TiSix film (11). The metal plug (13) is buried in the contact hole (9a) and the source contact trench (8a) so as to be positioned above the TiN film (12). Consequently, the reliability of a semiconductor device (10) is improved.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device.

Background Art

[0002] Conventionally, a contact structure has been proposed in which an adhesion layer made of titanium (Ti) or a barrier layer made of titanium silicon nitride (Ti—Si—N) is provided between a front surface electrode and a semiconductor substrate, or a titanium silicide (TiSi) film formed by siliciding a Ti film, or a contact structure including a TiSi film formed by plasma enhanced chemical vapor deposition (PECVD) (see, for example, Patent Documents 1 to 5 below). In addition, a semiconductor device including a gate electrode including a TiSi film deposited by sputtering has been proposed (see, for example, Patent Document 6 below).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the above-mentioned Patent Documents 1 to 4, the Ti film included in the laminated structure of the front surface electrode inhibits the effect of hydrogen annealing to restore crystal damage to the semiconductor substrate. Furthermore, in Patent Document 4, the volume expansion of the TiSi film due to silicide increases the stress locally generated in the semiconductor substrate. In Patent Document 5, the chlorine (Cl) included in the introduction gas composition of PECVD for forming the TiSi film causes corrosion of the semiconductor substrate.

[0005] This disclosure aims to provide a highly reliable semiconductor device and a method for manufacturing a semiconductor device in order to overcome the problems of the prior art described above. [Means for solving the problem]

[0006] A semiconductor device according to one aspect of this disclosure is as follows: A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate. A second semiconductor region of a second conductivity type is provided between the front surface of the semiconductor substrate and the first semiconductor region. An element structure including a pn junction between the second semiconductor region and the first semiconductor region is provided on the front surface side of the semiconductor substrate. An interlayer insulating film is provided on the front surface of the semiconductor substrate. The interlayer insulating film covers the element structure. A contact hole penetrates the interlayer insulating film in the depth direction and reaches the semiconductor substrate. The contact structure is in contact with the semiconductor substrate at the contact hole.

[0007] The first electrode is electrically connected to the second semiconductor region via the contact structure. The second electrode is provided on the back surface of the semiconductor substrate. The contact structure consists of a titanium silicide film, a titanium nitride film, and a metal plug. The titanium silicide film is in contact with the semiconductor substrate at the contact hole and extends along the side wall of the contact hole to the surface of the interlayer insulating film. The titanium nitride film is provided along the surface of the titanium silicide film. The metal plug is embedded inside the contact hole on the titanium nitride film.

[0008] Furthermore, a method for manufacturing a semiconductor device according to one aspect of this disclosure is as follows: A first step is performed to form a second semiconductor region of a second conductivity type in contact with a first semiconductor region of a first conductivity type inside the semiconductor substrate on the surface region of the front surface of the semiconductor substrate, and to form an element structure including a pn junction between the second semiconductor region and the first semiconductor region. A second step is performed to form an interlayer insulating film covering the element structure on the front surface of the semiconductor substrate. A third step is performed to form a contact hole that penetrates the interlayer insulating film in the depth direction and reaches the semiconductor substrate. A fourth step is performed to form a contact structure in contact with the semiconductor substrate at the contact hole. A fifth step is performed to form a first electrode electrically connected to the second semiconductor region via the contact structure.

[0009] After the fifth step, a first annealing step is performed to restore crystal damage to the semiconductor substrate by heat treatment in a hydrogen atmosphere. The fourth step includes first to third deposition steps. In the first deposition step, a titanium silicide film is deposited by sputtering, covering the entire surface of the interlayer insulating film and contacting the semiconductor substrate in the contact holes. In the second deposition step, a titanium nitride film is deposited on the surface of the titanium silicide film by sputtering. In the third deposition step, a metal plug is embedded on the titanium nitride film inside the contact hole. The contact structure consisting of the titanium silicide film, the titanium nitride film, and the metal plug is formed. [Effects of the Invention]

[0010] The semiconductor device and method for manufacturing the semiconductor device described herein have the effect of improving reliability. [Brief explanation of the drawing]

[0011] [Figure 1] Figure 1 is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 1. [Figure 2] Figure 2 is a cross-sectional view showing the state of a semiconductor device according to Embodiment 1 during the manufacturing process. [Figure 3] Figure 3 is a cross-sectional view showing the state of a semiconductor device according to Embodiment 1 during the manufacturing process. [Figure 4] Figure 4 is a cross-sectional view showing the state of a semiconductor device according to Embodiment 1 during the manufacturing process. [Figure 5] Figure 5 is a cross-sectional view showing the state of a semiconductor device according to Embodiment 1 during the manufacturing process. [Figure 6] Figure 6 is a cross-sectional view showing the state of a semiconductor device according to Embodiment 1 during the manufacturing process. [Figure 7] Figure 7 is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 2. [Figure 8] Figure 8 is a cross-sectional view showing the semiconductor device according to Embodiment 2 during the manufacturing process. [Figure 9] Figure 9 shows the relationship between the degree of crystal damage recovery of a semiconductor substrate by hydrogen annealing and the barrier metal. [Figure 10] Figure 10 is a cross-sectional view showing the structure of Comparative Example 1. [Figure 11] Figure 11 is a cross-sectional view showing the structure of Comparative Example 2. [Figure 12] Figure 12 is a cross-sectional view showing the manufacturing process of Comparative Example 2. [Figure 13] Figure 13 is a cross-sectional view showing the manufacturing process of Comparative Example 2. [Figure 14] Figure 14 is a cross-sectional view showing the manufacturing process of Comparative Example 2. [Figure 15] Figure 15 is a cross-sectional view showing the manufacturing process of Comparative Example 2. [Figure 16] Figure 16 is a cross-sectional view showing the manufacturing process of Comparative Example 2. [Figure 17] Figure 17 is a cross-sectional view showing the manufacturing process of Comparative Example 2. [Figure 18] Figure 18 is a cross-sectional view showing the manufacturing process of Comparative Example 2. [Modes for carrying out the invention]

[0012] <Summary of the embodiments of this disclosure> (1) A semiconductor device according to one aspect of this disclosure is as follows: A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate. A second semiconductor region of a second conductivity type is provided between the front surface of the semiconductor substrate and the first semiconductor region. An element structure including a pn junction between the second semiconductor region and the first semiconductor region is provided on the front surface side of the semiconductor substrate. An interlayer insulating film is provided on the front surface of the semiconductor substrate. The interlayer insulating film covers the element structure. A contact hole penetrates the interlayer insulating film in the depth direction and reaches the semiconductor substrate. The contact structure is in contact with the semiconductor substrate at the contact hole.

[0013] The first electrode is electrically connected to the second semiconductor region via the contact structure. The second electrode is provided on the back surface of the semiconductor substrate. The contact structure consists of a titanium silicide film, a titanium nitride film, and a metal plug. The titanium silicide film is in contact with the semiconductor substrate at the contact hole and extends along the side wall of the contact hole to the surface of the interlayer insulating film. The titanium nitride film is provided along the surface of the titanium silicide film. The metal plug is embedded inside the contact hole on the titanium nitride film.

[0014] According to the above disclosure, the contact resistance between the first electrode and the semiconductor substrate is reduced by electrically connecting the first electrode and the semiconductor substrate via a TiSix film (titanium silicide film). Furthermore, according to the above disclosure, special high-temperature heat treatments such as silicide formation are not required to form the TiSix film. Therefore, localized stress on the semiconductor substrate can be suppressed. In addition, since no Ti film that adsorbs hydrogen is formed on the surface of the interlayer insulating film, recovery of crystal damage to the semiconductor substrate due to hydrogen annealing is facilitated. Moreover, because no Ti film is formed on the surface of the interlayer insulating film, a decrease in adhesion to the interlayer insulating film due to the reaction between the material gas and the Ti film during the formation of the metal plug can be prevented.

[0015] (2) The semiconductor device according to this disclosure also includes, in (1) above, a contact trench of a predetermined depth provided on the front surface of the semiconductor substrate, continuous with the contact hole. The titanium silicide film may be provided along the side wall of the contact hole and the inner wall of the contact trench.

[0016] According to the disclosures mentioned above, Because the contact area between the TiSix film and the semiconductor substrate is increased, it is possible to suppress the increase in contact resistance between the first electrode and the semiconductor substrate. .

[0017] (3) In addition, in the semiconductor device relating to this disclosure, the thickness of the titanium silicide film may be uniform from the side wall of the contact hole to the side wall of the contact trench, as described in (2) above.

[0018] According to the disclosure described above, the stress on the interlayer insulating film and the semiconductor substrate becomes uniform at the sidewalls of the contact holes and the sidewalls of the contact trenches.

[0019] (4) In addition, in the semiconductor device relating to this disclosure, the interlayer insulating film may be located at a distance of 10 nm or less from the contact trench in a direction parallel to the front surface of the semiconductor substrate, as described in (2) above.

[0020] According to the disclosure described above, the step coverage of the metal plug is improved.

[0021] (5) In addition, in any one of (1) to (4) described above, the semiconductor device according to this disclosure has the titanium silicide film terminated on the side surface of the interlayer insulating film. The first electrode may be provided on the upper surface of the interlayer insulating film, in contact with the interlayer insulating film.

[0022] According to the disclosure described above, the adhesion of the first electrode is improved, and delamination of the first electrode from the interlayer insulating film can be suppressed.

[0023] (6) In addition, in any one of (1) to (4) described above, the semiconductor device according to this disclosure is characterized in that the titanium silicide film covers the entire surface of the interlayer insulating film. The first electrode is provided on the upper surface of the interlayer insulating film via the titanium silicide film and the titanium nitride film.

[0024] According to the disclosure described above, damage to the interlayer insulating film caused by ultrasonic vibrations during wire bonding to the first electrode can be suppressed.

[0025] (7) A method for manufacturing a semiconductor device according to one aspect of this disclosure is as follows: A first step is performed to form a second semiconductor region of a second conductivity type in contact with a first semiconductor region of a first conductivity type inside the semiconductor substrate on the surface region of the front surface of the semiconductor substrate, and to form an element structure including a pn junction between the second semiconductor region and the first semiconductor region. A second step is performed to form an interlayer insulating film covering the element structure on the front surface of the semiconductor substrate. A third step is performed to form a contact hole that penetrates the interlayer insulating film in the depth direction and reaches the semiconductor substrate. A fourth step is performed to form a contact structure in contact with the semiconductor substrate at the contact hole.

[0026] A fifth step is performed to form a first electrode electrically connected to the second semiconductor region via the contact structure. After the fifth step, a first annealing step is performed to restore crystal damage to the semiconductor substrate by heat treatment in a hydrogen atmosphere. The fourth step includes first to third deposition steps. In the first deposition step, a titanium silicide film is deposited by sputtering, covering the entire surface of the interlayer insulating film and contacting the semiconductor substrate in the contact holes. In the second deposition step, a titanium nitride film is deposited on the surface of the titanium silicide film by sputtering. In the third deposition step, a metal plug is embedded on the titanium nitride film inside the contact holes. The contact structure consisting of the titanium silicide film, the titanium nitride film, and the metal plug is formed.

[0027] According to the above disclosure, the contact resistance between the first electrode and the semiconductor substrate is reduced by electrically connecting the first electrode and the semiconductor substrate via a TiSix film (titanium silicide film). Furthermore, according to the above disclosure, special high-temperature heat treatments such as silicide formation are not required to form the TiSix film. Therefore, localized stress on the semiconductor substrate can be suppressed. In addition, since no Ti film that adsorbs hydrogen is formed on the surface of the interlayer insulating film, recovery of crystal damage to the semiconductor substrate due to hydrogen annealing is facilitated. Moreover, because no Ti film is formed on the surface of the interlayer insulating film, a decrease in adhesion to the interlayer insulating film due to the reaction between the material gas and the Ti film during the formation of the metal plug can be prevented.

[0028] (8) The method for manufacturing a semiconductor device according to this disclosure also includes, in (7) above, a sixth step of forming a contact trench of a predetermined depth continuous with the contact hole on the front surface of the semiconductor substrate after the third step and before the fourth step. In the first deposition step, the titanium silicide film may be formed along the surface of the interlayer insulating film and the inner wall of the contact trench.

[0029] According to the disclosure described above, the contact area between the TiSix film and the semiconductor substrate is increased, which makes it possible to suppress the increase in contact resistance between the first electrode and the semiconductor substrate.

[0030] (9) Furthermore, the method for manufacturing a semiconductor device according to this disclosure may include a seventh step of planarizing the interlayer insulating film after the sixth step and before the fourth step, in (8) above.

[0031] According to the disclosure described above, the ability to embed metal plugs into contact trenches can be improved.

[0032] (10) In addition, in the method for manufacturing a semiconductor device according to this disclosure, in any one of (7) to (9) described above, the first deposition step and the second deposition step may be carried out continuously using the same sputtering apparatus.

[0033] According to the disclosures described above, the process can be simplified and costs can be reduced.

[0034] (11) Furthermore, in any one of the above steps (7) to (10), the fourth step is to use the metal plug as a mask and the titanium nitride film and The process further includes a removal step of etching back the titanium silicide film to expose the upper surface of the interlayer insulating film. In the fifth step, the first electrode may be formed on the upper surface of the interlayer insulating film in contact with the interlayer insulating film.

[0035] According to the disclosure described above, the adhesion of the first electrode is improved, and delamination of the first electrode from the interlayer insulating film can be suppressed.

[0036] (12) In addition, the method for manufacturing a semiconductor device according to this disclosure may be carried out in any one of the above-described steps (7) to (11) in an atmosphere with a temperature of 300°C or less.

[0037] According to the disclosure described above, it is possible to suppress localized stress in the semiconductor substrate.

[0038] (13) Furthermore, in any one of the above-described steps (7) to (12), the method for manufacturing a semiconductor device according to this disclosure includes an irradiation step in which the semiconductor substrate is irradiated with radiation after the first annealing step. After the irradiation step, a second annealing step may be performed in which the parasitic diode formed in the pn junction is adjusted to a predetermined reverse recovery characteristic by heat treatment in a hydrogen atmosphere.

[0039] According to the disclosure described above, it is possible to recover from crystal damage that causes a low gate threshold voltage.

[0040] <Knowledge forming the basis of this disclosure> The challenges of this embodiment include reducing the contact resistance between the front electrode and the semiconductor substrate, and recovering crystal damage to the semiconductor substrate caused by radiation irradiation such as electron beams or impurity ion implantation through hydrogen annealing (heat treatment in a hydrogen atmosphere). Conventionally, since titanium (Ti) has low contact resistance with n-type silicon (Si), a method of forming a titanium silicide (TiSix) film between the front electrode and the semiconductor substrate by silicide reaction of a Ti film with the semiconductor substrate (Si substrate) is known. However, the volume expansion of the TiSix film due to silicide increases the localized stress on the semiconductor substrate.

[0041] As the heat treatment temperature for silicide formation increases, the contact resistance between the TiSix film and the semiconductor substrate decreases. However, the volume expansion of the TiSix film due to silicide formation further increases the localized stress on the semiconductor substrate. For example, when the contact structure of the front electrode is embedded in a contact trench provided on the front surface of the semiconductor substrate to increase the contact area and reduce the contact resistance between the front electrode and the semiconductor substrate, the TiSix film is formed along the inner wall of the contact trench. Because the contact trench is narrow and shallow, there is concern that the volume expansion of the TiSix film due to silicide formation will further increase the localized stress on the semiconductor substrate.

[0042] Furthermore, when forming a TiSix film by silicide reaction with a semiconductor substrate, the Ti film, which is the material film of the TiSix film, is formed to cover the entire surface of the interlayer insulating film. However, this Ti film readily absorbs hydrogen, hindering the effect of hydrogen annealing, which is necessary to repair crystal damage to the semiconductor substrate. Therefore, even if hydrogen annealing is performed, it is difficult to recover characteristics such as gate threshold voltage. In particular, the p-type base region and n - In semiconductor devices that have been irradiated with electron beams or other radiation to improve switching characteristics such as the reverse recovery time (trr) of parasitic diodes (body diodes) formed at the pn junction (main junction) with the drift region, crystal damage caused to the semiconductor substrate by radiation irradiation is not sufficiently recovered.

[0043] Assuming that crystal damage to the semiconductor substrate may not be fully recovered, it is possible to adjust the predetermined characteristics of the product to a predetermined value by setting the predetermined characteristics higher in advance to account for the decrease due to crystal damage to the semiconductor substrate, for example, by excessively increasing the amount of impurities in a predetermined diffusion region within the semiconductor substrate. However, in this case, the predetermined characteristics may become higher than the predetermined value due to the recovery of crystal damage to the semiconductor substrate by hydrogen annealing, making it prone to characteristic fluctuations in reliability tests such as high-temperature application tests. For this reason, it is necessary to accept that the product specifications will take into account a certain degree of characteristic fluctuation due to crystal damage to the semiconductor substrate, resulting in inferior product reliability (reliability of various characteristics evaluated in reliability tests such as high-temperature application tests). This embodiment solves these problems.

[0044] Preferred embodiments of the semiconductor device and method for manufacturing the semiconductor device according to this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these signs. In the following description of embodiments and in the accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted.

[0045] (Details of Embodiment 1) The semiconductor device according to Embodiment 1 that solves the above problems will be described by taking a MOSFET (Metal Oxide Semiconductor Field Effect Transistor, a MOS-type field effect transistor having an insulating gate composed of a three-layer structure of metal - oxide film - semiconductor) as an example. FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 1. The semiconductor device 10 according to Embodiment 1 shown in FIG. 1 is a vertical MOSFET having a trench gate structure (element structure) with a contact structure composed of a titanium silicide (TiSix) film 11 (where x is a positive number), a titanium nitride (TiN) film 12, and a metal plug (lead-out electrode portion) 13 between the front surface electrode (first electrode) 14 and the semiconductor substrate (semiconductor chip) 8.

[0046] The semiconductor substrate 8 is, for example, an n - -type drift region (first semiconductor region) 1, an n - -type Si bulk substrate, or an n + -type drain region 15, an n + -type starting substrate (Si bulk substrate) with an n - -type drift region 1 formed thereon as an n - -type epitaxial layer. When the semiconductor substrate 8 is an n - -type drift region 1, an n - -type Si bulk substrate, the n + -type drain region 15 is a diffusion region formed by ion implantation in the surface region of the back surface of the semiconductor substrate 8. The n + -type drain region 15 is provided between the back surface of the semiconductor substrate 8 and the n - -type drift region 1, in contact with the n - -type drift region 1. On the entire back surface of the semiconductor substrate 8, a back surface electrode (second electrode) 16 serving as a drain electrode is provided in contact with the n + -type drain region 15.

[0047] The trench gate structure includes a p-type base region (second semiconductor region) 2, an n + -type source region 3, a p +It consists of a p-type contact region 4, a trench 5, a gate insulating film 6, and a gate electrode 7, and is provided on the front side of the semiconductor substrate 8. + Type source region 3 and p + The p-type contact region 4 is a diffusion region formed by ion implantation on the surface region of the front surface of the semiconductor substrate 8. The p-type base region 2 is formed on the front surface of the semiconductor substrate 8 and n - Between the drift region 1 and n - It is provided adjacent to the drift region 1. + Type source region 3 and p + The p-type contact regions 4 are selectively provided between the front surface of the semiconductor substrate 8 and the p-type base region 2, in contact with the p-type base region 2.

[0048] n + Type source region 3 and p + The contact region 4 makes ohmic contact with the TiSix film 11. + The contact area 4 is located away from the trench 5. + The contact region 4 extends from the front surface of the semiconductor substrate 8 to n + n is greater than type source area 3 + It reaches a deep position on the drain region 15 side (the back side of the semiconductor substrate 8). + Type contact region 4 does not need to be provided. In this case, p + Instead of the p-type contact region 4, the p-type base region 2 contacts the TiSix film 11. The p-type base region 2 of the semiconductor substrate 8, n + Type source area 3, p + Type contact area 4 and n + The part excluding the type drain region 15 is n - This is type drift region 1.

[0049] The trench 5 extends in the depth direction from the front surface of the semiconductor substrate 8 to n + n penetrates the p-type source region 3 and the p-type base region 2. -It terminates inside the type drift region 1. A gate insulating film 6 is provided along the inner wall (side wall and bottom surface) of the trench 5. A gate electrode 7 is embedded on the gate insulating film 6 inside the trench 5. + Type source region 3, p-type base region 2 and n - The type drift region 1 only needs to face the gate electrode 7 via the gate insulating film 6 on the side wall of the trench 5, and the upper end of the gate electrode 7 and the gate insulating film 6 (the end on the opening side of the trench 5) is n greater than the front surface of the semiconductor substrate 8. + The drain may terminate at a deeper position (i.e., inside the trench 5) on the drain region 15 side.

[0050] The interlayer insulating film 9 is provided on the front surface of the semiconductor substrate 8 and covers the gate electrode 7. A contact hole 9a is provided that penetrates the interlayer insulating film 9 in the depth direction and reaches the semiconductor substrate 8. The cross-sectional shape of the contact hole 9a may be substantially rectangular, or it may be substantially tapered (trapezoidal) with the width narrowing towards the semiconductor substrate 8 side. When a source contact trench 8a, which will be described later, is provided, it is preferable to improve the embedding of the metal plug 13 into the source contact trench 8a by making the thickness of the interlayer insulating film 9 relatively thin to reduce the aspect ratio (=depth / width) of the contact hole 9a, or by rounding the upper surface corners of the interlayer insulating film 9 (boundary between the top surface and the side surface) by reflowing (planarizing) the interlayer insulating film 9.

[0051] The interlayer insulating film 9 is composed of a silicon oxide (SiO2) film, such as a BPSG (Boro Phospho Silicate Glass) film 9-2. For example, by reflowing the BPSG film 9-2 with a total boron (B) concentration and phosphorus (P) concentration of 9-2 set to 6 mol% or less, the width w1 of the contact hole 9a widens relatively on the side opposite to the semiconductor substrate 8 (i.e., the portion continuous with the source contact trench 8a). This makes it less likely for the contact hole 9a to be blocked when the W film 13a (see Figure 5) is embedded, thereby improving the embedding of the metal plug 13 into the source contact trench 8a.

[0052] The interlayer insulating film 9 may include a deposited SiO2 film (hereinafter referred to as HTO film) 9-1 deposited by general high-temperature oxidation (HTO). In this case, the interlayer insulating film 9 has a two-layer structure in which, for example, an HTO film 9-1 and a BPSG film 9-2 are stacked in this order. The HTO film 9-1 has high film density and insulation performance comparable to, for example, a thermal oxide film, and has better insulation properties than a deposited SiO2 film formed by PECVD or sputtering. By including the HTO film 9-1 in the interlayer insulating film 9, the short-circuit withstand capability between the electrodes electrically insulated by the interlayer insulating film 9 (between the gate electrode 7 and the front electrode 14) is improved, thereby improving the reliability of the semiconductor device 10. A deposited SiO2 film using TEOS (Tetra Ethoxy Silane) may be used instead of the HTO film 9-1.

[0053] A source contact trench 8a is provided on the front surface of the semiconductor substrate 8, continuous with the contact hole 9a of the interlayer insulating film 9. The source contact trench 8a extends in the depth direction from the front surface of the semiconductor substrate 8 to n + Type source region 3 penetrates p + It terminates inside the type contact region 4. The source contact trench 8a extends from the front surface of the semiconductor substrate 8 to n + n is greater than type source area 3 + It reaches a deep position on the drain region 15 side. The bottom surface of the source contact trench 8a is p + Surrounded by the type contact region 4, p is present across the entire bottom surface of the source contact trench 8a. + The type contact region 4 is exposed. The side wall of the source contact trench 8a has n + Type source region 3 and p + The type contact region 4 is exposed. The cross-sectional shape of the source contact trench 8a may be substantially rectangular, or it may be substantially tapered with a width w2 that narrows towards the back side of the semiconductor substrate 8.

[0054] The width w2 of the source contact trench 8a is narrower than the width w1 of the contact hole 9a. This is because, after the source contact trench 8a, which is continuous with the contact hole 9a, is formed in a self-aligned manner using the etching mask used to form the contact hole 9a, the interlayer insulating film 9 (BPSG film 9-2) is reflowed. As a result, the side surface of the interlayer insulating film 9 (the side wall of the contact hole 9a) moves (retracts) by a predetermined distance d away from the source contact trench 8a, and the width w1 of the contact hole 9a widens. Between the side surface of the interlayer insulating film 9 and the side wall of the source contact trench 8a, the front surface of the semiconductor substrate 8 is exposed at a distance d of approximately 10 nm or less, creating a step difference in height at this distance d.

[0055] By providing the source contact trench 8a, the contact area between the TiSix film 11 and the semiconductor substrate 8 is increased. Therefore, even if the width w1 of the contact hole 9a is narrowed by miniaturizing the width between adjacent trenches 5, it is possible to suppress the increase in contact resistance between the front electrode 14 and the semiconductor substrate 8. In addition, by providing the source contact trench 8a, when the semiconductor substrate 8 is turned off, n - Holes within the mold drift region 1 are more easily drawn to the front electrode 14, improving avalanche withstand capability. When the semiconductor device 10 is in a low-voltage class of approximately 250V or less, or when miniaturized, avalanche breakdown becomes more likely due to parasitic bipolar operation, so it is advisable to provide a source contact trench 8a. By providing a source contact trench 8a, avalanche withstand capability can be improved in all voltage classes, not just in the low-voltage class.

[0056] A source contact trench 8a is not required. In this case, on the front surface of the semiconductor substrate 8 exposed to the contact hole 9a, n + Type source region 3 and p +The type contact region 4 makes ohmic contact with the TiSix film 11. The TiSix film 11 and the TiN film 12 are provided extending from the side wall (side surface of the interlayer insulating film 9) to the bottom surface (front surface of the semiconductor substrate 8 exposed to the contact hole 9a) of the contact hole 9a, and a metal plug 13 is embedded on the TiN film 12 inside the contact hole 9a. In the TiSix film 11 and the TiN film 12, the conditions of the side wall portion and the bottom surface portion of the contact hole 9a are the same as those of the side wall portion and the bottom surface portion of the source contact trench 8a.

[0057] TiSix film 11 and TiN film 12 are laminated in this order on the side walls of the contact hole 9a (side surfaces of the interlayer insulating film 9), the surface connecting the side walls of the contact hole 9a and the side walls of the source contact trench 8a (hereinafter referred to as the stepped surface), and the inner wall of the source contact trench 8a. The TiSix film 11 and TiN film 12 are not provided on the upper surface of the interlayer insulating film 9. The upper surface of the interlayer insulating film 9 is the part of the surface of the interlayer insulating film 9 other than the side walls of the contact hole 9a. Direct contact between the front electrode 14 and the upper surface of the interlayer insulating film 9 improves the adhesion of the front electrode 14 and suppresses delamination of the front electrode 14 from the interlayer insulating film 9.

[0058] Furthermore, by not providing the TiSix film 11 and TiN film 12 on the upper surface of the interlayer insulating film 9, damage to the relatively hard TiSix film 11 and TiN film 12 due to ultrasonic vibrations during wire bonding to the front electrode 14 can be suppressed. Also, by not providing the TiSix film 11 and TiN film 12 on the upper surface of the interlayer insulating film 9, the effect of hydrogen annealing to recover crystal damage to the semiconductor substrate 8 is not hindered. For this reason, the carrier life of the n-type drift region 1 due to radiation irradiation such as electron beams can be suppressed. time By performing control, crystal damage to the semiconductor substrate 8 can be recovered by hydrogen annealing, thereby restoring characteristics such as the gate threshold voltage.

[0059] The TiSix film 11 and TiN film 12 are formed (deposited) by sputtering, and the side walls of the contact holes 9a, the stepped surfaces (front surfaces of the semiconductor substrate 8) and the source contact trench 8a side wall The thickness tends to be thicker at the bottom of the source contact trench 8a compared to other parts. The thickness of the TiSix film 11 and the TiN film 12 is approximately uniform from the sidewall of the contact hole 9a to the sidewall of the source contact trench 8a. As a result, the stress on the interlayer insulating film 9 and the semiconductor substrate 8 is uniform at the sidewall of the contact hole 9a and the sidewall of the source contact trench 8a. Approximately uniform thickness means that the thickness is approximately the same within a range that includes tolerances due to manufacturing process variations.

[0060] The TiSix film 11 is n on the inner wall of the source contact trench 8a + Type source region 3 and p + Ohmic contact is made with the type contact region 4. By providing a source contact trench 8a, the contact area between the TiSix film 11 and the semiconductor substrate 8 can be increased, and the contact resistance between the TiSix film 11 and the semiconductor substrate 8 is reduced. Therefore, even if the width w1 of the contact hole 9a is narrowed due to miniaturization, the increase in contact resistance between the front electrode 14 and the semiconductor substrate 8 can be suppressed. The TiN film 12 is a barrier metal that has the function of preventing the diffusion of metal atoms from the front electrode 14 to the semiconductor substrate 8 side and the function of preventing mutual reactions between each part facing each other across the TiN film 12.

[0061] The edges of the TiSix film 11 are terminated on the surface of the interlayer insulating film 9 (for example, on the side surface of the interlayer insulating film 9). The edges of the TiN film 12 are terminated on the surface of the TiSix film 11. The TiSix film 11 has higher adhesion to the interlayer insulating film 9 than the TiN film 12. Therefore, by providing the TiSix film 11 between the TiN film 12 and the interlayer insulating film 9, the adhesion of the front surface electrode 14 is improved. A metal plug 13 is provided on the TiN film 12 so as to fill the contact hole 9a and the source contact trench 8a. The height of the upper surface of the metal plug 13 is at the same height as the edge of the TiN film 12, or lower on the semiconductor substrate 8 side than the height of the edge of the TiN film 12. The material of the metal plug 13 is, for example, tungsten (W), which has high embedding properties and poor adhesion to the semiconductor substrate 8. By providing the TiSix film 11 and the TiN film 12 between the semiconductor substrate 8 and the metal plug 13, the adhesion of the metal plug 13 is improved.

[0062] The contact structure of the front electrode 14 is formed by the TiSix film 11, the TiN film 12, and the metal plug 13. Alternatively, the front electrode 14 may be embedded in the contact hole 9a and the source contact trench 8a instead of the metal plug 13, without providing the metal plug 13. In this case, the TiN film 12 may not be provided. That is, the contact structure of the front electrode 14 may consist only of the TiSix film 11 that makes ohmic contact with the semiconductor substrate 8. The front electrode 14 is provided in contact with the upper surface of the interlayer insulating film 9 and the upper surface of the metal plug 13. The front electrode 14 is, for example, an aluminum (Al) film or an Al alloy film. The front electrode 14 is connected to the p-type base region 2, n-type base region via the metal plug 13, the TiN film 12, and the TiSix film 11. + Type source region 3 and p + It is electrically connected to the contact region 4 and functions as a source electrode.

[0063] A method for manufacturing the semiconductor device 10 according to Embodiment 1 will be described. Figures 2 to 6 are cross-sectional views showing the semiconductor device according to Embodiment 1 in the process of manufacturing. First, as shown in Figure 2, by a general method, n -A trench gate structure, an interlayer insulating film 9 (HTO film 9-1 and BPSG film 9-2), and a contact hole 9a are formed on the front surface of the semiconductor substrate 8, which will become the type drift region 1 (steps 1-3). Next, the front surface of the semiconductor substrate 8 is etched using the same resist mask used to form the contact hole 9a to form a source contact trench 8a continuous with the contact hole 9a (step 6). Then, the resist mask used to form the source contact trench 8a is removed. In this case, it is also possible to remove the resist mask after the formation of the contact hole 9a and form the source contact trench 8a using the interlayer insulating film 9 as a mask.

[0064] Next, the BPSG film 9-2 is reflowed by heat treatment while oxidizing the exposed surface of the semiconductor substrate 8 (in this case, the inner wall of the source contact trench 8a) (step 7). As a result, the upper corners of the BPSG film 9-2 are rounded, and the sides of the BPSG film 9-2 recede by a predetermined distance d away from the source contact trench 8a. Next, the oxide film covering the semiconductor substrate 8 inside the contact hole 9a is removed. At this time, along with the oxide film, the edges of the HTO film 9-1 (the parts exposed due to the receding of the sides of the BPSG film 9-2 by a predetermined distance d) are also removed, and the sides of the HTO film 9-1 also recede by a predetermined distance d away from the source contact trench 8a.

[0065] In this way, the sides of the interlayer insulating film 9 (HTO film 9-1 and BPSG film 9-2) recede by a predetermined distance d away from the source contact trench 8a, thereby widening the width w1 of the contact hole 9a. This improves the embedding of the W film 13a (see Figure 5), which is deposited on the surface of the semiconductor substrate 8 in a later process, into the source contact trench 8a. Furthermore, by reflowing the BPSG film 9-2 while oxidizing the exposed surface of the semiconductor substrate 8, the distance d at which the sides of the interlayer insulating film 9 recede away from the source contact trench 8a can be reduced to about 10 nm or less. As a result, the step coverage of the W film 13a deposited on the surface of the semiconductor substrate 8 in a later process is improved.

[0066] Next, as shown in Figure 3, a TiSix film 11 is deposited (formed) by sputtering along the surface (top and sides) of the interlayer insulating film 9 and the inner walls (bottom and side walls) of the source contact trench 8a in a temperature atmosphere of approximately 300°C or less (for example, approximately 200°C) (first deposition step). The thickness of the TiSix film 11 is, for example, approximately 40 nm. Since no special heat treatment such as silicideization of the Ti film is performed, the TiSix film 11 maintains its thickness at the time of sputtering and does not expand in volume. Next, as shown in Figure 4, a TiN film 12 is deposited (formed) along the surface of the TiSix film 11 by sputtering in a temperature atmosphere of approximately 300°C or less (for example, approximately 200°C) (second deposition step).

[0067] The TiSix film 11 and the TiN film 12 may be formed using different sputtering apparatuses. Alternatively, the TiSix film 11 and the TiN film 12 may be formed continuously using the same sputtering apparatus capable of mounting multiple sputtering targets, by appropriately switching the sputtering targets, introduced gas, etc. By continuously forming the TiSix film 11 and the TiN film 12 using the same sputtering apparatus, the process can be simplified and costs can be reduced. General conditions can be used for the sputtering targets, introduced gas, and other conditions used to form the TiSix film 11 and the TiN film 12, respectively.

[0068] Next, as shown in Figure 5, using WF6 gas as the material gas and monosilane (SiH4) gas or hydrogen (H2) gas as the source gas, a W film 13a is deposited (formed) on the outermost surface of the semiconductor substrate 8 by CVD, filling the contact holes 9a and source contact trenches 8a. At this time, the TiSix film 11 and TiN film 12, which cover the entire surface of the interlayer insulating film 9, function as barrier metals. Therefore, even if the material gas of the W film 13a permeates the TiN film 12 from a location where the barrier metal function of the TiN film 12 has deteriorated, the chemical reaction that generates fluorine (F) or H2, which reduces adhesion to the interlayer insulating film 9, as occurs when a titanium (Ti) film is provided as a barrier metal, does not occur.

[0069] Next, as shown in Figure 6, the W film 13a is etched back, leaving the W film 13a only inside the contact holes 9a and source contact trenches 8a (third deposition step). The W film 13a left inside the contact holes 9a and source contact trenches 8a becomes the metal plug 13. Next, the TiN film 12 and TiSix film 11 are etched back using the metal plug 13 as an etching mask to expose the upper surface of the interlayer insulating film 9 (removal step). The dry etching for etching back the W film 13a and the dry etching for etching back the TiN film 12 and TiSix film 11 may be performed continuously by switching the etching gas, or they may be performed using different etching apparatuses.

[0070] Next, a front surface electrode 14 is formed on the outermost surface of the front surface of the semiconductor substrate 8 by sputtering and photoetching (5th step). Then, the resist mask used to form the front surface electrode 14 is removed (ashing). After that, the crystal damage of the semiconductor substrate 8 is restored by hydrogen annealing in an atmosphere at a temperature of approximately 380°C (1st annealing step). This hydrogen annealing can be performed at any time after the formation of the front surface electrode 14, but if the semiconductor substrate 8 is damaged by etching or ashing, Immediately It can be done at this timing. especiallyIt is effective. Subsequently, an n+ type drain region 15 and a back electrode 16 are formed on the back side of the semiconductor substrate 8.

[0071] At any of the timings after the hydrogen annealing described above, the carrier life of the n-type drift region 1 is altered by radiation irradiation (irradiation process) from the front or back surface of the semiconductor substrate 8, such as by an electron beam. time Control may be performed. Alternatively, after radiation irradiation, instead of completely recovering the crystal damage caused by radiation irradiation, the amount of crystal damage to the semiconductor substrate 8 may be adjusted by performing hydrogen annealing in a temperature atmosphere of approximately 350°C, for example, so that the reverse recovery characteristics of the parasitic diode reach a predetermined lifetime (reverse recovery time) (second annealing step). This hydrogen annealing after radiation irradiation may recover the crystal damage that causes the gate threshold voltage to decrease. This completes the semiconductor device 10 shown in Figure 1.

[0072] The operation of the semiconductor device 10 according to Embodiment 1 will be described. A positive voltage is applied to the drain electrode (back electrode 16) relative to the source electrode (front electrode 14), p + Type 4 contact region and p-type base region 2 and n - Type drift regions 1 and n + The pn junction (main junction) with the drain region 15 is reverse-biased. In this state, if the voltage applied to the gate electrode 7 is less than the gate threshold voltage, the semiconductor device 10 (MOSFET) remains in the off state.

[0073] Only the front-facing electrodes 14 are placed on the interlayer insulating film 9 of the semiconductor device 10, so the effect of hydrogen annealing is not hindered. Therefore, even if the semiconductor device 10 is irradiated with radiation such as an electron beam to improve the switching characteristics of the parasitic diode, the crystal damage of the semiconductor substrate 8 is almost completely recovered by the subsequent hydrogen annealing, and the gate threshold voltage characteristics are restored (see Figure 9). Consequently, the semiconductor device 10 maintains its normally-off state.

[0074] On the other hand, when a positive voltage is applied to the drain electrode relative to the source electrode and a voltage greater than the gate threshold voltage is applied to the gate electrode 7, a channel (n-type inversion layer) is formed in the p-type base region 2 along the side wall of the trench 5. As a result, n + Type drain region 15 to n - Type drift region 1 and through the channel n + A drift current (main current) flows toward the source region 3, and the semiconductor device 10 turns on.

[0075] As described above, according to Embodiment 1, the front electrode and the semiconductor substrate are electrically connected via a TiSix film deposited on the semiconductor substrate by sputtering. By electrically connecting the front electrode and the semiconductor substrate via the TiSix film, the contact resistance between the front electrode and the semiconductor substrate can be reduced. Furthermore, according to Embodiment 1, when forming the TiSix film on the semiconductor substrate, special high-temperature heat treatment such as silicide formation is not required, and the TiSix film is directly deposited by sputtering in a low-temperature atmosphere of 300°C or less, thus suppressing localized stress on the semiconductor substrate.

[0076] Furthermore, for example, when forming a TiSix film by a silicide reaction with a semiconductor substrate, the Ti film, which is the material film of the TiSix film, covers the entire surface of the interlayer insulating film. Therefore, the effect of hydrogen annealing to recover crystal damage to the semiconductor substrate is inhibited, or in order to obtain the effect of hydrogen annealing, it is necessary to remove the portion of the Ti film that covers the upper surface of the interlayer insulating film. On the other hand, according to Embodiment 1, since the TiSix film is deposited directly by sputtering, no Ti film is formed on the surface of the interlayer insulating film, making it easier to recover crystal damage to the semiconductor substrate by hydrogen annealing. For example, even in products (semiconductor devices) that have been irradiated with radiation such as electron beams to improve switching characteristics such as the reverse recovery time of the body diode, the crystal damage to the semiconductor substrate can be sufficiently recovered by hydrogen annealing.

[0077] In other words, according to Embodiment 1, it is not necessary to pre-set a high gate threshold voltage to account for the decrease due to crystal damage to the semiconductor substrate, such as by excessively increasing the amount of impurities in a predetermined diffusion region within the semiconductor substrate, assuming that the gate threshold voltage will decrease due to crystal damage to the semiconductor substrate. Therefore, characteristic fluctuations are less likely to occur in reliability tests such as high-temperature application tests, and the reliability of the product (reliability of various characteristics evaluated in reliability tests such as high-temperature application tests) is improved. Furthermore, according to Embodiment 1, since a Ti film is not used as a barrier metal, the problems that arise from the reaction between the material gas and the Ti film during the formation of the metal plug (see comparative example described later) do not occur. Therefore, it is possible to prevent a decrease in adhesion with the interlayer insulating film.

[0078] Furthermore, when using CVD for the deposition of TiSix and TiN films, for example, the conditions such as the type of gas used for each film formation differ, making it impossible to continuously form TiSix and TiN films using the same CVD apparatus. On the other hand, according to Embodiment 1, by depositing the TiSix film by sputtering, it becomes possible to continuously form TiSix and TiN films using the same sputtering apparatus. This simplifies the process and reduces costs. In addition, since the process of transporting the semiconductor wafer between the formation of the TiSix film and the formation of the TiN film can be omitted, contamination during wafer transport is suppressed, the yield rate improves, and the reliability of the product is enhanced.

[0079] (Details of Embodiment 2) The semiconductor device according to Embodiment 2, which solves the above-mentioned problems, is described below. Figure 7 is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 2. Figure 8 is a cross-sectional view showing the semiconductor device according to Embodiment 2 in the process of manufacturing. The difference between the semiconductor device 20 according to Embodiment 2 and the semiconductor device 10 according to Embodiment 1 (see Figure 1) is that the TiSix film 21 and TiN film 22 constituting the contact structure of the front electrode 14 extend between the front electrode 14 and the interlayer insulating film 9, covering the entire surface of the interlayer insulating film 9.

[0080] The configuration of the TiSix film 21 and TiN film 22 inside the contact hole 9a and source contact trench 8a is the same as that of the TiSix film 11 and TiN film 12 in Embodiment 1, respectively. The TiSix film 21 and TiN film 22 function as barrier metals that suppress the diffusion of metal atoms from the front electrode 14 to the interlayer insulating film 9. The TiSix film 21 and TiN film 22 also have the function of suppressing damage to the interlayer insulating film 9 caused by ultrasonic vibrations during wire bonding to the front electrode 14.

[0081] The method for manufacturing the semiconductor device 20 according to Embodiment 2 is the same as the method for manufacturing the semiconductor device 10 according to Embodiment 1, but without the etch-back of the TiSix film 11 and the TiN film 12 (see Figure 6). That is, the steps from the formation of the trench gate structure to the formation of the metal plug 13 are carried out in order, as in Embodiment 1 (Figures 2-5, 8). Then, with the TiSix film 11 and the TiN film 12 remaining on the upper surface of the interlayer insulating film 9 (Figure 8), the steps from the formation of the front surface electrode 14 onwards are carried out in order to complete the semiconductor device 20 shown in Figure 7.

[0082] Even if the TiSix film 11 and TiN film 12 remain on the upper surface of the interlayer insulating film 9, the effect of hydrogen annealing to recover crystal damage to the semiconductor substrate 8 is not inhibited. Furthermore, the TiSix film 21 has higher adhesion to the interlayer insulating film 9 compared to the TiN film 22 and the front surface electrode 14. Therefore, the adhesion of the front surface electrode 14 is improved by the TiSix film 21. In addition, the process of removing part of the TiSix film 11 and TiN film 12 can be omitted, making it possible to reduce the number of processes and the amount of particles.

[0083] As described above, according to Embodiment 2, the same effects as in Embodiment 1 can be obtained even if the upper surface of the interlayer insulating film is covered with a TiSix film and a TiN film. According to Embodiment 2, the yield rate can be improved and costs can be reduced by reducing the number of processes and reducing particles.

[0084] (Example of experiment) The relationship between the degree of crystal damage recovery of semiconductor substrates by hydrogen annealing and the barrier metal was investigated. Figure 9 shows the relationship between the degree of crystal damage recovery of semiconductor substrates by hydrogen annealing and the barrier metal. Figure 9 shows the results of investigating the degree of crystal damage recovery of semiconductor substrates by hydrogen annealing using four samples (hereinafter referred to as Samples 1 to 4) with different conditions (presence or absence of barrier metal, presence or absence of crystal damage in the semiconductor substrate) for a typical trench gate structure MOSFET (hereinafter referred to as the experimental example).

[0085] Sample 1 has a Ti film on the interlayer insulating film as a barrier metal, and the semiconductor substrate does not have crystal damage due to radiation irradiation (Ti present, no damage). Sample 2 has a Ti film on the interlayer insulating film as a barrier metal, and the semiconductor substrate has crystal damage due to radiation irradiation (Ti present, damage present). Sample 3 does not have a barrier metal, and the semiconductor substrate has crystal damage due to radiation irradiation (Ti absent, damage present). Sample 4 does not have a barrier metal, and the semiconductor substrate does not have crystal damage due to radiation irradiation (Ti absent, no damage).

[0086] Figure 9's "Damage Recovery Degree" indicates whether the gate threshold voltage of the semiconductor substrate after recovery from crystal damage by hydrogen annealing has recovered to the design value of the gate threshold voltage. The degree of crystal damage recovery of the semiconductor substrate by hydrogen annealing in sample 4 is used as the baseline (=100%). In Figure 9, "Damaged / Not Damaged" indicates the presence or absence of crystal damage due to radiation irradiation. In all samples 1 to 4, hydrogen annealing was performed on semiconductor substrates that had similar crystal damage from other manufacturing processes (e.g., ion implantation).

[0087] As shown in Figure 9, the results for sample 2 confirmed that the presence of a Ti film as a barrier metal prevented sufficient recovery of crystal damage to the semiconductor substrate caused by radiation irradiation. Furthermore, the results for sample 3 confirmed that the absence of a Ti film as a barrier metal allowed for recovery of crystal damage to the semiconductor substrate caused by radiation irradiation to a level comparable to that of samples 1 and 4, which had no such damage. Additionally, since the damage recovery rate of sample 3 was higher than that of sample 1, it can be seen that the absence of a Ti film as a barrier metal also leads to a higher recovery rate for crystal damage to the semiconductor substrate caused by processes other than radiation irradiation.

[0088] (Comparative example) As a comparative example, we will describe a MOSFET in which the contact resistance between the front electrode and the semiconductor substrate is reduced by providing a high-hardness, high-melting-point metal film such as Ti or nickel (Ni), or a titanium silicide (TiSi) film obtained by silicideizing a Ti film, between the front electrode and the semiconductor substrate. Figures 10 and 11 are cross-sectional views showing the structures of Comparative Examples 1 and 2, respectively. The semiconductor devices 110 and 120 shown in Figures 10 and 11 (hereinafter referred to as Comparative Examples 1 and 2) are vertical MOSFETs with a general trench gate structure, and each has a different contact structure between the front electrode 114 and the semiconductor substrate 108.

[0089] In Comparative Examples 1 and 2, the trench gate structure is a p-type base region 102, n + Type source area 103, p + It consists of a type contact region 104, a trench 105, a gate insulating film 106, and a gate electrode 107, and is connected to the front surface of the semiconductor substrate 108 and n - It is provided between the type drift region 101. The interlayer insulating film 109 is provided on the front surface of the semiconductor substrate 108 and covers the gate electrode 107. The back surface of the semiconductor substrate 108 and n - Between the drift region 101 and n + A drain region 115 is provided. On the back surface of the semiconductor substrate 108, n + A back surface electrode 116, which serves as the drain electrode, is provided in contact with the drain region 115.

[0090] Comparative Example 1 (semiconductor device 110 shown in Figure 10) has a source contact trench 108a on the front surface of the semiconductor substrate 108, continuous with the contact hole 109a of the interlayer insulating film 109. The inner wall of the source contact trench 108a has n + Type source region 103 and p + The type contact region 104 is exposed. Along the side wall of the contact hole 109a (the side surface of the interlayer insulating film 109) and the inner wall of the source contact trench 108a, a metal film 111 with high hardness and a high melting point, such as Ti or Ni, and a TiN film 112 are sequentially formed by sputtering.

[0091] The metal film 111 and the TiN film 112 extend to the upper surface of the interlayer insulating film 109, covering the entire upper surface of the interlayer insulating film 109. A W plug 113 is provided on the TiN film 112 to fill the contact hole 109a and the source contact trench 108a. A front surface electrode 114 is provided on the TiN film 112 and the W plug 113. The front surface electrode 114 is connected via the W plug 113, the TiN film 112, and the metal film 111. + Type source region 103 and p + It is electrically connected to the contact area 104 and functions as a source electrode.

[0092] Comparative Example 2 (semiconductor device 120 shown in Figure 11) differs from Comparative Example 1 in that a TiSi film 121 is provided only on the Si portion instead of the metal film 111. Comparative Example 2 has a thicker interlayer insulating film 109 compared to Comparative Example 1 because it does not have a source contact trench 108a. The TiSi film 121 is formed by a silicide reaction between Ti atoms in the Ti film (Ti film 121a described later: see Figures 13 and 14) and Si atoms in the semiconductor substrate 108, and is provided only on the Si portion (i.e., the front surface of the semiconductor substrate 108) within the contact hole 109a of the interlayer insulating film 109.

[0093] The TiSi film 121 is not provided on the surface of the interlayer insulating film 109. The thickness of the TiSi film 121 is, for example, about 60 nm, and it extends from the front surface of the semiconductor substrate 108 to n + The film terminates at a position shallower than the mold source region 103. Although not shown, even when Comparative Example 2 has a source contact trench 108a, the TiSi film 121 is provided only on the Si portion (i.e., the inner wall of the source contact trench 108a). The TiN film 122 is provided along the surface of the TiSi film 121 and the surface of the interlayer insulating film 109. The W plug 123 is embedded on the TiN film 122 inside the contact hole 109a.

[0094] The manufacturing method of Comparative Example 2 (semiconductor device 120 shown in Figure 11) will be described. Figures 12 to 18 are cross-sectional views showing the manufacturing process of Comparative Example 2. First, as shown in Figure 12, a p-type base region 102, n + Type source area 103, p + A trench gate structure is formed consisting of a type contact region 104, a trench 105, a gate insulating film 106, and a gate electrode 107. Next, an interlayer insulating film 109 is formed over the entire surface of the front surface of the semiconductor substrate 108. Then, a contact hole 109a is formed that penetrates the interlayer insulating film 109 in the depth direction and reaches the semiconductor substrate 108.

[0095] Next, as shown in Figure 13, in a temperature atmosphere of about 300°C, a Ti film 121a with a thickness of, for example, about 40 nm is formed by sputtering along the surface of the interlayer insulating film 109 and the surface of the semiconductor substrate 108 that is exposed to the contact hole 109a. Then, as shown in Figure 14, the Ti film 121a and the semiconductor substrate 108 are subjected to a silicide reaction by rapid thermal annealing (RTA) at, for example, about 600°C, to form a TiSi film 121 on the front surface of the semiconductor substrate 108 within the contact hole 109a. Due to volume expansion caused by silicide formation, the thickness of the TiSi film 121 increases to about 60 nm.

[0096] Next, as shown in Figure 15, the remaining unreacted Ti film 121a on the surface of the interlayer insulating film 109 is removed. Then, as shown in Figure 16, a TiN film 122 is formed along the surface of the TiSi film 121 and the surface of the interlayer insulating film 109 by sputtering. Next, as shown in Figure 17, a W film 123a is formed on the outermost surface of the front surface of the semiconductor substrate 108 by CVD to fill the contact hole 109a. Next, as shown in Figure 18, the W film 123a is etched back, leaving only the portion that will become the W plug 123 inside the contact hole 109a.

[0097] Next, a front electrode 114 is formed on the outermost surface of the semiconductor substrate 108. An n+ type drain region 115 and a back electrode 116 are formed on the back side of the semiconductor substrate 108. Next, the carrier life of the n- type drift region 101 is determined by irradiation with radiation such as an electron beam. time Control the process up to this point (especially the carrier life in the n-type drift region 101). time Radiation irradiation for control causes crystal damage to the semiconductor substrate 108, resulting in changes in various characteristics such as the gate threshold voltage. Therefore, comparative example 2 is completed by recovering the crystal damage of the semiconductor substrate 8 through hydrogen annealing.

[0098] In Comparative Example 1 described above, contact structures consisting of not only a Ti film (metal film 111) but also two layers of a Ti film and a TiN film, or three layers of a Ti film, a TiN film, and a Ti film are known. The Ti film has low contact resistance with n-type Si (semiconductor substrate 108). Therefore, in Comparative Example 1, even if the width of the contact hole 109a is narrowed due to miniaturization, it is possible to suppress the increase in contact resistance between the front electrode 114 and the semiconductor substrate 108. However, in Comparative Example 1, if the metal film 111 between the front electrode 114 and the interlayer insulating film 109 is a Ti film, this Ti film inhibits the effect of hydrogen annealing.

[0099] Furthermore, in Comparative Example 1, there is a risk that the WF6 gas, which is the material gas of the W plug 113, will permeate the TiN film 12 and come into contact with the Ti film. When the WF6 gas comes into contact with the Ti film, fluorine and H2 are generated, which reduces the adhesion with the interlayer insulating film 109. In addition, a part of the Ti film disappears, causing lifting and cracking in the upper TiN film 112. As a result, the adhesion of the front electrode 114 decreases. For example, the above problems can be solved by replacing the metal film 111 with a Ni film instead of a Ti film, or by removing the portion of the Ti film that covers the surface of the interlayer insulating film 109, but this reduces the function of the metal film 111 as a barrier metal.

[0100] Furthermore, if the portion of the Ti film (metal film 111) covering the surface of the interlayer insulating film 109 is removed, the ultrasonic vibrations during wire bonding to the front electrode 114 will damage the interlayer insulating film 109. Also, removing the portion of the Ti film covering the surface of the interlayer insulating film 109 will increase costs due to an increase in the number of processes and a decrease in the yield rate due to particle generation. Moreover, if the portion of the Ti film covering the surface of the interlayer insulating film 109 is removed, the TiN film 112, which has lower adhesion to the interlayer insulating film 109 than the Ti film, will come into contact with the interlayer insulating film 109, thereby reducing the adhesion between the interlayer insulating film 109 and the front electrode 114.

[0101] In Comparative Example 2, removing the remaining Ti film 121a, which is the material for the TiSi film 121 (see Figure 15), results in a decrease in the yield rate due to an increase in the number of processes and particle generation, similar to Comparative Example 1. If the remaining Ti film 121a is left on the interlayer insulating film 109 without removal, the same problems as in Comparative Example 1 occur during the formation of the W plug 123 and during hydrogen annealing. In addition, in Comparative Example 2, the contact resistance between the TiSi film 121 and the semiconductor substrate 108 is reduced, but the volume expansion due to silicide causes the thickness of the TiSi film 121 to become thicker than the thickness of the Ti film 121a at the time of deposition, and the greater the thickness, the greater the localized stress on the semiconductor substrate 108.

[0102] Furthermore, in Comparative Examples 1 and 2, assuming that the crystal damage of the semiconductor substrate 108 is not sufficiently recovered by hydrogen annealing, the predetermined characteristics are set higher in advance to account for the decrease due to the crystal damage of the semiconductor substrate 108 by excessively increasing the impurity dose in a predetermined diffusion region within the semiconductor substrate 108, thereby adjusting the predetermined characteristics of the product to a predetermined value. However, there is a risk that the predetermined characteristics will become higher than the predetermined value due to the recovery of the crystal damage of the semiconductor substrate 108 by hydrogen annealing. For this reason, characteristic fluctuations are likely to occur in reliability tests such as high-temperature application tests, resulting in inferior reliability of the product (semiconductor device 110, 120).

[0103] For example, in Patent Document 4 mentioned above, a polycrystalline silicon (poly-Si) film deposited on a semiconductor substrate is reacted with titanium radicals generated while heated to approximately 500°C to form a TiSi film. Therefore, similar to Comparative Example 2, the volume expansion of the TiSi film due to silicide formation increases the localized stress on the semiconductor substrate. Furthermore, if the silicide formation of the polycrystalline silicon film does not reach from the top surface of the polycrystalline silicon film to the semiconductor substrate in the depth direction, the contact resistance with the semiconductor substrate increases. In addition, because the Ti film is included in the metal wiring, the effect of hydrogen annealing is inhibited, similar to Comparative Example 1.

[0104] For example, in the above-mentioned Patent Document 5, a TiSi film is directly formed on a semiconductor substrate by PECVD. However, if chlorine (Cl) contained in the PECVD introduction gas composition diffuses into the semiconductor substrate or is mixed in as a residue in the TiSi film or semiconductor substrate, it can cause corrosion of the TiSi film and semiconductor substrate. Furthermore, deposited films formed using plasma-treated material gases have high stress and high resistance. To reduce the resistance of the deposited film, it is assumed that it is necessary to reduce the sheet resistance by making the thickness of the deposited film uniform in the plane, for example by heat treatment, which increases the number of process steps.

[0105] Furthermore, while Patent Document 5 describes a method in which a Si film is deposited on a semiconductor substrate by CVD, and then a Ti film is deposited by PECVD, the Si film and the Ti film are reacted to form a TiSi film. However, it is difficult to form a Si film by any method other than crystal growth through a chemical reaction between the introduced gas and the semiconductor substrate (Si substrate). Even if a Si film can be deposited by CVD, if the Ti film deposited on the entire surface of the semiconductor substrate, including the surface of the Si film, is then reacted with the Si film, the stress on the TiSi film increases due to volume expansion. Also, the remaining portion of the Ti film that does not react inhibits the effect of hydrogen annealing, similar to Comparative Example 1.

[0106] On the other hand, according to Embodiments 1 and 2 (see Figures 1 and 7), the metal films that function as barrier metals and are provided on at least a portion of the surface of the interlayer insulating film 9 are TiSix films 11 and 21 and TiN films 12 and 22, and no Ti film is provided. Therefore, the effect of hydrogen annealing is not inhibited, and there is no decrease in adhesion to the interlayer insulating film 9 due to contact between the material gas of the metal plugs 13 and 23 and the metal films that function as barrier metals. Furthermore, the TiSix films 11 and 21 are formed by sputtering in a low-temperature atmosphere of about 300°C or less, and it is possible to suppress localized stress on the semiconductor substrate 8. Therefore, the reliability of the product is improved.

[0107] Furthermore, according to Embodiment 2 (see Figure 7), the entire surface of the interlayer insulating film 9 is covered with the TiSix film 21 and the TiN film 22, which improves its effect as a barrier metal. In addition, the TiSix film 21 and the TiN film 22 can suppress damage to the interlayer insulating film 9 caused by ultrasonic vibrations during wire bonding to the front electrode 14. Moreover, according to Embodiment 2, since the TiSix film 21 and the TiN film 22 are not selectively removed, the number of processes and particle reduction improve the yield rate and reduce costs.

[0108] Furthermore, in the above-mentioned Patent Documents 1 to 4, the TiSiN film included in the laminated structure of the front electrode differs from the TiSix film 11 and 21 in Embodiments 1 and 2 in that it inhibits the effect of hydrogen annealing to recover crystal damage to the semiconductor substrate. Also, in Patent Document 1, after forming a Ti film, a TiSiN layer is formed by sputtering, and then oxidation and heat treatment are performed to oxidize the upper surface of the TiSiN layer to form a titanium silicon nitride oxide layer, which is the oxide layer of the TiSiN layer, and these are laminated to form a capacitor, which differs from forming contact with the semiconductor substrate as in Embodiments 1 and 2. In addition, in Patent Document 1, high-temperature heat treatment exceeding 600°C is performed, so the stress locally generated in the semiconductor substrate becomes large due to volume expansion caused by alloying.

[0109] In the above-mentioned Patent Document 2, the TiSiN layer is formed between the semiconductor substrate and the interlayer insulating film, which differs from the structure of the TiSix films 11 and 21 in these embodiments 1 and 2. Furthermore, because high-temperature heat treatment is performed, the stress locally generated in the semiconductor substrate becomes large due to volume expansion caused by alloying. The above-mentioned Patent Document 3 has a structure in which a first conductive layer containing Si is formed on the surface of the semiconductor substrate, a second conductive layer containing a high-melting-point metal such as a TiSiN layer, Si, and nitrogen is formed thereon, and a third conductive layer containing platinum group elements is formed thereon, with these conductive layers connected. This prevents interdiffusion between Si and platinum group elements even when high-temperature heat treatment is performed, and therefore differs from the structure that forms contact with the semiconductor substrate as in these embodiments 1 and 2. Furthermore, in the above-mentioned Patent Document 3, because high-temperature heat treatment is performed, the stress locally generated in the semiconductor substrate becomes large due to volume expansion caused by alloying.

[0110] In the above-mentioned Patent Document 4, high aspect ratio contact holes reaching the semiconductor substrate are formed in the interlayer insulating film, and polycrystalline or amorphous Si films of a thickness that does not fill the contact holes are laminated on the surface of the interlayer insulating film, the side surfaces of the contact holes, and the bottom surface of the contact holes (semiconductor substrate surface). A Ti film is deposited by PECVD, converting the Si film into a TiSi film, and further forming a TiN film on the Ti film surface. This differs from the method for forming the TiSix films 11 and 21 in these embodiments. It also differs from these embodiments in that polycrystalline or amorphous Si films are laminated. Furthermore, in the above-mentioned Patent Document 4, volume expansion of the TiSi film due to silicide formation in high-temperature plasma may increase localized stress on the semiconductor substrate, and plasma damage may remain.

[0111] The first example of the contact layer formation method described in Patent Document 5 involves forming high aspect ratio contact holes reaching the semiconductor substrate in the interlayer insulating film and then laminating a TiSi film of a thickness that does not fill the contact holes using PECVD, which differs from the TiSix film formation method 1 and 2 of this embodiment. Furthermore, in Patent Document 5, the chlorine (Cl) contained in the PECVD introduction gas composition for forming the TiSi film can cause fluctuations in the semiconductor substrate's properties, reduced reliability, and corrosion. There is also a risk of residual plasma damage. Moreover, in the first example of the contact layer formation method described in Patent Document 5, if heat treatment at a temperature higher than the TiSi film formation temperature is performed after the formation of the TiSi film, the stress locally generated in the semiconductor substrate will increase.

[0112] The second example of the contact layer formation method described in Patent Document 5 above involves forming high aspect ratio contact holes reaching the semiconductor substrate in the interlayer insulating film, forming a Si film of a thickness that does not fill the contact holes by low-pressure CVD (LPCVD), and then forming a Ti film by PECVD while reacting it with the Si film to convert it into a TiSi film. This differs from the TiSix film formation method 11,21 in Embodiments 1 and 2. Furthermore, in the second example of the contact layer formation method described in Patent Document 5 above, residual Cl in the TiCl gas used may cause characteristic fluctuations and reduced reliability, and there is a risk of plasma damage. In addition, due to silicide formation in the plasma, the volume expansion of the TiSi film increases the localized stress on the semiconductor substrate.

[0113] The above-mentioned Patent Document 6 describes a method for reducing gate resistance by forming a polysilicon film as the gate electrode and then forming a TiSi film on the polysilicon film using the PVD method. However, because the side etching of the TiSi film is large, an oxide film is formed on the side surface of the gate electrode to prevent the gate width from narrowing. The contact structure of the front electrode is not disclosed, and it differs from the method of forming contact with the semiconductor substrate as in Embodiments 1 and 2. Furthermore, in Patent Document 6, high-temperature heat treatment is performed, which increases the localized stress on the semiconductor substrate due to volume expansion caused by alloying.

[0114] In contrast, in these two embodiments, the TiSix film is deposited on the semiconductor substrate by sputtering as described above, thus avoiding the problems described in the above-mentioned references 1 to 6.

[0115] In summary, this disclosure is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit of this disclosure. For example, the embodiments described above are not limited to trench gate MOSFETs, but can be applied to various semiconductor devices in which the contact structure of the front electrode makes ohmic contact with the semiconductor substrate at the contact holes of the interlayer insulating film. Furthermore, although the first conductivity type is n-type and the second conductivity type is p-type in each embodiment, this disclosure is also valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial applicability]

[0116] As described above, the semiconductor device and method for manufacturing a semiconductor device according to this disclosure are useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines, and are particularly suitable for semiconductor devices miniaturized by contact trenches. [Explanation of Symbols]

[0117] 1 n - Type drift region 2 p-type base region 3 n + Type source area 4 p + Type Contact Area 5 Trench 6 Gate insulating film 7 Airports 8 Semiconductor substrates 8a Source Contact Trench 9 Interlayer insulating film 9-1 HTO membrane 9-2 BPSG membrane 9a Contact Hole 10,20 Semiconductor equipment 11,21 TiSix membrane 12,22 TiN film 13,23 Metal plug 13a W membrane 14 Front surface electrodes 15 n + Type drain region 16 Backside electrode d The distance at which the side surface of the interlayer insulating film recedes away from the source contact trench. w1 Contact hole width w2 Source Contact Trench Width

Claims

1. A first semiconductor region of a first conductivity type provided inside a semiconductor substrate, A second semiconductor region of a second conductivity type is provided between the front surface of the semiconductor substrate and the first semiconductor region, An element structure including a pn junction between the second semiconductor region and the first semiconductor region, provided on the front side of the semiconductor substrate, An interlayer insulating film is provided on the front surface of the semiconductor substrate and covers the element structure, A contact hole that penetrates the interlayer insulating film in the depth direction and reaches the semiconductor substrate, A contact structure that contacts the semiconductor substrate through the contact hole, A first electrode electrically connected to the second semiconductor region via the contact structure, A second electrode provided on the back surface of the semiconductor substrate, Equipped with, The aforementioned contact structure is A titanium silicide film is in contact with the semiconductor substrate through the contact hole and extends along the side wall of the contact hole to the surface of the interlayer insulating film, A titanium nitride film provided along the surface of the titanium silicide film, It consists of a metal plug provided on the titanium nitride film and embedded in the contact hole, The semiconductor substrate is provided with a contact trench of a predetermined depth, which is continuous with the contact hole, The titanium silicide film is a deposited film, provided along the side walls of the contact holes and the inner walls of the contact trenches, and covering the entire surface of the interlayer insulating film. The thickness of the titanium silicide film is uniform from the side wall of the contact hole to the side wall of the contact trench. A semiconductor device characterized in that the first electrode is provided on the upper surface of the interlayer insulating film via the titanium silicide film and the titanium nitride film.

2. The semiconductor device according to claim 1, characterized in that the interlayer insulating film is located at a distance of 10 nm or less from the contact trench in a direction parallel to the front surface of the semiconductor substrate.

3. A first step of forming a device structure including a pn junction between the second semiconductor region and the first semiconductor region, by forming a second semiconductor region of a second conductivity type in contact with a first semiconductor region of a first conductivity type inside the semiconductor substrate on the surface region of the front surface of the semiconductor substrate, A second step involves forming an interlayer insulating film covering the element structure on the front surface of the semiconductor substrate, A third step involves forming contact holes that penetrate the interlayer insulating film in the depth direction and reach the semiconductor substrate, A fourth step involves forming a contact structure that contacts the semiconductor substrate through the contact hole, A fifth step is to form a first electrode electrically connected to the second semiconductor region via the contact structure, Following the fifth step, a first annealing step is performed to restore crystal damage to the semiconductor substrate by heat treatment in a hydrogen atmosphere, Includes, The aforementioned fourth step is, A first deposition step involves depositing a titanium silicide film by sputtering, which covers the entire surface of the interlayer insulating film and contacts the semiconductor substrate through the contact holes. A second deposition step involves depositing a titanium nitride film on the surface of the titanium silicide film by sputtering, The process includes a third deposition step of filling the contact holes with metal plugs formed on the titanium nitride film, The contact structure consisting of the titanium silicide film and the titanium nitride film and the metal plug is formed. After the third step and before the fourth step, a sixth step is included in which a contact trench of a predetermined depth continuous with the contact hole is formed on the front surface of the semiconductor substrate. A method for manufacturing a semiconductor device, characterized in that the titanium silicide film is formed along the surface of the interlayer insulating film and the inner wall of the contact trench in the first deposition step.

4. The method for manufacturing a semiconductor device according to claim 3, further comprising a seventh step of planarizing the interlayer insulating film after the sixth step and before the fourth step.

5. The method for manufacturing a semiconductor device according to claim 3, characterized in that the first deposition step and the second deposition step are carried out in succession using the same sputtering apparatus.

6. The fourth step further includes a removal step of etching back the titanium nitride film and the titanium silicide film using the metal plug as a mask to expose the upper surface of the interlayer insulating film, The method for manufacturing a semiconductor device according to claim 3, characterized in that, in the fifth step, the first electrode is formed on the upper surface of the interlayer insulating film in contact with the interlayer insulating film.

7. The method for manufacturing a semiconductor device according to claim 3, characterized in that the first deposition step is performed in a temperature atmosphere of 300°C or less.

8. An irradiation step of irradiating the semiconductor substrate with radiation after the first annealing step, The method for manufacturing a semiconductor device according to claim 3, further comprising a second annealing step, after the irradiation step, in which the parasitic diode formed in the pn junction is adjusted to a predetermined reverse recovery characteristic by heat treatment in a hydrogen atmosphere.

9. The method for manufacturing a semiconductor device according to claim 3, characterized in that the second deposition step is performed in a temperature atmosphere of 300°C or less.

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