Semiconductor device and method for manufacturing a semiconductor device

Abstract

This disclosure provides a semiconductor device and a method for manufacturing a semiconductor device that can suppress variations in etching depth during PEC etching. The semiconductor device comprises a substrate, a channel layer and a barrier layer sequentially stacked on the substrate, and a gate electrode. The barrier layer has a lower semiconductor layer, an intermediate semiconductor layer stacked on the lower semiconductor layer, and an upper semiconductor layer stacked on the intermediate semiconductor layer. The lower semiconductor layer has a higher bandgap energy than the upper semiconductor layer. The intermediate semiconductor layer has a higher bandgap energy than the lower semiconductor layer. The gate electrode is formed on the intermediate semiconductor layer exposed through an opening provided in the upper semiconductor layer.

Claims

1. circuit board and A channel layer and a barrier layer are sequentially stacked on the substrate, Equipped with a gate electrode, The barrier layer comprises a lower semiconductor layer, an intermediate semiconductor layer laminated on the lower semiconductor layer, and an upper semiconductor layer laminated on the intermediate semiconductor layer. The lower semiconductor layer has a higher band gap energy than the upper semiconductor layer. The intermediate semiconductor layer has a higher band gap energy than the lower semiconductor layer. The gate electrode is formed on the intermediate semiconductor layer exposed through an opening provided in the upper semiconductor layer, The bandgap energy of the aforementioned intermediate semiconductor layer gradually increases from top to bottom. Semiconductor equipment.

2. A substrate and A channel layer and a barrier layer are sequentially stacked on the substrate, Equipped with a gate electrode, The barrier layer comprises a lower semiconductor layer, an intermediate semiconductor layer laminated on the lower semiconductor layer, and an upper semiconductor layer laminated on the intermediate semiconductor layer. The lower semiconductor layer has a higher band gap energy than the upper semiconductor layer. The intermediate semiconductor layer has a higher band gap energy than the lower semiconductor layer. The gate electrode is formed on the intermediate semiconductor layer exposed through an opening provided in the upper semiconductor layer, The lower semiconductor layer, the intermediate semiconductor layer, and the upper semiconductor layer are composed of the same group III nitride semiconductor, but with different composition ratios. Semiconductor equipment.

3. circuit board and A channel layer and a barrier layer are sequentially stacked on the substrate, An insulating film formed on the barrier layer, Insulation injection area and It comprises a first gate electrode and a second gate electrode, The barrier layer comprises a lower semiconductor layer, an intermediate semiconductor layer laminated on the lower semiconductor layer, and an upper semiconductor layer laminated on the intermediate semiconductor layer. The lower semiconductor layer has a higher band gap energy than the upper semiconductor layer. The intermediate semiconductor layer has a higher band gap energy than the lower semiconductor layer. The first gate electrode is formed on the intermediate semiconductor layer within an opening that penetrates the insulating film and the upper semiconductor layer and exposes the intermediate semiconductor layer. The second gate electrode is formed on the upper semiconductor layer within an opening in the insulating film that exposes the upper semiconductor layer, A semiconductor device in which the region including the first gate electrode and the region including the second gate electrode are separated by the insulating injection region that penetrates from the barrier layer to the substrate.

4. The semiconductor device according to claim 3, wherein the bandgap energy of the intermediate semiconductor layer gradually increases from top to bottom of the intermediate semiconductor layer.

5. The semiconductor device according to claim 3, wherein the lower semiconductor layer, the intermediate semiconductor layer, and the upper semiconductor layer are composed of the same group III nitride semiconductor, and their composition ratios are different.

6. The process of stacking channel layers on a substrate, A step of stacking a barrier layer on the channel layer, the barrier layer having a lower semiconductor layer, an intermediate semiconductor layer stacked on the lower semiconductor layer, and an upper semiconductor layer stacked on the intermediate semiconductor layer, A step of removing the upper semiconductor layer at the position where the gate electrode is to be formed by photoelectrochemical etching using excitation light having an energy greater than or equal to the band gap energy of the upper semiconductor layer and less than or equal to the band gap energy of the intermediate semiconductor layer, thereby exposing the intermediate semiconductor layer, A step of forming the gate electrode on the exposed intermediate semiconductor layer, A method for manufacturing a semiconductor device, including the method described above.

7. The method for manufacturing a semiconductor device according to claim 6, further comprising the step of forming an electrode on the upper semiconductor layer for releasing electrons generated in the photoelectrochemical etching to the outside, prior to the photoelectrochemical etching step.

8. The method for manufacturing a semiconductor device according to claim 7, wherein the electrode is a source electrode or a drain electrode.

9. The process of stacking channel layers on a substrate, A step of stacking a barrier layer on the channel layer, the barrier layer having a lower semiconductor layer, an intermediate semiconductor layer stacked on the lower semiconductor layer, and an upper semiconductor layer stacked on the intermediate semiconductor layer, The process involves forming an insulating injection region that penetrates from the barrier layer to the substrate, and separating the upper semiconductor layer into a first region and a second region in a plan view. A step of forming a first electrode on the upper semiconductor layer in the aforementioned first region, The process involves forming a second electrode on the upper semiconductor layer in the second region, A step of forming an insulating film that exposes at least a portion of the first electrode and covers the second electrode, A step of selectively etching only the first region by photoelectrochemical etching using excitation light having an energy greater than or equal to the band gap energy of the upper semiconductor layer and less than or equal to the band gap energy of the intermediate semiconductor layer, thereby removing the upper semiconductor layer at the position where the first gate electrode is formed and exposing the intermediate semiconductor layer, A step of forming the first gate electrode on the intermediate semiconductor layer exposed in the first region, The process involves forming a second gate electrode on the upper semiconductor layer in the second region, A method for manufacturing a semiconductor device, including the method described above.

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