Semiconductor equipment

Abstract

A channel layer (2), a barrier layer (3), and a cap layer (4) formed on a substrate (1) are formed in this order. N-type first and second contact layers (7, 8) are respectively formed in first and second recesses (5, 6) formed up to a part of the channel layer (2) through the cap layer (4) and the barrier layer (3). A source electrode (9) is formed on the first contact layer (7). A drain electrode (10) is formed on the second contact layer (8). A gate electrode (11) is formed on the cap layer (4) between the source electrode (9) and the drain electrode (10). The cross-sectional shape of the first recess (5) is a reverse taper, and the lateral width of the first contact layer (7) increases toward the bottom of the first recess (5).

Claims

1. circuit board and A channel layer formed on the substrate, A barrier layer formed on the channel layer, A cap layer formed on the barrier layer, n-type first and second contact layers are formed in first and second recesses that penetrate the cap layer and the barrier layer and extend to a part of the channel layer, respectively. A source electrode formed on the first contact layer, A drain electrode formed on the second contact layer, The system comprises a gate electrode formed on the cap layer between the source electrode and the drain electrode, A semiconductor device characterized in that the cross-sectional shape of the first recess is an inverse taper, and the width of the first contact layer widens towards the bottom of the first recess.

2. The first contact layer has a high impurity concentration region at the bottom edge of the first recess, where the impurity concentration is higher than in other parts of the first contact layer. The semiconductor device according to claim 1, characterized in that the two-dimensional electron gas layer of the channel layer is generated near the high impurity concentration region.

3. The impurity concentration in the aforementioned high impurity concentration region is 1 × 10 １９ cm －３ The semiconductor device according to claim 2, characterized in that it is as described above.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that the bottoms of the first and second recesses are at the same height as the two-dimensional electron gas layer of the channel layer.

5. The semiconductor device according to any one of claims 1 to 3, characterized in that the first and second contact layers cover the side walls of the cap layer within the first and second recesses.

6. The semiconductor device according to claim 5, characterized in that the first and second contact layers each have overlapping portions that extend outside the first and second recesses and rest on top of the cap layer.

7. The semiconductor device according to claim 6, characterized in that the width of the overlap portion is greater than the opening width of the first and second recesses and less than the width of the bottom of the first and second recesses.

8. The semiconductor device according to any one of claims 1 to 3, characterized in that the cross-sectional shape of the second recess is an inverse taper, and the width of the second contact layer widens towards the bottom of the second recess.

9. The second contact layer covers the sidewall of the cap layer within the second recess. The semiconductor device according to any one of claims 1 to 3, characterized in that the cross-sectional shape of the second recess is a forward taper, and the width of the second contact layer narrows towards the bottom of the second recess.

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