Quantum error mitigation based on scaled gates

Abstract

Techniques related to quantum error mitigation are provided. For example, one or more embodiments described herein may include a system that may include a memory that may store computer-executable components. The system may also include a processor that is operatively coupled to the memory and may execute the computer-executable components stored in the memory. The computer-executable components may include an error mitigation component that may add a set of scaled quantum gates to the quantum circuit for error mitigation. The set of scaled quantum gates may include a quantum gate and an inversion of the quantum gate. The set of scaled quantum gates may also have a rotation angle based on a pulse schedule to achieve a target stretch factor.

Description

[Technical Field]

[0001] This disclosure relates to error mitigation in quantum circuits, and more specifically, to the incorporation of scaled quantum gates into quantum circuits to realize one or more extension coefficients that can control the amount of noise generated in the quantum circuit. [Background technology]

[0002] Quantum computers can be negatively affected by intrinsic noise that may be present throughout the execution time of quantum circuits. For example, qubit operations in a quantum circuit may be associated with error values ​​arising from one or more noise sources, such as the coherence time of a qubit. Error values ​​can degrade the computational results of a quantum circuit. Furthermore, the amount of error may increase as the number of qubit operations or circuit components (e.g., quantum gates) or both increases. To mitigate the amount of error in the results of a quantum circuit, quantum error mitigation techniques introduce a controlled amount of noise into the quantum circuit to extrapolate to noise-free results.

[0003] An exemplary quantum error mitigation technique is Richardson extrapolation, in which a quantum circuit is executed at various circuit execution times, with each execution corresponding to a specific extension factor. Pulse-based and digital-based methods exist for Richardson extrapolation. Pulse-based Richardson extrapolation is performed by changing the pulse schedule duration for the same set of quantum gates required to execute the quantum circuit. Multiple copies of the gate set, executed by schedules with identical but different durations, can be coordinated and used to execute the same quantum circuit. Digital-based Richardson extrapolation is performed by inserting noisy quantum gates as a way to extend the execution time of the quantum circuit. Typically, two CNOT gates, including the identity gate, are inserted into the original quantum circuit for each CNOT gate. [Overview of the Initiative]

[0004] The following is an overview to enable a basic understanding of one or more embodiments of the present invention. This overview is not intended to identify major or important elements, nor is it intended to precisely describe the scope of any particular embodiment or claim. The sole purpose of this overview is to present the concepts in a simplified form as a prelude to the more detailed descriptions presented later. One or more embodiments described herein describe a system, computer implementation method, apparatus, or computer program product, or combination thereof, capable of performing quantum error mitigation of quantum operations.

[0005] According to one embodiment, a system is provided. This system may include a memory capable of storing computer executable components. This system may also include a processor operably coupled to the memory and capable of executing the computer executable components stored in the memory. The computer executable components may include an error mitigation component that can add a set of scaled quantum gates to the quantum circuit for error mitigation. The set of scaled quantum gates may include quantum gates and inversions of quantum gates. The set of scaled quantum gates may also have a rotation angle based on a pulse schedule to achieve a target stretch factor. An advantage of such a system may be the improved stretch factor resolution employed in error mitigation.

[0006] In some examples, the rotation angle of a scaled set of quantum gates can control the amount of noise introduced into a quantum circuit. The advantage of such a system can be the control of noise introduction via quantum gates that do not need to be calibrated.

[0007] According to the embodiment, a computer implementation method is provided. The computer implementation method may include adding a set of scaled quantum gates to a quantum circuit for error mitigation by a system operably coupled to a processor. The set of scaled quantum gates may include quantum gates and inversions of quantum gates. The set of scaled quantum gates may also have a rotation angle based on a pulse schedule to achieve a target elongation coefficient. An advantage of such a computer implementation method may be the use of quantum error mitigation techniques using quantum circuits of varying depths.

[0008] In some examples, computer implementations may involve the system inserting a set of quantum gates into a quantum circuit based on a target quantum gate present in the quantum circuit. The advantage of such computer implementations can be the use of the inserted set of quantum gates to facilitate Richardson extrapolation algorithms within cloud-based computing environments.

[0009] According to one embodiment, a computer program product is provided for mitigating errors in quantum circuits. The computer program product may comprise a computer-readable storage medium in which program instructions are embodied. The program instructions are executable by a processor, causing the processor to add a set of scaled quantum gates to the quantum circuit. The set of scaled quantum gates may include quantum gates and their inversions. The set of scaled quantum gates may also have a rotation angle based on a pulse schedule to achieve a target expansion coefficient. An advantage of such a computer program product may be an increase in the acceptable circuit depth for the execution of Richardson extrapolation algorithms.

[0010] In some examples, program instructions can further instruct the processor to extract the calibration of a target quantum gate and determine the pulse execution of the target quantum gate. The program instructions can also further instruct the processor to generate a pulse schedule for a set of quantum gates based on the pulse execution of the target quantum gate and the target elongation coefficient. The pulse schedule can then be used to scale the rotation angles of the set of quantum gates, thereby defining a scaled set of quantum gates. An advantage of such a computer program product can be the enabled execution of a high-density distribution of elongation coefficient values. [Brief explanation of the drawing]

[0011] [Figure 1] This figure shows a block diagram of an exemplary non-restrictive system in which quantum error mitigation can be performed by a set of one or more inserted quantum gates implemented using a scaled pulse schedule, according to one or more embodiments described herein. [Figure 2A] This figure shows an exemplary non-restrictive quantum circuit that may be executed to run one or more quantum algorithms on one or more quantum computers according to one or more embodiments described herein. [Figure 2B] This figure shows an exemplary modified non-restrictive quantum circuit generated by inserting one or more sets of quantum gates based on the presence of multi-qubit quantum gates in the original quantum circuit, according to one or more embodiments described herein. [Figure 3] This figure shows an exemplary, non-limiting system capable of generating one or more scaled pulse schedules, implemented using a modified quantum circuit that includes one or more sets of quantum gates in relation to one or more native multi-qubit quantum gates, according to one or more embodiments described herein. [Figure 4] This figure shows an exemplary non-limiting graph that can characterize the relationship between the extension coefficient value and the rotation angle, which may be represented by a set of one or more quantum gates inserted into a quantum circuit according to one or more embodiments described herein. [Figure 5] This figure shows an exemplary, non-limiting scaled pulse schedule that can be implemented on one or more quantum circuits modified to include one or more sets of scalable quantum gates, according to one or more embodiments described herein. [Figure 6] This figure shows an exemplary non-limiting system that runs a modified quantum circuit using various scaled pulse schedules over multiple iterations, according to one or more embodiments described herein. [Figure 7] This figure shows an exemplary, non-limiting system that employs a Richardson extrapolation algorithm, according to one or more embodiments described herein, to determine error-reduced computational results associated with the execution of quantum circuits using various scaled pulse schedules. [Figure 8] This figure shows an exemplary non-limiting graph that can demonstrate improved extension coefficient resolution, which can be achieved by various quantum error mitigation techniques according to one or more embodiments described herein. [Figure 9] This figure shows a flowchart of an exemplary non-restrictive computer implementation method in which quantum error mitigation can be facilitated by executing various scaled pulse schedules on one or more quantum circuits modified to include one or more sets of quantum gates, according to one or more embodiments described herein. [Figure 10] This figure shows a cloud computing environment according to one or more embodiments described herein. [Figure 11] This figure shows an abstract model layer according to one or more embodiments described herein. [Figure 12] FIG. 1 is a block diagram showing an exemplary, non-limiting operating environment that can facilitate one or more embodiments described herein. DETAILED DESCRIPTION

[0012] The following detailed description is merely exemplary in nature and is not intended to limit the embodiments, or the application or uses of the embodiments, in any way. Furthermore, there is no intention to be bound by any expressed or implied information presented in the preceding Background or Summary of the Invention sections, or the Detailed Description section.

[0013] Reference will now be made in detail to one or more embodiments, examples of which are illustrated in the accompanying drawings. Throughout the drawings, like reference numerals are used to refer to like elements. In the following description, numerous specific details are set forth for purposes of explanation to enable one or more embodiments to be thoroughly understood. However, it is apparent that one or more embodiments may be practiced without these specific details in a variety of instances.

[0014] Pulse-based Richardson extrapolation requires significant calibration overhead for each stretched pulse schedule. For example, other pulse parameters may also be modified by implementing alternating durations. For instance, implementing an X-gate with a longer duration may require scaling the amplitude and possibly additional parameters accordingly. Thus, pulses in a schedule containing different parameter values ​​require calibration, thereby incurring significant calibration overhead. Furthermore, digital-based Richardson extrapolation has limited resolution (e.g., the range of applicable elongation factors is limited based on the number of gates) and is therefore unsuitable for quantum circuits with considerable circuit depth. Given the problems associated with other implementations of quantum error mitigation (e.g., pulse-based and digital-based Richardson extrapolation), this disclosure may be implemented to produce solutions to one or more of these problems by an error mitigation technique that inserts a 2-qubit gate having a scaled pulse schedule to achieve one or more target elongation factors into a quantum circuit. It is advantageous that one or more embodiments described herein can increase the acceptable circuit depth compared to digital-based Richardson extrapolation. Furthermore, the various embodiments described herein can be efficiently employed in cloud computing environments because, at a minimum, the scaled 2-qubit gate being implemented does not need to be calibrated using each pulse schedule (for example, as required in pulse-based Richardson extrapolation).

[0015] Various embodiments of the present invention may relate to computer processing systems, computer implementation methods, devices, or computer program products, or combinations thereof, that facilitate efficient, effective, and autonomous (e.g., without direct human guidance) quantum error mitigation. For example, one or more embodiments described herein may include the insertion of one or more scaled 2-qubit gate sets into a particular quantum circuit in relation to one or more native gates of the quantum circuit. The inserted gates may be inverses of each other such that the added gates constitute the identity of the original quantum circuit. Furthermore, the pulse schedule of the added 2-qubit gates may be scaled to achieve one or more target elongation coefficients. For example, the rotation angle of the added 2-qubit gates may be based on a scaled pulse schedule compared to one or more native gates of the quantum circuit. The quantum circuit including the added 2-qubit gates can be executed using multiple pulse schedules, with each execution achieving each elongation coefficient and thereby achieving each introduced noise amount. After multiple executions of the modified quantum circuit, the computational results may be extrapolated to a noise determination close to zero.

[0016] Computer processing systems, computer implementations, devices, or computer program products, or combinations thereof, employ hardware, software, or both to solve problems that are inherently highly technical, not abstract, and cannot be performed as a series of mental activities by humans (e.g., quantum error mitigation). For example, one or more individuals cannot execute quantum circuits using various extension coefficients controlled by scaled quantum gates to extrapolate near-zero-noise calculations.

[0017] Furthermore, one or more embodiments described herein can constitute a technical improvement over conventional quantum error mitigation by modifying a particular quantum circuit to include a set of one or more quantum gates along with a pulse schedule scaled to achieve a target elongation coefficient. Moreover, various embodiments described herein can demonstrate a technical improvement over conventional quantum error mitigation by employing a set of one or more scaled quantum gates without the large calibration overhead typically required to implement a target pulse schedule. Furthermore, one or more embodiments described herein can have practical applications by enabling fine resolution of elongation coefficient values ​​that may be achieved by a set of one or more inserted quantum gates. For example, various embodiments described herein may include a parametric distribution of possible elongation coefficients to facilitate greater circuit depths than standard quantum error mitigation techniques.

[0018] Figure 1 shows a block diagram of an exemplary, non-limiting system 100 that can mitigate error values ​​in one or more quantum circuit calculations. For brevity, repetition of descriptions of similar elements employed in other embodiments described herein is omitted. The systems (e.g., system 100), apparatus, or process embodiments in various embodiments of the present invention can constitute one or more machine-executable components embodied in one or more machines (e.g., embodied in one or more computer-readable media associated with one or more machines). Such components, when executed by one or more machines (e.g., computers, computing devices, or virtual machines, or a combination thereof), can cause the machines to perform the described operations.

[0019] As shown in Figure 1, the system 100 may comprise one or more servers 102, one or more networks 104, an input device 106, or a quantum computer 108, or a combination thereof. The server 102 may comprise an error mitigation component 110. The error mitigation component 110 may further comprise a gate component 114 or both. The server 102 may also comprise at least one memory 116, or be otherwise associated with at least one memory 116. The server 102 may further comprise a system bus 118 that can be coupled to various components, including, but not limited to, the error mitigation component 110 and associated components, memory 116, or a processor 120, or a combination thereof. Although the server 102 is shown in Figure 1, in other embodiments, various types of multiple devices may be associated with or comprise the features shown in Figure 1. Furthermore, the server 102 may communicate with one or more cloud computing environments.

[0020] One or more networks 104 may include, but are not limited to, wired and wireless networks, including cellular networks, wide area networks (WANs) (e.g., the Internet), or local area networks (LANs). For example, server 102 may communicate with one or more input devices 106 and / or quantum computer 108 (and vice versa) using substantially any desirable wired or wireless technology, including, but not limited to, cellular, WAN, Wireless Fidelity (WiFi®), Wi-Max, WLAN, or Bluetooth® technology, or a combination thereof. Furthermore, while the error mitigation component 110 may be located on one or more servers 102 in the shown embodiments, it should be understood that the architecture of system 100 is not limited in this way. For example, error mitigation component 110 or one or more components of error mitigation component 110 may reside on another computer device, such as another server device, or a client device, or a combination thereof.

[0021] One or more input devices 106 may include, but are not limited to, one or more computerized devices such as a personal computer, desktop computer, laptop computer, mobile phone (e.g., smartphone), computerized tablet (e.g., equipped with a processor), smartwatch, keyboard, touchscreen, or mouse, or a combination thereof. One or more input devices 106 may be employed to input one or more quantum circuits 122 or extension coefficient settings 124 or both to the system 100, thereby sharing the aforementioned data with the server 102 (e.g., via a direct connection, or via one or more networks 104, or both). For example, one or more input devices 106 may transmit data to a communication component 112 (e.g., via a direct connection, or via one or more networks 104, or both). Furthermore, one or more input devices 106 may include one or more displays that can present one or more outputs generated by the system 100 to the user. For example, one or more displays may include, but are not limited to, a cathode tube display (CRT), a light-emitting diode display (LED), an electroluminescent display (ELD), a plasma display panel (PDP), a liquid crystal display (LCD), or an organic light-emitting diode display (OLED), or a combination thereof.

[0022] In various embodiments, one or more input devices 106 or one or more networks 104 or both may be employed to input one or more settings or commands or both to the system 100. For example, in various embodiments described herein, one or more input devices 106 may be employed to operate or control the server 102 or related components or both, or to perform both. Furthermore, one or more input devices 106 may be employed to display one or more outputs (e.g., displays, data, or visualizations, or a combination thereof) generated by the server 102 or related components or both. Furthermore, in one or more embodiments, one or more input devices 106 may be contained within a cloud computing environment, or operably coupled to a cloud computing environment, or both.

[0023] For example, one or more input devices 106 may be used to input one or more quantum circuits 122 into system 100. In various embodiments, error mitigation components 110 may employ various quantum error mitigation techniques described herein to mitigate the amount of errors associated with computations resulting from the execution of one or more quantum circuits 122. For example, one or more quantum computers 108 may use one or more quantum circuits 122 to execute one or more quantum algorithms. One or more quantum circuits 122 can represent a computation routine of one or more quantum computers 108. For example, one or more quantum circuits 122 can represent one or more coherent quantum operations on quantum data. In various embodiments, one or more quantum circuits 122 can represent (delineate) the number of qubits or the connectivity of qubits or both employed by one or more quantum computers 108 to execute one or more quantum algorithms. For example, one or more quantum circuits 122 can represent, with respect to one or more qubits, initialization and reset operations (e.g., initialization of one or more qubits to one or more desired states), quantum gates (e.g., Hadamard gates, phase shifter gates, controlled gates, uncontrolled gates, phase rotation gates, controlled-not (CNOT) gates, single-qubit gates, multi-qubit gates, cross-resonance gates, or similar, or combinations thereof), measurement operations, or classically controlled quantum gates, or combinations thereof.

[0024] Furthermore, one or more input devices 106 may be employed to input one or more extension coefficient settings 124 to the system 100 (for example, here one or more extension coefficient settings 124 may be stored, for example, in one or more memories 116). In various embodiments, one or more quantum gates of one or more quantum circuits 122 may be driven according to one or more pulse schedules. The pulse schedule can represent a sequence of microwave pulses (for example, generated by one or more quantum computers 108) that can be parameterized, for example, by waveform, amplitude, or time, or a combination thereof. In various embodiments, one or more parameters of the microwave pulses driving the quantum gates may be changed by an increment defined by an extension coefficient value. For example, the extension coefficient value can define a gradual change to the waveform, amplitude, or time, or a combination thereof, of the driving microwave pulse. For example, the extension coefficient value can define the extension of the microwave pulse in time or amplitude, or both. In another example, the elongation coefficient value can define the scaling of pulse time, rise / fall time, latency, constant amplitude portion of the pulse, or similar, or a combination thereof. Thus, the elongation coefficient value can define the amount of change to one or more parameters of the microwave pulse driving the quantum gate. In various embodiments, one or more elongation coefficient settings 124 can define the range of elongation coefficient values ​​implemented by the error mitigation component 110. Furthermore, one or more elongation coefficient settings 124 can define the microwave pulse parameters that are modified by the elongation coefficient values. For example, the quantum circuit 122 can be executed in multiple iterations, each iteration using a different elongation coefficient value from the elongation coefficient settings 124. By changing the pulse schedule of the quantum gate in each iteration of execution, the quantum circuit 122 may be subjected to different amounts of noise associated with the same quantum computation in each execution.In one or more embodiments, the error mitigation component 110 may generate one or more extension factor settings 124, or the error mitigation component 110 may use one or more default extension factor settings 124 (stored in one or more memories 116), or both.

[0025] In various embodiments, one or more quantum computers 108 may include quantum hardware devices that can utilize the laws of quantum mechanics (e.g., superposition or quantum entanglement or both) to facilitate computation (e.g., while satisfying the DiVincenzo criterion). In one or more embodiments, one or more quantum computers 108 may include a quantum data plane, a control processor plane, a control and measurement plane, or qubit technology, or a combination thereof.

[0026] In one or more embodiments, the quantum data plane may include one or more quantum hardware components having physical qubits, structures for fixing the positions of the qubits, or support circuits, or a combination thereof. The support circuits can, for example, facilitate the measurement of the state of the qubits, or (for example, in the case of gate-based systems) perform gate operations on the qubits, or both. In some embodiments, the support circuits may include a wired network that can enable multiple qubits to exchange information with each other. Furthermore, the wired network can facilitate the transmission of control signals via direct electrical connections or electromagnetic radiation (e.g., optical signals, microwave signals, or low-frequency signals, or a combination thereof), or both. For example, the support circuits may include one or more superconducting resonators operably coupled to one or more qubits. As described herein, the term “superconducting” can characterize materials that exhibit superconducting properties below their superconducting critical temperature, such as aluminum (e.g., a superconducting critical temperature of 1.2 Kelvin) or niobium (e.g., a superconducting critical temperature of 9.3 Kelvin). Furthermore, those skilled in the art will recognize that other superconducting materials (e.g., hydride superconductors such as lithium hydride / magnesium hydride alloys) may be used in the various embodiments described herein.

[0027] In one or more embodiments, the control processor plane can identify, trigger, or perform a Hamiltonian sequence of quantum gate operations or measurements, or both, which execute a program (provided by a host processor, such as server 102, via error mitigation component 110) to implement a quantum algorithm (defined, for example, by one or more quantum circuits 122). For example, the control processor plane can translate compiled code into commands for the control and measurement planes. In one or more embodiments, the control processor plane can further execute one or more quantum error correction algorithms.

[0028] In one or more embodiments, the control and measurement plane can convert digital signals generated by the control processor plane, which can define the quantum operations to be performed, into analog control signals for performing operations on one or more qubits in the quantum data plane. The control and measurement plane can also convert one or more analog measurement outputs of qubits in the data plane into classical binary data that can be shared with other components of the system 100 (for example, via the control processor plane, such as an error mitigation component 110).

[0029] Those skilled in the art will recognize that various qubit technologies can provide the basis for one or more qubits in one or more quantum computers. Furthermore, the control and measurement plane may include a laser source or microwave source directed at one or more of the ions to influence the quantum state of the ions, a laser for cooling the ions, or enabling measurement of the ions, or both, or one or more photon detectors for measuring the state of the ions, or a combination thereof. In another example, a superconducting qubit (e.g., a superconducting quantum interference device (SQUID)) can be a lithographically defined electronic circuit that can be cooled to a millikelvin temperature to exhibit a quantized energy level (e.g., resulting from the quantized state of an electron charge or magnetic flux). Superconducting qubits can be based on Josephson junctions, such as transmon qubits. Superconducting qubits can also be adapted to microwave-controlled electronic equipment and may be used in conjunction with gate-based technologies or integrated cryogenic control. Further exemplary qubit technologies may include, but are not limited to, photon qubits, quantum dot qubits, gate-based neutral atom qubits, semiconductor qubits (e.g., optically or electrically gated), or topological qubits, or combinations thereof.

[0030] In one or more embodiments, the communication component 112 can receive one or more quantum circuits 122 from one or more input devices 106 (for example, via a direct electrical connection, or via one or more networks 104, or both) and share the data with various related components of the error mitigation component 110. Furthermore, the communication component 112 can facilitate the sharing of data between the error mitigation component 110 and one or more quantum computers 108, or vice versa, or both (for example, via a direct electrical connection, or via one or more networks 104, or both).

[0031] In various embodiments, the gate component 114 can analyze one or more quantum circuits 122 and identify the native multi-qubit quantum gates of the quantum circuits 122. For example, the gate component 114 can identify each multi-qubit quantum gate contained in one or more quantum circuits 122, such as a two-qubit quantum gate. In one or more embodiments, the gate component 114 can identify the type, location, or sequence, or combination thereof of multi-qubit quantum gates. For example, one or more multi-qubit quantum gates may be represented within one or more quantum circuits 122 by one or more standardized representations, such as lines connecting each qubit operation. The gate component 114 can scan one or more quantum circuits 122 and relate the multi-qubit quantum gates by relating the standardized representations to each other.

[0032] Figure 2A shows an exemplary non-restrictive quantum circuit 122a that may be input to the system 100 via one or more input devices 106, analyzed by an error mitigation component 110, or executed by one or more quantum computers 108, or a combination thereof. For brevity, repetition of descriptions of similar elements employed in other embodiments described herein is omitted. As shown in Figure 2A, the exemplary quantum circuit 122a represents a quantum operation with respect to a first qubit q0 and a second qubit q1. Furthermore, the exemplary quantum circuit 122a includes two CNOT quantum gates 202. The CNOT gates 202 of the exemplary quantum circuit 122a are constructed from cross-resonance gates (e.g., Hadamard gates or Pauli gates or both) between the first qubit q0 and the second qubit q1. In various embodiments, the gate component 114 can analyze the exemplary quantum circuit 122a and identify each of the two CNOT quantum gates 202 as a multi-qubit gate (e.g., a 2-qubit gate) contained within the exemplary quantum circuit 122a.

[0033] In various embodiments, the gate component 114 can further query the calibration component 126 with respect to the calibrated parameters associated with each of the identified multi-qubit quantum gates. For example, each multi-qubit quantum gate contained within one or more quantum circuits 122 may be implemented by quantum gate hardware contained within one or more quantum computers 108. The calibration component 126 can calibrate the hardware to reduce systematic errors within one or more quantum computers 108. When running the quantum circuit 122 containing one or more multi-qubit gates (e.g., 2-qubit gates), the realized results may differ from the intended effect due to one or more errors such as drift or crosstalk. The calibration component 126 can determine the calibrated pulse schedule for each of the identified multi-qubit gates using one or more calibration techniques (e.g., Floquet calibration or XEB calibration or both).

[0034] Furthermore, the gate component 114 can modify one or more quantum circuits 122 based on identified multi-qubit quantum gates. In various embodiments, the gate component 114 can insert a set of quantum gates into one or more quantum circuits 122 for each identified multi-qubit quantum gate. The set of quantum gates may include pairs of inverted quantum gates that constitute an identity gate. For example, the set of quantum gates may include a first quantum gate and a second quantum gate, where the second quantum gate is the inverted version of the first quantum gate. If the set of quantum gates operates ideally (e.g., without error), the computational results realized by the new quantum circuit 122 can be the same as those of the original quantum circuit 122 due to the identity nature of the inserted set of quantum gates.

[0035] Figure 2B shows an exemplary modified non-restrictive quantum circuit 122b that may include one or more sets of inserted quantum gates added by gate component 114 according to one or more embodiments described herein. Repetition of descriptions of similar elements employed in other embodiments described herein is omitted for brevity. The modified quantum circuit 122b shown in Figure 2B is based on the exemplary quantum circuit 122a shown in Figure 2A. For each of the multi-qubit quantum gates (e.g., two CNOT gates 202) included in the exemplary quantum circuit 122a, gate component 114 may insert an additional set of quantum gates (e.g., a first quantum gate and its inverted form).

[0036] In one or more embodiments, the type of quantum gate inserted into the quantum circuit 122 may be based on the physical mechanism that gives rise to the native multi-qubit quantum gates of the quantum circuit 122. Furthermore, the physical mechanism or hardware architecture or both of the multi-qubit quantum gates contained within one or more quantum computers 108 may be defined by the calibration component 126 as part of calibration information shared with the error mitigation component 110 (e.g., via one or more networks 104). For example, in the exemplary quantum circuit 122a, the two identified multi-qubit quantum gates are CNOT gates based on RZX rotation established by cross-resonance. Thus, for each CNOT gate 202, the gate component 114 is R ZX A set of gates 204 can be inserted, thereby allowing the gate component 114 to insert a set of quantum gates corresponding to the physical mechanism underlying native multi-qubit gates. For example, as shown in Figure 2B, the gate component 114 can insert R for each CNOT gate 202. ZX By inserting the set of gates 204, the modified quantum circuit 122b can be generated. Each R ZX Gate set 204 is R ZX(θ) gate and subsequent inversion R ZX (-θ) may be included. As shown in FIG. 2B, a set of quantum gates (e.g., the set of R ZX gates 204) can be inserted into the quantum circuit 122 (e.g., the exemplary quantum circuit 122a) at the next position of the associated native multi-qubit quantum gate (e.g., the CNOT gate 202). In another example, one or more of the identified multi-qubit quantum gates can be implemented as a swap-type gate, such as an adjustable coupler gate within one or more quantum computers 108, and the gate component 114 can insert a set of one or more quantum gates corresponding to a scalable version of the swap-type gate (e.g., a scalable version of the adjustable coupler gate). In one or more embodiments where the quantum gate is characterized as exp(-iθG / 2), the gate component 114 can insert an inversion of the quantum gate by adopting -θ. θ can be a rotation angle, "G" can be a generator (e.g., "G" can be a Hermitian operator), and "i" can be the square root of "-1". For example, the Rzx gate can include the generator ZX, assuming Z and X are Pauli operators. Thereby, in one or more examples, the gate component 114 identifies the generator G from the native multi-qubit gate and inserts a set of quantum gates characterized by R G (θ) and R G (-θ). For example, the CNOT gate 202 can include a generator G equal to ZX, and the gate component 114 can insert a set of R ZX (θ) and R ZX (-θ) characterized R ZX gates 204. In another example, the adjustable coupler gate can include a generator G equal to XX + YY, and the gate component 114 can include R XX+YY (θ) and R XX+YYA set of quantum gates characterized by (-θ) can be inserted.

[0037] In one or more embodiments, the gate component 114 can refer to the gate insertion table 128 to determine the type of set of quantum gates to be inserted into one or more quantum circuits 122. For example, the gate insertion table 128 may include, along with the type of insertable gates, the type of native quantum gates or hardware architecture, or both (e.g., cross-resonance gates, tunable coupler gates, or similar, or a combination thereof). For example, the gate insertion table 128 may include, for example, R ZX As a type of insertable gate associated with cross-resonance-based hardware, R is a gate that can be used to create CNOT gates. ZX It may include gates. As shown in Figure 1, the gate insertion table 128 may be stored, for example, in one or more memories 116.

[0038] Figure 3 shows an exemplary non-limiting error mitigation component 110 further comprising a scaling component 302 according to one or more embodiments described herein. For brevity, repetition of descriptions of similar elements employed in other embodiments described herein has been omitted. In various embodiments, the scaling component 302 can generate a scaled pulse schedule for a set of inserted quantum gates based on identified and native multi-qubit quantum gate calibration information and extension coefficient settings 124. In one or more embodiments, the pulse schedule can scale the rotation angles of the set of inserted quantum gates to realize a scaled set of quantum gates that achieve a target extension coefficient value.

[0039] In various embodiments, one or more sets of inserted quantum gates can be scaled by the error mitigation component 110 to achieve an elongation coefficient value defined by one or more elongation coefficient settings 124. For example, the target elongation coefficient value of a set of inserted quantum gates may be a function of the rotation angle of the set of inserted quantum gates. For example, as the rotation angle of the set of inserted quantum gates changes, the elongation coefficient value associated with a particular execution of the modified quantum circuit 122 may also change. In one or more embodiments, the scaling component 302 can set the elongation coefficient values ​​that occur for one or more sets of inserted quantum gates by defining the rotation angle of one or more sets of inserted quantum gates. For example, one or more elongation coefficient settings 124 can define multiple elongation coefficient values, or a range of elongation coefficient values, or both, that are executed using one or more quantum circuits 122 over multiple execution iterations. The scaling component 302 can determine the rotation angles of one or more sets of inserted quantum gates for each target elongation coefficient value, based on the relationship between defined elongation coefficient values ​​and rotation angles (which may be defined, for example, by one or more formulas, charts, tables, or graphs, or combinations thereof, stored in one or more scaling reference databases 304 as described below).

[0040] For example, Equation 1 shown below is based on the identification of the CNOT gate 202 in the quantum circuit 122 (as illustrated in Figures 2A and 2B, for example), and the R inserted into the quantum circuit 122. ZX The relationship between the extension coefficient value and the rotation angle of gate set 204 can be characterized.

[0041]

number

[0042] In various embodiments, the relationship between the gate rotation angle and the elongation coefficient value for various types of quantum gates may be defined in one or more scaling reference databases 304. For example, one or more scaling reference databases 304 may include a plurality of types of quantum gates that can be inserted into one or more quantum circuits 122 by the gate component 114. In relation to each type of quantum gate, one or more scaling reference databases 304 may include formulas, graphs, tables, or similar, or a combination thereof, that characterize the mathematical relationship between the elongation coefficient value occurring for a particular quantum gate and the rotation angle of a particular quantum gate. In one or more embodiments, data may be added to one or more scaling reference databases 304 via one or more input devices 106. Also, one or more scaling reference databases 304 may be stored in one or more memories 116.

[0043] Figure 4 shows an exemplary non-limiting graph 400 that can illustrate the relationship between the extension coefficient value characterized by Equation 1 and the rotation angle according to one or more embodiments described herein. For brevity, repetition of descriptions of similar elements employed in other embodiments described herein has been omitted. In various embodiments, graph 400 is shown with R inserted for one or more target extension coefficient values. ZX To determine the rotation angles of the gate set 204, they can be included in one or more scaling reference databases 304, or referenced by scaling components 302, or both.

[0044] As shown in Figure 4, in various embodiments, the range of possible extension coefficients that can be implemented with the inserted quantum gate set may be limited by one or more properties of the relevant native multi-qubit quantum gate. For example, the exemplary R characterized by Graph 400 ZX The set of gates 204 can achieve a minimum elongation coefficient value of 1.8. In various embodiments, the minimum or maximum elongation coefficient value that can be achieved with respect to the inserted set of quantum gates can be based on the parameters of the native multi-qubit quantum gates of the initial quantum circuit 122 (e.g., included in the calibration information determined by the calibration component 126). For example, in the echo-crossed resonance gate, the minimum elongation coefficient value achievable without pulse calibration can be determined by the rising or falling edges of single-qubit and two-qubit pulses. The maximum elongation coefficient value can be set based on the capabilities of one or more quantum computers 108 hardware, including but not limited to control electronic memory, coherence time, imposed constraints (e.g., total schedule duration), or similar, or a combination thereof.

[0045] In various embodiments, the scaling component 302 can define a set of target elongation coefficient values ​​that can be within a minimum threshold, a maximum threshold, or both, of a set of one or more inserted quantum gates, and within or within a range of elongation coefficient values ​​defined by one or more elongation coefficient settings 124. Furthermore, the scaling component 302 can determine the rotation angle of the quantum gate associated with each target elongation coefficient in the set of target elongation coefficients.

[0046] In one or more embodiments, the scaling component 302 can further generate a set of pulse schedules to implement each of the determined quantum gate rotation angles. The set of pulse schedules may include a scaled pulse schedule from the calibrated pulse schedule of the native multi-qubit quantum gates of the initial quantum circuit 122 (e.g., exemplary quantum circuit 122a) to realize a specific rotation angle of the associated set of inserted quantum gates of the tuned quantum circuit 122 (e.g., modified quantum circuit 122b). In various embodiments, the scaling component 302 can generate a scaled pulse schedule of the associated set of inserted quantum gates by using one or more scaling techniques on the calibrated pulse schedule of the native multi-qubit quantum gates. Exemplary scaling techniques that may be used by the scaling component 302 to generate a scaled pulse schedule may include, but are not limited to, using a single cross-resonance pulse, using a rotation term, using a pulse echo, scaling the flat top of a rectangular pulse including a Gaussian rise or fall, scaling an adjustable coupler pulse that generates an interchangeable gate or a controlled phase gate or both, or similar, or a combination thereof.

[0047] In one or more embodiments, the scaling component 302 can implement one or more scaling techniques to modify one or more parameters of the calibrated pulse schedule of a native multi-qubit quantum gate. For example, one or more scaling techniques can modify the amplitude, cycle time, or both of the calibrated pulse schedule. Thereafter, the scaled pulse schedule generated by the scaling component 302 can result in an alternative execution duration for one or more quantum circuits 122.

[0048] Figure 5 shows an exemplary and non-limiting scaled pulse schedule that can be generated by the scaling component 302, implemented using one or more inserted quantum gates according to one or more embodiments described herein. For brevity, repetition of descriptions of similar elements employed in other embodiments described herein is omitted. Figure 5 shows one or more inserted R gates of the modified quantum circuit 122b to realize one or more of the extension coefficients and / or rotation angles characterized by Graph 400. ZX Three exemplary scaled pulse schedules that can be generated by the scaling component 302, performed on the set of gates 204, are shown. Each of the exemplary scaled pulse schedules can be performed across both quantum gates in the set of quantum gates (e.g., the first inserted quantum gate and its inversion).

[0049] As shown in Figure 5, a first exemplary scaled pulse schedule 502 can be generated by the scaling component 302 by adjusting one or more parameters, such as the width of the cross-resonance pulse. A second exemplary scaled pulse schedule 504 can be generated by the scaling component 302 by adding one or more pulse echoes to a calibrated pulse schedule. A third exemplary scaled pulse schedule 506 can be generated by the scaling component 302 by modifying the waveform of a calibrated pulse schedule using a rotation term. In various embodiments, one or more sets of inserted quantum gates can be implemented according to scaled pulse schedules generated by multiple scaling techniques. For example, the scaling component 302 can implement at least one or a combination thereof of the first exemplary scaled pulse schedule 502, the second exemplary scaled pulse schedule 504, and the third scaled pulse schedule 506. For example, the scaling component 302 can generate a scaled pulse schedule by adjusting the waveform of a calibrated pulse schedule and introducing one or more echo pulses. In another example, the scaling component 302 can adjust the waveform of a calibrated pulse schedule and use one or more rotation terms to generate a scaled pulse schedule. In yet another example, the scaling component can introduce one or more echo pulses or rotation terms, or both, into a calibrated pulse schedule to generate one or more scaled pulse schedules.

[0050] Figure 6 shows an exemplary non-limiting error mitigation component 110 further comprising an execution component 602 according to one or more embodiments described herein. For brevity, repetition of descriptions of similar elements employed in other embodiments described herein has been omitted. In various embodiments, the execution component 602 can execute one or more tuned quantum circuits 122 (for example, tuned to include one or more sets of inserted quantum gates) multiple times in each iteration, using each scaled pulse schedule generated by the scaling component 302.

[0051] In one or more embodiments, the execution component 602 can execute a tuned quantum circuit 122 (e.g., including a set of one or more inserted quantum gates) multiple times on one or more quantum computers 108, and each iteration of the execution may be associated with a target elongation coefficient value. Each target elongation coefficient value may also be associated with a rotation angle (e.g., determined by the scaling component 302) of the set of one or more inserted quantum gates. Furthermore, each rotation angle may be implemented by each scaled pulse schedule generated by the scaling component 302, which can be scaled based on a calibrated pulse schedule (e.g., determined by the calibration component 126) of one or more native multi-qubit quantum gates identified by the gate component 114.

[0052] For example, the execution component 602 can perform a first execution of a tuned quantum circuit 122 (including, for example, a set of one or more inserted quantum gates) on one or more quantum computers 108. During the first execution, one or more quantum computers 108 can drive one or more inserted quantum gates according to a first scaled pulse schedule to realize a first expansion coefficient value (for example, based on an expansion coefficient setting 124, from a set of expansion coefficient values ​​set, for example, by the scaling component 302). Furthermore, the execution component 602 can perform a second execution of the same tuned quantum circuit 122 (including, for example, a set of one or more inserted quantum gates) on one or more quantum computers 108. During the second execution, one or more quantum computers 108 can drive one or more inserted quantum gates according to a second scaled pulse schedule to realize a second expansion coefficient value (or, for example, establish a second gate rotation angle different from the gate rotation angle established during the first execution, or both). Similarly, the execution component 602 can perform any number of additional executions of the same tuned quantum circuit 122, each execution performing a different scaled pulse schedule.

[0053] In each execution of the tuned quantum circuit 122, the execution component 602 can collect the computation results output by one or more quantum computers 108. Because each execution is associated with a different extension coefficient value, the computation results of each execution can vary due to the inclusion of different amounts of noise. Furthermore, the execution component 602 can generate a results database 604 associated with one or more tuned quantum circuits 122. For example, the results database 604 may include the computation results from each execution along with the target extension coefficient value associated with each execution of one or more tuned quantum circuits 122. For example, one or more results databases 604 may be stored in one or more memories 116.

[0054] Figure 7 shows an exemplary non-limiting error mitigation component 110 further comprising an extrapolation component 702 according to one or more embodiments described herein. For brevity, repetition of descriptions of similar elements employed in other embodiments described herein has been omitted. In various embodiments, the extrapolation component 702 can determine near-zero noise computations associated with one or more specific quantum circuits 122 using one or more extrapolation techniques with respect to one or more result databases 604. Exemplary extrapolation techniques that may be used by the extrapolation component 702 may be Richardson extrapolation or other extrapolation methods. For example, the extrapolation component 702 can use a Richardson extrapolation algorithm to extrapolate computation results contained in one or more result databases 604 to the zero-noise limit.

[0055] Figure 8 shows an exemplary non-limiting graph 800 that can demonstrate the improved resolution achievable by System 100 compared to standard error mitigation techniques according to one or more embodiments described herein. For brevity, repetition of descriptions of similar elements employed in other embodiments described herein is omitted. Graph 800 can evaluate one or more quantum circuits 122 (e.g., exemplary quantum circuit 122a) used to calculate the ground state energy of a hydrogen molecule. Square symbols can represent the exact value of the ground state energy. Black circles can represent each execution of exemplary quantum circuit 122a using various scaled pulse schedules according to the various embodiments described herein. As shown in graph 800, each scaled pulse schedule can be associated with different extension coefficient values, resulting in different calculation results. Black triangles can represent executions of exemplary quantum circuit 122a using digital-based Richardson extrapolation techniques. Furthermore, white circles represent extrapolated results determined from executions of scaled pulse schedules using the Richardson extrapolation algorithm. Additionally, the white triangles represent extrapolated results determined from a digital-based Richardson implementation using the Richardson extrapolation algorithm.

[0056] A comparison of the scaling pulse scheduling implementation with that of the digital-based Richardson extrapolation demonstrates that the various embodiments described herein can achieve a greater number of extension coefficient values. Furthermore, these greater number of extension coefficient values ​​can be densely distributed within a finer range (e.g., from the minimum extension coefficient value implemented to the maximum extension coefficient value implemented). In contrast, the implementation of standard extension coefficient values ​​is limited to a wider range of fewer usable extension coefficient values. Moreover, the improved resolution of the set of implemented target extension coefficient values ​​has enabled extrapolation of more accurate ground-state energy calculations.

[0057] Figure 9 shows a flowchart of an exemplary non-limiting computer implementation method 900 that may be implemented by System 100 to perform quantum error mitigation according to one or more embodiments described herein. For the sake of brevity, repetition of descriptions of similar elements employed in other embodiments described herein has been omitted.

[0058] In 902, the computer implementation method 900 may include receiving one or more quantum circuits 122 (for example, via a communication component 112) by a system 100 operably coupled to a processor 120. In various embodiments, one or more quantum circuits 122 may be input to the system 100 via one or more input devices 106. Also, one or more quantum circuits 122 may represent one or more quantum operations or quantum gates, or both, for the execution of one or more quantum algorithms on one or more quantum computers 108.

[0059] In 904, the computer implementation method 900 may include the system 100 determining a set of target elongation coefficient values ​​(for example, by a scaling component 302). In various embodiments, the elongation coefficient values ​​may define changes to the pulse schedule that drives one or more multi-qubit quantum gates during the execution of one or more quantum circuits 122. In one or more embodiments, one or more input devices 106 may be employed to input the elongation coefficient setting 124 to the system 100, where the elongation coefficient setting 124 may include a plurality of elongation coefficient values ​​or a range of elongation coefficient values ​​or both, targeting implementation in one or more error mitigation techniques.

[0060] In 906, the computer implementation method 900 may include, by system 100, identifying one or more multi-qubit quantum gates contained within one or more quantum circuits 122 (for example, by gate component 114). For example, one or more multi-qubit quantum gates may be 2-qubit quantum gates. Examples of types of multi-qubit quantum gates may include, but are not limited to, cross-resonance gates (e.g., CNOT gates), Pauli gates, entangled gates, exchange-like gates, controlled-phase gates, multi-control phase gates, or similar, or combinations thereof. In 908, the computer implementation method 900 may include, by system 100, retrieving calibrated pulse schedules for one or more identified multi-qubit quantum gates (for example, by calibration component 126). For example, one or more quantum computers 108 may calibrate quantum hardware associated with multi-qubit quantum gates defined by one or more quantum circuits 122 and return calibration data to error mitigation component 110. In 910, the computer implementation method 900 may include, by system 100, inserting a set of quantum gates into one or more quantum circuits 122 for each identified multi-qubit quantum gate native to the quantum circuit (e.g., by gate component 114). In various embodiments, each inserted set of quantum gates may include a first quantum gate and a second quantum gate which is the inversion of the first quantum gate, such that the set of quantum gates can constitute the identity of the original quantum circuit 122.

[0061] In 912, the computer implementation method 900 may include determining the rotation angle of the inserted quantum gates based on the elongation coefficients from a set of target elongation coefficients (e.g., by the scaling component 302) by the system 100. For example, according to one or more embodiments described herein, the relationship between one or more elongation coefficient values ​​of the inserted quantum gates and the rotation angle may be defined by one or more formulas, charts, tables, or similar, or a combination thereof, contained in one or more gate insertion tables 128. For example, determining in 910 may use a graph such as graph 400 that can characterize how the elongation coefficient values ​​realized by the inserted quantum gates can be based on the gate rotation angle.

[0062] In 914, the computer implementation method 900 may include generating a scaled pulse schedule for a set of inserted quantum gates based on a rotated or calibrated pulse schedule, or both, by the system 100 (e.g., by a scaling component 302). In various embodiments, generating in 914 can generate a scaled pulse schedule that can be performed on a set of inserted quantum gates using one or more scaling techniques. For example, a scaled pulse schedule can be generated by modifying the waveform of a calibrated pulse schedule, introducing one or more pulse echoes, or using one or more rotation terms, or a combination thereof. In one or more embodiments, scaling a pulse schedule can, for example, modify the cycle duration associated with executing one or more quantum circuits 122.

[0063] In 916, the computer implementation method 900 may include, by system 100, executing one or more tuned quantum circuits 122 (e.g., including a set of one or more inserted quantum gates) on one or more quantum computers 108 using scaled pulse schedules (e.g., by execution component 602). In 918, the computer implementation method 900 may evaluate whether there are additional target elongation coefficient values ​​to be implemented. If there are additional target elongation coefficient values ​​to be implemented, the computer implementation method 900 may then repeat steps 912-916. For example, the computer implementation method 900 may include determining a gate rotation angle, generating a scaled pulse schedule, and executing the tuned quantum circuit 122 with respect to each target elongation coefficient value in the set of target elongation coefficient values. Thereafter, the computer implementation method 900 may execute the tuned quantum circuit 122 over multiple iterations, each iteration realizing different elongation coefficient values ​​by various scaled pulse schedules.

[0064] If there are no additional target extension coefficient values ​​to be implemented, the computer implementation method 900 may proceed to 920. In 920, the computer implementation method 900 may include collecting computational results associated with each execution of one or more tuned quantum circuits by the system 100 (e.g., by the execution component 602). In 922, the computer implementation method 900 may include extrapolating computational results from one or more quantum computers 108 (e.g., by the extrapolation component 702) by the system 100 to determine error-reduced results. For example, the Richardson extrapolation algorithm may be used to extrapolate zero-noise results from multiple executions of one or more tuned quantum circuits 122.

[0065] While this disclosure includes a detailed description of cloud computing, it should be understood that implementations of the concepts described herein are not limited to cloud computing environments. Embodiments of the present invention can be implemented in combination with any other type of computing environment that is currently known or may be developed in the future.

[0066] Cloud computing is a service delivery model that enables convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services), allowing these resources to be provisioned and released quickly with minimal administrative effort or interaction with service providers. This cloud model may include at least five features, at least three service models, and at least four deployment models.

[0067] The features are as follows:

[0068] On-demand self-service: Cloud users can unilaterally and automatically provision computing power, such as server time and network storage, as needed, without requiring human interaction with service providers.

[0069] Broad network access: The capabilities of the cloud are available over a network and can be accessed using standard mechanisms, thus facilitating use by heterogeneous thin-client or thick-client platforms (e.g., mobile phones, laptops, and PDAs).

[0070] Resource Pool: A provider's computing resources are pooled and delivered to multiple users using a multi-tenant model. Various physical and virtual resources are dynamically allocated and reallocated as needed. There is a sense of location independence, and users typically have neither control nor know the exact location of the resources provided, although at a higher level of abstraction, they may be able to specify a location (e.g., country, state, or data center).

[0071] Rapid Adaptability: Cloud capabilities can be provisioned quickly and flexibly, sometimes automatically, scale out rapidly, and be released quickly to scale in rapidly. The capacity available for provisioning often appears to the user as if they can purchase any amount at any time without limit.

[0072] Measured Services: Cloud systems leverage metering capabilities to automatically control and optimize resource usage at an appropriate level of abstraction for each type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both service providers and users.

[0073] The service model is as follows:

[0074] SaaS (Software as a Service): The capability provided to the user is the use of the provider's applications running on cloud infrastructure. These applications can be accessed from various client devices via thin client interfaces such as web browsers (e.g., web-based email). Users do not manage or control the underlying cloud infrastructure, including the network, servers, operating system, storage, or individual application functions, except for the possibility of making limited user-specific application configuration settings.

[0075] PaaS (Platform as a Service): The ability provided to the user is to deploy applications created or acquired by the user, using programming languages ​​and tools supported by the provider, onto a cloud infrastructure. The user does not manage or control the underlying cloud infrastructure, including the network, servers, operating system, or storage, but can control the configuration of the deployed application and, in some cases, the application hosting environment.

[0076] IaaS (Infrastructure as a Service): The capabilities provided to users include provisioning of processing, storage, networking, and other basic computing resources, allowing users to deploy and run any software, including operating systems and applications. Users do not manage or control the underlying cloud infrastructure, but they can control the operating system, storage, and deployed applications, and in some cases, have limited control over selected network components (e.g., host firewalls).

[0077] The deployment model is as follows:

[0078] Private Cloud: This cloud infrastructure is operated solely for the organization. It can be managed by this organization or a third party and can reside on-premises or off-premises.

[0079] Community Cloud: This cloud infrastructure is shared by multiple organizations and supports specific communities that share common interests (e.g., missions, security requirements, policies, and compliance considerations). It can be managed by these organizations or third parties and can reside on-premises or off-premises.

[0080] Public Cloud: This cloud infrastructure is available for use by general users or large industry groups and is owned by the organization that sells the cloud service.

[0081] Hybrid Cloud: This cloud infrastructure is a combination of two or more clouds (private, community, or public) that are joined together while retaining their own distinct entities, through standardized or proprietary technologies that enable the portability of data and applications (e.g., cloud bursting to adjust load balancing between clouds).

[0082] Cloud computing environments are service-oriented environments that emphasize statelessness, loose coupling, modularity, and semantic interoperability. At the heart of cloud computing is the infrastructure, which includes a network of interconnected nodes.

[0083] Referring now to Figure 10, an exemplary cloud computing environment 1000 is shown. As illustrated, the cloud computing environment 1000 includes one or more cloud computing nodes 1002 that can communicate with local computing devices used by cloud users (e.g., a personal digital assistant (PDA) or mobile phone 1004, a desktop computer 1006, a laptop computer 1008, or an automotive computer system 1010, or a combination thereof). The nodes 1002 may communicate with each other. The nodes 1002 may be physically or virtually grouped within one or more networks into private clouds, community clouds, public clouds, or hybrid clouds, or a combination thereof, as described herein. This allows the cloud computing environment 1000 to provide an infrastructure, platform, or SaaS, or a combination thereof, that does not require cloud users to maintain resources on their local computing devices. The types of computing devices 1004-1010 shown in Figure 10 are intended for illustrative purposes only, and it is understood that computing node 1002 and cloud computing environment 1000 can communicate with any type of computer-controlled device via any type of network or network-addressable connection (e.g., a connection using a web browser) or both.

[0084] Referring here to Figure 11, a set of functional abstraction layers provided by the cloud computing environment 1000 (Figure 10) is shown. Repeated descriptions of similar elements used in other embodiments described herein are omitted for brevity. It should be understood in advance that the components, layers, and functions shown in Figure 11 are for illustrative purposes only and that embodiments of the present invention are not limited thereto. The following layers and corresponding functions are provided as illustrated:

[0085] The hardware and software layer 1102 includes hardware components and software components. Examples of hardware components include the mainframe 1104, RISC (Reduced Instruction Set Computer) architecture-based servers 1106, 1108, blade server 1110, storage device 1112, and network and network components 1114. In some embodiments, the software components include network application server software 1116 and database software 1118.

[0086] The virtualization layer 1120 includes an abstraction layer that can provide virtual entities such as virtual servers 1122, virtual storage 1124, virtual networks 1126 including virtual private networks, virtual applications and operating systems 1128, and virtual clients 1130.

[0087] For example, the management layer 1132 can provide the following functions: Resource provisioning 1134 dynamically procures computing and other resources used to perform tasks within the cloud computing environment. Measurement and pricing 1136 tracks the costs incurred when resources are used within the cloud computing environment and generates and sends invoices for the use of those resources. For example, those resources may include application software licenses. Security verifies the identities of cloud users and tasks and protects data and other resources. The user portal 1138 provides users and system administrators with access to the cloud computing environment. Service level management 1140 allocates and manages cloud computing resources to meet required service levels. Service Level Agreement (SLA) planning and execution 1142 prepares and procures cloud computing resources in advance of anticipated future demands in accordance with SLAs.

[0088] Workload layer 1144 shows examples of functions available in a cloud computing environment. Examples of workloads and functions that may be provided from this layer include mapping and navigation 1146, software development and lifecycle management 1148, virtual classroom education delivery 1150, data analysis processing 1152, transaction processing 1154, and quantum computing 1156. Various embodiments of the present invention can perform one or more quantum error mitigation techniques on one or more quantum circuits using a cloud computing environment described with reference to Figures 10 and 11, according to one or more embodiments described herein.

[0089] The present invention may be a system, method, or computer program product, or a combination thereof, at any possible level of technical detail of integration. The computer program product may include a computer-readable storage medium containing computer-readable program instructions for causing a processor to perform aspects of the present invention. The computer-readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device. The computer-readable storage medium may be, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exclusive list of further specific examples of computer-readable storage media includes portable floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM) or flash memory, static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or raised structures in grooves on which instructions are recorded, and any appropriate combination thereof. When used herein, computer-readable storage media should not be construed as themselves being radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmitting media (e.g., light pulses passing through fiber optic cables), or transient signals such as electrical signals transmitted through wires.

[0090] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing device / processing device, or to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof). This network may include copper transmission cables, optical transmission fibers, wireless transmitters, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface within each computing device / processing device receives computer-readable program instructions from the network and transfers those computer-readable program instructions for storage on a computer-readable storage medium within each computing device / processing device.

[0091] The computer-readable program instructions for performing the operation of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuits, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk® and C++, and procedural programming languages ​​such as the C programming language or similar programming languages. The computer-readable program instructions may be executed as a whole on the user's computer, partially as a standalone software package on the user's computer, partially on the user's computer and on a remote computer, respectively, or as a whole on a remote computer or on a server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (for example, via the Internet using an Internet Service Provider). In some embodiments, to carry out aspects of the present invention, an electronic circuit including, for example, a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer-readable program instructions to customize the electronic circuit by utilizing state information of computer-readable program instructions.

[0092] Aspects of the present invention will be described herein by reference to flowcharts or block diagrams, or both, of methods, apparatuses (systems), and computer program products, according to embodiments of the present invention. It will be understood that each block in a flowchart or block diagram, or both, and any combination of blocks contained in a flowchart or block diagram, or both, can be implemented by computer-readable program instructions.

[0093] These computer-readable program instructions may be provided to a general-purpose computer, a dedicated computer, or a processor of another programmable data processing device to create a machine, so that instructions executed via the processor of a computer or other programmable data processing device can create means to perform functions / operations specified in a flowchart or block diagram or both blocks. These computer-readable program instructions may be stored on a computer-readable storage medium in a particular manner, such as a product containing instructions that perform modes of functions / operations specified in a flowchart or block diagram or both blocks, and can instruct a computer, a programmable data processing device, or other device, or a combination thereof, to function.

[0094] Computer-readable program instructions may be read into a computer, other programmable data processing device, or other device so that instructions executed on a computer, other programmable device, or other device perform functions / operations specified in a flowchart or block diagram, or both, thereby causing a series of operable steps to be executed on a computer, other programmable device, or other device that generates a computer implementation process.

[0095] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a defined logical function. In some alternative implementations, the functions shown in the blocks may occur in an order different from the order shown in the figures. For example, two consecutively shown blocks may actually be executed substantially simultaneously, or possibly in reverse order, depending on the functions they contain. Note also that each block in the block diagram or flowchart diagram, or both, and any combination of blocks contained in the block diagram or flowchart diagram, or both, may be implemented by a dedicated hardware-based system that performs a defined function or operation, or a combination of dedicated hardware and computer instructions.

[0096] To provide further background to the various embodiments described herein, Figure 12 and the following description are intended to outline a suitable computing environment 1200 in which the various embodiments described herein may be implemented. While the embodiments have been described above in the general context of computer executable instructions that can be run on one or more computers, those skilled in the art will recognize that the embodiments may also be implemented in combination with other program modules, or as a combination of hardware and software, or both.

[0097] Typically, a program module includes routines, programs, components, data structures, etc., that perform a specific task or implement a specific abstract data type. Furthermore, those skilled in the art will understand that the methods of the present invention can be practiced using other computer system configurations, including single-processor or multi-processor computer systems, minicomputers, mainframe computers, Internet of Things (IoT) devices, distributed computing systems, as well as personal computers, handheld computing devices, microprocessor-based consumer electronics, or programmable consumer electronics, each of which can be operably coupled to one or more associated devices.

[0098] The embodiments described herein can also be practiced in a distributed computing environment in which specific tasks are performed by remote processing devices linked via a communication network. In a distributed computing environment, program modules may reside in both local and remote memory storage devices. For example, in one or more embodiments, a computer executable component may include or consist of one or more distributed memory units and be executed from memory. As used herein, the terms “memory” and “memory unit” are interchangeable. Furthermore, in one or more embodiments described herein, the code of a computer executable component may be executed in a distributed manner, for example, by multiple processors coupled or working in coordination to execute code from one or more distributed memory units. As used herein, the term “memory” may include a single memory or memory unit in one location, or multiple memories or memory units in one or more locations.

[0099] Computing devices typically include a variety of media, which may include computer-readable storage media, machine-readable storage media, or communication media, or a combination thereof. In this specification, the two terms are used distinctly from each other as follows: Computer-readable storage media or machine-readable storage media can be any available storage media that can be accessed by a computer, and include both volatile and non-volatile media, removable and non-removable media. For example, computer-readable storage media or machine-readable storage media can be implemented in relation to any method or technique for storing information such as computer-readable or machine-readable instructions, program modules, structured or unstructured data.

[0100] Computer-readable storage media may include, but are not limited to, random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD), Blu-ray disc (BD) or other optical disc storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices, semiconductor drives or other semiconductor storage devices, or other tangible media or non-transient media or both that can be used to store desired information. In this regard, the terms “tangible” or “non-transient” as used herein, when applied to storage, memory, or computer-readable media, should be understood to exclude only transient signals that propagate by themselves as modifying phrases, and not to waive any rights to all standard storage, memory, or computer-readable media that are not merely transient signals that propagate by themselves.

[0101] Computer-readable storage media can be accessed by one or more local or remote computing devices for various operations relating to the information stored on the media, for example, through access requests, queries, or other data retrieval protocols.

[0102] Communication media typically include any information distribution or transport medium that embodies computer-readable instructions, data structures, program modules, or other structured or unstructured data in data signals such as modulated data signals (e.g., carrier waves or other transport mechanisms). The term “modulated data signal” refers to a signal having one or more characteristics that are set or modified in a manner that encodes information within one or more signals. Examples of communication media include, but are not limited to, wired media such as wired networks or direct wired connections, and wireless media such as acoustic, RF, infrared, and other wireless media.

[0103] Referring again to Figure 12, an exemplary environment 1200 for implementing various embodiments of the aspects described herein includes a computer 1202, which includes a processing unit 1204, system memory 1206, and a system bus 1208. The system bus 1208 connects system components, including but not limited to the system memory 1206, to the processing unit 1204. The processing unit 1204 can be any of various commercially available processors. Dual microprocessors and other multiprocessor architectures can also be employed as the processing unit 1204.

[0104] The system bus 1208 can be one of several types of bus structures that can further interconnect to memory buses (with or without a memory controller), peripheral buses, and local buses using any of the various commercially available bus architectures. The system memory 1206 includes ROM 1210 and RAM 1212. The basic input / output system (BIOS) can be stored in non-volatile memory such as ROM, erasable programmable read-only memory (EPROM), or EEPROM, and the BIOS includes basic routines that help transfer information between elements within the computer 1202 during boot-up and other times. RAM 1212 may also include high-speed RAM such as static RAM for caching data.

[0105] Computer 1202 further includes an internal hard disk drive (HDD) 1214 (e.g., EIDE, SATA), one or more external storage devices 1216 (e.g., magnetic floppy disk drive (FDD), memory stick or flash drive reader, memory card reader, or a combination thereof), and an optical disk drive 1220 (e.g., a drive capable of reading from or writing to CD-ROM disks, DVDs, BDs, etc.). Although the internal HDD 1214 is shown as being located inside computer 1202, the internal HDD 1214 may also be configured for use in a suitable external enclosure (not shown). Furthermore, although not shown in environment 1200, a solid-state drive (SSD) may be used in addition to or instead of the HDD 1214. The HDD 1214, external storage device 1216, and optical disc drive 1220 can be connected to the system bus 1208 by the HDD interface 1224, the external storage interface 1226, and the optical drive interface 1228, respectively. The interface 1224 for external drive implementation may include at least one or both of the Universal Serial Bus (USB) interface technology and the IEEE 1394 interface technology. Other external drive connection technologies are included in the intent of the embodiments described herein.

[0106] Drives and associated computer-readable storage media provide non-volatile storage such as data, data structures, and computer-executable instructions. The drives and storage media of computer 1202 are suitable for storing any data in a suitable digital format. While the above description of computer-readable storage media refers to various storage devices, it should be understood by those skilled in the art that other types of storage media that can be read by a computer, whether currently existing or to be developed in the future, may also be used in the exemplary operating environment, and furthermore, any such storage media may contain computer-executable instructions for performing the methods described herein.

[0107] A drive and RAM 1212 may store an operating system 1230, one or more application programs 1232, other program modules 1234, and multiple program modules including program data 1236. All or part of the operating system, applications, modules, or data, or any combination thereof, may also be cached in RAM 1212. The systems and methods described herein can be implemented using various commercially available operating systems or combinations of operating systems.

[0108] Computer 1202 may optionally include emulation techniques. For example, a hypervisor (not shown) or other intermediary may emulate the hardware environment of operating system 1230, and the emulated hardware may optionally differ from the hardware shown in Figure 12. In such embodiments, operating system 1230 may include one VM among several virtual machines (VMs) hosted on computer 1202. Furthermore, operating system 1230 may provide application 1232 with a runtime environment such as the Java® runtime environment or the .NET framework. The runtime environment is a consistent execution environment that enables application 1232 to run on any operating system that contains the runtime environment. Similarly, operating system 1230 may support containers, and application 1232 may be in the form of a container, which is a lightweight, standalone executable software package containing, for example, code, runtime, system tools, system libraries, and configuration for the application.

[0109] Furthermore, computer 1202 can be enabled using security modules such as a trusted processing module (TPM). For example, with a TPM, the boot component hashs the next boot component in time, waits for a match between the hash result and a protected value, and then loads the next boot component. This process can be performed at any layer in the code execution stack of computer 1202, for example, at the application execution level or at the operating system (OS) kernel level, thereby enabling security at any level of code execution.

[0110] The user can input commands and information to the computer 1202 via one or more wired / wireless input devices (e.g., a keyboard 1238, a touchscreen 1240, and a pointing device such as a mouse 1242). Other input devices (not shown) may include microphones, infrared (IR) remote controls, radio frequency (RF) remote controls, or other remote controls, joysticks, virtual reality controllers or virtual reality headsets or both, gamepads, styluses, image input devices (e.g., cameras), gesture sensor input devices, vision movement sensor input devices, emotion or face detection devices, and biometric input devices (e.g., fingerprint or iris scanners). These and other input devices are often connected to the processing unit 1204 via an input device interface 1244 which can be coupled to the system bus 1208, but can also be connected via other interfaces such as parallel ports, IEEE 1394 serial ports, game ports, USB ports, IR interfaces, and BLUETOOTH® interfaces.

[0111] Monitor 1246 or other types of display devices may also be connected to the system bus 1208 via an interface such as a video adapter 1248. In addition to monitor 1246, a computer typically includes other peripheral output devices (not shown), such as speakers, printers, or a combination thereof.

[0112] Computer 1202 can operate within a network environment using logical connections to one or more remote computers, such as remote computers 1250, via wired communication, wireless communication, or both. Remote computers 1250 can be workstations, server computers, routers, personal computers, portable computers, microprocessor-based entertainment equipment, peer devices, or other common network nodes, and typically include many or all of the elements described in relation to computer 1202, but for brevity, only the memory / storage device 1252 is shown. The logical connections shown in the diagram include wired / wireless connections to a local area network (LAN) 1254 or a larger network (e.g., a wide area network (WAN) 1256) or both. Such LAN and WAN network environments are common in offices and companies, facilitating enterprise-wide computer networks such as intranets, all of which can connect to global communication networks (e.g., the Internet).

[0113] When computer 1202 is used in a LAN network environment, it can be connected to the local network 1254 via a wired, wireless, or both communication network interface or adapter 1258. The adapter 1258 can facilitate wired or wireless communication with LAN 1254, and LAN 1254 may also include a wireless access point (AP) positioned to communicate with adapter 1258 in wireless mode.

[0114] When used within a WAN network environment, computer 1202 may include a modem 1260 or be connected to a communication server on WAN 1256 by other means for establishing communication via WAN 1256, such as over the Internet. The modem 1260, which may be an internal or external wired or wireless device, may be connected to the system bus 1208 via an input device interface 1244. Within the network environment, program modules shown in relation to computer 1202 or a part thereof may be stored in a remote memory / storage device 1252. It will be understood that the shown network connection is an example, and other means for establishing communication links between computers may be used.

[0115] When computer 1202 is used in either a LAN network environment or a WAN network environment, it can access a cloud storage system or other network-based storage system in addition to, or instead of, the external storage device 1216 described above. Generally, the connection between computer 1202 and the cloud storage system can be established via LAN 1254 or WAN 1256, for example, by adapter 1258 or modem 1260, respectively. When computer 1202 is connected to the relevant cloud storage system, the external storage interface 1226 can manage the storage provided by the cloud storage system, similar to other types of external storage, using adapter 1258 or modem 1260 or both. For example, the external storage interface 1226 can be configured to provide access to the cloud storage source as if the cloud storage source were physically connected to computer 1202.

[0116] Computer 1202 can function to communicate with any wireless device or entity configured to operate in wireless communication (e.g., printers, scanners, desktop computers or portable computers or both, portable data assistants, communication satellites, any part or location of equipment associated with wirelessly discoverable tags (e.g., kiosks, newsstands, shelves, etc.), and telephones). This communication may include Wireless Fidelity (WiFi®) and Bluetooth® wireless technologies. Thus, this communication may be a predefined structure, similar to conventional networks, or simply ad-hoc communication between at least two devices.

[0117] The foregoing includes only examples of systems, computer program products, and computer implementation methods. Naturally, it is impossible to describe all possible combinations of components, products, or computer implementation methods, or combinations thereof, for the purpose of illustrating this disclosure; however, those skilled in the art will recognize that many other combinations and arrangements of the disclosure are possible. Furthermore, where terms such as “includes,” “has,” and “possess” are used in the embodiments for carrying out the invention, claims, appendices, and drawings, they are intended to be inclusive in the same way as the term “equipped,” as “equipped” is interpreted when used as a provisional term in the claims. The descriptions of various embodiments are presented for illustrative purposes only and are not intended to be exhaustive, nor are they limited to the disclosed embodiments. It will be apparent to those skilled in the art that many modifications and variations are possible without departing from the scope and spirit of the described embodiments. The terminology used herein has been selected to best describe the principles of the embodiments, their practical applications, or any technical improvements beyond the technology available on the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. Memory for storing computer executable components, A processor operably coupled to the memory and capable of executing the computer executable components stored in the memory. A system comprising the computer executable component, A system comprising an error mitigation component that adds a set of scaled quantum gates to a quantum circuit for error mitigation, wherein the set of scaled quantum gates includes quantum gates and inversions of the quantum gates, and the set of scaled quantum gates has a rotation angle based on a pulse schedule to achieve a target elongation coefficient.

2. The system according to claim 1, wherein the rotation angle of the set of scaled quantum gates controls the amount of noise generated in the quantum circuit.

3. The system according to claim 1, further comprising a gate component for inserting a set of quantum gates into the quantum circuit based on a target quantum gate present in the quantum circuit.

4. The system according to claim 3, wherein the set of quantum gates includes a single cross-resonance pulse, a cross-resonance pulse including a rotation term, an echo cross-resonance pulse including the rotation term, or an RZX gate performed directly by a CX gate.

5. The system according to claim 3, further comprising a calibration component that performs calibration of the target quantum gate and determines the pulse execution of the target quantum gate.

6. The system according to claim 5, further comprising a scaling component that generates the pulse schedule for a set of quantum gates based on the pulse execution of the target quantum gate and the target elongation coefficient, wherein the pulse schedule scales the rotation angle of the set of quantum gates to define the scaled set of quantum gates.

7. The system according to claim 5 or 6, further comprising an execution component that executes the quantum circuit using the set of scaled quantum gates.

8. The system according to claim 7, further comprising an extrapolation component for extrapolating the results realized by the execution component to reduce noise in the quantum circuit.

9. A computer implementation method using computer-based information processing, The system, operably coupled to the processor, adds a set of scaled quantum gates to the quantum circuit for error mitigation. A computer implementation method comprising the set of scaled quantum gates comprising a quantum gate and an inversion thereof, wherein the set of scaled quantum gates has a rotation angle based on a pulse schedule to achieve a target elongation coefficient.

10. The computer implementation method according to claim 9, wherein the rotation angle of the set of scaled quantum gates controls the amount of noise generated in the quantum circuit.

11. The computer implementation method according to claim 9, further comprising inserting a set of quantum gates into the quantum circuit based on a target quantum gate present in the quantum circuit using the system.

12. The computer implementation method according to claim 11, wherein the set of quantum gates includes a single cross-resonance pulse, a cross-resonance pulse including a rotation term, an echo cross-resonance pulse including the rotation term, or an RZX gate implemented directly by a CX gate.

13. The computer implementation method according to claim 11, further comprising using the system to extract the calibration of the target quantum gate and to determine the pulse execution of the target quantum gate.

14. The computer implementation method according to claim 13, further comprising the system generating the pulse schedule for the set of quantum gates based on the pulse execution of the target quantum gate and the target extension coefficient, wherein the pulse schedule scales the rotation angle of the set of quantum gates to define the scaled set of quantum gates.

15. The system executes the quantum circuit using the scaled set of quantum gates, The system reduces noise in the quantum circuit by extrapolating the results from the execution. The computer implementation method according to claim 14, further comprising:

16. A computer program for mitigating errors in a quantum circuit, characterized by causing a processor to add a set of scaled quantum gates to the quantum circuit, wherein the set of scaled quantum gates includes quantum gates and inversions of the quantum gates, and the set of scaled quantum gates has rotation angles based on a pulse schedule to achieve a target elongation coefficient.

17. A computer-readable recording medium for causing a processor to perform the computer implementation method described in any one of claims 9 to 15.

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