Memory chip, chip stacking structure, and memory

Abstract

The present disclosure provides a memory chip, a chip stack structure, and a memory. For the memory chip, n through-hole sets in a first region and n through-hole sets in a second region are symmetric with respect to a first axis, n through-hole sets in a third region and n through-hole sets in a fourth region are symmetric with respect to the first axis, n through-hole sets in the first region and n through-hole sets in the fourth region are symmetric with respect to a second axis. For each through-hole set, a first through-hole and a second through-hole are symmetric with respect to a third axis, a third through-hole and a fourth through-hole are symmetric with respect to the third axis, and the first through-hole and the fourth through-hole are symmetric with respect to a fourth axis.

Description

Technical Field

[0001] (Cross - reference to related applications) This application claims the priority of a Chinese patent application filed with the Chinese Patent Office on June 8, 2023, with the application number 202310680606.3 and the invention title "Memory Chip, Chip Stack Structure and Memory", and all of its content is incorporated herein by reference.

[0002] This application relates to, but is not limited to, memory chips, chip stack structures and memories.

Background Art

[0003] With the development of integrated circuit technology, the manufacturing process of semiconductor devices has made remarkable progress. However, in recent years, the development of two - dimensional semiconductor technology has faced various problems such as physical limits, limits of current development technology, and limits of memory electron density. In such a situation, in order to solve the difficulties faced by two - dimensional semiconductor devices and reduce the production cost of unit memory cells, a bonding process can be used to stack multiple chips to form a three - dimensional semiconductor device. However, for three - dimensional semiconductor devices, the connection structure between different chips still has problems such as large parasitic capacitance and large parasitic resistance, which affect the signal transmission quality.

Summary of the Invention

[0004] This disclosure provides a memory chip, a chip stack structure and a memory.

[0005] The technical solution of this disclosure is realized as follows.

[0006] In a first aspect, an embodiment of the present disclosure provides a memory chip comprising 2 × 2 regions distributed in an array along the active surface of the memory chip, each region being penetrated by a set of n through holes, where n is a natural number, the set of n through holes in the first region and the set of n through holes in the second region being symmetric with respect to a first axis, the set of n through holes in the third region and the set of n through holes in the fourth region being symmetric with respect to the first axis, the set of n through holes in the first region and the set of n through holes in the fourth region being symmetric with respect to a second axis, both the first axis and the second axis being located on the active surface, and the first axis and the second axis being perpendicular to each other and on the active surface The axes intersect at the center of the surface, and for each set of through-holes, each set of through-holes includes 2 × 2 through-holes distributed in an array, the first and second through-holes are symmetrical with respect to the third axis, the third and fourth through-holes are symmetrical with respect to the third axis, and the first and fourth through-holes are symmetrical with respect to the fourth axis, both the third and fourth axes are located on the active surface, the third and fourth axes are perpendicular to each other and intersect at the center of the set of through-holes, the first axis and the third axis of each set of through-holes are both parallel to the first side of the memory chip, and the second axis and the fourth axis of each set of through-holes are both parallel to the second side of the memory chip.

[0007] In some embodiments, the n first through holes in the first region and the n second through holes in the second region are symmetric with respect to the first axis, the n third through holes in the third region and the n fourth through holes in the fourth region are symmetric with respect to the first axis, and the n first through holes in the first region and the n fourth through holes in the fourth region are symmetric with respect to the second axis.

[0008] In some embodiments, the n second through holes in the first region and the n first through holes in the second region are symmetric with respect to the first axis, the n fourth through holes in the third region and the n third through holes in the fourth region are symmetric with respect to the first axis, and the n second through holes in the first region and the n third through holes in the fourth region are symmetric with respect to the second axis.

[0009] In some embodiments, the n third through holes in the first region and the n fourth through holes in the second region are symmetric with respect to the first axis, the n first through holes in the third region and the n second through holes in the fourth region are symmetric with respect to the first axis, and the n third through holes in the first region and the n second through holes in the fourth region are symmetric with respect to the second axis.

[0010] In some embodiments, the n fourth through holes in the first region and the n third through holes in the second region are symmetric with respect to the first axis, the n second through holes in the third region and the n first through holes in the fourth region are symmetric with respect to the first axis, and the n fourth through holes in the first region and the n first through holes in the fourth region are symmetric with respect to the second axis.

[0011] In some embodiments, one of the through-holes penetrates the memory chip in a direction perpendicular to the active surface, and different through-holes within the same memory chip are electrically isolated.

[0012] In some embodiments, the memory chip further includes 4n first drive circuits, the 4n through-holes are connected to the 4n first drive circuits in a one-to-one correspondence, and only one through-hole in each set of through-holes is connected to the first drive circuit.

[0013] In some embodiments, the memory chip further includes a positioning structure which, by being located in a reference region, indicates the location of the reference region, and the reference region is one of the 2x2 regions.

[0014] In a second aspect, an embodiment of the present disclosure provides a chip stacking structure comprising at least one stacking unit, each of which comprises a first memory chip, a second memory chip, a third memory chip, and a fourth memory chip sequentially stacked along a third direction, the third direction being perpendicular to the active surface of each of the memory chips, the first memory chip, the second memory chip, the third memory chip, and the fourth memory chip are all memory chips as described in the first aspect, the first memory chip and the second memory chip are stacked face-to-face, the second memory chip and the third memory chip are stacked back-to-back, and the third memory chip and the fourth memory chip are stacked face-to-face.

[0015] In some embodiments, the first region in the first memory chip, the second region in the second memory chip, the third region in the third memory chip, and the fourth region in the fourth memory chip are aligned along a third direction; the second region in the first memory chip, the first region in the second memory chip, the fourth region in the third memory chip, and the third region in the fourth memory chip are aligned along a third direction; the third region in the first memory chip, the fourth region in the second memory chip, the first region in the third memory chip, and the second region in the fourth memory chip are aligned along a third direction; and the fourth region in the first memory chip, the third region in the second memory chip, the second region in the third memory chip, and the first region in the fourth memory chip are aligned along a third direction.

[0016] In some embodiments, the n first through-holes in the first region of the first memory chip, the n second through-holes in the second region of the second memory chip, the n third through-holes in the third region of the third memory chip, and the n fourth through-holes in the fourth region of the fourth memory chip are aligned along a third direction, and the n second through-holes in the first region of the first memory chip, the n first through-holes in the second region of the second memory chip, the n fourth through-holes in the third region of the third memory chip, and the n third through-holes in the fourth region of the fourth memory chip are aligned along a third direction. The n third through-holes in the first region of the first memory chip, the n fourth through-holes in the second region of the second memory chip, the n first through-holes in the third region of the third memory chip, and the n second through-holes in the fourth region of the fourth memory chip are aligned along the third direction, and the n fourth through-holes in the first region of the first memory chip, the n third through-holes in the second region of the second memory chip, the n second through-holes in the third region of the third memory chip, and the n first through-holes in the fourth region of the fourth memory chip are aligned along the third direction.

[0017] In some embodiments, the n first through-holes in the second region of the first memory chip, the n second through-holes in the first region of the second memory chip, the n third through-holes in the fourth region of the third memory chip, and the n fourth through-holes in the third region of the fourth memory chip are aligned along a third direction, and the n second through-holes in the second region of the first memory chip, the n first through-holes in the first region of the second memory chip, the n fourth through-holes in the fourth region of the third memory chip, and the n third through-holes in the third region of the fourth memory chip are aligned along a third direction. The n third through-holes in the second region of the first memory chip, the n fourth through-holes in the first region of the second memory chip, the n first through-holes in the fourth region of the third memory chip, and the n second through-holes in the third region of the fourth memory chip are aligned along the third direction, and the n fourth through-holes in the second region of the first memory chip, the n third through-holes in the first region of the second memory chip, the n second through-holes in the fourth region of the third memory chip, and the n first through-holes in the third region of the fourth memory chip are aligned along the third direction.

[0018] In some embodiments, the n first through-holes in the third region of the first memory chip, the n second through-holes in the fourth region of the second memory chip, the n third through-holes in the first region of the third memory chip, and the n fourth through-holes in the second region of the fourth memory chip are aligned along the third direction, and the n second through-holes in the third region of the first memory chip, the n first through-holes in the fourth region of the second memory chip, the n fourth through-holes in the first region of the third memory chip, and the n third through-holes in the second region of the fourth memory chip are aligned along the third direction. The n third through-holes in the third region of the first memory chip, the n fourth through-holes in the fourth region of the second memory chip, the n first through-holes in the first region of the third memory chip, and the n second through-holes in the second region of the fourth memory chip are aligned along the third direction, and the n fourth through-holes in the third region of the first memory chip, the n third through-holes in the fourth region of the second memory chip, the n second through-holes in the first region of the third memory chip, and the n first through-holes in the second region of the fourth memory chip are aligned along the third direction.

[0019] In some embodiments, the n first through-holes in the fourth region of the first memory chip, the n second through-holes in the third region of the second memory chip, the n third through-holes in the second region of the third memory chip, and the n fourth through-holes in the first region of the fourth memory chip are aligned along a third direction, and the n second through-holes in the fourth region of the first memory chip, the n first through-holes in the third region of the second memory chip, the n fourth through-holes in the second region of the third memory chip, and the n third through-holes in the first region of the fourth memory chip are aligned along a third direction. The n third through-holes in the fourth region of the first memory chip, the n fourth through-holes in the third region of the second memory chip, the n first through-holes in the second region of the third memory chip, and the n second through-holes in the first region of the fourth memory chip are aligned along the third direction, and the n fourth through-holes in the fourth region of the first memory chip, the n third through-holes in the third region of the second memory chip, the n second through-holes in the second region of the third memory chip, and the n first through-holes in the first region of the fourth memory chip are aligned along the third direction.

[0020] In some embodiments, the first region in the first memory chip, the fourth region in the second memory chip, the third region in the third memory chip, and the second region in the fourth memory chip are aligned along the third direction; the second region in the first memory chip, the third region in the second memory chip, the fourth region in the third memory chip, and the first region in the fourth memory chip are aligned along the first direction; the third region in the first memory chip, the second region in the second memory chip, the first region in the third memory chip, and the fourth region in the fourth memory chip are aligned along the third direction; and the fourth region in the first memory chip, the first region in the second memory chip, the second region in the third memory chip, and the third region in the fourth memory chip are aligned along the third direction.

[0021] In some embodiments, the n first through-holes in the first region of the first memory chip, the n fourth through-holes in the fourth region of the second memory chip, the n third through-holes in the third region of the third memory chip, and the n second through-holes in the second region of the fourth memory chip are aligned along a third direction, and the n second through-holes in the first region of the first memory chip, the n third through-holes in the fourth region of the second memory chip, the n fourth through-holes in the third region of the third memory chip, and the n first through-holes in the second region of the fourth memory chip are aligned along a third direction. The n third through-holes in the first region of the first memory chip, the n second through-holes in the fourth region of the second memory chip, the n first through-holes in the third region of the third memory chip, and the n fourth through-holes in the second region of the fourth memory chip are aligned along the third direction, and the n fourth through-holes in the first region of the first memory chip, the n first through-holes in the fourth region of the second memory chip, the n second through-holes in the third region of the third memory chip, and the n third through-holes in the second region of the fourth memory chip are aligned along the third direction.

[0022] In some embodiments, the n first through-holes in the second region of the first memory chip, the n fourth through-holes in the third region of the second memory chip, the n third through-holes in the fourth region of the third memory chip, and the n second through-holes in the first region of the fourth memory chip are aligned along a third direction, and the n second through-holes in the second region of the first memory chip, the n third through-holes in the third region of the second memory chip, the n fourth through-holes in the fourth region of the third memory chip, and the n first through-holes in the first region of the fourth memory chip are aligned along a third direction. The n third through-holes in the second region of the first memory chip, the n second through-holes in the third region of the second memory chip, the n first through-holes in the fourth region of the third memory chip, and the n fourth through-holes in the first region of the fourth memory chip are aligned along the third direction, and the n fourth through-holes in the second region of the first memory chip, the n first through-holes in the third region of the second memory chip, the n second through-holes in the fourth region of the third memory chip, and the n third through-holes in the first region of the fourth memory chip are aligned along the third direction.

[0023] In some embodiments, the n first through-holes in the third region of the first memory chip, the n fourth through-holes in the second region of the second memory chip, the n third through-holes in the first region of the third memory chip, and the n second through-holes in the fourth region of the fourth memory chip are aligned along the third direction, and the n second through-holes in the third region of the first memory chip, the n third through-holes in the second region of the second memory chip, the n fourth through-holes in the first region of the third memory chip, and the n first through-holes in the fourth region of the fourth memory chip are aligned along the third direction. The n third through-holes in the third region of the first memory chip, the n second through-holes in the second region of the second memory chip, the n first through-holes in the first region of the third memory chip, and the n fourth through-holes in the fourth region of the fourth memory chip are aligned along the third direction, and the n fourth through-holes in the third region of the first memory chip, the n first through-holes in the second region of the second memory chip, the n second through-holes in the first region of the third memory chip, and the n third through-holes in the fourth region of the fourth memory chip are aligned along the third direction.

[0024] In some embodiments, the n first through-holes in the fourth region of the first memory chip, the n fourth through-holes in the first region of the second memory chip, the n third through-holes in the second region of the third memory chip, and the n second through-holes in the third region of the fourth memory chip are aligned along the third direction, and the n second through-holes in the fourth region of the first memory chip, the n third through-holes in the first region of the second memory chip, the n fourth through-holes in the second region of the third memory chip, and the n first through-holes in the third region of the fourth memory chip are aligned along the third direction. The n third through-holes in the fourth region of the first memory chip, the n second through-holes in the first region of the second memory chip, the n first through-holes in the second region of the third memory chip, and the n fourth through-holes in the third region of the fourth memory chip are aligned along the third direction, and the n fourth through-holes in the fourth region of the first memory chip, the n first through-holes in the first region of the second memory chip, the n second through-holes in the second region of the third memory chip, and the n third through-holes in the third region of the fourth memory chip are aligned along the third direction.

[0025] In some embodiments, for two memory chips connected front to front, through-holes aligned along a third direction between them are connected by a hybrid bonding structure; for two memory chips connected back to back, through-holes aligned along a third direction between them are connected by conductive bumps; or for two memory chips connected front to front or back to back, through-holes aligned along a third direction between them are both connected by a hybrid bonding structure; or for two memory chips connected front to front or back to back, through-holes aligned along a third direction between them are both connected by conductive bumps.

[0026] In some embodiments, each of the memory chips further includes 4n first drive circuits. In each of the memory chips, the 4n first drive circuits are connected to the first ends of the 4n first through holes in a one-to-one correspondence, and the first ends of the first through holes are located on the active surface of the memory chip.

[0027] In some embodiments, the chip stack structure further includes a logic chip. The first stack unit is stacked on the logic chip along the third direction, and the other stack units are sequentially stacked on the previous stack unit along the third direction. The logic chip includes 16n fifth through holes and 16n second drive circuits. 4n fifth through holes are aligned with 4n first through holes in the first memory chip in a one-to-one correspondence along the third direction. 4n fifth through holes are aligned with 4n second through holes in the first memory chip in a one-to-one correspondence along the third direction. 4n fifth through holes are aligned with 4n third through holes in the first memory chip in a one-to-one correspondence along the third direction. 4n fifth through holes are aligned with 4n fourth through holes in the first memory chip in a one-to-one correspondence along the third direction. The 16n second drive circuits are connected to the first ends of the 16n fifth through holes in a one-to-one correspondence, and the first ends of the fifth through holes are located on the active surface of the logic chip.

[0028] In some embodiments, the chip stack structure further includes 16n electrical paths. When the chip stack structure includes m stack units, one fifth through hole, m first through holes, m second through holes, m third through holes, and m fourth through holes that are aligned along the third direction are connected to form one electrical path, and m is a positive integer.

[0029] In a third aspect, embodiments of the present disclosure provide a memory, and the memory includes the chip stack structure described in the second aspect.

[0030] Embodiments of the present disclosure provide a memory chip, a chip stack structure, and a memory. By reducing the number of settings of the drive circuit and the data selector, not only the parasitic capacitance is reduced, but also the chip stack structure formed by the memory chip realizes a signal rotation transmission effect through a direct connection structure of through holes, and the parasitic resistance is also reduced.

Brief Description of the Drawings

[0031] [Figure 1] It is a signal transmission schematic diagram of a chip stack structure. [Figure 2] It is a signal transmission schematic diagram of another chip stack structure. [Figure 3] It is a schematic diagram showing the configuration of a memory chip according to an embodiment of the present disclosure. [Figure 4] It is a schematic diagram showing the configuration of another memory chip according to an embodiment of the present disclosure. [Figure 5] It is a schematic diagram showing the configuration of yet another memory chip according to an embodiment of the present disclosure. [Figure 6] It is a schematic diagram showing the configuration of a chip stack structure according to an embodiment of the present disclosure. [Figure 7] It is Schematic Diagram 1 of a first chip stack structure according to an embodiment of the present disclosure. [Figure 8] It is Schematic Diagram 2 of a first chip stack structure according to an embodiment of the present disclosure. [Figure 9] It is Schematic Diagram 3 of a first chip stack structure according to an embodiment of the present disclosure. [Figure 10] It is Schematic Diagram 1 of a second chip stack structure according to an embodiment of the present disclosure. [Figure 11] It is Schematic Diagram 2 of a second chip stack structure according to an embodiment of the present disclosure. [Figure 12] It is Schematic Diagram 3 of a second chip stack structure according to an embodiment of the present disclosure. [Figure 13] It is a signal transmission schematic diagram of a first chip stack structure according to an embodiment of the present disclosure. [Figure 14] It is a signal transmission schematic diagram of a second chip stack structure according to an embodiment of the present disclosure. [Figure 15]This is a schematic diagram showing the memory configuration according to an embodiment of the present disclosure. [Modes for carrying out the invention]

[0032] In the following, the technical solutions in the embodiments of this disclosure will be described more clearly and completely with reference to the drawings in the embodiments of this disclosure. It should be understood that the specific embodiments described herein are intended solely to illustrate the relevant application and are not intended to limit this application. Furthermore, for the convenience of explanation, only the parts of the drawings relevant to the relevant application are shown. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art. The terms used in this disclosure are adopted solely to illustrate the embodiments of this disclosure and are not intended to limit this disclosure. In the following, the phrase “several embodiments” describes a subset of all possible embodiments, but it should be understood that “several embodiments” may be the same subset or a different subset of all possible embodiments and can be combined with each other without contradiction. Furthermore, it should be understood that terms such as “first / second / third” in the embodiments of this disclosure do not limit a particular order but distinguish similar subjects. Understandably, since "1st / 2nd / 3rd" can be changed in any appropriate order or sequence, the embodiments of this disclosure described herein may be performed in an order other than those illustrated or described herein.

[0033] Dynamic Random Access Memory (DRAM) Synchronous Dynamic Random Access Memory (SDRAM) Double Data Rate Memory (DDR SDRAM) Low-voltage, low-power DDR (LPDDR).

[0034] Before describing embodiments of this disclosure, we define three directions that describe the three-dimensional structure relating to the plane in the following embodiments. Taking the Cartesian coordinate system as an example, the three directions may include the X-axis, Y-axis, and Z-axis directions (not applicable to embodiments of this disclosure). A semiconductor chip may include a top surface located at the front (active surface) and a bottom surface located at the back surface opposite the front (inactive surface). Assuming that the flatness of the top and bottom surfaces is not considered, we define a third direction that intersects (e.g., perpendicularly) the top and bottom surfaces of the semiconductor chip. Two directions that intersect each other on the active surface of the semiconductor chip, namely a first direction and a second direction, can be defined, and the direction of the active surface of the semiconductor chip can be determined based on the first and second directions. In embodiments of this disclosure, the first and second directions may be perpendicular to each other, while in other embodiments, the first and second directions may not be perpendicular.

[0035] In particular, the drawings shown in this disclosure are not intended to represent actual diagrams of specific microelectronic devices or their components, but are merely ideal representations for illustrating exemplary embodiments. Therefore, the drawings are not necessarily to scale.

[0036] Each embodiment of this disclosure will be described in detail below with reference to the drawings.

[0037] In one embodiment, a memory chip is provided, which includes a plurality of through-holes (also called silicon through-holes, which enable signal transmission between different chips), and all through-holes can be located in any position. In particular, groups of four through-holes can be functionally considered as a single through-hole group, and there are no restrictions on the position of each of these four through-holes.

[0038] In one specific embodiment, eight of the aforementioned memory chips and one logic chip are stacked to form a 3D memory device. Simultaneously, the through-holes of each of the eight memory chips are aligned along a third direction, and the nine through-holes that are aligned along the third direction are connected to form a single electrical path. Referring to Figure 1, Figure 1 is a schematic diagram of signal transmission in a chip stacking structure. As shown in Figure 1, this chip stacking structure includes memory chips 0 to 7 and a logic chip. In Figure 1, each memory chip shows only four through-holes D0 to D3, and these four through-holes D0 to D3 belong to the same through-hole set. In this case, the through-holes D0 in the eight memory chips and the one logic chip are all aligned to form a single electrical path, and the through-holes D1 in the eight memory chips and the one logic chip are all aligned to form a single electrical path... The other through-holes are similar.

[0039] Simultaneously, each memory chip and logic chip is further provided with multiple drive circuits (in Figure 1, only one drive circuit is shown with a dashed box, while the other drive circuits are not shown with boxes), and each through-hole is connected to one drive circuit. Each memory chip is further provided with multiple data selectors (e.g., mux0 to 7 in Figure 1), and each set of through-holes corresponds to one data selector; that is, all through-holes in a set of through-holes are connected to the data ports of the data selectors via their respective drive circuits. In other words, the data selector can choose which through-holes transmit signals to output inside the memory chip, or which through-holes transmit signals from the memory chip to output.

[0040] Within the entire memory device, these eight memory chips are managed by dividing them into four channels (CH0, CH1, CH4, CH5). Memory chips 0 and 4 belong to channel CH0, memory chips 1 and 5 belong to channel CH1, memory chips 2 and 6 belong to channel CH4, and memory chips 3 and 7 belong to channel CH5. Correspondingly, the input / output signal I / O_CH0 of channel CH0 is transmitted via an electrical pathway consisting of "through-hole D0 in the logic chip, through-hole D0 in memory chip 0 - through-hole D0 in memory chip 1 - through-hole D0 in memory chip 2 - through-hole D0 in memory chip 3 - through-hole D0 in memory chip 4 - through-hole D0 in memory chip 5 - through-hole D0 in memory chip 6 - through-hole D0 in memory chip 7". The selection signals for data selector mux0 in memory chip 0 and data selector mux4 in memory chip 4 are both SEL_C0, meaning that the input / output signal I / O_CH0 can enter memory chip 0 and memory chip 4 via the above electrical pathway, and the signal output process can be understood similarly.

[0041] As can be seen from the above, memory chip 0 may obtain a signal only from through-hole D0, memory chip 1 may obtain a signal only from through-hole D1, and so on; in other words, each memory chip may obtain a signal from only one through-hole within a set of through-holes. It should be noted that different memory chips may need to obtain signals from different through-holes. However, during process manufacturing, all memory chips must be designed to have exactly the same structure (this can minimize costs and labor), so all through-holes in a memory chip must be designed with corresponding drive structures and data selectors to achieve structural consistency. Furthermore, when adopting the chip stacking structure shown in Figure 1, one drive circuit corresponds to each through-hole, and during the operation of this chip stacking structure, all drive circuits in all memory chips in the same channel must be operated, resulting in a heavy load and large parasitic capacitance, which seriously affects the performance of the chips within it, limits transmission efficiency, increases power consumption, and also limits the number of chips that can be stacked in a three-dimensional device.

[0042] In another embodiment, referring to Figure 2, which is a schematic diagram of signal transmission in another chip stacking structure. In Figure 2, only some of the through-holes are shown (D0-D3), with the others omitted. In Figure 4, the identifiers of the through-holes aligned along the third direction are the same. As shown in Figure 2, the chip stacking structure includes eight memory chips and one logic chip, similarly aligned along the third direction, but the through-holes in each memory chip are rotationally connected to other through-holes at different positions in other memory chips, achieving an overall spiral upward connection, i.e., the input output signal I / O_CH0 of channel CH0 is transmitted through "through-hole D0 in the logic chip, through-hole D1 in memory chip 0 - through-hole D2 in memory chip 1 - through-hole D3 in memory chip 2 - through-hole D0 in memory chip 3 - through-hole D1 in memory chip 4 - through-hole D2 in memory chip 5 - through-hole D3 in memory chip 6 - through-hole D0 in memory chip 7", and other signals are similar.

[0043] In this way, memory chip 0 can obtain the input-output signal I / O_CH0 via the output terminal of the through-hole D0 in the logic chip, memory chip 1 can obtain the input-output signal I / O_CH1 via the input terminal of the through-hole D0 in memory chip 0, memory chip 2 can obtain the input-output signal I / O_CH4 via the input terminal of the through-hole D0 in memory chip 1, and memory chip 3 can output the input-output signal I / O_CH5 via the input terminal of the through-hole D0 in memory chip 2... For each memory chip, only one through-hole per set of through-holes needs to be connected to the drive circuit, there is no need to provide a data selector, and parasitic capacitance can be reduced by reducing the number of devices. However, the process of rotating through-hole connection in Figure 2 (for example, through-hole D0 of memory chip 0 is connected to through-hole D1 of memory chip 1) is more complex than the direct through-hole connection structure in Figure 1. Specifically, it is necessary to provide horizontal interconnection structures between adjacent through-holes in each memory chip in Figure 2 (one of which is indicated by a star in Figure 2). The signal interconnection structure may be a metal interconnection wire, a through-hole, etc. In order to realize through-hole rotational connection, the input signal must first be transmitted upward from through-hole D0 to below through-hole D0 of memory chip 1 (without being transmitted to through-hole D0 of memory chip 1), and then horizontally from below through-hole D0 of memory chip 1 to through-hole D1 of memory chip 1. Therefore, in the process of sequentially transmitting the input signal from through-hole D0 of the logic chip to through-hole D0 of memory chip 4, it is also necessary to pass through the interconnection structure within each memory chip, and the same applies to the output signal. Consequently, parasitic resistance inevitably increases, and the complexity of the process also increases.

[0044] In particular, in the chip stacking structures shown in Figures 1 and 2, all chips have their active surfaces facing upwards. This means that different memory chips are stacked back-to-front, and both memory chips and logic chips are stacked back-to-front, meaning that the inactive surface of the upper chip is in contact with the active surface of the lower chip.

[0045] In summary, on the one hand, the chip stacking structure in Figure 1 has too many drive circuits and data selectors, resulting in high load and parasitic capacitance, and on the other hand, the chip stacking structure in Figure 2 has high parasitic resistance due to its rotating structure. On the other hand, both the stacking structures in Figures 1 and 2 have certain problems and cannot be directly applied to a front-to-front stacking structure. Specifically, one method to further realize a front-to-front chip stacking structure is to use two sets of masks to create two different types of chips: one with the active side facing upwards and another with the active side facing downwards. However, this method is highly complex and the cost cannot be controlled. Another method is to create another set of through-holes and connect both sets of through-holes to the same drive circuit in the memory chip. However, this makes the internal wiring of the memory chip more complex, increasing not only the complexity of the process but also the power consumption.

[0046] Therefore, the embodiments of this disclosure propose memory chips and chip stacking structures that not only have small parasitic capacitance and parasitic resistance but also enable a front-to-front stacking method.

[0047] In yet another embodiment of the present disclosure, referring to Figure 3, which is a schematic diagram showing the configuration of a memory chip 10 according to an embodiment of the present disclosure. The memory chip 10 includes 2 × 2 regions distributed in an array along the active surface of the memory chip 10, which in the following description will be referred to as the first region 11, the second region 12, the third region 13, and the fourth region 14, respectively. Furthermore, regarding the active surface of the memory chip 10, there are a first axis AA' and a second axis BB' on the active surface of the memory chip 10, which are perpendicular to each other and intersect at the center of the active surface, with the first axis AA' parallel to one side of the memory chip 10 and the second axis BB' parallel to the other side of the memory chip 10. In particular, Figure 3 can be considered as a cross-sectional view along the active surface of the memory chip 10.

[0048] Referring to Figure 3, each region is penetrated by n through-hole sets 20 (only one through-hole set is shown for each region in Figure 3, with others omitted), where n is a natural number. The n through-hole sets 20 of the first region 11 and the n through-hole sets 20 of the second region 12 are symmetric with respect to the first axis AA', the n through-hole sets 20 of the third region 13 and the n through-hole sets 20 of the fourth region 14 are symmetric with respect to the first axis AA', and the n through-hole sets 20 of the first region 11 and the n through-hole sets 20 of the fourth region 14 are symmetric with respect to the second axis BB'. Here, "n through-hole sets 20 of the first region 11" specifically means "n through-hole sets 20 penetrating the first region 11 within the memory chip 10," and other expressions are similar.

[0049] It should be explained that while the number and position of through-hole sets 20 within each region can be adjusted according to the actual situation, the number of through-hole sets in each of the four regions must always be the same and must follow the symmetrical distribution rule described above. Figure 4 shows three through-hole sets 20 in each region, and of course the number of through-hole sets 20 could be 2, 4, 5, 6, 7, etc., and other cases can be understood adaptively.

[0050] In the embodiments of this disclosure, each through-hole set 20 has four through-holes, and following the same distribution rule, one of the through-hole sets 20 will be described below as an example.

[0051] Referring to Figure 3, for each through-hole set 20 (for example, the through-hole set 20 in the first region 11), there exists a third axis CC' and a fourth axis DD', both of which are located on the active plane. The third axis CC' is parallel to the first axis AA', and the fourth axis DD' is parallel to the second axis BB'. The third axis CC' and the fourth axis DD' are perpendicular to each other and intersect at the center of the through-hole set 20.

[0052] Each through-hole set 20 includes 2 × 2 through-holes distributed in an array, the first through-hole D0 and the second through-hole D1 are symmetric with respect to the third axis CC', the third through-hole D2 and the fourth through-hole D3 are symmetric with respect to the third axis CC', and the first through-hole D0 and the fourth through-hole D3 are symmetric with respect to the fourth axis DD'.

[0053] It should be explained that each through-hole set 20 has its own third axis CC' and fourth axis DD'. In other words, the first through-hole D0 and the second through-hole D1 of the same through-hole set 20 are symmetric with respect to the third axis CC' of the through-hole set 20, the third through-hole D2 and the fourth through-hole D3 of the same through-hole set 20 are symmetric with respect to the third axis CC' of the through-hole set 20, the first through-hole D0 and the fourth through-hole D3 of the same through-hole set 20 are symmetric with respect to the fourth axis DD' of the through-hole set 20, and the second through-hole D1 and the third through-hole D2 of the same through-hole set 20 are symmetric with respect to the fourth axis DD' of the through-hole set 20.

[0054] It should be explained that through-holes, also known as through-silicon vias (TSVs), are specifically vertical interconnection structures that penetrate silicon wafers / memory chips.

[0055] It should be explained that the above-mentioned memory chip 10 can be specifically applied to DRAM, SDRAM, DDR, LPDDR, etc.

[0056] It should be noted that one of the through-holes penetrates the memory chip in a direction perpendicular to the active surface (i.e., the third direction), and different through-holes within the same memory chip 10 are electrically isolated.

[0057] It should be noted that, in the embodiments of this disclosure, there are no limitations on the numbering order of each region or the numbering order of the through holes in each through-hole set 20.

[0058] In some embodiments, referring to Figure 3 or Figure 4, the n first through holes D0 in the first region 11 and the n second through holes D1 in the second region 12 are symmetric with respect to the first axis AA', the n third through holes D2 in the third region 13 and the n fourth through holes D3 in the fourth region 14 are symmetric with respect to the first axis AA', the n first through holes D0 in the first region 11 and the n fourth through holes D3 in the fourth region 14 are symmetric with respect to the second axis BB', and the n second through holes D1 in the second region 12 and the n third through holes D2 in the third region 13 are symmetric with respect to the second axis BB'.

[0059] In some embodiments, referring to Figure 3 or Figure 4, the n second through holes D1 in the first region 11 and the n first through holes D0 in the second region 12 are symmetric with respect to the first axis AA', the n fourth through holes D3 in the third region 13 and the n third through holes D2 in the fourth region 14 are symmetric with respect to the first axis AA', the n second through holes D1 in the first region 11 and the n third through holes D2 in the fourth region 14 are symmetric with respect to the second axis BB', and the n first through holes D0 in the second region 12 and the n fourth through holes D3 in the third region 13 are symmetric with respect to the second axis BB'.

[0060] In some embodiments, referring to Figure 3 or Figure 4, the n third through holes D2 in the first region 11 and the n fourth through holes D3 in the second region 12 are symmetric with respect to the first axis AA', the n first through holes D0 in the third region 13 and the n second through holes D1 in the fourth region 14 are symmetric with respect to the first axis AA', the n third through holes D2 in the first region 11 and the n second through holes D1 in the fourth region 14 are symmetric with respect to the first axis AA', and the n fourth through holes D3 in the second region 12 and the n first through holes D0 in the third region 13 are symmetric with respect to the second axis BB'.

[0061] In some embodiments, referring to Figure 3 or Figure 4, the n fourth through holes D3 in the first region 11 and the n third through holes D2 in the second region 12 are symmetric with respect to the first axis AA', the n second through holes D1 in the third region 13 and the n first through holes D0 in the fourth region 14 are symmetric with respect to the first axis AA', the n fourth through holes D3 in the first region 11 and the n first through holes D0 in the fourth region 14 are symmetric with respect to the second axis BB', and the n third through holes D2 in the second region 12 and the n second through holes D1 in the third region 13 are symmetric with respect to the second axis BB'.

[0062] In some embodiments, referring to Figure 5, the memory chip 10 further includes 4n first drive circuits 30, where 4n through-holes are connected to the 4n first drive circuits 30 in a one-to-one correspondence, and only one through-hole in each through-hole set 20 is connected to a first drive circuit 30. In other words, for each through-hole set 20, signals transmitted through only one through-hole enter or exit the chip.

[0063] In some embodiments, the memory chip 10 further includes a positioning structure (not shown) which indicates the location of a reference region by being positioned in the reference region, where the reference region is one of 2 × 2 regions (first region, second region, third region, or fourth region).

[0064] It should be explained that during the chip manufacturing process, it is necessary to manufacture multiple chips simultaneously. To distinguish between different regions within a chip, a positioning structure must be created in the first region of each memory chip (which may be the second, third, or fourth region, but the same region must be selected as the reference region across different chips). This allows the position of the reference region to be identified by the positioning structure during subsequent assembly, and simultaneously, the positions of other regions can be determined in combination with the orientation of the chip's active surface.

[0065] Furthermore, the memory chip 10 may include multiple positioning structures, and different positioning structures are located in different regions, thereby indicating the absolute position of the region. For example, the memory chip 10 may include four positioning structures, with one positioning structure distributed in each of the first to fourth regions, and since the four positioning structures are different from each other, each region can be better identified, that is, the first to fourth regions can all be considered as reference regions.

[0066] In this way, the embodiments of the present disclosure provide a memory chip 10 in which the through-holes within the memory chip 10 have a special symmetry and can be directly applied to a front-to-front stacked structure without requiring two sets of masks or two sets of through-holes. Furthermore, only one through-hole in each set of through-holes is connected to the drive circuit, eliminating the need to provide a data selector for through-hole selection and reducing the number of devices. This reduces parasitic capacitance and saves circuit area compared to the memory chip in Figure 1, as well as reducing chip manufacturing costs. Additionally, when subsequent memory chips 10 form a stacked structure, they can reduce parasitic resistance compared to the memory chip in Figure 2 (see below for specific reasons).

[0067] In yet another embodiment of the present disclosure, referring to Figure 6, which shows a chip stacking structure 40 according to an embodiment of the present disclosure, the chip stacking structure 40 comprises at least one stacking unit, each stacking unit comprising a first memory chip 41, a second memory chip 42, a third memory chip 43, and a fourth memory chip 44 stacked sequentially along a third direction, the third direction being perpendicular to the active surface of each memory chip, the first memory chip 41, the second memory chip 42, the third memory chip 43, and the fourth memory chip 44 are all the aforementioned memory chips 10, the first memory chip 41 and the second memory chip 42 are stacked face to face, i.e., the top surface (i.e., active surface) of the first memory chip 41 and the top surface of the second memory chip 42 are adjacent, and the second memory chip 42 and the third memory chip 43 are stacked back to back. The memory chips are stacked in a back-to-back configuration, meaning the back surface (i.e., the inactive side) of the second memory chip 42 and the back surface of the third memory chip 43 are adjacent, while the third memory chip 43 and the fourth memory chip 44 are stacked front to front, meaning the top surface of the third memory chip 43 and the top surface of the fourth memory chip 44 are adjacent.

[0068] One possibility is that for two memory chips connected front to front, through-holes aligned along a third direction for both chips are connected by a hybrid bonding structure (also called hyperbonding or bonding pillars), and for two memory chips connected back to back, through-holes aligned along a third direction for both chips are connected by conductive bumps (also called UBumps or microbumps).

[0069] Another possibility is that, for two memory chips connected front-to-front or back-to-back, the through-holes aligned along a third direction between them are connected by a hybrid bonding structure. In other words, the through-holes aligned along a third direction between two memory chips connected front-to-front are connected by a hybrid bonding structure, and the through-holes aligned along a third direction between two memory chips connected back-to-back are also connected by a hybrid bonding structure.

[0070] Another possibility is that, for two memory chips connected front-to-front or two memory chips connected back-to-back, the through-holes aligned along a third direction between them are connected by conductive bumps. In other words, the through-holes aligned along a third direction between two memory chips connected front-to-front are connected by conductive bumps, and the through-holes aligned along a third direction between two memory chips connected back-to-back are also connected by conductive bumps.

[0071] It should be explained that, compared to conductive bumps, front-to-front connections using a hybrid bonding structure enhance the adhesion between adjacent memory chips, and because there are essentially no gaps, the height of the chip stacking structure can be significantly reduced, which is one of the advantages of front-to-front stacking. Of course, two memory chips connected back-to-back are also connected by a hybrid bonding structure, but the connection performance is weaker than that of front-to-front connections.

[0072] In one specific embodiment, referring to Figure 7, the first region 11 in the first memory chip 41a, the second region 12 in the second memory chip 42a, the third region 13 in the third memory chip 43a, and the fourth region 14 in the fourth memory chip 44a are aligned along the third direction. The second region 12 in the first memory chip 41a, the first region 11 in the second memory chip 42a, the fourth region 14 in the third memory chip 43a, and the third region 13 in the fourth memory chip 44a are aligned along the third direction. The third region 13 in the first memory chip 41a, the fourth region 14 in the second memory chip 42a, the first region 11 in the third memory chip 43a, and the second region 12 in the fourth memory chip 44a are aligned along the third direction. The fourth region 14 in the first memory chip 41a, the third region 13 in the second memory chip 42a, the second region 12 in the third memory chip 43a, and the first region 11 in the fourth memory chip 44a are aligned along the third direction.

[0073] It should be explained that a memory chip may be divided into a high-bit transmission area and a low-bit transmission area, and the arrows in Figure 7 are uniformly located in the high-bit transmission area of ​​the memory chip.

[0074] In other words, after the first memory chip 41a is provided, the second memory chip 42a is provided on top of the first memory chip 41a in a front-to-front configuration, and the positions of the upper bit transmission area in the second memory chip 42a and the lower bit transmission area in the first memory chip 41a along the third direction are approximately the same. Then, the third memory chip 43a is provided on top of the second memory chip 42a in a back-to-back configuration, and simultaneously, the positions of the upper bit transmission area in the third memory chip 43a and the upper bit transmission area in the second memory chip 42a along the third direction are approximately the same, except that the positions of the specific devices within these two memory chips do not overlap (specifically, they exhibit a mirror image relationship). Then, the fourth memory chip 44a is provided on top of the third memory chip 43a in a front-to-front configuration, and simultaneously, the positions of the upper bit transmission area in the fourth memory chip 44a and the lower bit transmission area in the third memory chip 43a along the third direction are approximately the same. As a result, the first memory chip 41a, the second memory chip 42a, the third memory chip 43a, and the fourth memory chip 44a form a single stacked unit.

[0075] Furthermore, it should be explained that the chip stacking structure 40 may include multiple stacking units. Referring to Figure 9, after forming the first stacking unit, the fifth memory chip 45a is placed on top of the fourth memory chip 44a on back-to-back surfaces. The positions of the upper bit transmission area in the fifth memory chip 45a and the upper bit transmission area in the fourth memory chip 44a along the third direction are approximately the same, but the positions of the specific devices within these two memory chips do not overlap (specifically, they exhibit a mirror image relationship). Subsequently, the sixth memory chip 46a is placed on top of the fifth memory chip 45a in a front-to-front configuration, and it is necessary to control the positions of the upper bit transmission area in the sixth memory chip 46a and the lower bit transmission area in the fifth memory chip 45a along the third direction to be approximately the same. Then, the seventh memory chip 47a is placed on top of the sixth memory chip 46a in a back-to-back configuration, and at the same time, the positions of the upper bit transmission area in the seventh memory chip 47a and the upper bit transmission area in the sixth memory chip 46a along the third direction to be approximately the same, but the positions of the specific devices within these two memory chips do not overlap (specifically, they exhibit a mirror image relationship). Then, the eighth memory chip 48a is placed on top of the seventh memory chip 47a in a front-to-front configuration, and at the same time, the positions of the upper bit transmission area in the eighth memory chip 48a and the lower bit transmission area in the seventh memory chip 47a along the third direction to be approximately the same, thereby forming a single stacked unit. In other words, the fifth memory chip 45a of the second stacked unit can be considered as the first memory chip 41a of the first stacked unit, the sixth memory chip 46a of the second stacked unit can be considered as the second memory chip 42a of the first stacked unit, the seventh memory chip 47a of the second stacked unit can be considered as the third memory chip 43a of the first stacked unit, and the eighth memory chip 48a of the second stacked unit can be considered as the fourth memory chip 44a of the first stacked unit. Referring to Figure 8, Figure 8 is a schematic diagram of the active surface tiling of each chip of the stacked unit shown in Figure 7. In particular, the four through holes shown by dashed lines in Figure 7 are represented as four through holes enclosed by dashed lines in Figure 8.

[0076] On the other hand, referring to Figure 8, each through-hole in the first region 11 within the first memory chip 41a has the following positional characteristics.

[0077] (1) The n first through-holes D0 in the first region 11 of the first memory chip 41a, the n second through-holes D1 in the second region 12 of the second memory chip 42a, the n third through-holes D2 in the third region 13 of the third memory chip 43a, and the n fourth through-holes D3 in the fourth region 14 of the fourth memory chip 44a are aligned along the third direction.

[0078] (2) The n second through-holes D1 in the first region 11 of the first memory chip 41a, the n first through-holes D0 in the second region 12 of the second memory chip 42a, the n fourth through-holes D3 in the third region 13 of the third memory chip 43a, and the n third through-holes D2 in the fourth region 14 of the fourth memory chip 44a are aligned along the third direction.

[0079] (3) The n third through-holes D2 in the first region 11 of the first memory chip 41a, the n fourth through-holes D3 in the second region 12 of the second memory chip 42a, the n first through-holes D0 in the third region 13 of the third memory chip 43a, and the n second through-holes D1 in the fourth region 14 of the fourth memory chip 44a are aligned along the third direction.

[0080] (4) The n fourth through-holes D3 in the first region 11 of the first memory chip 41a, the n third through-holes D2 in the second region 12 of the second memory chip 42a, the n second through-holes D1 in the third region 13 of the third memory chip 43a, and the n first through-holes D0 in the fourth region 14 of the fourth memory chip 44a are aligned along the third direction.

[0081] In particular, Figures 7 and 8 show only one set of through-holes within a single region as an example. However, in reality, there are multiple sets of through-holes in each region, and through-hole sets in different regions have similar alignment characteristics. The alignment of other through-holes is not shown. Figures 7 and 8, along with the accompanying textual explanation, can be adaptively understood by referring to them.

[0082] On the other hand, each through-hole in the second region 12 within the first memory chip 41a has the following positional characteristics.

[0083] (1) The n first through-holes D0 in the second region 12 of the first memory chip 41a, the n second through-holes D1 in the first region 11 of the second memory chip 42a, the n third through-holes D2 in the fourth region 14 of the third memory chip 43a, and the n fourth through-holes D3 in the third region 13 of the fourth memory chip 44a are aligned along the third direction.

[0084] (2) The n second through-holes D1 in the second region 12 of the first memory chip 41a, the n first through-holes D0 in the first region 11 of the second memory chip 42a, the n fourth through-holes D3 in the fourth region 14 of the third memory chip 43a, and the n third through-holes D2 in the third region 13 of the fourth memory chip 44a are aligned along the third direction.

[0085] (3) The n third through-holes D2 in the second region 12 of the first memory chip 41a, the n fourth through-holes D3 in the first region 11 of the second memory chip 42a, the n first through-holes D0 in the fourth region 14 of the third memory chip 43a, and the n second through-holes D1 in the third region 13 of the fourth memory chip 44a are aligned along the third direction.

[0086] (4) The n fourth through-holes D3 in the second region 12 of the first memory chip 41a, the n third through-holes D2 in the first region 11 of the second memory chip 42a, the n second through-holes D1 in the fourth region 14 of the third memory chip 43a, and the n first through-holes D0 in the third region 13 of the fourth memory chip 44a are aligned along the third direction.

[0087] On the other hand, each through-hole in the third region 13 within the first memory chip 41a has the following positional characteristics.

[0088] (1) The n first through-holes D0 in the third region 13 of the first memory chip 41a, the n second through-holes D1 in the fourth region 14 of the second memory chip 42a, the n third through-holes D2 in the first region 11 of the third memory chip 43a, and the n fourth through-holes D3 in the second region 12 of the fourth memory chip 44a are aligned along the third direction.

[0089] (2) The n second through-holes D1 in the third region 13 of the first memory chip 41a, the n first through-holes D0 in the fourth region 14 of the second memory chip 42a, the n fourth through-holes D3 in the first region 11 of the third memory chip 43a, and the n third through-holes D2 in the second region 12 of the fourth memory chip 44a are aligned along the third direction.

[0090] (3) The n third through-holes D2 in the third region 13 of the first memory chip 41a, the n fourth through-holes D3 in the fourth region 14 of the second memory chip 42a, the n first through-holes D0 in the first region 11 of the third memory chip 43a, and the n second through-holes D1 in the second region 12 of the fourth memory chip 44a are aligned along the third direction.

[0091] (4) The n fourth through-holes D3 in the third region 13 of the first memory chip 41a, the n third through-holes D2 in the fourth region 14 of the second memory chip 42a, the n second through-holes D1 in the first region 11 of the third memory chip 43a, and the n first through-holes D0 in the second region 12 of the fourth memory chip 44a are aligned along the third direction.

[0092] Furthermore, on the other hand, each through-hole in the fourth region 14 within the first memory chip 41a has the following positional characteristics.

[0093] (1) The n first through-holes D0 in the fourth region 14 of the first memory chip 41a, the n second through-holes D1 in the third region 13 of the second memory chip 42a, the n third through-holes D2 in the second region 12 of the third memory chip 43a, and the n fourth through-holes D3 in the first region 11 of the fourth memory chip 44a are aligned along the third direction.

[0094] (2) The n second through-holes D1 in the fourth region 14 of the first memory chip 41a, the n first through-holes D0 in the third region 13 of the second memory chip 42a, the n fourth through-holes D3 in the second region 12 of the third memory chip 43a, and the n third through-holes D2 in the first region 11 of the fourth memory chip 44a are aligned along the third direction.

[0095] (3) The n third through-holes D2 in the fourth region 14 of the first memory chip 41a, the n fourth through-holes D3 in the third region 13 of the second memory chip 42a, the n first through-holes D0 in the second region 12 of the third memory chip 43a, and the n second through-holes D1 in the first region 11 of the fourth memory chip 44a are aligned along the third direction.

[0096] (4) The n fourth through-holes D3 in the fourth region 14 of the first memory chip 41a, the n third through-holes D2 in the third region 13 of the second memory chip 42a, the n second through-holes D1 in the second region 12 of the third memory chip 43a, and the n first through-holes D0 in the first region 11 of the fourth memory chip 44a are aligned along the third direction.

[0097] As described above, Figures 7 to 9 show specific chip stacking methods, and Figures 10 to 12 show other specific chip stacking methods, which will be explained in detail below.

[0098] Referring to Figure 10, the first region 11 in the first memory chip 41b, the fourth region 14 in the second memory chip 42b, the third region 13 in the third memory chip 43b, and the second region 12 in the fourth memory chip 44b are aligned along the third direction. The second region 12 in the first memory chip 41b, the third region 13 in the second memory chip 42b, the fourth region 14 in the third memory chip 43b, and the first region 11 in the fourth memory chip 44b are aligned along the first direction. The third region 13 in the first memory chip 41b, the second region 12 in the second memory chip 42b, the first region 11 in the third memory chip 43b, and the fourth region 14 in the fourth memory chip 44b are aligned along the third direction, and the fourth region 14 in the first memory chip 41b, the first region 11 in the second memory chip 42b, the second region 12 in the third memory chip 43b, and the third region 13 in the fourth memory chip 44b are aligned along the third direction.

[0099] Similarly, the arrows in Figure 10 are consistently located in the upper bit transmission area of ​​the memory chip.

[0100] In other words, the positions of the upper bit transmission area in the second memory chip 42b and the upper bit transmission area in the first memory chip 41b along the third direction are almost the same, but the positions of the specific devices within these two memory chips do not overlap (specifically, they exhibit a mirror image relationship), the positions of the upper bit transmission area in the third memory chip 43b and the lower bit transmission area in the second memory chip 42b along the third direction are almost the same, and the positions of the upper bit transmission area in the fourth memory chip 44b and the upper bit transmission area in the third memory chip 43b along the third direction are almost the same, but the positions of the specific devices within these two memory chips do not overlap (specifically, they exhibit a mirror image relationship).

[0101] Similarly, the number of stacked units may be multiple. Referring to Figure 12, after forming the first stacked unit, the fifth memory chip 45b to the eighth memory chip 48b are continuously stacked, and the positions of the upper bit transmission area in the fifth memory chip 45b and the lower bit transmission area in the fourth memory chip 44b along the third direction are approximately the same, and the positions of the upper bit transmission area in the sixth memory chip 46b and the upper bit transmission area in the fifth memory chip 45b along the third direction are approximately the same, however the positions of the specific devices in these two memory chips do not overlap (specifically, they exhibit a mirror image relationship). The positions of the upper bit transmission area in the seventh memory chip 47b and the lower bit transmission area in the sixth memory chip 46b along the third direction are approximately the same, and the positions of the upper bit transmission area in the eighth memory chip 48b and the upper bit transmission area in the seventh memory chip 47b along the third direction are approximately the same, however the positions of the specific devices in these two memory chips do not overlap (specifically, they exhibit a mirror image relationship).

[0102] Referring to Figure 11, Figure 11 is a schematic diagram of the active surface tiling of each chip in the stacked unit shown in Figure 10. In particular, the four through-holes shown as dashed lines in Figure 10 are represented as four through-holes enclosed by dashed lines in Figure 11.

[0103] On the other hand, referring to Figure 11, each through-hole in the first region 11 within the first memory chip 41b has the following positional characteristics.

[0104] (1) The n first through-holes D0 in the first region 11 of the first memory chip 41b, the n fourth through-holes D3 in the fourth region 14 of the second memory chip 42b, the n third through-holes D2 in the third region 13 of the third memory chip 43b, and the n second through-holes D1 in the second region 12 of the fourth memory chip 44b are aligned along the third direction. (2) The n second through-holes D1 in the first region 11 of the first memory chip 41b, the n third through-holes D2 in the fourth region 14 of the second memory chip 42b, the n fourth through-holes D3 in the third region 13 of the third memory chip 43b, and the n first through-holes D0 in the second region 12 of the fourth memory chip 44b are aligned along the third direction. (3) The n third through-holes D2 in the first region 11 of the first memory chip 41b, the n second through-holes D1 in the fourth region 14 of the second memory chip 42b, the n first through-holes D0 in the third region 13 of the third memory chip 43b, and the n fourth through-holes D3 in the second region 12 of the fourth memory chip 44b are aligned along the third direction. (4) The n fourth through-holes D3 in the first region 11 of the first memory chip 41b, the n first through-holes D0 in the fourth region 14 of the second memory chip 42b, the n second through-holes D1 in the third region 13 of the third memory chip 43b, and the n third through-holes D2 in the second region 12 of the fourth memory chip 44b are aligned along the third direction.

[0105] In particular, Figures 10 and 11 show only one set of through-holes within a single region as an example. However, in reality, there are multiple sets of through-holes in each region, and through-hole sets in different regions have similar alignment characteristics. The alignment of other through-holes is not shown. You can adaptively understand this by referring to Figures 10 and 11 in conjunction with the textual explanation.

[0106] On the other hand, each through-hole in the second region 12 within the first memory chip 41b has the following positional characteristics.

[0107] (1) The n first through-holes D0 in the second region 12 of the first memory chip 41b, the n fourth through-holes D3 in the third region 13 of the second memory chip 42b, the n third through-holes D2 in the fourth region 14 of the third memory chip 43b, and the n second through-holes D1 in the first region 11 of the fourth memory chip 44b are aligned along the third direction. (2) The n second through-holes D1 in the second region 12 of the first memory chip 41b, the n third through-holes D2 in the third region 13 of the second memory chip 42b, the n fourth through-holes D3 in the fourth region 14 of the third memory chip 43b, and the n first through-holes D0 in the first region 11 of the fourth memory chip 44b are aligned along the third direction. (3) The n third through-holes D2 in the second region 12 of the first memory chip 41b, the n second through-holes D1 in the third region 13 of the second memory chip 42b, the n first through-holes D0 in the fourth region 14 of the third memory chip 43b, and the n fourth through-holes D3 in the first region 11 of the fourth memory chip 44b are aligned along the third direction. (4) The n fourth through-holes D3 in the second region 12 of the first memory chip 41b, the n first through-holes D0 in the third region 13 of the second memory chip 42b, the n second through-holes D1 in the fourth region 14 of the third memory chip 43b, and the n third through-holes D2 in the first region 11 of the fourth memory chip 44b are aligned along the third direction.

[0108] On the other hand, each through-hole in the third region 13 within the first memory chip 41b has the following positional characteristics.

[0109] (1) The n first through-holes D0 in the third region 13 of the first memory chip 41b, the n fourth through-holes D3 in the second region 12 of the second memory chip 42b, the n third through-holes D2 in the first region 11 of the third memory chip 43b, and the n second through-holes D1 in the fourth region 14 of the fourth memory chip 44b are aligned along the third direction. (2) The n second through-holes D1 in the third region 13 of the first memory chip 41b, the n third through-holes D2 in the second region 12 of the second memory chip 42b, the n fourth through-holes D3 in the first region 11 of the third memory chip 43b, and the n first through-holes D0 in the fourth region 14 of the fourth memory chip 44b are aligned along the third direction. (3) The n third through-holes D2 in the third region 13 of the first memory chip 41b, the n second through-holes D1 in the second region 12 of the second memory chip 42b, the n first through-holes D0 in the first region 11 of the third memory chip 43b, and the n fourth through-holes D3 in the fourth region 14 of the fourth memory chip 44b are aligned along the third direction. (4) The n fourth through-holes D3 in the third region 13 of the first memory chip 41b, the n first through-holes D0 in the second region 12 of the second memory chip 42b, the n second through-holes D1 in the first region 11 of the third memory chip 43b, and the n third through-holes D2 in the fourth region 14 of the fourth memory chip 44b are aligned along the third direction.

[0110] Furthermore, on the other hand, each through-hole in the fourth region 14 within the first memory chip 41b has the following positional characteristics.

[0111] (1) The n first through-holes D0 in the fourth region 14 of the first memory chip 41b, the n fourth through-holes D3 in the first region 11 of the second memory chip 42b, the n third through-holes D2 in the second region 12 of the third memory chip 43b, and the n second through-holes D1 in the third region 13 of the fourth memory chip 44b are aligned along the third direction. (2) The n second through-holes D1 in the fourth region 14 of the first memory chip 41b, the n third through-holes D2 in the first region 11 of the second memory chip 42b, the n fourth through-holes D3 in the second region 12 of the third memory chip 43b, and the n first through-holes D0 in the third region 13 of the fourth memory chip 44b are aligned along the third direction. (3) The n third through-holes D2 in the fourth region 14 of the first memory chip 41b, the n second through-holes D2 in the first region 11 of the second memory chip 42b, the n first through-holes D0 in the second region 12 of the third memory chip 43b, and the n fourth through-holes D3 in the third region 13 of the fourth memory chip 44b are aligned along the third direction. (4) The n fourth through-holes D3 in the fourth region 14 of the first memory chip 41b, the n first through-holes D0 in the first region 11 of the second memory chip 42b, the n second through-holes D1 in the second region 12 of the third memory chip 43b, and the n third through-holes D2 in the third region 13 of the fourth memory chip 44b are aligned along the third direction.

[0112] In this way, the chip stacking structures shown in Figures 10 to 12 also satisfy the usage requirements.

[0113] In some embodiments, referring to Figures 13 and 14, Figures 13 and 14 are schematic diagrams of signal transmission in the chip stacking structure 40. In particular, Figure 13 corresponds to the chip stacking structure shown in Figure 7, and Figure 14 corresponds to the chip stacking structure shown in Figure 10. In particular, in the following description, the first memory chip 41 may refer to the first memory chip 41a or the first memory chip 41b, and the same applies to other memory chips.

[0114] As shown in Figure 13 or Figure 14, each memory chip further includes 4n first drive circuits 30 (only one per memory chip is shown in Figure 13), and in each memory chip, the 4n first drive circuits 30 are connected one-to-one to the first ends of 4n first through holes D0, where the first ends are located on the active surface of the memory chip.

[0115] In other words, in any of the first memory chip 41, second memory chip 42, third memory chip 43, or fourth memory chip 44, the first drive circuit 30 within it is connected to the first through-hole D0. That is, the first memory chip 41, second memory chip 42, third memory chip 43, or fourth memory chip 44 employs exactly the same structure.

[0116] In some embodiments, referring to Figures 9 and 12, the chip stacking structure 40 further includes logic chips 50, where the first stacking unit is stacked on top of the logic chips 50 along a third direction, and the other stacking units are sequentially stacked on top of the previous stacking unit along the third direction. Here, the stacking between the first memory chip and the logic chips 50 is back-to-front, or back-to-back between the first memory chip and the logic chips 50.

[0117] Referring to Figures 13 and 14, the logic chip 50 includes 16n fifth through-holes 502 and 16n second drive circuits 501.

[0118] Of the 16n fifth through-holes 502, 4n fifth through-holes 502 are aligned in a one-to-one correspondence along the third direction with 4n first through-holes D0 in the first memory chip 41, 4n fifth through-holes 502 are aligned in a one-to-one correspondence along the third direction with 4n second through-holes D1 in the first memory chip 41, 4n fifth through-holes 502 are aligned in a one-to-one correspondence along the third direction with 4n third through-holes D2 in the first memory chip 41, and 4n fifth through-holes 502 are aligned in a one-to-one correspondence along the third direction with 4n fourth through-holes D3 in the first memory chip 41. The 16n second drive circuits 501 are connected one-to-one to the first ends of the 16n fifth through holes 502, the first ends of which are located on the active side of the logic chip 50.

[0119] In other words, although the through-holes in the logic chip 50 and the aforementioned memory chip 10 are located in the same positions, each through-hole in the logic chip 50 is connected to a single drive circuit.

[0120] It should be explained that Figures 13 and 14 are abstract circuit principle diagrams, and the drive circuit is only shown next to the through-holes to which it is connected. The connection relationships are not specifically depicted, and can be understood adaptively in conjunction with the textual explanation.

[0121] The chip stacking structure 40 further includes 16n electrical passages, one fifth through-hole, at least one first through-hole D0, at least one second through-hole D1, at least one third through-hole D2, and at least one fourth through-hole D3, which are aligned along a third direction and connected to form one electrical passage.

[0122] It should be explained that when the chip stacking structure 40 contains m stacking units, one fifth through-hole 502, m first through-holes D0, m second through-holes D1, m third through-holes D2, and m fourth through-holes D3, which are aligned along the third direction, are connected to form a single electrical passage, where m is a positive integer.

[0123] In this way, referring to Figure 13 or Figure 14, the input output signal I / O_CH0 of channel CH0 is transmitted through "through hole 502 in the logic chip, through hole D0 in memory chip 0 - through hole D1 in memory chip 1 - through hole D2 in memory chip 2 - through hole D3 in memory chip 3 - through hole D0 in memory chip 4 - through hole D1 in memory chip 5 - through hole D2 in memory chip 6 - through hole D3 in memory chip 7", and other signals are transmitted similarly. At this time, the first memory chip 41 acquires the input output signal I / O_CH0 through the input terminal of its own through hole D0, the second memory chip 42 acquires the input output signal I / O_CH1 through the input terminal of its own through hole D0, the third memory chip 43 acquires the input output signal I / O_CH4 through the input terminal of its own through hole D0, the fourth memory chip 44 acquires the input output signal I / O_CH5 through the input terminal of its own through hole D0, and so on. In other words, referring to Figure 13 or Figure 14, from a physical standpoint, the through-holes within the chip stacking structure 40 are still direct connection structures, but from the perspective of the absolute position of the through-holes on the active surface, the through-holes within it can be considered a functional rotational structure. That is, the physical direct connection structure realizes the signal transmission effect shown in Figure 2 (i.e., through-hole D0 - through-hole D1 - through-hole D2 - through-hole D3... such a rotational transmission effect). Simply put, while a lateral interconnection structure is essential in the physical helical structure of the chip stacking structure in Figure 2, the chip stacking structure in Figure 13 or Figure 14 is a physical direct connection structure, does not require a lateral interconnection structure, parasitic resistance is greatly reduced, and transmission speed and transmission performance are greatly improved.

[0124] In one embodiment, the general manufacturing process for the chip stacking structure 40 is as follows.

[0125] In step S801, a wafer is provided.

[0126] In step S802, the wafer is divided into multiple chip regions, and the main body structure of the memory chip is formed in each chip region.

[0127] In step S803, the wafer is cut to obtain a plurality of memory chips.

[0128] In step S804, 4m memory chips and one logic chip are aligned along a third direction (the alignment rules are as described above), a conductive bump and / or hybrid bonding structure is formed between the two chips, and a single chip stacked structure 40 is formed.

[0129] In another embodiment, the schematic manufacturing process for the chip stacking structure 40 is as follows:

[0130] In step S901, 4m wafers are provided.

[0131] In step S902, each wafer is divided into multiple chip regions, and the main structure of the memory chip described above is formed in each chip region.

[0132] In step S903, 4m of the wafers are aligned along the third direction (the alignment rules are as described above) to form conductive bumps and / or hybrid bonding structures between two adjacent wafers.

[0133] It should be explained that for two adjacent wafers, there are multiple pairs of memory chips aligned along a third direction, and a conductive bump and / or hybrid bonding structure is formed for each pair of memory chips aligned along the third direction.

[0134] In step S904, 4m wafers are cut to obtain multiple pre-lamination structures.

[0135] In step S905, multiple pre-stacked structures and multiple logic chips are assembled in correspondence to form multiple chip stacked structures 40.

[0136] Furthermore, in another embodiment, the schematic manufacturing process for the chip stacking structure 40 is as follows:

[0137] In step S1001, 4m+1 wafers are provided.

[0138] In step S1002, each wafer is divided into multiple chip regions, the main body structure of the memory chip described above is formed in each chip region within 4m wafers, and the main body structure of the logic chip described above is formed in each chip region within one wafer.

[0139] In step S1003, 4m+1 wafers are aligned along the third direction (the alignment rules are as described above) to form conductive bumps and / or hybrid bonding structures between two adjacent wafers.

[0140] It should be explained that for two adjacent wafers, there are multiple pairs of memory chips aligned along a third direction, and a conductive bump and / or hybrid bonding structure is formed for each pair of memory chips aligned along the third direction.

[0141] In step S1004, 4m+1 wafers are cut to obtain multiple chip stacked structures 40.

[0142] As can be seen from the above, the memory chip according to the embodiment of this disclosure not only reduces parasitic capacitance by reducing the number of drive circuits and data selector settings, but also, the chip stacking structure formed by the memory chip achieves a signal rotation transmission effect through a direct connection structure of through holes and reduces parasitic resistance. Simulation experiments have shown that the stacking structure provided by this embodiment of this disclosure has approximately 7% less parasitic capacitance and approximately 95% less parasitic resistance than the structure shown in Figure 2. As a result, it becomes possible to stack more chips and the signal transmission quality is improved.

[0143] In yet another embodiment of the present disclosure, referring to Figure 15, which is a schematic diagram showing the configuration of a memory 70 according to an embodiment of the present disclosure. As shown in Figure 15, the memory 70 includes at least the aforementioned chip stacking structure 40.

[0144] The foregoing are merely preferred embodiments of the Disclosure and are not intended to limit the scope of protection of the Disclosure. It should be noted that in this Specification, the terms “equipment,” “include,” or any other variation thereof are intended to encompass non-exclusive inclusion, thereby including not only those elements but also other elements not expressly enumerated, or elements specific to such process, method, article, or apparatus. Unless otherwise specified, elements defined in the expression “includes…” do not preclude the existence of other identical elements in a process, method, article, or apparatus that includes that element. The sequence numbers of the embodiments of the Disclosure above are for illustrative purposes only and do not indicate any hierarchy of the embodiments. The methods disclosed in the embodiments of some methods provided in this Disclosure can be combined in any way without contradiction to obtain new embodiments of the methods. The features disclosed in the embodiments of some products provided in this Disclosure can be combined in any way without contradiction to obtain new embodiments of the products. The features disclosed in the embodiments of some methods or apparatus provided in this Disclosure can be combined in any way without contradiction to obtain new embodiments of the methods or apparatus. The above describes only specific embodiments of the Disclosure, and the scope of protection of the Disclosure is not limited thereto. Any modifications or substitutions that a person skilled in the art could easily conceive of within the technical scope disclosed herein should be included within the scope of protection of the Disclosure. Accordingly, the scope of protection of the Disclosure shall be subject to the scope of protection of the claims. [Industrial applicability]

[0145] The embodiments of this disclosure provide a memory chip, a chip stacking structure, and a memory, which not only reduce parasitic capacitance by reducing the number of drive circuits and data selector settings, but also achieve a signal rotation transmission effect through a direct connection structure of through holes in the chip stacking structure formed by the memory chip, thereby reducing parasitic resistance.

Claims

1. A memory chip (10), wherein the memory chip (10) includes 2 × 2 regions distributed in an array along the active surface of the memory chip (10), and each region is penetrated by a set of n through holes (20), where n is a natural number. The n through-hole sets (20) in the first region (11) and the n through-hole sets (20) in the second region (12) are symmetric with respect to the first axis (AA'), the n through-hole sets (20) in the third region (13) and the n through-hole sets (20) in the fourth region (14) are symmetric with respect to the first axis (AA'), the n through-hole sets (20) in the first region (11) and the n through-hole sets (20) in the fourth region (14) are symmetric with respect to the second axis (BB'), the first axis (AA') and the second axis (BB') are both located on the active plane, the first axis (AA') and the second axis (BB') are perpendicular to each other and intersect at the center of the active plane, Each of the through-hole sets (20) includes 2 × 2 through-holes distributed in an array, the first through-hole (D0) and the second through-hole (D1) are symmetric with respect to the third axis (CC'), the third through-hole (D2) and the fourth through-hole (D3) are symmetric with respect to the third axis (CC'), the first through-hole (D0) and the fourth through-hole (D3) are symmetric with respect to the fourth axis (DD'), both the third axis (CC') and the fourth axis (DD') are located on the active surface, the third axis (CC') and the fourth axis (DD') are perpendicular to each other and intersect at the center of the through-hole set (20), The first axis (AA') and the third axis (CC') of each through-hole set (20) are both parallel to the first side of the memory chip (10), and the second axis (BB') and the fourth axis (DD') of each through-hole set (20) are both parallel to the second side of the memory chip (10). The n first through holes (D0) in the first region (11) and the n second through holes (D1) in the second region (12) are symmetric with respect to the first axis (AA'), The n third through holes (D2) in the third region (13) and the n fourth through holes (D3) in the fourth region (14) are symmetric with respect to the first axis (AA'), The n first through holes (D0) in the first region (11) and the n fourth through holes (D3) in the fourth region (14) are symmetric with respect to the second axis (BB'), The n second through holes (D1) in the first region (11) and the n first through holes (D0) in the second region (12) are symmetric with respect to the first axis (AA'), The n fourth through holes (D3) in the third region (13) and the n third through holes (D2) in the fourth region (14) are symmetric with respect to the first axis (AA'), The n second through holes (D1) in the first region (11) and the n third through holes (D2) in the fourth region (14) are symmetric with respect to the second axis (BB'), The n third through holes (D2) in the first region (11) and the n fourth through holes (D3) in the second region (12) are symmetric with respect to the first axis (AA'), The n first through holes (D0) in the third region (13) and the n second through holes (D1) in the fourth region (14) are symmetric with respect to the first axis (AA'), The n third through holes (D2) in the first region (11) and the n second through holes (D1) in the fourth region (14) are symmetric with respect to the second axis (BB'), The n fourth through holes (D3) in the first region (11) and the n third through holes (D2) in the second region (12) are symmetric with respect to the first axis (AA'), The n second through holes (D1) in the third region (13) and the n first through holes (D0) in the fourth region (14) are symmetric with respect to the first axis (AA'), The n fourth through holes (D3) in the first region (11) and the n first through holes (D0) in the fourth region (14) are symmetric with respect to the second axis (BB'). Memory chip (10).

2. The memory chip (10) further includes 4n first drive circuits (30), The 4n through holes are connected to the 4n first drive circuits (30) in a one-to-one correspondence, and only one through hole in each through hole set (20) is connected to the first drive circuit (30). The memory chip (10) further includes a positioning structure, The positioning structure indicates the location of the reference region by being positioned within the reference region, and the reference region is one of the 2x2 regions. The memory chip (10) according to claim 1.

3. A memory chip (10), wherein the memory chip (10) includes 2 × 2 regions distributed in an array along the active surface of the memory chip (10), and each region is penetrated by a set of n through holes (20), where n is a natural number. The n through-hole sets (20) in the first region (11) and the n through-hole sets (20) in the second region (12) are symmetric with respect to the first axis (AA'), the n through-hole sets (20) in the third region (13) and the n through-hole sets (20) in the fourth region (14) are symmetric with respect to the first axis (AA'), the n through-hole sets (20) in the first region (11) and the n through-hole sets (20) in the fourth region (14) are symmetric with respect to the second axis (BB'), the first axis (AA') and the second axis (BB') are both located on the active plane, the first axis (AA') and the second axis (BB') are perpendicular to each other and intersect at the center of the active plane, Each of the through-hole sets (20) includes 2 × 2 through-holes distributed in an array, the first through-hole (D0) and the second through-hole (D1) are symmetric with respect to the third axis (CC'), the third through-hole (D2) and the fourth through-hole (D3) are symmetric with respect to the third axis (CC'), the first through-hole (D0) and the fourth through-hole (D3) are symmetric with respect to the fourth axis (DD'), both the third axis (CC') and the fourth axis (DD') are located on the active surface, the third axis (CC') and the fourth axis (DD') are perpendicular to each other and intersect at the center of the through-hole set (20), The first axis (AA') and the third axis (CC') of each through-hole set (20) are both parallel to the first side of the memory chip (10), and the second axis (BB') and the fourth axis (DD') of each through-hole set (20) are both parallel to the second side of the memory chip (10). The memory chip (10) further includes 4n first drive circuits (30), The 4n through holes are connected to the 4n first drive circuits (30) in a one-to-one correspondence, and only one through hole in each through hole set (20) is connected to the first drive circuit (30). Memory chip (10).

4. A memory chip (10), wherein the memory chip (10) includes 2 × 2 regions distributed in an array along the active surface of the memory chip (10), each region being penetrated by a set of n through holes (20), where n is a natural number. The n through-hole sets (20) in the first region (11) and the n through-hole sets (20) in the second region (12) are symmetric with respect to the first axis (AA'), the n through-hole sets (20) in the third region (13) and the n through-hole sets (20) in the fourth region (14) are symmetric with respect to the first axis (AA'), the n through-hole sets (20) in the first region (11) and the n through-hole sets (20) in the fourth region (14) are symmetric with respect to the second axis (BB'), the first axis (AA') and the second axis (BB') are both located on the active plane, the first axis (AA') and the second axis (BB') are perpendicular to each other and intersect at the center of the active plane, Each of the through-hole sets (20) includes 2 × 2 through-holes distributed in an array, the first through-hole (D0) and the second through-hole (D1) are symmetric with respect to the third axis (CC'), the third through-hole (D2) and the fourth through-hole (D3) are symmetric with respect to the third axis (CC'), the first through-hole (D0) and the fourth through-hole (D3) are symmetric with respect to the fourth axis (DD'), both the third axis (CC') and the fourth axis (DD') are located on the active surface, the third axis (CC') and the fourth axis (DD') are perpendicular to each other and intersect at the center of the through-hole set (20), The first axis (AA') and the third axis (CC') of each through-hole set (20) are both parallel to the first side of the memory chip (10), and the second axis (BB') and the fourth axis (DD') of each through-hole set (20) are both parallel to the second side of the memory chip (10). The memory chip (10) further includes a positioning structure, The positioning structure indicates the location of the reference region by being positioned within the reference region, and the reference region is one of the 2x2 regions. Memory chip (10).

5. A chip stacking structure (40), wherein the chip stacking structure (40) includes at least one stacking unit, each of which includes a first memory chip (41, 41a, 41b), a second memory chip (42, 42a, 42b), a third memory chip (43, 43a, 43b), and a fourth memory chip (44, 44a, 44b) sequentially stacked along a third direction, the third direction being perpendicular to the active plane of each of the memory chips, and each of the first memory chip (41, 41a, 41b), the second memory chip (42, 42a, 42b), the third memory chip (43, 43a, 43b), and the fourth memory chip (44, 44a, 44b) is a memory chip (10) according to claim 1, 3, or 4. A chip stacking structure (40) in which the first memory chips (41, 41a, 41b) and the second memory chips (42, 42a, 42b) are stacked face to face, the second memory chips (42, 42a, 42b) and the third memory chips (43, 43a, 43b) are stacked back to back, and the third memory chips (43, 43a, 43b) and the fourth memory chips (44, 44a, 44b) are stacked face to face.

6. The first region (11) in the first memory chip (41, 41a, 41b), the second region (12) in the second memory chip (42, 42a, 42b), the third region (13) in the third memory chip (43, 43a, 43b), and the fourth region (14) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The second region (12) in the first memory chip (41, 41a, 41b), the first region (11) in the second memory chip (42, 42a, 42b), the fourth region (14) in the third memory chip (43, 43a, 43b), and the third region (13) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The third region (13) in the first memory chip (41, 41a, 41b), the fourth region (14) in the second memory chip (42, 42a, 42b), the first region (11) in the third memory chip (43, 43a, 43b), and the second region (12) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The fourth region (14) in the first memory chip (41, 41a, 41b), the third region (13) in the second memory chip (42, 42a, 42b), the second region (12) in the third memory chip (43, 43a, 43b), and the first region (11) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The chip stacking structure (40) according to claim 5.

7. The n first through-holes (D0) in the first region (11) of the first memory chip (41, 41a, 41b), the n second through-holes (D1) in the second region (12) of the second memory chip (42, 42a, 42b), the n third through-holes (D2) in the third region (13) of the third memory chip (43, 43a, 43b), and the n fourth through-holes (D3) in the fourth region (14) of the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n second through-holes (D1) in the first region (11) of the first memory chip (41, 41a, 41b), the n first through-holes (D0) in the second region (12) of the second memory chip (42, 42a, 42b), the n fourth through-holes (D3) in the third region (13) of the third memory chip (43, 43a, 43b), and the n third through-holes (D2) in the fourth region (14) of the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n third through-holes (D2) in the first region (11) of the first memory chip (41, 41a, 41b), the n fourth through-holes (D3) in the second region (12) of the second memory chip (42, 42a, 42b), the n first through-holes (D0) in the third region (13) of the third memory chip (43, 43a, 43b), and the n second through-holes (D1) in the fourth region (14) of the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n fourth through-holes (D3) in the first region (11) of the first memory chip (41, 41a, 41b), the n third through-holes (D2) in the second region (12) of the second memory chip (42, 42a, 42b), the n second through-holes (D1) in the third region (13) of the third memory chip (43, 43a, 43b), and the n first through-holes (D0) in the fourth region (14) of the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n first through-holes (D0) in the second region (12) within the first memory chip (41, 41a, 41b), the n second through-holes (D1) in the first region (11) within the second memory chip (42, 42a, 42b), the n third through-holes (D2) in the fourth region (14) within the third memory chip (43, 43a, 43b), and the n fourth through-holes (D3) in the third region (13) within the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n second through-holes (D1) in the second region (12) within the first memory chip (41, 41a, 41b), the n first through-holes (D0) in the first region (11) within the second memory chip (42, 42a, 42b), the n fourth through-holes (D3) in the fourth region (14) within the third memory chip (43, 43a, 43b), and the n third through-holes (D2) in the third region (13) within the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n third through-holes (D2) in the second region (12) within the first memory chip (41, 41a, 41b), the n fourth through-holes (D3) in the first region (11) within the second memory chip (42, 42a, 42b), the n first through-holes (D0) in the fourth region (14) within the third memory chip (43, 43a, 43b), and the n second through-holes (D1) in the third region (13) within the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n fourth through-holes (D3) in the second region (12) within the first memory chip (41, 41a, 41b), the n third through-holes (D2) in the first region (11) within the second memory chip (42, 42a, 42b), the n second through-holes (D1) in the fourth region (14) within the third memory chip (43, 43a, 43b), and the n first through-holes (D0) in the third region (13) within the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n first through-holes (D0) in the third region (13) within the first memory chip (41, 41a, 41b), the n second through-holes (D1) in the fourth region (14) within the second memory chip (42, 42a, 42b), the n third through-holes (D2) in the first region (11) within the third memory chip (43, 43a, 43b), and the n fourth through-holes (D3) in the second region (12) within the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n second through-holes (D1) in the third region (13) within the first memory chip (41, 41a, 41b), the n first through-holes (D0) in the fourth region (14) within the second memory chip (42, 42a, 42b), the n fourth through-holes (D3) in the first region (11) within the third memory chip (43, 43a, 43b), and the n third through-holes (D2) in the second region (12) within the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n third through-holes (D2) in the third region (13) within the first memory chip (41, 41a, 41b), the n fourth through-holes (D3) in the fourth region (14) within the second memory chip (42, 42a, 42b), the n first through-holes (D0) in the first region (11) within the third memory chip (43, 43a, 43b), and the n second through-holes (D1) in the second region (12) within the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n fourth through-holes (D3) in the third region (13) within the first memory chip (41, 41a, 41b), the n third through-holes (D2) in the fourth region (14) within the second memory chip (42, 42a, 42b), the n second through-holes (D1) in the first region (11) within the third memory chip (43, 43a, 43b), and the n first through-holes (D0) in the second region (12) within the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n first through-holes (D0) in the fourth region (14) within the first memory chip (41, 41a, 41b), the n second through-holes (D1) in the third region (13) within the second memory chip (42, 42a, 42b), the n third through-holes (D2) in the second region (12) within the third memory chip (43, 43a, 43b), and the n fourth through-holes (D3) in the first region (11) within the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n second through-holes (D1) in the fourth region (14) within the first memory chip (41, 41a, 41b), the n first through-holes (D0) in the third region (13) within the second memory chip (42, 42a, 42b), the n fourth through-holes (D3) in the second region (12) within the third memory chip (43, 43a, 43b), and the n third through-holes (D2) in the first region (11) within the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n third through-holes (D2) in the fourth region (14) within the first memory chip (41, 41a, 41b), the n fourth through-holes (D3) in the third region (13) within the second memory chip (42, 42a, 42b), the n first through-holes (D0) in the second region (12) within the third memory chip (43, 43a, 43b), and the n second through-holes (D1) in the first region (11) within the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n fourth through-holes (D3) in the fourth region (14) within the first memory chip (41, 41a, 41b), the n third through-holes (D2) in the third region (13) within the second memory chip (42, 42a, 42b), the n second through-holes (D1) in the second region (12) within the third memory chip (43, 43a, 43b), and the n first through-holes (D0) in the first region (11) within the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The chip stacking structure (40) according to claim 6.

8. The first region (11) in the first memory chip (41, 41a, 41b), the fourth region (14) in the second memory chip (42, 42a, 42b), the third region (13) in the third memory chip (43, 43a, 43b), and the second region (12) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The second region (12) in the first memory chip (41, 41a, 41b), the third region (13) in the second memory chip (42, 42a, 42b), the fourth region (14) in the third memory chip (43, 43a, 43b), and the first region (11) in the fourth memory chip (44, 44a, 44b) are aligned along the first direction. The third region (13) in the first memory chip (41, 41a, 41b), the second region (12) in the second memory chip (42, 42a, 42b), the first region (11) in the third memory chip (43, 43a, 43b), and the fourth region (14) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The fourth region (14) in the first memory chip (41, 41a, 41b), the first region (11) in the second memory chip (42, 42a, 42b), the second region (12) in the third memory chip (43, 43a, 43b), and the third region (13) in the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The chip stacking structure (40) according to claim 5.

9. The n first through-holes (D0) in the first region (11) of the first memory chip (41, 41a, 41b), the n fourth through-holes (D3) in the fourth region (14) of the second memory chip (42, 42a, 42b), the n third through-holes (D2) in the third region (13) of the third memory chip (43, 43a, 43b), and the n second through-holes (D1) in the second region (12) of the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n second through-holes (D1) in the first region (11) of the first memory chip (41, 41a, 41b), the n third through-holes (D2) in the fourth region (14) of the second memory chip (42, 42a, 42b), the n fourth through-holes (D3) in the third region (13) of the third memory chip (43, 43a, 43b), and the n first through-holes (D0) in the second region (12) of the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n third through-holes (D2) in the first region (11) of the first memory chip (41, 41a, 41b), the n second through-holes (D1) in the fourth region (14) of the second memory chip (42, 42a, 42b), the n first through-holes (D0) in the third region (13) of the third memory chip (43, 43a, 43b), and the n fourth through-holes (D3) in the second region (12) of the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n fourth through-holes (D3) in the first region (11) of the first memory chip (41, 41a, 41b), the n first through-holes (D0) in the fourth region (14) of the second memory chip (42, 42a, 42b), the n second through-holes (D1) in the third region (13) of the third memory chip (43, 43a, 43b), and the n third through-holes (D2) in the second region (12) of the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n first through-holes (D0) in the second region (12) within the first memory chip (41, 41a, 41b), the n fourth through-holes (D3) in the third region (13) within the second memory chip (42, 42a, 42b), the n third through-holes (D2) in the fourth region (14) within the third memory chip (43, 43a, 43b), and the n second through-holes (D1) in the first region (11) within the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n second through-holes (D1) in the second region (12) within the first memory chip (41, 41a, 41b), the n third through-holes (D2) in the third region (13) within the second memory chip (42, 42a, 42b), the n fourth through-holes (D3) in the fourth region (14) within the third memory chip (43, 43a, 43b), and the n first through-holes (D0) in the first region (11) within the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n third through-holes (D2) in the second region (12) within the first memory chip (41, 41a, 41b), the n second through-holes (D1) in the third region (13) within the second memory chip (42, 42a, 42b), the n first through-holes (D0) in the fourth region (14) within the third memory chip (43, 43a, 43b), and the n fourth through-holes (D3) in the first region (11) within the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n fourth through-holes (D3) in the second region (12) within the first memory chip (41, 41a, 41b), the n first through-holes (D0) in the third region (13) within the second memory chip (42, 42a, 42b), the n second through-holes (D1) in the fourth region (14) within the third memory chip (43, 43a, 43b), and the n third through-holes (D2) in the first region (11) within the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n first through-holes (D0) in the third region (13) of the first memory chip (41, 41a, 41b), the n fourth through-holes (D3) in the second region (12) of the second memory chip (42, 42a, 42b), the n third through-holes (D2) in the first region (11) of the third memory chip (43, 43a, 43b), and the n second through-holes (D1) in the fourth region (14) of the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n second through-holes (D1) in the third region (13) within the first memory chip (41, 41a, 41b), the n third through-holes (D2) in the second region (12) within the second memory chip (42, 42a, 42b), the n fourth through-holes (D3) in the first region (11) within the third memory chip (43, 43a, 43b), and the n first through-holes (D0) in the fourth region (14) within the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n third through-holes (D2) in the third region (13) within the first memory chip (41, 41a, 41b), the n second through-holes (D1) in the second region (12) within the second memory chip (42, 42a, 42b), the n first through-holes (D0) in the first region (11) within the third memory chip (43, 43a, 43b), and the n fourth through-holes (D3) in the fourth region (14) within the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n fourth through-holes (D3) in the third region (13) of the first memory chip (41, 41a, 41b), the n first through-holes (D0) in the second region (12) of the second memory chip (42, 42a, 42b), the n second through-holes (D1) in the first region (11) of the third memory chip (43, 43a, 43b), and the n third through-holes (D2) in the fourth region (14) of the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n first through-holes (D0) in the fourth region (14) within the first memory chip (41, 41a, 41b), the n fourth through-holes (D3) in the first region (11) within the second memory chip (42, 42a, 42b), the n third through-holes (D2) in the second region (12) within the third memory chip (43, 43a, 43b), and the n second through-holes (D1) in the third region (13) within the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n second through-holes (D1) in the fourth region (14) within the first memory chip (41, 41a, 41b), the n third through-holes (D2) in the first region (11) within the second memory chip (42, 42a, 42b), the n fourth through-holes (D3) in the second region (12) within the third memory chip (43, 43a, 43b), and the n first through-holes (D0) in the third region (13) within the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n third through-holes (D2) in the fourth region (14) within the first memory chip (41, 41a, 41b), the n second through-holes (D1) in the first region (11) within the second memory chip (42, 42a, 42b), the n first through-holes (D0) in the second region (12) within the third memory chip (43, 43a, 43b), and the n fourth through-holes (D3) in the third region (13) within the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The n fourth through-holes (D3) in the fourth region (14) of the first memory chip (41, 41a, 41b), the n first through-holes (D0) in the first region (11) of the second memory chip (42, 42a, 42b), the n second through-holes (D1) in the second region (12) of the third memory chip (43, 43a, 43b), and the n third through-holes (D2) in the third region (13) of the fourth memory chip (44, 44a, 44b) are aligned along the third direction. The chip stacking structure (40) according to claim 8.

10. For two memory chips connected front to front, through-holes aligned along a third direction are connected by a hybrid bonding structure; for two memory chips connected back to back, through-holes aligned along a third direction are connected by conductive bumps, or For two memory chips connected front-to-front or back-to-back, the through-holes aligned along the third direction of both are connected by a hybrid bonding structure, or For two memory chips connected front-to-front or back-to-back, the through-holes aligned along a third direction are all connected by conductive bumps. The chip stacking structure (40) according to claim 5.

11. Each of the memory chips further includes 4n first drive circuits (30), In each of the memory chips, the 4n first drive circuits (30) are connected in a one-to-one correspondence to the first ends of the 4n first through holes (D0), and the first ends of the first through holes (D0) are located on the active surface of the memory chip. The chip stacking structure (40) according to claim 10.

12. The chip stacking structure (40) further includes logic chips (50), the first stacking unit being stacked on the logic chips (50) along a third direction, and the other stacking units being sequentially stacked on the previous stacking unit along the third direction. The logic chip (50) includes 16n fifth through-holes (502) and 16n second drive circuits (501), the 4n fifth through-holes (502) are aligned one-to-one with the 4n first through-holes (D0) in the first memory chip (41, 41a, 41b) along the third direction, and the 4n fifth through-holes (502) are aligned one-to-one with the 4n second through-holes (D1) in the first memory chip (41, 41a, 41b) along the third direction. The 4n fifth through holes (502) exhibit a one-to-one alignment along the direction, and the 4n third through holes (D2) in the first memory chip (41, 41a, 41b) exhibit a one-to-one alignment along the third direction, and the 4n fifth through holes (502) exhibit a one-to-one alignment along the third direction with the 4n fourth through holes (D3) in the first memory chip (41, 41a, 41b), The 16n second drive circuits (501) are connected one-to-one to the first ends of the 16n fifth through holes (502), and the first ends of the fifth through holes (502) are located on the active surface of the logic chip (50). The chip stacking structure (40) according to claim 11.

13. The chip stacking structure (40) further includes 16n electrical pathways, When the chip stacking structure (40) includes m stacking units, one fifth through-hole (502), m first through-holes (D0), m second through-holes (D1), m third through-holes (D2), and m fourth through-holes (D3) that are aligned along the third direction are connected to form one electrical passage, where m is a positive integer. The chip stacking structure (40) according to claim 12.

14. A memory comprising the chip stacking structure (40) described in claim 5.

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