Semiconductor equipment

Abstract

To provide a semiconductor device in which a parasitic inductance is reduced and a parasitic resistance is reduced.SOLUTION: A semiconductor device A1 includes: a semiconductor element 1; a semiconductor element 2; a control element 3; a leadframe 4 including a plurality of leads; a wire 5B bonded to a source electrode 12 of the semiconductor element 1; and a wire 5C bonded to a drain electrode 21 of the semiconductor element 2. The plurality of leads include a lead 4A on which the semiconductor element 1 is mounted, a lead 4B on which the semiconductor element 2 is mounted, and a lead 4C on which the control element 3 is mounted. The lead 4A and the lead 4B overlap with each other as viewed in an x direction, and the lead 4C overlaps with both the lead 4A and the lead 4B as viewed in a y direction. The lead 4A includes a die pad portion 411 to which the semiconductor element 1 is bonded, and a bonding portion 412 to which the wire 5B is bonded. The bonding portion 412 is located between the semiconductor element 1 and the semiconductor element 2 as viewed in a z direction, and the wire 5C is bonded thereto.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device equipped with multiple semiconductor elements. [Background technology]

[0002] Conventionally, semiconductor devices are known in which multiple semiconductor elements are molded in a single resin material. Such semiconductor devices are called system-in-package devices. Patent Document 1 discloses a semiconductor device that packages two switching elements and a control IC into one package. The control IC is a semiconductor element that controls each switching element. Each switching element performs switching operations in response to signals from the control IC. Such semiconductor devices are mounted on circuit boards of electronic devices, for example, and used in power supply circuits such as DC / DC converters. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2003-218309 [Overview of the project] [Problems that the invention aims to solve]

[0004] In recent years, with the increasing energy efficiency and performance of electronic devices, semiconductor devices are required to reduce power consumption and improve the responsiveness of switching operations. Reducing parasitic inductance and parasitic resistance are effective ways to achieve these goals.

[0005] This disclosure was conceived in view of the above circumstances, and its purpose is to provide a semiconductor device in which multiple semiconductor elements are packaged together, thereby reducing parasitic inductance and parasitic resistance. [Means for solving the problem]

[0006] The semiconductor device provided by this disclosure comprises: a first semiconductor element having a first main surface and a first back surface spaced apart in the thickness direction, with a first drain electrode, a first source electrode and a first gate electrode disposed on the first main surface; a second semiconductor element having a second main surface and a second back surface spaced apart in the thickness direction, with a second drain electrode, a second source electrode and a second gate electrode disposed on the second main surface; a control element that conducts to the first gate electrode and the second gate electrode; and a lead frame including a plurality of spaced-apart leads, wherein the plurality of leads include a first lead facing the first back surface and on which the first semiconductor element is mounted; a second lead facing the second back surface and on which the second semiconductor element is mounted; and a third lead on which the control element is mounted, wherein the first lead and the second lead overlap each other when viewed in a first direction perpendicular to the thickness direction, and the third lead overlaps both the first lead and the second lead when viewed in a second direction perpendicular to both the thickness direction and the first direction. [Effects of the Invention]

[0007] According to the semiconductor device of this disclosure, in a semiconductor device in which multiple semiconductor elements and a control element are packaged together, parasitic inductance and parasitic resistance can be reduced. [Brief explanation of the drawing]

[0008] [Figure 1] This is a perspective view showing a semiconductor device according to the first embodiment. [Figure 2] This is a plan view showing a semiconductor device according to the first embodiment. [Figure 3] This is a bottom view showing a semiconductor device according to the first embodiment. [Figure 4] This is a cross-sectional view along the line IV-IV in Figure 2. [Figure 5] This is a cross-sectional view along the VV line in Figure 2. [Figure 6] This is a cross-sectional view along the line VI-VI in Figure 2. [Figure 7]It is a circuit configuration diagram showing a semiconductor device according to the first embodiment. [Figure 8] It is a plan view showing a semiconductor device according to the second embodiment. [Figure 9] It is a plan view showing a semiconductor device according to the third embodiment. [Figure 10] It is a cross-sectional view taken along the line X-X of FIG. 9. [Figure 11] It is a cross-sectional view showing a semiconductor device according to a modification of the third embodiment. [Figure 12] It is a plan view showing a semiconductor device according to the fourth embodiment. [Figure 13] It is a perspective view showing a semiconductor device according to a modification. [Figure 14] It is a bottom view showing a semiconductor device according to a modification.

Mode for Carrying Out the Invention

[0009] Preferred embodiments of the semiconductor device of the present disclosure will be described below with reference to the drawings. In addition, the same or similar components are denoted by the same reference numerals, and the description thereof will be omitted.

[0010] In the present disclosure, "object A overlaps object B in a certain direction" means, unless otherwise specified, "object A overlaps all of object B in a certain direction" and "object A overlaps a part of object B in a certain direction". In addition, terms such as "first", "second", "third", etc. in the present disclosure are merely used as labels and are not necessarily intended to assign an order to their objects.

[0011] <First Embodiment> The semiconductor device A1 according to the first embodiment will be described with reference to FIGS. 1 to 7. The semiconductor device A1 is used in a power converter such as an inverter or a converter, for example.

[0012] First, the module structure of the semiconductor device A1 according to the first embodiment will be described with reference to FIGS. 1 to 6. In its module structure, the semiconductor device A1 includes two semiconductor elements 1 and 2, a control element 3, a lead frame 4, a plurality of connection members 5, and a sealing member 6. Also, in the semiconductor device A1, the lead frame 4 includes a plurality of leads 4A to 4J separated from each other. Further, the plurality of connection members 5 includes a plurality of wires 5A to 5N.

[0013] FIG. 1 is a perspective view showing the semiconductor device A1, showing the case when viewed from the bottom side. FIG. 2 is a plan view showing the semiconductor device A1, with the sealing member 6 shown by an imaginary line (two-dot chain line). FIG. 3 is a bottom view showing the semiconductor device A1, with the sealing member 6 shown by an imaginary line (two-dot chain line). FIG. 4 is a cross-sectional view taken along the line IV-IV of FIG. 2. FIG. 5 is a cross-sectional view taken along the line V-V of FIG. 2. FIG. 6 is a cross-sectional view taken along the line VI-VI of FIG. 2. In FIGS. 4 to 6, the illustration of the plurality of connection members 5 is omitted.

[0014] For convenience of explanation, three mutually orthogonal directions are defined as the x-direction, the y-direction, and the z-direction. The z-direction is the thickness direction of the semiconductor device A1. The x-direction is the left-right direction in the plan view (see FIG. 2) of the semiconductor device A1. The y-direction is the up-down direction in the plan view (see FIG. 2) of the semiconductor device A1. Also, one of the x-directions is the x1-direction, and the other of the x-directions is the x2-direction. Similarly, one of the y-directions is the y1-direction, the other of the y-directions is the y2-direction, one of the z-directions is the z1-direction, and the other of the z-directions is the z2-direction. In the present disclosure, there are cases where the z1-direction is downward and the z2-direction is upward. The x-direction and the y-direction correspond to the "first direction" and the "second direction" described in the claims.

[0015] The semiconductor device A1 is mounted on a circuit board such as an electronic device. The semiconductor device A1 has, for example, a surface-mount package structure, and in the present embodiment, it has a package form called SON (Small Outline Non-lead), for example.

[0016] Both semiconductor elements 1 and 2 are components that perform the electrical functions of semiconductor device A1. Each semiconductor element 1 and 2 is a switching element, for example, an n-type MOSFET. However, each semiconductor element 1 and 2 is not limited to an n-type MOSFET, but may also be a p-type MOSFET. Furthermore, each semiconductor element 1 and 2 is not limited to a MOSFET, but may be a field-effect transistor including a MISFET (Metal-Insulator-Semiconductor FET) or HEMT (High Electron Mobility Transistor), a bipolar transistor, or another transistor such as an IGBT (Insulated Gate Bipolar Transistor). That's fine.

[0017] Each semiconductor element 1 and 2 is, for example, rectangular in a plan view (viewed in the z direction), as shown in Figure 2. Semiconductor element 1 is mounted on lead 4A, and semiconductor element 2 is mounted on lead 4B. The two semiconductor elements 1 and 2 are aligned in the x direction, as shown in Figures 2 and 4. Each constituent material of each semiconductor element 1 and 2 includes, for example, GaN (gallium nitride). However, the constituent materials of each semiconductor element 1 and 2 are not limited to GaN, and may include, for example, SiC (silicon carbide), Si (silicon), GaAs (gallium arsenide), or Ga2O3 (gallium oxide). Semiconductor element 1 corresponds to the "first semiconductor element" described in the claims, and semiconductor element 2 corresponds to the "second semiconductor element" described in the claims.

[0018] The semiconductor element 1 has a main surface 1a and a back surface 1b. The main surface 1a and the back surface 1b are spaced apart in the z direction. The main surface 1a faces the z2 direction, and the back surface 1b faces the z1 direction. The back surface 1b faces the lead 4A. The main surface 1a corresponds to the "first main surface" described in the claims, and the back surface 1b corresponds to the "first back surface" described in the claims.

[0019] The semiconductor element 1 is a three-terminal element having three electrodes. In this embodiment, the semiconductor element 1 includes a drain electrode 11, a source electrode 12, and a gate electrode 13. The drain electrode 11, the source electrode 12, and the gate electrode 13 are arranged on the main surface 1a of the element. The drain electrode 11 corresponds to the "first drain electrode" described in the claims, the source electrode 12 corresponds to the "first source electrode" described in the claims, and the gate electrode 13 corresponds to the "first gate electrode" described in the claims.

[0020] The drain electrode 11 includes a plurality of pad portions 111. Each pad portion 111 is strip-shaped and extends in the x-direction. Each pad portion 111 conducts to the drain region inside the semiconductor element 1. The source electrode 12 includes a plurality of pad portions 121. Each pad portion 121 is strip-shaped and extends in the x-direction. Each pad portion 121 conducts to the source region inside the semiconductor element 1. The plurality of pad portions 111 and the plurality of pad portions 121 are aligned in the y-direction and arranged alternately. The gate electrode 13 includes two pad portions 131 and 132. Each pad portion 131 and 132 conducts to the gate region (channel region) inside the semiconductor element 1. Each pad portion 131 and 132 is located at the edge furthest from the semiconductor element 2 in the x-direction. The two pad portions 131 and 132 are spaced apart in the y-direction. In the example shown in Figure 2, the pad portion 131 is located at the corner on the x1 and y1 directions in a plan view. The pad portion 132 is located at the corner on the x1 and y2 directions in a plan view. Both pad portions 131 and 132 are at the same potential. Note that the gate electrode 13 does not necessarily include the pad portion 132. Each pad portion 131 and 132 corresponds to the "first pad portion" as described in the claims.

[0021] The semiconductor element 1 receives a drive signal from the control element 3, and switches between a conductive state and an interrupted state (performs a switching operation) in response to the drive signal. The drive signal is input to the gate electrode 13. The semiconductor element 1 corresponds to the "first semiconductor element" described in the claims.

[0022] The semiconductor element 2 has a main surface 2a and a back surface 2b. The main surface 2a and the back surface 2b are spaced apart in the z direction. The main surface 2a faces the z2 direction, and the back surface 2b faces the z1 direction. The back surface 2b faces the lead 4B. The main surface 2a corresponds to the "second main surface" described in the claims, and the back surface 2b corresponds to the "second back surface" described in the claims.

[0023] The semiconductor element 2 is a three-terminal element having three electrodes. In this embodiment, the semiconductor element 2 includes a drain electrode 21, a source electrode 22, and a gate electrode 23. The drain electrode 21, the source electrode 22, and the gate electrode 23 are arranged on the main surface 2a of the element. The drain electrode 21 corresponds to the "second drain electrode" described in the claims, the source electrode 22 corresponds to the "second source electrode" described in the claims, and the gate electrode 23 corresponds to the "second gate electrode" described in the claims.

[0024] The drain electrode 21 includes a plurality of pad portions 211. Each pad portion 211 is strip-shaped and extends in the x-direction. Each pad portion 211 conducts to the drain region inside the semiconductor element 2. The source electrode 22 includes a plurality of pad portions 221. Each pad portion 221 is strip-shaped and extends in the x-direction. Each pad portion 221 conducts to the source region inside the semiconductor element 2. The plurality of pad portions 211 and the plurality of pad portions 221 are aligned in the y-direction and arranged alternately. The gate electrode 23 includes two pad portions 231 and 232. Each pad portion 231 and 232 conducts to the gate region (channel region) inside the semiconductor element 2. Each pad portion 231 and 232 is located at the edge furthest from the semiconductor element 1 in the x-direction. The two pad portions 231 and 232 are spaced apart in the y-direction. In the example shown in Figure 2, the pad portion 231 is located at the corner on the x2 and y1 directions in a plan view. The pad portion 232 is located at the corner on the x2 and y2 directions in a plan view. Both pad portions 231 and 232 are at the same potential. Note that the gate electrode 23 does not necessarily include the pad portion 232. Each pad portion 231 and 232 corresponds to the "second pad portion" as described in the claims.

[0025] The semiconductor element 2 receives a drive signal from the control element 3, and switches between a conductive state and an interrupted state (performs a switching operation) in response to the drive signal. The drive signal is input to the gate electrode 23. The semiconductor element 2 corresponds to the "second semiconductor element" described in the claims.

[0026] The control element 3 controls the switching operation of the two semiconductor elements 1 and 2. The control element 3 generates drive signals to drive each semiconductor element 1 and 2, and outputs the generated drive signals to each of the semiconductor elements 1 and 2. The control element 3 is, for example, an IC (integrated circuit). The control element 3 is a semiconductor element composed of semiconductor material. The control element 3 is mounted on lead 4C. When viewed in the y direction, the control element 3 overlaps a portion of each of the semiconductor elements 1 and 2.

[0027] The control element 3 has a main surface 3a and a back surface 3b. The main surface 3a and the back surface 3b are spaced apart in the z direction. The main surface 3a faces the z2 direction, and the back surface 3b faces the z1 direction. The back surface 3b faces the lead 4C.

[0028] The control element 3 includes an element electrode 31. The element electrode 31 is arranged on the main surface 3a of the element. The element electrode 31 includes a plurality of pad portions 311 to 318. Each of the plurality of pad portions 311 to 318 is either an input terminal or an output terminal of the control element 3. Each pad portion 311 to 318 is the part to which the connecting member 5 is joined. The arrangement of each pad portion 311 to 318 in a plan view is not limited to the example shown in Figure 2.

[0029] Pad portion 311 has one end of wire 5L attached to it, and conduction is possible to lead 4H via wire 5L. Pad portion 312 has one end of wire 5J attached to it, and conduction is possible to lead 4C via wire 5J. Pad portion 313 has one end of wire 5M attached to it, and conduction is possible to lead 4I via wire 5M. Pad portion 314 has one end of wire 5N attached to it, and conduction is possible to lead 4J via wire 5N. Pad portion 315 has one end of wire 5F attached to it, and conduction is possible to gate electrode 13 (pad portion 131) of semiconductor element 1 via wire 5F. Pad portion 316 has one end of wire 5H attached to it, and conduction is possible to gate electrode 23 (pad portion 231) of semiconductor element 2 via wire 5H. Pad portion 317 has one end of wire 5K attached to it, and conduction is possible to lead 4G via wire 5K. One end of the wire 5E is attached to the pad portion 318, and electrical conductivity is established to the lead 4A via the wire 5E.

[0030] The lead frame 4 is mounted on two semiconductor elements 1 and 2 and a control element 3. The lead frame 4, together with a plurality of connecting members 5, forms a conductive path in the semiconductor device A1. The lead frame 4 is made of a conductive material. The constituent material of the lead frame 4 is, for example, a metal containing Cu (copper). However, the constituent material may be a metal other than Cu. In addition, the surface of the lead frame 4 may be plated as appropriate. As shown in Figure 2, the lead frame 4 includes a plurality of leads 4A to 4J that are spaced apart from each other. A portion of each lead 4A to 4J is exposed from the sealing member 6, and this exposed portion is a terminal when the semiconductor device A1 is mounted on an external circuit board.

[0031] Lead 4A mounts semiconductor element 1. One end of each of several wires 5B is connected to lead 4A, and through these wires 5B, it is electrically connected to the source electrode 12 of semiconductor element 1. Also, one end of each of several wires 5C is connected to lead 4A, and through these wires 5C, it is electrically connected to the drain electrode 21 of semiconductor element 2. Furthermore, one end of wire 5E is connected to lead 4A, and through this wire 5E, it is electrically connected to the element electrode 31 (pad portion 318) of control element 3. Lead 4B mounts semiconductor element 2. One end of each of several wires 5D is connected to lead 4B, and through these wires 5D, it is electrically connected to the source electrode 22 of semiconductor element 2. Lead 4C mounts control element 3. One end of wire 5J is connected to lead 4C, and through this wire 5J, it is electrically connected to the element electrode 31 (pad portion 312) of control element 3. Lead 4D has one end of each of the multiple wires 5A connected to it, and conducts to the drain electrode 11 of the semiconductor element 1 via the multiple wires 5A. Lead 4E has one end of wire 5G connected to it, and conducts to the gate electrode 13 (pad portion 132) of the semiconductor element 1 via wire 5G. Lead 4F has one end of wire 5I connected to it, and conducts to the gate electrode 23 (pad portion 232) of the semiconductor element 2 via wire 5I. Lead 4G has one end of wire 5K connected to it, and conducts to the element electrode 31 (pad portion 317) of the control element 3 via wire 5K. Lead 4H has one end of wire 5L connected to it, and conducts to the element electrode 31 (pad portion 311) of the control element 3 via wire 5L. Lead 4I has one end of wire 5M connected to it, and conducts to the element electrode 31 (pad portion 313) of the control element 3 via wire 5M. Lead 4J has one end of wire 5N connected to it, and through wire 5N, it is electrically connected to the element electrode 31 (pad portion 314) of the control element 3.

[0032] As shown in Figures 2 and 4, lead 4A includes a die pad portion 411 and a bonding portion 412. The die pad portion 411 and the bonding portion 412 are integrally formed. It is done so. Furthermore, the die pad portion 411 and the bonding portion 412 may be separate.

[0033] The die pad portion 411 is the area on which the semiconductor element 1 is mounted. The semiconductor element 1 is bonded via a bonding material (not shown). The die pad portion 411 faces the back surface 1b of the element. The die pad portion 411 corresponds to the "first die pad portion" described in the claims.

[0034] The bonding portion 412 is the part to which one of the multiple connecting members 5 is joined. In this embodiment, one end each of multiple wires 5B, multiple wires 5C, and wire 5E is joined to the bonding portion 412. The bonding portion 412 is electrically connected to the source electrode 12 of the semiconductor element 1 via the multiple wires 5B, and to the drain electrode 21 of the semiconductor element 2 via the multiple wires 5C. The bonding portion 412 is also electrically connected to the element electrode 31 (pad portion 318) of the control element 3 via the wire 5E. In a plan view, the bonding portion 412 is located between the semiconductor element 1 and the semiconductor element 2. The bonding portion 412 corresponds to the "first bonding portion" described in the claims.

[0035] As shown in Figures 2 and 4, the lead 4B includes a die pad portion 421 and a bonding portion 422. The die pad portion 421 and the bonding portion 422 are integrally formed. However, the die pad portion 421 and the bonding portion 422 may be separate.

[0036] The die pad portion 421 is the area on which the semiconductor element 2 is mounted. The semiconductor element 2 is bonded via a bonding material (not shown). The die pad portion 421 faces the back surface 2b of the element. The die pad portion 421 corresponds to the "second die pad portion" described in the claims.

[0037] The bonding portion 422 is the part to which one of the multiple connecting members 5 is joined. In this embodiment, one end of each of the multiple wires 5D is joined to the bonding portion 422. The bonding portion 422 is electrically connected to the source electrode 22 of the semiconductor element 2 via the multiple wires 5D. The bonding portion 422 corresponds to the "second bonding portion" described in the claims.

[0038] As shown in Figure 2, both leads 4A and 4B are positioned in the y2 direction relative to lead 4C. Both leads 4A and 4B overlap with lead 4C when viewed in the y direction, but do not overlap with lead 4C when viewed in the x direction. Also, leads 4A and 4B are adjacent in the x direction. Leads 4A and 4B overlap when viewed in the x direction.

[0039] Leads 4E and 4F overlap when viewed in the x-direction. As shown in Figure 2, lead 4E is positioned near the pad portion 132 in a plan view and is closer to the pad portion 132 than the other leads (except lead 4A). As shown in Figure 2, lead 4F is positioned near the pad portion 232 in a plan view and is closer to the pad portion 132 than the other leads (except lead 4B).

[0040] The bonding portion 422 of lead 4D and lead 4B overlaps with each other when viewed in the x-direction. Also, lead 4D, lead 4A, and lead 4B overlap with each other when viewed in the x-direction and are arranged in this order in the x-direction. Lead 4D is conductive to the drain electrode 11 of semiconductor element 1, lead 4A is conductive to the source electrode 12 of semiconductor element 1 and the drain electrode 21 of semiconductor element 2, and lead 4B is conductive to the source electrode 22 of semiconductor element 2. Therefore, the two The current path from lead 4D to lead 4B, via semiconductor elements 1 and 2, is formed along the x-direction.

[0041] Leads 4E, 4D, 4G, and 4H overlap each other when viewed in the y-direction and are arranged in this order in the y-direction. Also, the bonding portions 422 of leads 4F and 4B, and leads 4I and 4J overlap each other when viewed in the y-direction and are arranged in this order in the y-direction.

[0042] Leads 4G, 4H, 4I, and 4J each overlap with lead 4C when viewed in the x-direction. The two leads 4G and 4H are positioned in the x1 direction relative to lead 4C, and the two leads 4I and 4J are positioned in the x2 direction relative to lead 4C. Leads 4G and 4I overlap with each other when viewed in the x-direction. Leads 4H and 4J overlap with each other when viewed in the x-direction.

[0043] Each lead 4A to 4J has a recess 49 formed therein, as shown in Figures 3 to 6. The recess 49 is a portion of each lead 4A to 4J that is recessed from the surface facing the z1 direction toward the z2 direction. As shown in Figure 3, the recess 49 is formed along the outer edge of each lead 4A to 4J in a plan view. The recess 49 is covered by a sealing member 6. In the examples shown in Figures 4 to 6, the wall surface of the recess 49 is curved, but it does not have to be curved. The recess 49 is provided to prevent the leads 4A to 4J from coming loose.

[0044] In this embodiment, lead 4A corresponds to the "first lead" as described in the claims. Lead 4B corresponds to the "second lead" as described in the claims. Lead 4C corresponds to the "third lead" as described in the claims. Lead 4D corresponds to the "fourth lead" as described in the claims. Lead 4E corresponds to the "fifth lead" as described in the claims. Lead 4F corresponds to the "sixth lead" as described in the claims. Each of leads 4G to 4J corresponds to the "seventh lead" as described in the claims.

[0045] Each of the multiple connecting members 5 provides electrical conductivity between two spaced-apart members. Each connecting member 5 is made of a conductive material. As shown in Figure 2, the multiple connecting members 5 include multiple wires 5A to 5N. Each wire 5A to 5N is a so-called bonding wire. The constituent material of each wire 5A to 5N may be any of the following: a metal containing Au (gold), a metal containing Al (aluminum), or a metal containing Cu.

[0046] As shown in Figure 2, each of the multiple wires 5A has one end joined to the pad portion 111 of the drain electrode 11 of the semiconductor element 1 and the other end joined to the lead 4D. Each of the multiple wires 5B has one end joined to the pad portion 121 of the source electrode 12 of the semiconductor element 1 and the other end joined to the bonding portion 412 of the lead 4A. Each of the multiple wires 5C has one end joined to the pad portion 211 of the drain electrode 21 of the semiconductor element 2 and the other end joined to the bonding portion 412 of the lead 4A. Each of the multiple wires 5D has one end joined to the pad portion 221 of the source electrode 22 of the semiconductor element 2 and the other end joined to the bonding portion 422 of the lead 4B. Wire 5E has one end joined to the pad portion 318 of the element electrode 31 of the control element 3 and the other end joined to the bonding portion 412 of the lead 4A. Wire 5F is joined at one end to the pad portion 315 of the element electrode 31 of the control element 3, and at the other end to the pad portion 131 of the gate electrode 13 of the semiconductor element 1. Wire 5G is joined at one end to the lead 4E, and at the other end to the pad portion 132 of the gate electrode 13 of the semiconductor element 1. Wire 5H is joined at one end to the pad portion 316 of the element electrode 31 of the control element 3, and at the other end to the pad portion 231 of the gate electrode 23 of the semiconductor element 2. Wire 5I is joined at one end to the lead 4F, and at the other end to the pad portion 232 of the gate electrode 23 of the semiconductor element 2. Wire 5J is joined at one end to the pad portion 312 of the element electrode 31 of the control element 3, and at the other end to the lead 4C. Wire 5K is joined at one end to the pad portion 317 of the element electrode 31 of the control element 3, and the other end is joined to lead 4G. Wire 5L is joined at one end to the pad portion 311 of the element electrode 31 of the control element 3, and the other end is joined to lead 4H. Wire 5M is joined at one end to the pad portion 313 of the element electrode 31 of the control element 3, and the other end is joined to lead 4I. Wire 5N is joined at one end to the pad portion 314 of the element electrode 31 of the control element 3, and the other end is joined to lead 4J.

[0047] In the example shown in Figure 2, three wires 5A are joined to each of the three pad portions 111. Similarly, three wires 5B are joined to each of the two pad portions 121. Likewise, three wires 5C are joined to each of the three pad portions 211. Furthermore, three wires 5D are joined to each of the two pad portions 221. In addition, the portion of wire 5E joined to the bonding portion 412 is located in the x-direction between the portion of each wire 5B joined to the bonding portion 412 and the portion of each wire 5C joined to the bonding portion 412. The number of wires 5A to 5N is not limited to the numbers shown in Figure 2, and may be appropriately changed considering the area of ​​each pad section 111, 121, 131, 132, 211, 221, 231, 232, 311 to 318 in plan view, the wire diameter of each wire 5A to 5N, and the amount of current flowing through each wire 5A to 5N.

[0048] In this embodiment, wire 5A corresponds to the "first connecting member" as described in the claims. Wire 5B corresponds to the "second connecting member" as described in the claims. Wire 5C corresponds to the "third connecting member" as described in the claims. Wire 5D corresponds to the "fourth connecting member" as described in the claims. Wire 5E corresponds to the "fifth connecting member" as described in the claims. Wire 5F corresponds to the "sixth connecting member" as described in the claims. Wire 5G corresponds to the "seventh connecting member" as described in the claims. Wire 5H corresponds to the "eighth connecting member" as described in the claims. Wire 5I corresponds to the "ninth connecting member" as described in the claims. Each of the wires 5K to 5N corresponds to the "tenth connecting member" as described in the claims.

[0049] The sealing member 6 is a protective member for the semiconductor elements 1 and 2 and the control element 3. The sealing member 6 covers the semiconductor elements 1 and 2, the control element 3, a part of the lead frame 4, and a plurality of connecting members 5. The constituent material of the sealing member 6 is an electrically insulating resin material, such as epoxy resin. The sealing member 6 is, for example, rectangular in plan view. However, the shape of the sealing member 6 is not limited to the examples shown in Figures 1 to 6. The sealing member 6 has a resin main surface 61, a resin back surface 62, and a plurality of resin side surfaces 631 to 634.

[0050] The resin main surface 61 and the resin back surface 62 are spaced apart in the z direction, as shown in Figures 4 to 6. The resin main surface 61 faces the z2 direction, and the resin back surface 62 faces the z1 direction. A portion of each lead 4A to 4J (the surface facing the z1 direction) is exposed from the resin back surface 62. Each of the multiple resin side surfaces 631 to 634 is sandwiched between the resin main surface 61 and the resin back surface 62 in the z direction, and is connected to both of them. The resin side surfaces 631 and 632 are spaced apart in the x direction, with resin side surface 631 facing the x1 direction and resin side surface 632 facing the x2 direction. The resin side surfaces 633 and 634 are spaced apart in the y direction, with resin side surface 633 facing the y1 direction and resin side surface 634 facing the y2 direction.

[0051] Next, the circuit configuration of the semiconductor device A1 according to the first embodiment will be described with reference to Figure 7. In the following description, the reference potential will be the ground voltage V. GND There are cases like this. .

[0052] Figure 7 shows the semiconductor device A1 applied to a synchronous rectification type step-down DC / DC converter. The circuit diagram for this case is shown. This DC / DC converter is a power supply circuit that steps down the input voltage Vin to generate the desired output voltage Vout. The output voltage Vout is supplied to the load LO. Note that the circuit diagram shown in Figure 7 is just one example.

[0053] As shown in Figure 7, semiconductor device A1 has a circuit configuration that includes multiple external terminals T1 to T10, two semiconductor elements 1 and 2, and a control element 3. Furthermore, as shown in Figure 7, semiconductor device A1 is connected to two external power supplies PS1 and PS2 and multiple discrete components (multiple capacitors C1 to C4 and an inductor L1). Note that one or more of the discrete components may be built into semiconductor device A1.

[0054] The external power supply PS1 generates the power supply voltage VCC for driving the control element 3. The high-potential terminal of the external power supply PS1 is connected to the external terminal T1. The low-potential terminal of the external power supply PS1 is connected to the first ground terminal GND1 and is grounded to the reference potential. Capacitor C1 is connected in parallel to the external power supply PS1. Capacitor C1 is a bypass capacitor that stabilizes the power supply voltage VCC.

[0055] The external power supply PS2 generates the input voltage Vin. The high-potential terminal of the external power supply PS2 is connected to the external terminal T3. The low-potential terminal of the external power supply PS2 is connected to the second ground terminal GND2 and grounded to the reference potential. Note that this shows both the first ground terminal GND1 and the second ground terminal GND2 as ground terminals of the reference potential, but the reference potential of the first ground terminal GND1 and the reference potential of the second ground terminal GND2 may be different. Capacitor C2 is connected in parallel to the external power supply PS2. Capacitor C2 is a bypass capacitor that stabilizes the input voltage Vin.

[0056] Inductor L1 has its first end connected to external terminal T7 and its second end connected to load LO and capacitor C3. Capacitor C3 has its first end connected to inductor L1 and its second end connected to second ground terminal GND2. Inductor L1 and capacitor C3 form an LC filter circuit. Capacitor C4 has its first end connected to external terminal T7 and its second end connected to external terminal T8. Capacitor C4, together with diode D1 (described later), forms a bootstrap circuit. Capacitor C4 generates the boot voltage VB.

[0057] External terminal T1 is the input terminal of the power supply voltage VCC. External terminal T1 is connected to the high-potential terminal of the external power supply PS1. Inside the semiconductor device A1, external terminal T1 is connected to control element 3 (connection terminal TC1 described later). External terminal T1 corresponds to lead 4H in the module structure of semiconductor device A1, for example.

[0058] External terminal T2 is connected to the first ground terminal GND1 and grounded to a reference potential. Inside the semiconductor device A1, external terminal T2 is connected to control element 3 (connection terminal TC2, described later). External terminal T2 corresponds, for example, to lead 4C in the module structure of semiconductor device A1.

[0059] External terminal T3 is the input terminal of the input voltage Vin. External terminal T3 is connected to the high-potential terminal of the external power supply PS2. Inside semiconductor device A1, external terminal T3 is connected to the drain of semiconductor element 1. External terminal T3 corresponds to lead 4D in the module structure of semiconductor device A1, for example.

[0060] External terminal T4 is connected to the second ground terminal GND2 and grounded to a reference potential. Within semiconductor device A1, external terminal T4 is connected to the source of semiconductor element 2. External terminal T4 corresponds, for example, to lead 4B in the module structure of semiconductor device A1.

[0061] External terminal T5 is the input terminal for the control signal SH. The control signal SH is a signal for controlling the switching operation of semiconductor element 1. The control signal SH is, for example, a rectangular pulse wave that alternates between high and low levels. Inside semiconductor device A1, external terminal T5 is connected to control element 3 (connection terminal TC3, described later). External terminal T5 corresponds to lead 4I in the module structure of semiconductor device A1, for example.

[0062] External terminal T6 is the input terminal for the control signal SL. The control signal SL is a signal for controlling the switching operation of semiconductor element 2. The control signal SL is, for example, a rectangular pulse wave that alternates between high and low levels. The high-level period and the low-level period of the control signal SL and the control signal SH are inverted relative to each other. External terminal T6 is connected to control element 3 (connection terminal TC4, described later) inside semiconductor device A1. External terminal T6 corresponds to lead 4J in the module structure of semiconductor device A1, for example.

[0063] External terminal T7 is for output voltage V SW This is the output terminal. Output voltage V SWThis is a voltage signal generated by the switching operations of semiconductor element 1 and semiconductor element 2. The external terminal T7 is connected to the connection point between the source of semiconductor element 1 and the drain of semiconductor element 2 inside the semiconductor device A1. The external terminal T7 corresponds, for example, to lead 4A in the module structure of semiconductor device A1.

[0064] External terminal T8 is the input terminal for the boot voltage VB. The boot voltage VB is a voltage signal generated by capacitor C4 and diode D1 (described later). External terminal T8 is connected to the second terminal of capacitor C4. Inside semiconductor device A1, external terminal T8 is connected to control element 3 (connection terminal TC7 (described later)). External terminal T8 corresponds, for example, to lead 4G in the module structure of semiconductor device A1.

[0065] External terminal T9 is the input terminal for the drive signal GH2. The drive signal GH2 is a signal for driving the semiconductor element 1 and is input directly from an external device (not shown). The drive signal GH2 is, for example, a rectangular pulse wave that alternates between high and low levels. Inside the semiconductor device A1, external terminal T9 is connected to the gate of the semiconductor element 1. External terminal T9 corresponds to, for example, lead 4E in the module structure of the semiconductor device A1.

[0066] External terminal T10 is the input terminal for the drive signal GL2. The drive signal GL2 is a signal for driving the semiconductor element 2 and is input directly from an external device (not shown). The drive signal GL2 is, for example, a rectangular pulse wave that alternates between high and low levels. The high-level period and the low-level period of the drive signal GH2 and the drive signal GL2 are inverted relative to each other. The external terminal T10 is connected to the gate of the semiconductor element 2 inside the semiconductor device A1. The external terminal T10 corresponds to, for example, lead 4F in the module structure of the semiconductor device A1.

[0067] The correspondence between each external terminal T1 to T10 in the circuit configuration and each lead 4A to AJ in the module structure is not limited to those described above. For example, the combination of correspondences between each external terminal T1, T5, T6, T8 and each lead 4G to 4J can be changed as appropriate. This combination of correspondences can be changed as appropriate depending on the arrangement of the pad portions 311, 313, 314, 317 of the control element 3 in a plan view.

[0068] As mentioned above, the two semiconductor elements 1 and 2 are composed of n-type MOSFETs. Each semiconductor element 1 and 2 switches between a conduction state (on state) and a disconnection state (off state) according to the drive signals GH1, GH2, GL1, and GL2 input to the gate. The two semiconductor elements 1 and 2 constitute a half-bridge type switching circuit, and semiconductor element 1 is the... The upper arm of the switching circuit is semiconductor element 2, and the lower arm of the switching circuit is semiconductor element 2.

[0069] The drain of semiconductor element 1 is connected to external terminal T3, and the source of semiconductor element 1 is connected to the drain of semiconductor element 2. The gate of semiconductor element 1 is connected to control element 3 (connection terminal TC5, described later) and also to external terminal T9.

[0070] Semiconductor element 1 performs switching operations in response to a drive signal GH1 input to its gate from control element 3. When the drive signal GH1 input to the gate of semiconductor element 1 is at a high level, it enters a conductive state, and when the drive signal GH1 input to the gate of semiconductor element 1 is at a low level, it enters a closed state. Furthermore, semiconductor element 1 performs switching operations in response to a drive signal GH2 input to its gate from external terminal T9. When the drive signal GH2 input to the gate of semiconductor element 1 is at a high level, it enters a conductive state, and when the drive signal GH2 input to the gate of semiconductor element 1 is at a low level, it enters a closed state. Note that semiconductor element 2 is assumed to be a normally-off type, but it may also be a normally-on type. In addition, the signal input to the gate of semiconductor element 1 may be both of the two drive signals GH1 and GH2, or one of them.

[0071] The drain of semiconductor element 2 is connected to the source of semiconductor element 1, and the source of semiconductor element 2 is connected to external terminal T4. The gate of semiconductor element 2 is connected to control element 3 (connection terminal TC6, described later) and also to external terminal T10.

[0072] The semiconductor element 2 performs switching operations in response to the drive signal GL1 input to its gate from the control element 3. When the drive signal GL1 input to the gate of the semiconductor element 2 is at a high level, it enters a conductive state, and when the drive signal GL1 input to the gate of the semiconductor element 2 is at a low level, it enters an interrupted state. Furthermore, the semiconductor element 2 performs switching operations in response to the drive signal GL2 input to its gate from the external terminal T10. When the drive signal GL2 input to the gate of the semiconductor element 2 is at a high level, it enters a conductive state, and when the drive signal GL2 input to the gate of the semiconductor element 2 is at a low level, it enters an interrupted state. Note that the semiconductor element 2 is assumed to be a normally-off type, but it may also be a normally-on type. In addition, the signal input to the gate of the semiconductor element 2 may be both of the two drive signals GL1 and GL2, or either one of them.

[0073] The connection point between the source of semiconductor element 1 and the drain of semiconductor element 2 is connected to external terminal T7 and also to control element 3 (connection terminal TC8, described later). The switching operation of semiconductor element 1 and semiconductor element 2 generates an output voltage V at external terminal T7. SW It is applied.

[0074] The control element 3 primarily controls the switching operation of two semiconductor elements 1 and 2. Based on control signals SH and SL, the control element 3 generates drive signals GH1 and GL1 and inputs the generated drive signals GH1 and GL1 to the semiconductor elements 1 and 2. The control element 3 includes multiple connection terminals TC1 to TC8, two drive circuits DR1 and DR2, and a diode D1 in its internal circuitry. The control element 3 is an IC in which the two drive circuits DR1 and DR2 and the diode D1 are integrated into a single chip.

[0075] Connection terminal TC1 is connected to external terminal T1 and is the input terminal of the power supply voltage VCC in control element 3. Connection terminal TC2 is connected to external terminal T2 and is grounded to the reference potential. Connection terminal TC3 is connected to external terminal T5 and is the input terminal of the control signal SH in control element 3. Connection terminal TC4 is connected to external terminal T6 and is the input terminal of the control signal SL in control element 3. Connection terminal TC5 is the output terminal of the drive signal GH1. The connection terminal TC5 is connected to the gate of semiconductor element 1. The connection terminal TC6 is the output terminal of the drive signal GL1. The connection terminal TC6 is connected to the gate of semiconductor element 2. The connection terminal TC7 is connected to the external terminal T8 and is the input terminal of the boot voltage VB in the control element 3. The connection terminal TC8 is connected to the connection point between semiconductor element 1 (source) and semiconductor element 2 (drain).

[0076] The drive circuit DR1 generates a drive signal GH1 based on the input control signal SH. The drive signal GH1 is a signal for switching the semiconductor element 1, and is a signal obtained by raising the control signal SH to the level required for the switching operation of the semiconductor element 1. The drive circuit DR1 outputs the generated drive signal GH1 from the connection terminal TC5. Since the connection terminal TC5 is connected to the gate of the semiconductor element 1, the drive signal GH1 is input to the gate of the semiconductor element 1. The drive signal GH1 is a signal that sets the boot voltage VB to a high level and the source voltage of the semiconductor element 1 to a low level. The source voltage of the semiconductor element 1 is input to the drive circuit DR1 via the connection terminal TC8. The gate voltage of the semiconductor element 1 is given with reference to the source voltage of the semiconductor element 1.

[0077] The drive circuit DR2 generates a drive signal GL1 based on the input control signal SL. The drive signal GL1 is a signal for switching the semiconductor element 2, and is a signal obtained by raising the control signal SL to the level required for the switching operation of the semiconductor element 2. The drive circuit DR2 outputs the generated drive signal GL1 from the connection terminal TC6. Since the connection terminal TC6 is connected to the gate of the semiconductor element 2, the drive signal GL1 is input to the gate of the semiconductor element 2. The drive signal GL1 is input to the power supply voltage VCC at a high level and the ground voltage V GND This is a signal that sets the level to low. The gate voltage of semiconductor element 2 is ground. Voltage V GND It is given based on that.

[0078] Diode D1 has its anode connected to terminal TC1 and its cathode connected to terminal TC7. Diode D1, together with capacitor C4, forms a bootstrap circuit. The bootstrap circuit generates a boot voltage VB and supplies it to the drive circuit DR1. Note that diode D1 may be located outside the control element 3.

[0079] Next, we will explain an example of the operation of semiconductor device A1.

[0080] When control signals SH and SL are input from external terminals T5 and T6 to control element 3 in semiconductor device A1, drive signals GH1 and GL1 are generated by control element 3. Then, the drive signals GH1 and GL1 are input to the gates of semiconductor elements 1 and 2 from control element 3. Alternatively, drive signals GH2 and GL2 are input to the gates of semiconductor elements 1 and 2 from external terminals T9 and T10 respectively. As a result, a first period in which semiconductor element 1 is in the conducting state and semiconductor element 2 is in the blocking state, and a second period in which semiconductor element 1 is in the blocking state and semiconductor element 2 is in the conducting state are alternately repeated. At this time, input voltage Vin is applied to external terminal T7 during the first period. On the other hand, external terminal T7 is grounded to the reference potential (ground voltage V GND is applied) during the second period. Therefore , the output voltage V SW from external terminal T7 is a pulse wave with a high level being input voltage Vin and a low level being ground voltage V GND . And the output voltage V SW is converted to output voltage Vout of a DC voltage by being smoothed by inductor L 1 and capacitor C3. By operating as described above, semiconductor device A1 transforms (step - down) input voltage Vin to output voltage Vout.

[0081] The first period and the second period are alternately repeated at a predetermined cycle, and the step - down ratio can be changed according to the ratio of the first period to the second period in one cycle. For example, when the first period is 25% of one cycle (the second period is 75% of one cycle), the output voltage Vout is transformed to 1 / 4 times of input voltage Vi n (Vout = Vin×(25 / 100)). A dead time during which both semiconductor elements 1 and 2 are in the blocking state may be provided between the first period and the second period.

[0082] The functions and effects of semiconductor device A1 configured as described above are as follows.

[0083] According to the first embodiment, semiconductor device A1 includes leads 4A, 4B, and 4C. Leads 4A and 4B overlap each other when viewed in the x-direction, and lead 4C overlaps both leads 4A and 4B when viewed in the y-direction. Lead 4A is mounted on semiconductor element 1, lead 4B is mounted on semiconductor element 2, and lead 4C is mounted on control element 3. This makes it possible to shorten the distance between semiconductor element 1 and semiconductor element 2 compared to the semiconductor device described in Patent Document 1. Specifically, in the semiconductor device described in Patent Document 1, in a plan view, two semiconductor elements (switching elements) are arranged on opposite sides of a control element (control IC). Therefore, the connection between the two semiconductor elements must be routed while avoiding the control element, which tends to result in longer wiring distances. On the other hand, in semiconductor device A1, since control element 3 is not located between semiconductor element 1 and semiconductor element 2, the wiring distance connecting semiconductor element 1 and semiconductor element 2 (in this embodiment, the lengths of each wire 5B, 5C and a portion of lead 4A) can be shortened. Therefore, since the parasitic inductance and parasitic resistance of semiconductor device A1 can be reduced, it is possible to achieve higher efficiency and energy savings.

[0084] According to the first embodiment, both leads 4A and 4B are positioned in the y2 direction relative to lead 4C, and overlap with lead 4C when viewed in the y direction. Therefore, lead 4A on which semiconductor element 1 is mounted and lead 4B on which semiconductor element 2 is mounted can be positioned on one side of the y direction (y2 direction), and lead 4C on which control element 3 is mounted can be positioned on the other side of the y direction (y1 direction). When semiconductor device A1 is energized, semiconductor elements 1 and 2 and control element 3 generate heat. The amount of heat generated by semiconductor elements 1 and 2 is greater than the amount of heat generated by control element 3. If this heat from semiconductor elements 1 and 2 is transferred to control element 3, the heat from semiconductor elements 1 and 2 may cause malfunction or performance degradation of control element 3. However, semiconductor device A1 separates each semiconductor element 1 and 2 from the control element 3 by positioning leads 4A and 4B on one side of lead 4C in the y direction (y2 direction side). As a result, semiconductor device A1 can suppress the heat transferred from semiconductor elements 1 and 2 to control element 3, thereby preventing malfunctions and performance degradation of control element 3.

[0085] According to the first embodiment, leads 4D, 4A, and 4B overlap when viewed in the x-direction and are arranged in this order in the x-direction. Furthermore, the pad portions 111, 121, 211, and 221 of semiconductor elements 1 and 2 are each strip-shaped and extend in the x-direction. As a result, semiconductor device A1 can have the wiring of the current paths (power current paths) flowing through the drain-source of semiconductor element 1 and the drain-source of semiconductor element 2 in a straight line. These power current paths are the current paths in the power conversion of semiconductor device A1. In particular, when semiconductor elements 1 and 2 are driven at high frequencies, the wiring of the power current paths is not perpendicular, which is effective in suppressing noise.

[0086] According to the first embodiment, lead 4A includes a die pad portion 411 and a bonding portion 412, which are integrally formed. This allows heat from the semiconductor element 1 to be diffused not only to the die pad portion 411 but also to the bonding portion 412. Therefore, semiconductor device A1 can suppress the rise in the junction temperature of the semiconductor element 1 due to heat generated by the semiconductor element 1. A rise in junction temperature is a cause of damage to the semiconductor element 1. In other words, semiconductor device A1 can suppress damage to the semiconductor element 1. Similarly, lead 4B includes a die pad portion 421 and a bonding portion 422, These are formed integrally. This allows heat from the semiconductor element 2 to be diffused not only to the die pad portion 421 but also to the bonding portion 422. Therefore, the semiconductor device A1 can suppress the rise in the junction temperature of the semiconductor element 2 due to the heat generated by the semiconductor element 2. In other words, the semiconductor device A1 can suppress damage to the semiconductor element 2.

[0087] According to the first embodiment, the pad portion 131 of the gate electrode 13 of the semiconductor element 1 is located on the edge side of the main surface 1a of the element, closer to the lead 4C in the y-direction. This allows the semiconductor device A1 to shorten the distance between the pad portion 131 and the control element 3 in a plan view. As a result, the length of the wire 5F can be shortened, and parasitic inductance and resistance of the wire 5F can be suppressed. In particular, since the wire 5F is the transmission line for the drive signal GH1, a decrease in the responsiveness of the switching operation of the semiconductor element 1 and malfunctions of the switching operation can be suppressed. Similarly, the pad portion 231 of the gate electrode 23 of the semiconductor element 2 is located on the edge side of the main surface 2a of the element, closer to the lead 4C in the y-direction. This allows the semiconductor device A1 to shorten the distance between the pad portion 231 and the control element 3 in a plan view. As a result, the length of the wire 5H can be shortened, and parasitic inductance and resistance of the wire 5H can be suppressed. In particular, since wire 5H is the transmission line for the drive signal GL1, it can suppress a decrease in the responsiveness of the switching operation of the semiconductor element 2 and malfunctions of the switching operation.

[0088] According to the first embodiment, in a plan view, lead 4E is positioned near the pad portion 132 and is closer to the pad portion 132 than the other leads (except lead 4A). This allows the length of the wire 5G connecting lead 4E and the pad portion 132 to be shortened, thereby suppressing parasitic inductance and parasitic resistance of wire 5G. In particular, when inputting a drive signal GH2 from an external device to semiconductor device A1, since wire 5G is the transmission line for the drive signal GH2, this suppresses a decrease in the responsiveness of the switching operation of semiconductor element 1 and malfunctions of the switching operation. Also, in a plan view, lead 4F is positioned near the pad portion 232 and is closer to the pad portion 132 than the other leads (except lead 4B). This allows the length of the wire 5I connecting lead 4F and the pad portion 232 to be shortened, thereby suppressing parasitic inductance and parasitic resistance of wire 5I. In particular, when inputting the drive signal GL2 from an external device to the semiconductor device A1, since wire 5I is the transmission line for the drive signal GL2, it is possible to suppress a decrease in the responsiveness of the switching operation of the semiconductor element 2 and malfunctions of the switching operation.

[0089] <Second Embodiment> Next, a semiconductor device A2 according to the second embodiment will be described with reference to Figure 8. Figure 8 is a plan view of the semiconductor device A2, in which the sealing member 6 is indicated by dashed lines.

[0090] As shown in Figure 8, semiconductor device A2 has a different lead frame 4 configuration compared to semiconductor device A1. Specifically, unlike the lead frame 4 of semiconductor device A1, the lead frame 4 of semiconductor device A2 does not include leads 4E and 4F.

[0091] As shown in Figure 8, the lead frame 4 of semiconductor device A2 has lead 4D extended to the position where lead 4E was located, since lead 4E is absent. Similarly, as shown in Figure 8, the bonding portion 422 of lead 4B is extended to the position where lead 4E was located, since lead 4F is absent. Also, because leads 4E and 4F are absent, the multiple connecting members 5 do not include wires 5G and 5I.

[0092] According to the second embodiment, semiconductor device A2, like semiconductor device A1, includes leads 4A, 4B, and 4C. Leads 4A and 4B overlap each other when viewed in the x-direction, and lead 4C overlaps both leads 4A and 4B when viewed in the y-direction. Therefore, like semiconductor device A1, semiconductor device A2 can shorten the distance of the wiring connecting semiconductor element 1 and semiconductor element 2 (in this embodiment, the lengths of each wire 5B, 5C and a portion of lead 4A). Therefore, semiconductor device A2 can reduce parasitic inductance and parasitic resistance, thereby achieving higher efficiency and energy savings.

[0093] According to the second embodiment, semiconductor device A2 has an extended lead 4D compared to semiconductor device A1. This allows semiconductor device A2 to reduce the wiring resistance in lead 4D compared to semiconductor device A1. In particular, since lead 4D is part of the aforementioned power system current path, semiconductor device A2 can suppress power loss in power conversion compared to semiconductor device A1. Similarly, semiconductor device A2 has an extended bonding portion 422 of lead 4B compared to semiconductor device A1. This allows semiconductor device A2 to reduce the wiring resistance in lead 4B compared to semiconductor device A1. In particular, since lead 4B is part of the aforementioned power system current path, semiconductor device A2 can suppress power loss in power conversion compared to semiconductor device A1. Furthermore, semiconductor element 2 is mounted on lead 4B, and heat from semiconductor element 2 is transferred to it. Therefore, the extension of lead 4B (bonding portion 422) improves the efficiency of heat diffusion from semiconductor element 2.

[0094] <Third Embodiment> Next, the semiconductor device A3 according to the third embodiment will be described with reference to Figures 9 and 10. Figure 9 is a plan view of the semiconductor device A3, in which the sealing member 6 is shown by dashed lines. Figure 10 is a cross-sectional view along line XX in Figure 9. In addition, as with the second embodiment, the lead frame 4 in the semiconductor device A3 does not necessarily have to include leads 4E and 4F.

[0095] As shown in Figures 9 and 10, semiconductor device A3 differs from semiconductor device A1 in that multiple connecting members 5 include clips 7A, 7B, 7C, and 7D instead of wires 5A, 5B, 5C, and 5D. Furthermore, in semiconductor device A3 shown in Figure 9, compared to semiconductor device A1, multiple pad portions 111 (drain electrodes 11) and multiple pad portions 121 (source electrodes 12) are swapped in the semiconductor element 1.

[0096] Clips 7A to 7D are each made by bending a plate-shaped metal member. The constituent material of clips 7A to 7D is, for example, a metal containing Cu or a metal containing Al. Alternatively, it may be a clad material such as CIC (Copper-Invar-Copper). In the example shown in 10, each clip 7A to 7D is bent perpendicularly to the upper surface of each lead 4A, 4B, and 4D, but they may also be inclined with respect to the z direction.

[0097] Clip 7A has a comb-like shape on one side in the x-direction (the x2 direction side in Figure 9), and this comb-like portion is joined to multiple pad portions 111. Clip 7B has a comb-like shape on one side in the x-direction (the x1 direction side in Figure 9), and this comb-like portion is joined to multiple pad portions 121. Clip 7C has a comb-like shape on one side in the x-direction (the x2 direction side in Figure 9), and this comb-like portion is joined to multiple pad portions 211. Clip 7D has a comb-like shape on one side in the x-direction (the x2 direction side in Figure 9), and this comb-like portion is joined to multiple pad portions 221. Note that the shapes of each clip 7A to 7D are not limited to the examples shown in Figure 9.

[0098] According to the third embodiment, semiconductor device A3, like semiconductor device A1, includes leads 4A, 4B, and 4C. Leads 4A and 4B overlap each other when viewed in the x-direction, and lead 4C overlaps both leads 4A and 4B when viewed in the y-direction. Therefore, like semiconductor device A1, semiconductor device A3 can shorten the distance of the wiring connecting semiconductor element 1 and semiconductor element 2 (in this embodiment, the lengths of each clip 7B, 7C and a portion of the lead 4A). Therefore, semiconductor device A3 can reduce parasitic inductance and parasitic resistance, thereby achieving higher efficiency and energy savings.

[0099] According to the third embodiment, the multiple connecting members 5 include clips 7A instead of wires 5A. Clips 7A can reduce the wiring resistance compared to wires 5A. In particular, since clips 7A are part of the aforementioned power system current path, semiconductor device A3 can suppress power loss in power conversion more effectively than semiconductor device A1. Similarly, the multiple connecting members 5 include clips 7B, 7C, and 7D instead of wires 5B, 5C, and 5D. Each clip 7B, 7C, and 7D can reduce the wiring resistance compared to each wire 5B, 5C, and 5D. In particular, since each clip 7B, 7C, and 7D is part of the aforementioned power system current path, semiconductor device A3 can suppress power loss in power conversion more effectively than semiconductor device A1.

[0100] In the third embodiment, each clip 7A to 7D is shown to have a structure in which a part of it is bent, but the embodiment is not limited to this. For example, as shown in Figure 11, each clip 7A to 7D may have a structure in which the thickness (dimension in the z direction) of a part of it is changed. Figure 11 is a cross-sectional view of a semiconductor device according to this modified example, and corresponds to the cross-section shown in Figure 10. For example, as shown in Figure 11, each clip 7A to 7D has a thin portion that is joined to semiconductor element 1 or semiconductor element 2, and a thick portion that is joined to any of leads 4A, 4B, or 4D.

[0101] In the third embodiment, the clip 7A was shown to have a comb-shaped portion, and this comb-shaped portion was joined to a plurality of pad portions 111 (drain electrodes 11), but the embodiment is not limited to this. For example, a plurality of strip-shaped clips 7A may be provided, and one clip 7A may be joined to each of the plurality of pad portions 111. The same applies to clips 7B to 7D.

[0102] <Fourth Embodiment> Next, the semiconductor device A4 according to the fourth embodiment will be described with reference to Figure 12. Figure 12 is a plan view of the semiconductor device A4, and the sealing member 6 is shown by dashed lines. In addition, in the semiconductor device A4, as in the second embodiment, the lead frame 4 does not have to include leads 4E and 4F. Also, in the semiconductor device A4, as in the third embodiment, clips 7A to 7D may be used instead of wires 5A to 5D.

[0103] As shown in Figure 12, semiconductor device A4 differs from semiconductor device A1 in the configuration of each electrode (drain electrodes 11, 21 and source electrodes 12, 22) of semiconductor elements 1 and 2. Specifically, the planar shapes of each pad portion 111, 121, 211, and 221 are different.

[0104] Each pad portion 111 of semiconductor device A4 is tapered. Specifically, in the x-direction, the y-dimension of each pad portion 111 decreases from the edge on the x1 side to the edge on the x2 side. In plan view, each pad portion 111 is approximately triangular. Each pad portion 121, 211, and 221 are also tapered. Specifically, in the x-direction, the y-dimension of each pad portion 121 decreases from the edge on the x2 side to the edge on the x1 side. In the x-direction, the y-dimension of each pad portion 211 decreases from the edge on the x1 side to the edge on the x2 side. In the x-direction, the y-dimension of each pad portion 221 decreases from the edge on the x2 side to the edge on the x1 side. In plan view, each pad portion 121, 211, and 221 is approximately triangular.

[0105] According to the fourth embodiment, semiconductor device A4, like semiconductor device A1, is equipped with leads 4A, 4B, and 4C. Leads 4A and 4B overlap each other when viewed in the x-direction, and lead 4C overlaps both leads 4A and 4B when viewed in the y-direction. Therefore, like semiconductor device A1, semiconductor device A4 can shorten the distance of the wiring connecting semiconductor element 1 and semiconductor element 2 (in this embodiment, the length of each wire 5B, 5C and a portion of lead 4A). Consequently, semiconductor device A4 can reduce parasitic inductance and parasitic resistance, thereby achieving higher efficiency and energy savings.

[0106] In the first to fourth embodiments, recesses 49 are shown formed on each lead 4A to 4J of each semiconductor device A1 to A4, but the invention is not limited to this, and recesses 49 may not be formed. Also, in each semiconductor device A1 to A4, the recesses 49 are shown to be formed along the outer edge of each lead 4A to 4J in a plan view, but the invention is not limited to this. For example, as shown in Figure 13, the recesses 49 may be formed along the edge of each lead 4A to 4J in a plan view that is in contact with any of the resin side surfaces 631 to 634. Figure 13 is a perspective view showing a semiconductor device according to the modified example, as viewed from the bottom side. In this case, a recess 69 is formed in the sealing member 6 along the outer edge in a plan view. The recesses 49 and 69 are connected. The semiconductor device shown in Figure 13 easily forms solder fillets when mounted on a circuit board of an electronic device or the like with solder. Therefore, it is possible to increase the possibility of visually confirming the soldering state of a leadless package semiconductor device.

[0107] In the first to fourth embodiments, the semiconductor devices A1 to A4 were shown to be in SON type package format, but the invention is not limited to this and may be composed of other package formats. For example, packages such as BGA (Ball Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), and QFN (Quad Flat Non-lead) may be used. It may also be configured in a J-type package. Note that these package formats are examples only and are not limited to these. For example, Figure 14 shows a semiconductor device (bottom view) formed in a QFN type package format.

[0108] The semiconductor device described herein is not limited to the embodiments described above. The specific configuration of each part of the semiconductor device described herein can be modified in various ways.

[0109] The semiconductor device relating to this disclosure includes embodiments relating to the following appendices. [Note 1] A first semiconductor element having a first main surface and a first back surface spaced apart in the thickness direction, wherein a first drain electrode, a first source electrode, and a first gate electrode are arranged on the first main surface, A second semiconductor element having a second main surface and a second back surface spaced apart in the thickness direction, wherein a second drain electrode, a second source electrode, and a second gate electrode are arranged on the second main surface, A control element that conducts to the first gate electrode and the second gate electrode, A lead frame containing multiple leads spaced apart from each other, It is equipped with, The plurality of leads include a first lead facing the first back surface and on which the first semiconductor element is mounted, a second lead facing the second back surface and on which the second semiconductor element is mounted, and a third lead on which the control element is mounted. The first lead and the second lead overlap each other when viewed in a first direction perpendicular to the thickness direction. A semiconductor device characterized in that the third lead overlaps both the first lead and the second lead when viewed in a second direction perpendicular to both the thickness direction and the first direction. [Note 2] The first gate electrode is positioned at the edge furthest from the second semiconductor element in the first direction. The semiconductor device according to Appendix 1, wherein the second gate electrode is located at the edge furthest from the first semiconductor element in the first direction. [Note 3] The semiconductor device according to Appendix 2, wherein both the first drain electrode and the first source electrode are strip-shaped extending in the first direction and are aligned in the second direction. [Note 4] The semiconductor device according to Appendix 3, wherein both the second drain electrode and the second source electrode are strip-shaped extending in the first direction and are aligned in the second direction. [Note 5] The system further comprises a first connecting member, one end of which is joined to the first drain electrode. The plurality of leads further include a fourth lead to which the other end of the first connecting member is joined, The semiconductor device according to Appendix 4, wherein the fourth lead overlaps both the first lead and the second lead when viewed in the first direction, and is located on the opposite side of the second lead with respect to the first lead in the first direction. [Note 6] The system further comprises a second connecting member, one end of which is joined to the first source electrode. The first lead includes a first die pad portion to which the first semiconductor element is bonded, and a first bonding portion to which the other end of the second connecting member is bonded. The semiconductor device described in Appendix 5, wherein the first bonding portion is located between the first semiconductor element and the second semiconductor element when viewed in the thickness direction. [Note 7] The system further comprises a third connecting member, one end of which is joined to the second drain electrode. The semiconductor device described in Appendix 6, wherein the other end of the third connecting member is joined to the first bonding portion. [Note 8] The semiconductor device described in Appendix 7, wherein the first die pad portion and the first bonding portion are integrally formed. [Note 9] The system further comprises a fourth connecting member, one end of which is joined to the second source electrode. The second lead includes a second die pad portion to which the second semiconductor element is bonded, and a second bonding portion to which the other end of the fourth connecting member is bonded. The semiconductor device according to Appendix 7 or Appendix 8, wherein the second die pad portion is closer to the first die pad portion than the second bonding portion when viewed in the thickness direction. [Note 10] The semiconductor device according to Appendix 9, wherein the second die pad portion and the second bonding portion are integrally formed. [Note 11] The system further comprises a fifth connecting member, one end of which is joined to the control element. The semiconductor device according to Appendix 9 or Appendix 10, wherein the other end of the fifth connecting member is joined to the first bonding portion. [Note 12] The semiconductor device according to Appendix 11, wherein the other end of the fifth connecting member is joined in the first direction between the other end of the second connecting member and the other end of the third connecting member. [Note 13] The system further comprises a sixth connecting member, one end of which is joined to the control element. The first gate electrode has two first pad portions spaced apart from each other in the second direction, The semiconductor device according to any one of appendices 9 to 12, wherein the other end of the sixth connecting member is joined to one of the two first pad portions. [Note 14] The semiconductor device described in Appendix 13, wherein the two first pad portions are at the same potential in the first semiconductor element. [Note 15] It further comprises a seventh connecting member, one end of which is joined to the other of the two first pad portions. The semiconductor device according to Appendix 13 or Appendix 14, wherein the plurality of leads further include a fifth lead to which the other end of the seventh connecting member is joined. [Note 16] One of the two first pad portions is positioned on the edge side of the first main surface that is closer to the third lead in the second direction, when viewed in the thickness direction. The semiconductor device according to Appendix 15, wherein the other of the two first pad portions is located on the edge side of the first main surface, in the second direction, that is furthest from the third lead, when viewed in the thickness direction. [Note 17] The semiconductor device according to Appendix 16, wherein the fifth lead is located next to the fourth lead in the second direction. [Note 18] It further comprises an eighth connecting member, one end of which is joined to the control element, The second gate electrode has two second pad portions that are spaced apart from each other in the second direction, The semiconductor device according to any one of appendices 15 to 17, wherein the other end of the eighth connecting member is joined to one of the two second pad portions. [Note 19] The semiconductor device according to Appendix 18, wherein the two second pad portions are at the same potential in the second semiconductor element. [Note 20] It further comprises a ninth connecting member, one end of which is joined to the other of the two second pad portions, The semiconductor device according to Appendix 18 or Appendix 19, wherein the plurality of leads further include a sixth lead to which the other end of the ninth connecting member is joined. [Note 21] One of the two second pad portions is positioned on the edge side of the second main surface, closer to the third lead, in the second direction, when viewed in the thickness direction. The semiconductor device according to Appendix 20, wherein the other of the two second pad portions is located on the edge side of the second main surface, in the second direction, that is furthest from the third lead, when viewed in the thickness direction. [Note 22] The semiconductor device according to Appendix 21, wherein the sixth lead is located next to the second die pad portion in the second direction. [Note 23] The semiconductor device described in Appendix 22, wherein the fifth lead and the sixth lead overlap when viewed in the first direction. [Note 24] It further comprises a plurality of 10th connecting members, each having one end joined to the control element, The plurality of leads further include a plurality of seventh leads to which the other ends of each of the plurality of tenth connecting members are joined. The semiconductor device described in any of Appendix 9 to Appendix 23, wherein all of the aforementioned seventh leads overlap the third leads when viewed in the first direction. [Note 25] The semiconductor device as described in Appendix 24, wherein the plurality of seventh leads include those that overlap the fourth lead when viewed in the second direction and those that overlap the second die pad portion when viewed in the second direction. [Note 26] The semiconductor device according to any one of the appendices 1 to 25, wherein the constituent materials of the first semiconductor device and the second semiconductor device are gallium nitride. [Explanation of Symbols]

[0110] A1~A4: Semiconductor equipment 1: Semiconductor element 1a: Main surface of the element 1b: Element back side 11: Drain electrode 111: Pad section 12: Source electrode 121: Pad section 13: Grid gate 131,132: Pad section 2: Semiconductor elements 2a: Main surface of the element 2b: Element back side 21: Drain electrode 211: Pad section 22: Source electrode 221: Pad section 23: Grid gate 231,232: Pad section 3: Control element 3a: Main surface of the element 3b: Back surface of the element 31: Element electrode 311~318: Pad section 4: Lead frame 4A~4J: Lead 411,421: Die pad section 412,422: Bonding section 49: Recess 5: Connecting member 5A~5N: Wire 6: Sealing member 7A~7D: Clip 61: Resin main surface 62: Resin back 631~634: Resin side 69: Recess C1~C4: Capacitors D1: Diode DR1, DR2: Drive circuits GND1: 1st ground terminal GND2: 2nd ground terminal L1: Inductor LO:Load PS1,PS2: External power supply T1~T10: External terminals TC1~TC8: Connection terminals

Claims

1. A first semiconductor element having a first main surface facing one direction in the thickness direction, with a first drain electrode, a first source electrode, and a first gate electrode arranged on the first main surface, A second semiconductor element having a second main surface that faces the same direction as the first main surface in the thickness direction, and having a second drain electrode, a second source electrode, and a second gate electrode arranged on the second main surface, A lead frame including the first and second leads, It is equipped with, The first lead includes a first die pad portion on which the first semiconductor element is mounted and a first bonding portion located next to the first die pad portion. The semiconductor device is characterized in that the second lead is positioned at a first distance from the first bonding portion in a first direction toward the first bonding portion from the first die pad portion, and includes a second die pad portion on which the second semiconductor element is mounted.

2. A first connecting member that electrically connects the first source electrode and the first bonding portion, The semiconductor device according to claim 1, further comprising a second connecting member for electrically connecting the second drain electrode and the first bonding portion.

3. The semiconductor device according to claim 2, wherein each of the first connecting member and the second connecting member extends in the first direction when viewed in the thickness direction.

4. The lead frame includes a third lead positioned at a second distance from the first lead in a second direction perpendicular to the thickness direction and the first direction, The third lead further comprises a control element, The semiconductor device according to claim 2 or 3, wherein the control element is electrically connected to the first gate electrode and the second gate electrode.

5. It further comprises a third connecting member, one end of which is joined to the control element, The semiconductor device according to claim 4, wherein the other end of the third connecting member is joined to the first bonding portion.

6. The semiconductor device according to claim 5, wherein the other end of the third connecting member is joined between the first connecting member and the second connecting member in the first direction.

7. The semiconductor device according to any one of claims 1 to 6, wherein the first die pad portion and the first bonding portion are integrally formed.

8. The second lead includes a second bonding portion located next to the second die pad portion in the first direction, The semiconductor device according to any one of claims 1 to 7, wherein the second bonding portion is located on the opposite side of the first lead with respect to the second die pad portion in the first direction.

9. The semiconductor device according to claim 8, further comprising a fourth connecting member for electrically connecting the second source electrode and the second bonding portion.

10. The semiconductor device according to claim 9, wherein the fourth connecting member extends in the first direction when viewed in the thickness direction.

11. The semiconductor device according to any one of claims 8 to 10, wherein the second die pad portion and the second bonding portion are integrally formed.

12. The semiconductor device according to any one of claims 1 to 11, wherein the first lead and the second lead overlap each other when viewed in the first direction.

13. The semiconductor device according to any one of claims 1 to 12, wherein the constituent material of the first semiconductor element and the second semiconductor element is gallium nitride.

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