Package substrates, semiconductor devices

Abstract

To achieve both GND potential stability and prevention of delamination.SOLUTION: A package substrate 1 that fixes a semiconductor chip 11 with a back surface 11b at a predetermined potential to a surface 1a facing the back surface includes: a wiring layer 3a having a predetermined potential: an insulating layer 4 laminated on an upper surface 3a1 of the wiring layer and having a plurality of openings 41 in which a part of the wiring layer is exposed formed at a position facing the back surface of the semiconductor chip; and a plurality of conductive bumps 6 provided on the upper surface of the wiring layer exposed through the openings, and each having a top portion 6a that is closer to the back surface of the semiconductor chip than a front surface 4a of the insulating layer.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a package substrate and a semiconductor device.

Background Art

[0002] In a BGA (ball grid array) package as a semiconductor device, a semiconductor chip is mounted on a BGA substrate (package substrate) with the back surface of the semiconductor chip facing the surface of the BGA substrate (package substrate). Here, as a method for stabilizing the GND (ground) voltage of the semiconductor chip, there is a method of conducting from the back surface of the semiconductor chip to the internal wiring of the BGA substrate through silver paste. When this method is used, in order to ensure conductivity, a technique is known in which a part of the solder resist (SR) on the surface of the BGA substrate is opened, and the copper pattern of the uppermost layer wiring facing the back surface of the semiconductor chip is exposed from this opening (Patent Document 1).

[0003] Here, when operating a device that operates at a high voltage and responds quickly, ensuring the stability of the GND voltage is required. If this cannot be ensured, there is a risk of electrical characteristic defects occurring in the device operation. In order to improve the GND level stability, it is effective to increase the opening area of the solder resist on the surface of the BGA substrate. Also, the silver paste has an adhesion to the solder resist.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, silver paste has limitations in its adhesion to copper and surface plating compared to its adhesion to solder resist. Therefore, if the opening area of ​​the solder resist is increased too much, the adhesion between the BGA substrate and the silver paste will decrease, and delamination may occur starting from the contact points between the copper and the silver paste.

[0006] In other words, when the opening area of ​​the solder resist is increased to improve the GND level stability of the semiconductor chip, the adhesion between the silver paste and the solder resist decreases, which can lead to problems such as delamination when a load is applied, or delamination during reflow soldering. Therefore, there is a demand to simultaneously improve the GND level stability of the semiconductor chip and suppress delamination between the semiconductor chip and the BGA substrate.

[0007] This invention has been made in view of the above circumstances, and aims to provide a package substrate and semiconductor device that can simultaneously improve the GND level stability of a semiconductor chip and improve operational stability by preventing delamination. [Means for solving the problem]

[0008] A package substrate according to one aspect of the present invention is A package substrate for fixing a semiconductor chip, whose back surface is at a predetermined potential, to a surface facing the back surface, A wiring layer having the predetermined potential, An insulating layer is laminated on the upper surface of the wiring layer and has a plurality of openings formed therein at a position facing the back surface of the semiconductor chip, in which a part of the wiring layer is exposed. A plurality of conductive bumps are provided on the upper surface of the wiring layer, each exposed from the aforementioned opening, and having a top portion that is closer to the back surface of the semiconductor chip than to the surface of the insulating layer, Having, This resolved the above issues.

[0009] Another aspect of the present invention relates to a semiconductor device, The above package substrate, The aforementioned semiconductor chip, A conductive adhesive for fixing the back surface of the semiconductor chip, the top of the conductive bump, and the surface of the insulating layer, Having, It is possible. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide a package substrate and semiconductor device that can simultaneously achieve improved GND level stability and improved operational stability due to delamination. [Brief explanation of the drawing]

[0011] [Figure 1] This is a cross-sectional view showing a first embodiment of the package substrate according to the present invention. [Figure 2] This is a top view showing a first embodiment of the package substrate according to the present invention. [Figure 3] This is a cross-sectional view showing a first embodiment of a semiconductor device according to the present invention. [Figure 4] This is a cross-sectional view showing a second embodiment of the semiconductor device according to the present invention. [Modes for carrying out the invention]

[0012] Hereinafter, a first embodiment of the package substrate and semiconductor device according to the present invention will be described with reference to the drawings. Figure 1 is a top view showing the package substrate in this embodiment. Figure 2 is a cross-sectional view showing the package substrate in this embodiment. In the figures, reference numeral 1 denotes the package substrate.

[0013] As shown in FIGS. 1 and 2, the package substrate 1 according to this embodiment is a BGA substrate. Solder balls (balls) 2 as external terminals are arranged on the back surface 1b of the rectangular package substrate 1. The package substrate 1 has a plurality of wiring layers 3 such as signal wirings or connection wirings, and vertical wirings 3c such as through holes installed inside, on the surface, and near the back surface thereof.

[0014] The package substrate 1 mounts and connects a semiconductor chip 11, which will be described later, on the surface 1a opposite to the solder balls (balls) 2. The semiconductor chip 11 is connected to the upper connection wiring layer (wiring layer) 3a closest to the surface 1a. A solder resist (insulating layer) 4 is laminated on the upper connection wiring layer (wiring layer) 3a. An opening 41 is formed in the solder resist (insulating layer) 4. The upper connection wiring layer (wiring layer) 3a exposed from this opening 41 serves as a terminal connected to the semiconductor chip 11.

[0015] Similarly, the semiconductor chip 11 is connected to the lower connection wiring layer (wiring layer) 3b closest to the back surface 1b of the package substrate 1. An insulating layer 5 is laminated on the lower connection wiring layer (wiring layer) 3b. An opening 5a is formed in the insulating layer 5. The lower connection wiring layer (wiring layer) 3b exposed from this opening 5a serves as a terminal connected to the solder balls 2. In the package substrate 1, the wiring layer 3 may be formed in addition to the above upper connection wiring layer (wiring layer) 3a, lower connection wiring layer (wiring layer) 3b, and vertical wiring 3c, and its configuration is not particularly limited. However, in this embodiment, other wirings are not shown. The upper connection wiring layer (wiring layer) 3a is set to the GND voltage of the semiconductor chip 11.

[0016] On the surface 1a of the package substrate 1, as shown in FIG. 2, a plurality of openings 41 are formed within a chip region (chip area) 1C that overlaps the semiconductor chip 11 in a plan view. The chip region (chip area) 1C is set corresponding to the contour shape of the semiconductor chip 11 to be described later, as shown by the dashed line in FIG. 2. A bonding region (bonding area) 1D for connecting bonding wires for connecting to the electrodes of the semiconductor chip 11 is formed near the outer periphery of the chip region (chip area) 1C.

[0017] The opening 41 opens to the surface 4a of the solder resist (insulating layer) 4. A plurality of openings 41 are formed separately from each other in the chip region (chip area) 1C. Although not shown, openings are also formed in the solder resist (insulating layer) 4 in the bonding region (bonding area) 1D.

[0018] In the present embodiment, all of the plurality of openings 41 have the same circular contour shape, but the contour is not limited to this. Also, all of the plurality of openings 41 have the same diameter dimension, but this diameter dimension does not have to be the same. Further, all of the plurality of openings 41 are arranged with the same separation distance, but the distance relationship is not limited to this.

[0019] The opening 41 penetrates the solder resist (insulating layer) 4 in the thickness direction. The upper surface 3a1 of the upper connection wiring layer (wiring layer) 3a is exposed in the opening 41. The opening 41 has the same contour shape over the entire length in the thickness direction of the solder resist (insulating layer) 4. The openings 41 all have the same depth dimension D1 in the chip region (chip area) 1C. The depth dimension D1 of the opening 41 is equal to the thickness dimension D1 of the solder resist (insulating layer) 4 in the chip region (chip area) 1C.

[0020] In other words, the solder resist (insulating layer) 4 has a uniform thickness D1 throughout at least the entire chip area 1C. This configuration is only required if the depth D1 of the openings 41 formed in the chip area 1C is equal, and is not limited to the depth of openings formed in other areas. Various configurations can be adopted for the components and their forms in the package substrate 1.

[0021] Each of the upper connecting wiring layers (wiring layers) 3a exposed in the opening 41 is provided with a conductive bump 6. Conductive bumps 6 can be formed in all openings 41 in the chip region (chip area) 1C. There may be openings 41 in the chip region (chip area) 1C that do not have conductive bumps 6. In the chip region (chip area) 1C, it is preferable that conductive bumps 6 be formed in at least half of the openings 41. In the chip region (chip area) 1C, it is more preferable that conductive bumps 6 be formed in two-thirds or more of the openings 41.

[0022] Furthermore, it is preferable that conductive bumps 6 are formed in openings 41 located along the periphery of the chip region (chip area) 1C. It is also preferable that conductive bumps 6 are formed in openings 41 located near the center of the chip region (chip area) 1C.

[0023] The lower end 6b of the conductive bump 6 contacts the upper surface 3a1 of the upper connection wiring layer (wiring layer) 3a that is exposed in the opening 41. The conductive bump 6 protrudes from the opening 41 in the thickness direction. In other words, the top portion 6a of the conductive bump 6 is formed at a position that protrudes from the opening 41 in the thickness direction. The top portion 6a of the conductive bump 6 is formed at a position that protrudes from the surface 4a of the solder resist (insulating layer) 4 by a predetermined protrusion height (height) D2 in the thickness direction. The top portion 6a of the conductive bump 6 is closer to the back surface 10b of the semiconductor chip 11, which will be described later, than to the surface 4a of the solder resist (insulating layer) 4.

[0024] In the thickness direction of the package substrate 1, the protrusion height D2 of the top 6a of the conductive bump 6 protruding from the surface 4a of the solder resist (insulating layer) 4 toward the back surface 11b of the semiconductor chip 11 (described later) is smaller than the depth D1 of the opening 41. In other words, D2 ≤ D1 It is preferable that this be the case.

[0025] The protrusion heights D2 of the multiple conductive bumps 6 can all be made equal. Alternatively, the protrusion heights D2 of the multiple conductive bumps 6 can be formed as the average value of the heights of the conductive bumps 6 that protrude from at least the surface 4a of the solder resist (insulating layer) 4.

[0026] When viewed in the thickness direction of the package substrate 1, the contour of the conductive bump 6 is smaller than or the same as the contour of the opening 41 formed in the solder resist (insulating layer) 4. Here, the contour of the conductive bump 6 refers to the outer contour when the package substrate 1 is viewed from above, and if the shape of the conductive bump 6 changes in the height direction of the conductive bump 6, it refers to its maximum outer contour. If the contour of the conductive bump 6 is smaller than the contour of the opening 41, there may be a portion within the opening 41 in which the upper surface 3a1 of the upper connecting wiring layer (wiring layer) 3a is exposed.

[0027] For example, if the conductive bump 6 is made of copper pillar, the contour of the conductive bump 6 is circular, the same as the contour of the opening 41, and the shape of the conductive bump 6 does not change in the height direction. Therefore, in this case, the conductive bump 6 made of copper pillar is formed in a substantially cylindrical shape having almost the same cross-sectional shape as the opening 41. The substantially cylindrical conductive bump 6 is erected from the upper surface 3a1 of the upper connection wiring layer (wiring layer) 3a exposed in the opening 41. Furthermore, in this case, the top portion 6a of the conductive bump 6 can be formed in a plane that is substantially flush with the upper surface 3a1 of the upper connecting wiring layer (wiring layer) 3a.

[0028] When the conductive bump 6 is made of copper pillars, in order to manufacture it, a surface 4a of the solder resist (insulating layer) 4 is formed on a substrate on which an upper connection wiring layer (wiring layer) 3a is formed by a predetermined manufacturing process. Furthermore, a photoresist is formed by a photolithography process or the like and exposed and developed to form a solder resist (insulating layer) 4 having a pattern corresponding to the opening 41 and a predetermined pattern.

[0029] Subsequently, a predetermined pattern, such as an opening 41, is formed on the solder resist (insulating layer) 4, exposing the upper surface 3a1 corresponding to the opening 41. Furthermore, after forming a predetermined mask that covers everything except the opening 41, conductive bumps 6, which are copper pillars, are grown on the upper surface 3a1 exposed from the opening 41 by plating or the like. At this time, the conductive bumps 6 are formed to a protrusion height D2 that extends from the surface 4a of the solder resist (insulating layer) 4 by growing them to a predetermined film thickness, for example by electroplating or electroless plating. This forms cylindrical conductive bumps 6 having a contour shape corresponding to the contour shape of the opening 41.

[0030] Alternatively, if the conductive bump 6 is a gold ball, the contour of the conductive bump 6 is smaller than or the same as the contour of the opening 41, and in the height direction of the conductive bump 6, the shape of the conductive bump 6 tapers towards the top 6a. In this case, the gold ball conductive bump 6 can be formed in a teardrop shape, tapering from the lower end 6b, which has approximately the same cross-sectional shape as the opening 41, towards the top 6a. This columnar conductive bump 6 is erected from the upper surface 3a1 of the upper connection wiring layer (wiring layer) 3a exposed in the opening 41. Furthermore, in this case, the top portion 6a of the conductive bump 6 can be formed in a pointed shape that moves away from the upper surface 3a1 of the upper connecting wiring layer (wiring layer) 3a. In this case, the top portion 6a of the formed conductive bump 6 may be left as is after the gold wire has been cut, or it may be shaped by hammering or other processes.

[0031] If the conductive bump 6 is a gold ball, in order to manufacture it, a solder resist (insulating layer) 4 having a pattern corresponding to the opening 41 and a predetermined pattern is formed, similar to the case where it is a copper pillar.

[0032] Subsequently, conductive bumps 6 are formed using conventionally known methods such as wire bonding. Specifically, after forming a gold ball with a wire bonder so as to contact the upper surface 3a1 exposed from the opening 41, a gold wire is formed into a predetermined shape and then cut to form conductive bumps 6 up to a protrusion height D2 that protrudes from the surface 4a of the solder resist (insulating layer) 4. This forms a ball-shaped conductive bump 6 that has a contour shape corresponding to the contour shape of the opening 41 and is deformed so that its top portion 6a protrudes.

[0033] Furthermore, the top portion 6a of the conductive bump 6 can be given a predetermined surface condition. Specifically, it is preferable to form predetermined irregularities on the surface of the top portion 6a in order to improve contact and adhesion with the silver paste 12 described later. This is the same whether the conductive bump 6 is a copper pillar or a gold ball.

[0034] In this embodiment, the package substrate 1 has a conductive bump 6 protruding from the top 6a of the upper connection wiring layer (wiring layer) 3a exposed in the opening 41. As a result, the surface area of ​​the conductive bump 6 is larger than the area of ​​the upper surface 3a1 of the upper connection wiring layer (wiring layer) 3a exposed in the opening 41. This increases the contact area with the silver paste (conductive adhesive) 12 when connecting from the upper connection wiring layer (wiring layer) 3a to the semiconductor chip 11, as will be described later. The bonding surface area between the silver paste 12 and the upper connection wiring layer (wiring layer) 3a increases.

[0035] This makes it possible to reduce resistance. Therefore, by improving the conductivity between the upper connection wiring layer (wiring layer) 3a and the semiconductor chip 11, for example, by improving conductivity with the upper connection wiring layer (wiring layer) 3a, which is the GND voltage, it is possible to ensure stable GND voltage at the semiconductor chip 11. At the same time, it is possible to reduce resistance and improve heat dissipation characteristics. Furthermore, since the area of ​​the opening 41 does not change, the adhesion between the silver paste 12 and the surface 4a of the solder resist (insulating layer) 4 does not deteriorate.

[0036] The protrusion height D2 of the top 6a of the conductive bump 6 protruding from the surface 4a of the solder resist (insulating layer) 4 is smaller than the depth D1 of the opening 41. As a result, when the conductive bump 6 is connected to the back surface 11b of the semiconductor chip 11 with the silver paste 12, the conductive bump 6 and the back surface 11b of the semiconductor chip 11 do not separate more than necessary, thereby improving conductivity and ensuring a stable GND voltage at the semiconductor chip 11.

[0037] Figure 3 is a cross-sectional view showing a semiconductor device in this embodiment. As shown in Figure 3, the semiconductor device 10 according to this embodiment includes a package substrate 1, a semiconductor chip 11, and a silver paste (conductive adhesive) 12. The semiconductor device 10 is set with a semiconductor chip 11 fixed (mounted) to the surface 1a of the package substrate 1, and the back surface 11b of the semiconductor chip 11 and the surface 1a of the package substrate 1 are bonded together with silver paste (conductive adhesive) 12. The conductive bumps 6, which are electrodes on the package substrate 1, and the back surface 11b of the semiconductor chip 11 are electrically connected by the silver paste (conductive adhesive) 12.

[0038] Furthermore, in the semiconductor device 10, the surface 11a of the semiconductor chip 11 and the surface 1a of the package substrate 1 are electrically connected by bonding wires 13. The bonding wires 13 are connected to electrodes formed in a bonding region (bonding area) 1D on the surface 1a of the package substrate 1. Note that the electrodes in this bonding region (bonding area) 1D are not shown in the diagram. On the surface 1a of the package substrate 1 of the semiconductor device 10, the semiconductor chip 11, bonding wires 13, and silver paste (conductive adhesive) 12 are sealed by a transfer mold 14.

[0039] Here, the back surface 11b of the semiconductor chip 11, the top surface 6a of the conductive bump 6 and the surface 4a of the solder resist (insulating layer) 4, and the silver paste (conductive adhesive) 12 are formed as follows. In the thickness direction of the package substrate 1, it is preferable that the separation distance D3 between the back surface 11b of the semiconductor chip 11 and the surface 4a of the solder resist (insulating layer) 4 is greater than or equal to the thickness D1 of the solder resist (insulating layer) 4.

[0040] In other words, the protruding height D2 of the top 6a of the conductive bump 6, the depth D1 of the opening 41, that is, the thickness D1 of the solder resist (insulating layer) 4, and the thickness D3 of the silver paste (conductive adhesive) 12 from the surface 4a of the solder resist (insulating layer) 4 to the back surface 11b of the semiconductor chip 11 are, D2 ≤ D1 ≤ D3 It is preferable that this be the case.

[0041] By setting the dimensional relationship in this way, the protruding heights D2 of multiple conductive bumps 6 can be made as close as possible. This prevents problems such as the granular material being pushed out when silver paste (conductive adhesive) 12 is applied between the top 6a of the conductive bump 6 and the back surface 11b of the semiconductor chip 11, due to the separation distance D3 from the surface 4a of the solder resist (insulating layer) 4 to the back surface 11b being too close. Furthermore, the top 6a of the conductive bump 6 and the back surface 11b of the semiconductor chip 11 are not too far apart, which would impair the conductive performance, i.e., the stability of the GND voltage at the semiconductor chip 11.

[0042] The manufacturing method for the semiconductor device 10 according to this embodiment involves applying silver paste (conductive adhesive) 12 to the surface 1a of the package substrate 1. After that, the semiconductor chip 11 is mounted on the package substrate 1, and then heat treatment is performed to bond the back surface 1b of the semiconductor chip 11 and the surface 1a of the package substrate 1 with the silver paste (conductive adhesive) 12. This sets the semiconductor chip 11 fixed (mounted) to the surface of the package substrate 1, and electrically connects the conductive bumps 6, which are electrodes on the package substrate 1 and electrodes that apply a bias to the back surface 11b of the semiconductor chip 11, to the back surface 1b of the semiconductor chip 11 using the silver paste (conductive adhesive) 12.

[0043] Subsequently, a wire bonding apparatus is used to electrically connect bonding pads on the surface 11a and other parts of the semiconductor chip 11, which serve as external electrodes, to external electrode pads in the bonding area 1D of the package substrate 1, using bonding wires 13 made of gold wire, aluminum wire, or the like. Furthermore, the semiconductor chip 11 and the bonding wires 13 are sealed with a transfer mold 14.

[0044] According to the semiconductor device 10 of this embodiment, since the conductive bump 6 is formed protruding from the surface 4a of the solder resist (insulating layer) 4, the conductive connection area between the conductive bump 6 and the silver paste (conductive adhesive) 12 is larger than the area of ​​the upper surface 3a1 exposed inside the opening 41. This ensures the necessary contact area between the conductive bump 6 and the silver paste (conductive adhesive) 12, thereby ensuring the stability of the GND voltage during the operation of the semiconductor chip 11, which is a high-voltage, high-speed response device, and reducing the occurrence of electrical characteristic malfunctions during device operation.

[0045] This makes it possible to improve the stability of the GND level without increasing the area of ​​the opening 41, that is, the area of ​​the upper surface 3a1 of the upper connection wiring layer (wiring layer) 3a exposed in the opening 41.

[0046] At the same time, since the area of ​​the opening 41, that is, the area of ​​the upper surface 3a1 of the upper connection wiring layer (wiring layer) 3a exposed to the opening 41, does not change, the area of ​​the surface 4a of the solder resist (insulating layer) 4 in the chip region (chip area) 1C also does not change. Therefore, the adhesion with the solder resist (insulating layer) 4 is not reduced. This prevents delamination from occurring due to stress such as applied load.

[0047] In other words, the semiconductor device 10 according to this embodiment makes it possible to simultaneously achieve improved GND level stability and improved operational stability due to delamination.

[0048] A second embodiment of the package substrate and semiconductor device according to the present invention will be described below with reference to the drawings. Figure 4 is a cross-sectional view showing the semiconductor device in this embodiment. The only difference in this embodiment from the first embodiment described above is the backside metal layer. Other components corresponding to the first embodiment described above are denoted by the same reference numerals and their descriptions are omitted.

[0049] As shown in Figure 4, the semiconductor device 10 according to this embodiment has a backside metal layer 15 formed on the back surface 11b of the semiconductor chip 11. The backside metal layer 15 is made of a predetermined metal and covers the entire back surface 11b of the semiconductor chip 11. In the semiconductor device 10 according to this embodiment, the conductivity between the semiconductor chip 11 and the package substrate 1 can be improved by forming a backside metal layer 15.

[0050] Furthermore, when forming the backside metal layer 15, it is possible to reduce the thickness D3 of the silver paste (conductive adhesive) 12 in accordance with the thickness of the backside metal layer 15. Alternatively, when forming the backside metal layer 15, it is also possible to set the thickness D3 of the silver paste (conductive adhesive) 12 to the above-described relationship without taking the thickness of the backside metal layer 15 into consideration.

[0051] In this embodiment, the same effects as those of the above-described embodiment can be achieved.

[0052] An example of an embodiment of the present invention will be described below.

[0053] In the semiconductor device of the present invention, its dimensions can be set as follows. Opening diameter: φ0.25mm Number of openings in chip area 1C: 41; approximately 130. Area of ​​the chip region (chip area) 1C excluding the opening 41: 160 mm² 2 Solder resist (insulating layer) 4 thickness D1: 30 μm Aperture 41, depth D1; 30 μm Silver paste (conductive adhesive) 12, thickness D3; 40 μm The protrusion height D2 of the top 6a of the conductive bump 6 from the surface 4a of the solder resist (insulating layer) 4 is 20 μm. Conductive bump 6; gold ball

[0054] The GND level stability and delamination occurrence were compared between the semiconductor device of the present invention as described above and a semiconductor device with the same configuration except for the absence of conductive bumps 6. It was found that the semiconductor device of the present invention with conductive bumps 6 showed improved GND level stability and significantly suppressed delamination. Furthermore, it was found that the height (D1+D2) from the upper surface 3a1 of the upper connection wiring layer (wiring layer) 3a to the top 6a of the conductive bump 6 is preferably about 2 / 3 or 5 / 7 of the distance (D1+D3) from the upper surface 3a1 of the upper connection wiring layer (wiring layer) 3a to the back surface 11b of the semiconductor chip 11. [Explanation of symbols]

[0055] 1…Package substrate 1a…Surface 1b…Back side 1C... Chip area 1D…Bonding area 2... Solder ball (ball) 2... Solder ball 3...Wiring layer 3a… Upper connection wiring layer (wiring layer) 3a1…Top surface 3b…Bottom connection wiring layer (wiring layer) 4…Solder resist (insulating layer) 4a…Surface 41…Opening 5…Insulating layer 5a...Opening 6... Conductive bump 6a…Top 6b…lower end 10… Semiconductor equipment 10b…Back side 11… Semiconductor chips 11b…Back side 12…Silver paste (conductive adhesive) 13…Bonding wire 14…Transfer mold 15…Backside metal layer

Claims

1. A semiconductor chip with its back surface at a predetermined potential, A package substrate for fixing the semiconductor chip to the surface facing the back surface, A conductive adhesive for fixing the back surface of the semiconductor chip and the front surface of the package substrate, A semiconductor device having, The aforementioned package substrate is A wiring layer having the predetermined potential, An insulating layer is laminated on the upper surface of the wiring layer and has a plurality of openings formed therein at a position facing the back surface of the semiconductor chip, in which a part of the wiring layer is exposed. A plurality of conductive bumps are provided on the upper surface of the wiring layer, each exposed from the aforementioned opening, and having a top portion that is closer to the back surface of the semiconductor chip than to the surface of the insulating layer, It has, In the thickness direction, the height at which the top of the conductive bump protrudes from the surface of the insulating layer toward the back surface of the semiconductor chip is smaller than the depth of the opening. In the thickness direction, the distance between the back surface of the semiconductor chip and the surface of the insulating layer is greater than or equal to the thickness of the insulating layer. A semiconductor device characterized by the following features.

2. The conductive bump is a copper pillar, the top of which is formed on a plane substantially parallel to the upper surface of the wiring layer, and has irregularities formed to improve adhesion with the conductive adhesive. The semiconductor device according to claim 1, characterized in that it is a semiconductor device.

3. The contour of the conductive bump, viewed from above, is smaller than or the same as the contour of the opening formed in the insulating layer. The semiconductor device according to claim 1, characterized in that it is a semiconductor device.

4. A backside metal layer is formed on the back surface of the semiconductor chip. The semiconductor device according to claim 1, characterized in that it is a semiconductor device.

Images