Solar cell and its manufacturing method, stacked cell, and photovoltaic module

Abstract

To provide, in the field of photovoltaic power, a solar cell and a method for manufacturing the same, a stacked cell, and a photovoltaic module.SOLUTION: The solar cell includes a substrate, a doped semiconductor layer located on the substrate, a passivation layer covering a surface of the doped semiconductor layer, and a plurality of electrodes arranged along a first direction. A second surface of the substrate is provided with a texture structure. The doped semiconductor layer is provided with a first hole penetrating the doped semiconductor layer, the first hole corresponding in a one-to-one manner with the texture structure. The texture structure is exposed from a bottom of the first hole. The passivation layer fills the first hole and covers the texture structure. The electrodes penetrate a thickness of the passivation layer so as to be in electrical contact with the doped semiconductor layer. The solar cell and the method for manufacturing the same, the stacked cell, and the photovoltaic module provided by the present embodiment can improve the photoelectric conversion efficiency of the solar cell.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] Embodiments of the present application relate to the field of photovoltaic power, and in particular, to solar cells and their manufacturing methods, stacked cells, and photovoltaic modules.

Background Art

[0002] Currently, with the depletion of fossil energy, solar cells are being increasingly widely used as an alternative for new energy. A solar cell is a device that converts solar light energy into electrical energy. Solar cells utilize the principle of photovoltaic power generation to generate carriers and extract the carriers at the electrodes, thereby contributing to the effective utilization of electrical energy.

[0003] TOPCon (Tunnel Oxide Passivated Contact) cells or TBC (TOPCon-BC) cells consisting of IBC using TOPCon technology require the fabrication of a passivation contact structure such as an ultrathin tunnel oxide layer and a highly doped polycrystalline silicon layer on the silicon surface. By utilizing the chemical passivation of the tunnel oxide layer and the field passivation effect of the polycrystalline silicon layer, the recombination rate of minority carriers on the silicon surface can be significantly reduced. On the other hand, the highly doped polycrystalline layer significantly improves the conductive performance of majority carriers and contributes to improving the open-circuit voltage and backside factor of the cell.

[0004] Chemical vapor deposition (CVD, LPCVD) is the main technology for manufacturing the tunnel oxide layer and the polycrystalline silicon layer. For example, low-pressure chemical vapor deposition (LPCVD) has the advantages of low cost, high production volume, and high performance of the produced film, and is currently widely applied. However, there may be some problems that affect the cell efficiency during the process of manufacturing the backside passivation contact structure.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The embodiments of this application provide a solar cell and a method for manufacturing the same, a stacked cell, and a photovoltaic module, which are advantageous in improving the photoelectric conversion efficiency of the solar cell. [Means for solving the problem]

[0006] According to some embodiments of the present invention, in one embodiment of the present invention, a solar cell is provided which includes a substrate, a doping semiconductor layer located on the substrate, a passivation layer covering the surface of the doping semiconductor layer, and a plurality of electrodes arranged along a first direction, wherein a portion of the surface of the substrate has a textured structure, the doping semiconductor layer has first holes penetrating the doping semiconductor layer, the first holes correspond one-to-one with the textured structure, the textured structure is exposed from the bottom of the first holes, the passivation layer fills the first holes and covers the textured structure, and the electrodes penetrate the thickness of the passivation layer and are in electrical contact with the doping semiconductor layer.

[0007] In some embodiments, the texture structure includes at least one protrusion structure, and the number of protrusion structures corresponding to one of the first holes is 1 to 5.

[0008] In some embodiments, the substrate comprises a first surface and a second surface that are positioned opposite each other, the first surface having a pyramidal structure, the pyramidal structure including a plurality of pyramids, and the second surface having a textured structure, wherein the one-dimensional dimension of the protrusions of the textured structure is less than or equal to the one-dimensional dimension of the pyramids.

[0009] In some embodiments, the one-dimensional dimension of the protrusion structure is in the range of 1 μm to 20 μm, and the height of the protrusion structure is in the range of 1 μm to 20 μm.

[0010] In some embodiments, the second surface comprises a tower foundation structure, the tower foundation structure includes a plurality of tower foundations, and some of the tower foundations are in contact with adjacent tower foundations.

[0011] In some embodiments, the one-dimensional dimension of the first hole ranges from 5 μm to 20 μm.

[0012] In some embodiments, the substrate is provided with grooves, the grooves correspond one-to-one with the first holes, and the texture structure is located within the grooves.

[0013] In some embodiments, the depth of the groove is 0.1 μm to 4 μm.

[0014] In some embodiments, the doped semiconductor layer includes at least one of an amorphous silicon doped layer, a polycrystalline silicon doped layer, a microcrystalline silicon doped layer, a silicon carbide doped layer, or a crystalline silicon doped layer.

[0015] In some embodiments, the doping semiconductor layer has a boundary, and the number of first holes near the boundary is greater than the number of first holes far from the boundary.

[0016] In some embodiments, the solar cell further includes a dielectric layer located between the substrate and the doped semiconductor layer, the dielectric layer having second holes corresponding to the first holes, and the textured structure being exposed from the bottom of the second holes.

[0017] In some embodiments, some of the electrodes are located in the first hole and cover the textured structure.

[0018] In some embodiments, the second surface comprises alternating P regions and N regions with a gap region between the P regions and the N regions, the doping semiconductor layer comprises a first doping semiconductor layer located in the P region and a second doping semiconductor layer located in the N region, the electrodes comprises a first electrode and a second electrode, the first electrode electrically contacting the first doping semiconductor layer and the second electrode electrically contacting the second doping semiconductor layer, the passivation layer covering the substrate surface of the gap region, the first doping semiconductor layer comprising a first sub-hole with the texture structure exposed from the bottom of the first sub-hole, and / or the second doping semiconductor layer comprising a second sub-hole with the texture structure exposed from the bottom of the second sub-hole.

[0019] According to some embodiments of the present application, in another embodiment of the present application, a method for manufacturing a solar cell is provided, the method for manufacturing a solar cell includes providing a substrate, the substrate having a first surface and a second surface that are placed opposite each other; forming a doping semiconductor layer, the doping semiconductor layer being a doping semiconductor layer located on the substrate; performing a texture forming process on the first surface such that the first surface has a pyramidal structure, the doping semiconductor layer having first holes penetrating the doping semiconductor layer; forming a texture structure on the second surface, the first holes corresponding one-to-one with the texture structure, and the texture structure being exposed from the bottom of the first holes; forming a passivation layer, the passivation layer covering the surface of the doping semiconductor layer, the passivation layer filling the first holes and covering the texture structure; and forming a plurality of electrodes arranged along a first direction, the electrodes penetrating the thickness of the passivation and electrically contacting the doping semiconductor layer.

[0020] In some embodiments, the second surface comprises alternating P regions and N regions, with a gap region between the P regions and the N regions, and further, before forming the doping semiconductor layer, a doping conductive film is formed, the doping conductive film covering the P regions, the N regions and the gap region, and the substrate of the gap region is etched to remove the doping conductive film located in the gap region.

[0021] According to some embodiments of the present application, in another embodiment of the present application, a stacked cell is further provided, which includes a bottom cell and a top cell, wherein the bottom cell is a solar cell as described in any of the above embodiments or a solar cell manufactured by the manufacturing method described in the above embodiments, and the top cell is located on the side of the bottom cell away from the electrodes of the substrate.

[0022] According to some embodiments of the present invention, in another embodiment of the present invention, a photovoltaic module is further provided, which includes a cell string comprising a plurality of solar cells described in any of the above embodiments, solar cells manufactured by the manufacturing method described in any of the above embodiments, or stacked cells described in the above embodiments, a sealing adhesive film for covering the surface of the cell string, and a cover plate for covering the surface of the sealing adhesive film away from the cell string. [Effects of the Invention]

[0023] The technical solution provided in the embodiment of this application has at least the following advantages.

[0024] In the solar cell provided in this embodiment, the surface of the substrate has a texture structure, and there is a first hole in the doped semiconductor layer. The first hole corresponds one-to-one with the texture structure, and the texture structure is exposed from the bottom of the first hole. The texture structure can enhance the internal reflection of the substrate and reduce the optical loss of the solar cell. The first hole, as an optical trapping structure, can enhance the internal reflection of incident light in the doped semiconductor layer and improve the battery efficiency. The passivation layer is filled in the first hole, and the passivation layer can achieve secondary passivation for the substrate. By realizing passivation for the substrate by the passivation layer and the doped semiconductor layer simultaneously, the surface defects of the substrate can be reduced and the photoelectric conversion efficiency of the solar cell can be improved.

[0025] Also, the doped semiconductor layer has a first hole. The first hole corresponds one-to-one with the texture structure, and the passivation layer is filled in the first hole. The combination of the doped semiconductor layer, the passivation layer, the texture structure, and the first hole can ensure the passivation performance of the solar cell, and by providing several optical trapping structures on the surface of the substrate, the internal reflectivity can be enhanced, the short-circuit current and the open-circuit voltage can be improved, and thus the battery efficiency can be improved.

Brief Description of the Drawings

[0026] One or more embodiments are exemplarily illustrated in the figures in the corresponding attached drawings. However, these exemplary descriptions do not limit the embodiments. Unless otherwise specified, the figures in the attached drawings are not limited by scale. To more clearly explain the technical solutions in the embodiments of the present application or the prior art, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative labor. [[ID=​​​​​​ [Figure 3] Figure 3 is a diagram showing a cross-sectional structure along A1 - A2 of Figure 2. [Figure 4] Figure 4 is a diagram showing the structure of a doped semiconductor layer of a solar cell provided in one embodiment of the present application. [Figure 5] Figure 5 is a diagram showing multiple structures of the first hole of a solar cell provided in one embodiment of the present application. [Figure 6] Figure 6 is a diagram showing one surface structure of a doped semiconductor layer of a solar cell provided in one embodiment of the present application. [Figure 7] Figure 7 is a diagram showing the structure of the first hole of a solar cell provided in one embodiment of the present application. [Figure 8] Figure 8 is a diagram showing the configuration of a protrusion structure of a solar cell provided in one embodiment of the present application. [Figure 9] Figure 9 is a diagram showing the structure of a substrate of a solar cell provided in one embodiment of the present application. [Figure 10] Figure 10 is a diagram showing another cross-sectional structure of a solar cell provided in one embodiment of the present application. [Figure 11] Figure 11 is a diagram showing the structure of a solar cell provided in one embodiment of the present application. [Figure 12] Figure 12 is an enlarged view of part D of Figure 11. [Figure 13] Figure 13 is a diagram showing a cross-sectional structure along B1 - B2 of Figure 12. [Figure 14] Figure 14 is a diagram showing the structure of a solar cell corresponding to the steps in the manufacturing method of a solar cell provided in one embodiment of the present application. [Figure 15] Figure 15 is a diagram showing the structure of a solar cell corresponding to the steps in the manufacturing method of a solar cell provided in one embodiment of the present application. [Figure 16] Figure 16 is a diagram showing the structure of a solar cell corresponding to the steps in the manufacturing method of a solar cell provided in one embodiment of the present application. [Figure 17] Figure 17 is a diagram showing the structure of a solar cell corresponding to the steps in the manufacturing method of a solar cell provided in one embodiment of the present application. [Figure 18] Figure 18 shows the structure of a solar cell corresponding to a step in a method for manufacturing a solar cell provided in one embodiment of the present invention. [Figure 19] Figure 19 shows the structure of a solar cell corresponding to the steps in a method for manufacturing a solar cell provided in one embodiment of the present invention. [Figure 20] Figure 20 shows the structure of a solar cell corresponding to a step in a method for manufacturing a solar cell provided in one embodiment of the present invention. [Figure 21] Figure 21 shows the structure of a stacked battery provided in one embodiment of the present invention. [Figure 22] Figure 22 shows the structure of a photovoltaic module provided in one embodiment of the present invention. [Figure 23] Figure 23 shows the cross-sectional structure along M1-M2 in Figure 22. [Modes for carrying out the invention]

[0027] As can be seen from the background technology, the photoelectric conversion efficiency of current solar cells is not good.

[0028] In the solar cell provided in this embodiment, the surface of the substrate has a textured structure, and there are first holes in the doping semiconductor layer, with the first holes corresponding one-to-one with the textured structure, and the textured structure is exposed from the bottom of the first holes. The textured structure can increase the internal reflection of the substrate and reduce the light loss of the solar cell. The first holes, acting as a light trapping structure, can enhance the internal reflection of incident light within the doping semiconductor layer and improve the battery efficiency. A passivation layer is filled into the first holes, and the passivation layer can achieve secondary passivation with respect to the substrate. By simultaneously achieving passivation with respect to the substrate by the passivation layer and the doping semiconductor layer, surface defects of the substrate can be reduced and the photoelectric conversion efficiency of the solar cell can be improved.

[0029] Furthermore, the doping semiconductor layer is provided with a first hole, which corresponds one-to-one with the texture structure, and the passivation layer fills the first hole. The combination of the doping semiconductor layer, passivation, texture structure, and first hole ensures the passivation performance of the solar cell, and by providing several light-trapping structures on the surface of the substrate, the internal reflectivity is increased, improving the short-circuit current and open-circuit voltage, and ultimately increasing the battery efficiency.

[0030] The embodiments of this application will be described in detail below, accompanied by the drawings. However, although numerous technical details are proposed in the embodiments of this application, as will be understood by those skilled in the art, in order to help the reader better understand this application, the technical concepts for which the embodiments of this application seek protection can be realized without these technical details or the various changes and modifications based on the embodiments below.

[0031] Figure 1 shows the structure of a solar cell provided in one embodiment of the present invention. Figure 2 is an enlarged view of portion C in Figure 1. Figure 3 shows the cross-sectional structure along A1-A2 in Figure 2. Figure 4 shows the structure of the doped semiconductor layer of the solar cell provided in one embodiment of the present invention. Figure 5 shows multiple types of structures of the first hole of the solar cell provided in one embodiment of the present invention. Figure 6 shows one surface structure of the doped semiconductor layer of the solar cell provided in one embodiment of the present invention. Figure 7 shows the structure of the first hole of the solar cell provided in one embodiment of the present invention. Figure 8 shows the configuration of the protrusion structure of the solar cell provided in one embodiment of the present invention. Figure 9 shows the structure of the substrate of the solar cell provided in one embodiment of the present invention.

[0032] According to some embodiments of the present invention, as shown in Figures 1 to 3, in one aspect of this embodiment, a solar cell is provided, which includes a substrate 100, a doping semiconductor layer 112 located on the substrate 100, a passivation layer 113 covering the surface of the doping semiconductor layer 112, and a plurality of electrodes 114 arranged along a first direction X, wherein a portion of the surface of the substrate 100 has a textured structure 14 (see Figure 7), the doping semiconductor layer 112 has first holes 1120 penetrating the doping semiconductor layer 112, the first holes 1120 correspond one-to-one with the textured structure 14, the textured structure 14 is exposed from the bottom of the first holes 1120, the passivation layer 113 fills the first holes 1120 and covers the textured structure 14, and the electrodes 114 penetrate the passivation layer 113 and are in electrical contact with the doping semiconductor layer 112.

[0033] In some embodiments, the material of the substrate 100 may be an elemental semiconductor material. Specifically, the elemental semiconductor material consists of a single element and may be, for example, silicon or germanium. Here, the elemental semiconductor material may be in a single-crystal state, a polycrystalline state, an amorphous state or a microcrystalline state (a state having both a single-crystal state and an amorphous state is called a microcrystalline state), and for example, silicon may be at least one of single-crystal silicon, polycrystalline silicon, amorphous silicon or microcrystalline silicon.

[0034] In some embodiments, the material of the substrate 100 may be a compound semiconductor material. Common compound semiconductor materials include, but are not limited to, materials such as silicon germanium, silicon carbide, gallium arsenide, indium gallium, perovskite, cadmium telluride, and copper indium selenide. The substrate 100 may be a sapphire substrate, a silicon substrate on an insulator, or a germanium substrate on an insulator.

[0035] In some embodiments, the substrate 100 may be an N-type semiconductor substrate or a P-type semiconductor substrate. The N-type semiconductor substrate is doped with an N-type doping element, which may be any of the Group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). The P-type semiconductor substrate is doped with a P-type doping element, which may be any of the Group III elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0036] In some embodiments, the substrate 100 comprises a first surface 11 and a second surface 12 that are positioned opposite each other, with the first surface 11 being the front surface and the second surface 12 being the back surface, or the first surface being the back surface and the second surface being the front surface. The solar cell is a single-sided cell, with the front surface used as a light-receiving surface to receive incident light and the back surface being the backlight surface. In some embodiments, the solar cell is a double-sided cell, meaning that both the first and second surfaces of the substrate can be used as light-receiving surfaces to receive incident light. Here, the backlight surface can also receive incident light, but its efficiency in receiving incident light is weaker than that of the light-receiving surface.

[0037] In the solar cells shown in Figure 3, and in Figures 10 and 13 described below, the first surface of the substrate is the front surface, and the second surface of the substrate is the back surface. In the solar cells shown in Figure 3, and in Figures 10 and 13 described below, improvements have been made to the back surface of the solar cell, with the doping semiconductor layer 112 located on the back surface of the substrate, thereby improving the passivation performance of the back surface of the solar cell. In the solar cells shown in Figure 3, and in Figures 10 and 13 described below, the side of the substrate facing upwards is the light-receiving surface, and the side of the substrate facing downwards is the backlight surface.

[0038] In some embodiments, the doping semiconductor layer 112 may be located on the first surface. The doping semiconductor layer 112 may be located on the front surface, and this embodiment does not limit the doping semiconductor layer 112 to being located on the first surface or the second surface; it is sufficient that the doping semiconductor layer 112 is located on the surface of the substrate. Take the solar cell shown in Figure 3, and Figures 10 and 13 described below as an example.

[0039] In some embodiments, the solar cell further includes a dielectric layer 111 located between the substrate 100 and the doped semiconductor layer 112, the dielectric layer 111 having a second hole 1110 corresponding to a first hole 1120, and the surface of the substrate 100 being exposed from the bottom of the second hole 1110.

[0040] The dielectric layer 111 is generally made thin to ensure carrier tunneling functionality, allowing carriers to tunnel through the dielectric layer 111 into the doping semiconductor layer 112. Because the thickness of the dielectric layer 111 is less than 15 nm, a second hole 1110 is formed within the dielectric layer 111 in the process of forming the first hole 1120, as there is a possibility of removing the dielectric layer 111 exposed from the first hole 1120. In some embodiments, there is no second hole within the dielectric layer in order to avoid causing overall etching damage to the dielectric layer during the process of forming the first hole. This also falls within the scope of protection of the embodiments of this application.

[0041] In some embodiments, a passivation contact structure is formed between the dielectric layer 111 and the doping semiconductor layer 112, allowing the doping semiconductor layer 112 to form band bending on the surface of the substrate 100, and the dielectric layer 111 to create an asymmetric offset in the band on the surface of the substrate 100, resulting in a lower potential barrier for the majority carriers than for the minority carriers. This allows the majority carriers to easily pass through the dielectric layer 111 and perform quantum tunneling, while the minority carriers have difficulty passing through the dielectric layer 111, thus enabling selective carrier transport.

[0042] Furthermore, the dielectric layer 111 exhibits a chemical passivation effect. Specifically, because interface state defects exist at the interface between the substrate 100 and the dielectric layer 111, the interface state density on the front surface of the substrate 100 increases. This increase in interface state density promotes the recombination of photogenerated carriers, increasing the backing factor, short-circuit current, and open-circuit voltage of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell. By positioning the dielectric layer 111 on the second surface 12 of the substrate 100, the dielectric layer 111 can exert a chemical passivation effect on the surface of the substrate 100. Specifically, by saturating the dangling bonds of the substrate 100, the defect state density of the substrate 100 is reduced, decreasing the recombination centers of the substrate 100 and reducing the carrier recombination rate.

[0043] In some embodiments, the thickness of the dielectric layer 111 is 0.5 nm to 5 nm. The thickness range of the dielectric layer 111 is 0.5 nm to 1.3 nm, 1.3 nm to 2.6 nm, 2.6 nm to 4.1 nm, or 4.1 nm to 5 nm. When the dielectric layer 111 is within any of the above ranges, the thinness of the dielectric layer 111 allows majority carriers to easily quantum tunnel through the dielectric layer 111, while minority carriers have difficulty passing through the dielectric layer 111, thereby enabling selective carrier transport.

[0044] In some embodiments, the doped semiconductor layer 112 exhibits a field passivation effect. Specifically, it forms an electrostatic field directed inward towards the substrate 100 on the surface of the substrate 100, causing minority carriers to escape from the interface, reducing the concentration of minority carriers, lowering the carrier recombination rate at the substrate 100 interface, increasing the open-circuit voltage, short-circuit current, and backing factor of the solar cell, and thereby improving the photoelectric conversion efficiency of the solar cell.

[0045] The doping semiconductor layer 112 may be doped with the same type of doping element as the substrate 100. For example, if the doping element of the substrate 100 is N-type, then the doping semiconductor layer 112 may be doped with an N-type doping element.

[0046] In some embodiments, the doped semiconductor layer 112 includes at least one of an amorphous silicon doped layer, a polycrystalline silicon doped layer, a microcrystalline silicon doped layer, a silicon carbide doped layer, or a crystalline silicon doped layer.

[0047] As shown in Figures 4 and 5, in some embodiments, the range of the one-dimensional dimension d of the first hole 1120 is 5 μm to 20 μm. The range of the one-dimensional dimension d of the first hole 1120 may also be 5 μm to 8 μm, 8 μm to 13 μm, 13 μm to 15.2 μm, 15.2 μm to 17 μm, or 17 μm to 20 μm. If the range of the one-dimensional dimension d of the first hole 1120 is within any of the above ranges, the hole of the first hole 1120 is appropriate, thereby minimizing the impact of the first hole 1120 on the strength of the doping semiconductor layer 112 itself and effectively avoiding delamination between the doping semiconductor layer 112 and the substrate 100. If the one-dimensional dimension d of the first hole 1120 is within any of the above ranges, the first hole 1120 can be filled with the passivation layer 113 without forming a cavity, thereby increasing the battery efficiency of the solar cell.

[0048] In some embodiments, the number and dimension d of the first holes 1120 may be used to provide space for thermal deformation of the doping semiconductor layer 112 and the passivation layer 113, provided that the one-dimensional dimension d of the first holes 1120 is within the above-mentioned range, thereby reducing the probability of curl bending occurring in the solar cell.

[0049] In some embodiments, Figure 5 is a diagram showing several types of structures of the first hole of a solar cell provided in one embodiment of the present application, and as shown in Figure 5, the shape of the first hole 1120 may be circular, rectangular, elliptical, or triangular as shown in the figure.

[0050] In some embodiments, the one-dimensional dimension d of the first hole 1120 may be the diameter of a circle, the length of the sides of a rectangle or triangle, or the longer side of an ellipse, and furthermore, the one-dimensional dimension d may be the line connecting the two corners.

[0051] In some embodiments, an N-type doping element is doped into the doped semiconductor layer 112, and the one-dimensional dimension d of the first hole 1120 is 30 μm or less. The one-dimensional dimension d of the first hole 1120 is 28 μm or less, the one-dimensional dimension d of the first hole 1120 is 23 μm or less, or the one-dimensional dimension d of the first hole 1120 is 20 μm or less.

[0052] In some embodiments, the doped semiconductor layer 112 is doped with an N-type doping element, the crystal grains of the doped semiconductor layer 112 are unified by the N-type doping element, and it has a single crystal structure. Furthermore, the doped semiconductor layer 112 containing the N-type doping element has a small grain size, a large and uniform number of grain boundaries, and a large one-dimensional dimension d of the formed first hole 1120.

[0053] In some embodiments, a P-type doping element is doped into the doping semiconductor layer 112, and the one-dimensional dimension d of the first hole 1120 is 10 μm or less. The one-dimensional dimension d of the first hole 1120 is 8 μm or less, the one-dimensional dimension d of the first hole 1120 is 5.8 μm or less, or the one-dimensional dimension d of the first hole 1120 is 4.3 μm or less. If the one-dimensional dimension d of the first hole 1120 is within any of the above ranges, the small diameter of the first hole 1120 has little effect on the strength of the doping semiconductor layer 112 itself and does not cause delamination between the doping semiconductor layer 112 and the substrate 100. If the one-dimensional dimension d of the first hole 1120 is within any of the above ranges, the first hole 1120 does not form a cavity and is filled with a passivation layer 113, which can improve the battery efficiency of the solar cell.

[0054] In some embodiments, a P-type doping element is doped into the doped semiconductor layer 112, and there is good compatibility between the P-type doping element and the dielectric layer 111. For example, when the P-type doping element is B, B can form BO bonds and B-Si bonds with silicon and oxygen, resulting in good contact performance between the doped semiconductor layer 112 and the dielectric layer 111, and between the doped semiconductor layer 112 and the dielectric layer, a small edge region, and a small one-dimensional dimension d of the formed first hole 1120.

[0055] As shown in Figures 6 and 9, the second surface also includes a tower foundation structure, which comprises multiple tower foundations 124, some of which are in contact with adjacent tower foundations 124. The tower foundation structure refers to a polished form of the pyramidal structure that does not include the top, and the height of the tower foundation structure is less than 1 / 3 of the height of the original pyramidal structure.

[0056] As shown in Figures 3 and 7, the texture structure 14 and the first holes 1120 constitute a light trapping structure, and the texture structure 14 can enhance the internal reflection of sunlight and improve the light absorption rate of the doping semiconductor layer and the substrate. The texture structure 14 includes at least one protrusion structure 123, and the number of protrusion structures 123 corresponding to one first hole 1120 is between 1 and 5. This increases the internal reflection of incident light and improves the photoelectric conversion efficiency. If the number of protrusion structures 123 in the first holes 1120 is within the above range, the dimensions of the protrusion structures 123 are relatively large, the surface defects of the substrate 100 are small, the recombination centers of the substrate 100 are small, and the passivation layer 113 can form good passivation with respect to the substrate 100.

[0057] In some embodiments, the texture structure 14 may include a pyramidal structure, a prismatic structure, or a protruding structure. The pyramidal structure includes an inverted pyramidal structure and a pyramidal structure. Figure 7 shows an example in which the texture structure 14 includes two pyramidal structures.

[0058] In some embodiments, the electrode 114 is in contact with the projection structure 123. This increases the contact area between the projection structure 123 and the electrode 114, improving the contact performance between the electrode 114 and the projection structure 123, and thereby increasing the battery yield.

[0059] In some embodiments, as shown in Figure 8, the range of the one-dimensional dimension S of the protrusion structure 123 is 1 μm to 20 μm, and the height h1 of the protrusion structure 123 is 1 μm to 20 μm. In some embodiments, the one-dimensional dimension S of the protrusion structure 123 may be 1 μm to 5 μm, 5 μm to 8 μm, 8 μm to 13 μm, 13 μm to 15 μm, or 15 μm to 20 μm. The height h1 of the protrusion structure 123 may be 1 μm to 4 μm, 4 μm to 10 μm, 10 μm to 14 μm, 14 μm to 16 μm, or 16 μm to 20 μm.

[0060] In some embodiments, the passivation layer 113 may be a single-layer or multi-layer structure, and the material of the passivation layer 113 may be one or more of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, titanium oxide, hafnium oxide, or aluminum oxide.

[0061] In some embodiments, the solar cell further includes an anti-reflective layer located on the surface of the passivation layer, with electrodes penetrating the anti-reflective layer and the passivation layer to electrically contact a doped semiconductor layer. The anti-reflective layer is used to reduce or eliminate reflected light from the surface of the solar cell, thereby increasing the light transmittance on the surface of the solar cell and reducing or eliminating stray light in the system. The material of the anti-reflective layer includes silicon nitride and silicon oxynitride.

[0062] Figure 10 shows another cross-sectional structure of a solar cell provided in one embodiment of the present invention. The substrate has grooves, the grooves correspond one-to-one with the first holes, and the textured structure is located within the grooves.

[0063] In some embodiments, the depth h of the groove 1000 is 0.1 μm to 4 μm. The depth h of the groove 1000 may also be 0.1 μm to 0.5 μm, 0.5 μm to 2 μm, 2 μm to 2.6 μm, 2.6 μm to 3.2 μm, or 3.2 μm to 4 μm.

[0064] In some embodiments, the doped semiconductor layer 112 is doped with an N-type doping element, and the depth h of the groove 1000 is less than 3 μm. In some embodiments, the doped semiconductor layer 112 is doped with a P-type doping element, and the depth h of the groove 1000 is less than 4 μm.

[0065] In some embodiments, if the depth h of the groove 1000 is within the above arbitrary range, the breakdown of the substrate due to the groove 1000 penetrating the substrate 100 can be avoided, and the groove 1000 can enhance the internal reflection of the solar cell as a light trapping structure.

[0066] In some embodiments, as shown in Figure 4, the doped semiconductor layer 112 has a boundary 115, and the number of first holes 1120 near the boundary is greater than the number of first holes 1120 far from the boundary 115. This means that a large number of first holes 1120 near the boundary 115 means a relatively small number of first holes 1120 far from the boundary 115, which in turn reduces the number of electrodes located within the first holes 1120 and allows for a larger collection area for the electrodes 114. A large number of first holes 1120 near the boundary 115 reduces the strength of the doped semiconductor layer 112 near the boundary 115, and consequently reduces the probability of damage occurring at the edges.

[0067] In some embodiments, as shown in Figures 6 and 9, the spacing between the first holes 1120 near the boundary 115 is discontinuous. As a result, the one-dimensional dimension d of the first holes 1120 is small, and there is a doping semiconductor layer 112 between the first holes 1120 as spacing, and the edge region 122 of the substrate also has a doping semiconductor layer 112 for collecting carriers from the substrate and ultimately collecting them on the electrodes.

[0068] In some embodiments, if there are many first holes 1120 close to the boundary 115, the total doping concentration corresponding to the doping semiconductor layer 112 close to the boundary 115 decreases accordingly, and consequently the probability of leakage current occurring at the edge can be reduced.

[0069] In some embodiments, some electrodes 114 are located in the first holes 1120 and cover the textured structure 14. Since the electrodes 114 are in direct electrical contact with the substrate 100 through the first holes 1120, they can directly collect carriers generated in the substrate 100. The first holes 1120 can be extra conductive channels that can increase the current collection efficiency in the edge region 122 and offset the effects of low efficiency due to the pinhole effect of the dielectric layer 111.

[0070] As shown in Figure 3, the solar cell further includes an emitter 101 located on a first surface 11, a first passivation layer 103 covering the surface of the emitter 101, and a thin grid 104 penetrating the first passivation layer 103 and making electrical contact with the emitter 101.

[0071] In some embodiments, the emitter 101 and the substrate 100 are made of the same material, and the emitter 101 and the substrate 100 can be formed by doping the same original substrate. The type of doping element in the emitter 101 is different from the type of doping element in the substrate 100. A portion of the original substrate is doped, and the doped portion of the original substrate is used as the emitter, while the remaining original substrate is used as the substrate.

[0072] In some embodiments, the emitter 101 is a doping layer formed on the first surface of the substrate, which is a semiconductor layer doped with an N-type doping element or a P-type doping element formed by a deposition process, and the semiconductor layer may be silicon, germanium, or polycrystalline silicon.

[0073] In some embodiments, the surface of the first surface 11 comprises a first texture structure 13, the first texture structure 13 including a plurality of protrusion structures 105.

[0074] In some embodiments, the first passivation layer 103 may be a single-layer structure or a multi-layer structure, and the material of the first passivation layer 103 may be one or more of the materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, titanium oxide, hafnium oxide, or aluminum oxide.

[0075] In some embodiments, the material of the first passivation layer 103 is the same as the material of the passivation layer 113, and the first passivation layer 103 is manufactured using the same manufacturing process as the passivation layer 113.

[0076] In some embodiments, either the electrode 114 or the fine grid 104 may be sintered with a melt-type paste. The method for forming the electrode 114 includes printing a metal paste onto a portion of the surface of the passivation layer 113 using a silkscreen printing technique. The method for forming the fine grid 104 includes printing a metal paste onto a portion of the surface of the first passivation layer 103 using a silkscreen printing technique. The metal paste may contain at least one of silver, aluminum, copper, tin, gold, lead, or nickel.

[0077] In some embodiments, when the solar cell has a double-sided TOPCon cell structure, the solar cell further comprises a tunnel dielectric layer located on the first surface and a polycrystalline silicon doped layer located on the surface of the tunnel dielectric layer, wherein the type of doping element in the polycrystalline silicon doped layer differs from the type of doping element in the substrate, for example, an N-type doping element is doped in the substrate and a P-type doping element is doped in the polycrystalline silicon doped layer.

[0078] In some embodiments, the dielectric layer and the doped semiconductor layer are located on the first surface of the substrate, while the tunnel dielectric layer and the polycrystalline silicon doped layer are located on the second surface of the substrate.

[0079] In some embodiments, the dielectric layer and doping semiconductor layer are located on a first surface of the substrate and further include an intrinsic dielectric layer, an amorphous silicon doped layer, and a transparent conductive layer, wherein the intrinsic dielectric layer is located on a second surface of the substrate, the amorphous silicon doped layer is located on the surface of the intrinsic dielectric layer, the transparent conductive layer is located on the surface of the amorphous silicon doped layer, electrodes are in electrical contact with the doping semiconductor layer, and a thin grid is in electrical contact with the transparent conductive layer.

[0080] As shown in Figure 3, the first surface has a pyramidal structure 13, which includes a plurality of pyramidal structures 105, and the second surface has a textured structure 14, where the one-dimensional dimension of the protrusion structure 123 of the textured structure 14 is less than or equal to the one-dimensional dimension of the pyramidal structures 105.

[0081] In the solar cell provided in this embodiment, the surface of the substrate 100 has a textured structure 14, and the doping semiconductor layer 112 has first holes 1120, with the first holes 1120 corresponding one-to-one with the textured structure 14, and the textured structure 14 being exposed from the bottom of the first holes 1120. The textured structure 14 can increase the internal reflection of the substrate 100 and reduce the light loss of the solar cell. The first holes 1120, as a light trapping structure, can enhance the internal reflection of incident light within the doping semiconductor layer 112 and improve the battery efficiency. The first holes 1120 are filled with a passivation layer 1123, which realizes secondary passivation of the substrate 100, and the passivation layer 113 and the doping semiconductor layer 112 simultaneously passivate the substrate 100, reducing surface defects of the substrate 100 and improving the photoelectric conversion efficiency of the solar cell.

[0082] Furthermore, the doping semiconductor layer 112 is provided with a first hole 1120, which corresponds one-to-one with the texture structure 14, and the first hole 1120 is filled with a passivation layer 113. The combination of the doping semiconductor layer 112, the passivation layer 113, the texture structure 14, and the first hole 1120 ensures the passivation performance of the solar cell. At the same time, the surface of the substrate 100 is provided with several light trapping structures to increase internal reflectivity, improve short-circuit current and open-circuit voltage, and ultimately increase battery efficiency.

[0083] Furthermore, another embodiment of this embodiment provides yet another solar cell. In the above embodiment, the electrode having a first polarity and the thin grid having a second polarity are located on the first and second surfaces of the substrate, respectively, whereas in the other embodiment, both the first electrode having a first polarity and the second electrode having a second polarity are located on the second surface of the substrate. The same or corresponding technical features as those in the above embodiment will not be repeated here.

[0084] Figure 11 is a diagram showing the structure of a solar cell provided in one embodiment of the present invention, Figure 12 is an enlarged view of portion D in Figure 11, and Figure 13 is a diagram showing the cross-sectional structure along the B1-B2 section of Figure 12.

[0085] As shown in Figures 11 to 13, the solar cell includes a substrate 200, a doping semiconductor layer located on the substrate 200, a passivation layer 213 covering the surface of the doping semiconductor layer, and a plurality of electrodes arranged along a first direction X. A portion of the surface of the substrate 200 has a textured structure, the doping semiconductor layer has first holes penetrating the doping semiconductor layer, the first holes correspond one-to-one with the textured structure, the textured structure is exposed from the bottom of the first holes, the passivation layer 213 fills the first holes and covers the textured structure, and the electrodes penetrate the passivation layer 213 and are in electrical contact with the doping semiconductor layer.

[0086] In some embodiments, the substrate 200 includes opposing first surface 21 and second surface 22, the surface of the first surface 21 having a pyramidal structure 23, the pyramidal structure 23 containing a plurality of pyramidal structures 205. The first surface 21 has a front surface field (FSF) whose dopant ions have the same conductivity as the dopant ions of the substrate 200, and by utilizing the field passivation effect, the surface minority carrier concentration can be reduced, the surface recombination rate can be lowered, the series resistance can be reduced, and the electron transport capability can be increased.

[0087] In some embodiments, the second surface 22 comprises alternating P regions and N regions, with a gap between the P and N regions.

[0088] In some embodiments, as shown in Figure 13, the gap region is flush with the P region and the N region, meaning the substrate is not etched, and insulation between the P region and the N region is achieved by several isolation film layers, which may be passivation layers.

[0089] Furthermore, the statement that the above-mentioned gap is flush with the P and N regions means that the height difference between the top surface of the gap and the P and N regions is within 1 μm, and therefore it is not absolutely flush.

[0090] In some embodiments, the gap is lower than the P and N regions, and the gap comprises a trench extending from the second surface to the first surface, where the trench is used to achieve automatic isolation between regions of different conductivity types, preventing the formation of PN junctions in the highly doped P and N regions of an IBC (Interdigitated Back Contact) cell, which would cause leakage current and affect battery efficiency.

[0091] In some embodiments, the surface of the gap may be a polished surface structure, or the surface of the gap may be a second textured structure, and the roughness of the first textured structure is greater than or equal to the roughness of the second textured structure.

[0092] Here, "roughness" refers to the arithmetic mean of the absolute values ​​of the vertical deviations between peaks and valleys within a sampled length relative to the mean horizontal line, with the mean horizontal line set for that sampled length. Roughness can be measured by comparison methods, light section methods, interferometry, and probe scanning methods.

[0093] In some embodiments, the doping semiconductor layer includes a first doping semiconductor layer 244 located in the P region and a second doping semiconductor layer 254 located in the N region, and the electrodes include a first electrode 2141 and a second electrode 2142, wherein the first electrode 2141 is in electrical contact with the first doping semiconductor layer 244 and the second electrode 2142 is in electrical contact with the second doping semiconductor layer 254, and a passivation layer 213 covers the substrate surface of the gap region, the first doping semiconductor layer 244 has a first sub-hole 2121 with a textured structure exposed from the bottom of the first sub-hole 2121, and / or the second doping semiconductor layer 254 has a second sub-hole 2122 with a textured structure exposed from the bottom of the second sub-hole 2122.

[0094] In some embodiments, the one-dimensional dimension of the first sub-hole 2121 is smaller than the one-dimensional dimension of the second sub-hole 2122.

[0095] In some embodiments, the dielectric layer includes a first dielectric layer 243 and a second dielectric layer 253, wherein a first doping semiconductor layer 244 is located on the first dielectric layer 243 and a second doping semiconductor layer 254 is located on the second dielectric layer 253.

[0096] In some embodiments, there is a second hole 2110 in the first dielectric layer, and there is a second hole 2110 in the second dielectric layer.

[0097] In some embodiments, the first dielectric layer 243 and the second dielectric layer 253 may be the same as the dielectric layer 111 in the previous embodiment, that is, the first dielectric layer 243 and the second dielectric layer 253 are tunnel dielectric layers. Similarly, the first doping semiconductor layer 244 and the second doping semiconductor layer 254 may be the doping semiconductor layer 112 in the previous embodiment. The difference is that the first doping semiconductor layer 244 is doped with a P-type doping element, and the second doping semiconductor layer 254 is doped with an N-type doping element.

[0098] In some embodiments, the first electrode 2141 and the second electrode 2142 may refer to the electrode 114 in the previous embodiment, the pyramidal structure 23, pyramidal 205, and first passivation layer 203 of the first surface 21 may refer to the pyramidal structure 13, pyramidal 105, and first passivation layer 103 in the previous embodiment, and the passivation layer 213 may refer to the passivation layer 113 in the previous embodiment. These will not be repeated here.

[0099] Figures 14 to 20 show the cross-sectional structure of a solar cell corresponding to each step in the method for manufacturing a solar cell provided in one embodiment of the present invention. In this embodiment, the solar cell provided in another embodiment is used as an example.

[0100] As shown in Figure 14, the manufacturing method includes providing a substrate 200. The substrate 200 comprises a first surface and a second surface 22 that are positioned opposite each other.

[0101] In some embodiments, the second surface 22 comprises a P region and an N region, with a gap between adjacent P and N regions.

[0102] As shown in Figures 14 to 18, the manufacturing method includes forming a doped semiconductor layer. The doped semiconductor layer is a doped semiconductor layer located on a substrate.

[0103] As shown in Figures 14 to 17, the manufacturing method includes forming a doping conductive film. The doping conductive film covers the P region, the N region and the spacing region, and the substrate in the spacing region is etched to remove the doping conductive film located in the spacing region.

[0104] As shown in Figure 14, the manufacturing method includes forming a first dielectric film 225 located on the second surface 22 of the substrate, and forming a first doping semiconductor film located on the surface of the first dielectric film 225. Here, while forming the first doping semiconductor film 226, a first silicon-doped glass layer 227 is formed on the first surface of the substrate 200 and on the surface of the first doping semiconductor film 226.

[0105] In some embodiments, the first dielectric film 225 is formed by thermal oxidation or chemical growth. The first dielectric film 225 is located in the P region, the N region, and the gap region.

[0106] In some embodiments, a manufacturing method for forming the first doped semiconductor film 226 includes a first deposition, a second deposition, and a high-temperature oxidation step, wherein in the first deposition, the deposition gas contains silane, the flow rate is controlled to 100-1,000 sccm, and the deposition temperature is controlled to 400-700°C to form an intrinsic semiconductor film. In the second deposition, the deposition gas contains a doping source gas and oxygen gas, the flow rate is controlled to 100-3,000 sccm, and the deposition temperature is controlled to 700-1,000°C to form a doped semiconductor film. In the high-temperature oxidation step, the gas contains nitrogen gas and oxygen gas, and in this process, the doped semiconductor film is converted to the first doped semiconductor film 226, and a first silicon-doped glass layer 227 is formed on the first surface of the substrate 200 and on the surface of the first doped semiconductor film 226.

[0107] As shown in Figure 15, the manufacturing method includes removing the first silicon-doped glass layer 227 in the spacing region and the N region. Using the first silicon-doped glass layer 227 in the first surface and P region as a doping source, a high-temperature diffusion treatment is performed to diffuse the P-type doping elements in the first silicon-doped glass layer 227 located in the P region into the first doped semiconductor film 226 located in the P region, and to dope a portion of the substrate near the first surface with the P-type doping elements in the first silicon-doped glass layer 227 on the first surface. After the high-temperature diffusion treatment, the first silicon-doped glass layer 227 in the first surface and P region is removed.

[0108] In some embodiments, during the process of removing the first silicon-doped glass layer 227, the etching solution may etch the first doping semiconductor film 226 and the first dielectric film 225, thus potentially removing the first doping semiconductor film 226 and the first dielectric film 225.

[0109] As shown in Figure 16, the manufacturing method involves forming a second dielectric film 228 and a second doping semiconductor film 229 on the surface of the N region and the surface of the first doping semiconductor film 226, and simultaneously forming a second silicon-doped glass layer 235 on the first surface of the substrate 200 and on the surface of the second doping semiconductor film 229.

[0110] As shown in Figure 17, the manufacturing method includes removing the second silicon-doped glass layer 235 on the first surface and the second silicon-doped glass layer 235 in the P region, removing the second dielectric film 228 and the second doping semiconductor film 229 in the P region, making the first dielectric film and the first doping semiconductor film in the P region into a first dielectric layer 243 and a first doping semiconductor layer 244, respectively, and making the second dielectric film and the second doping semiconductor film in the N region into a second dielectric layer 253 and a second doping semiconductor layer 254, respectively.

[0111] As shown in Figure 18, the manufacturing method includes forming a first doped semiconductor layer 244, a second doped semiconductor layer 254, and a protective layer 282 in the gap region. The protective layer 282 may be a shielding gas, a water film, or a mask layer.

[0112] As shown in Figure 19, the manufacturing method includes performing a texture formation process on the first surface so that the first surface has a pyramidal structure. The doped semiconductor layer has first holes that penetrate the doped semiconductor layer, and a texture structure is formed on the second surface, with the first holes corresponding one-to-one with the texture structure, and the texture structure being exposed from the bottom of the first holes.

[0113] In some embodiments, the texture formation process includes chemical etching, for example, by cleaning the substrate 200 with a mixed solution of potassium hydroxide and hydrogen peroxide. Specifically, by controlling the concentration ratio of potassium hydroxide and hydrogen peroxide, a pyramidal structure conforming to a desired morphology can be formed. In some embodiments, the pyramidal structure can also be formed by methods such as laser etching, mechanical methods, or plasma etching. In laser etching, a textured structure conforming to a desired morphology can be obtained by controlling the parameters of the laser process.

[0114] In some embodiments, by controlling the etching process of the etching solution, a first sub-hole 2121 is created in a portion of the first doping semiconductor layer 244 and a second sub-hole 2122 is created in the second doping semiconductor layer 254 during the removal of the first silicon-doped glass layer 227 and the second silicon-doped glass layer 235 and the texture formation process.

[0115] In some embodiments, as shown in Figure 20, before forming the doping semiconductor film, the substrate contains impurities 281, and because the thickness of the formed doping semiconductor film is thin, the thickness of the doping semiconductor film located on the impurities 281 is thin, and during the process of texture formation on the first surface of the substrate, an unavoidable etching effect occurs on the doping semiconductor layer, forming first holes and a texture structure.

[0116] In some embodiments, the doped semiconductor layer cannot be fully and effectively protected due to limitations of the protective layer. During the process of texture formation on the substrate, the etching solution etches the substrate surface and thereby forms a textured structure.

[0117] In some examples, the process parameters for texture formation involved a mixed solution of sodium hydroxide solution, an additive, and an aqueous solution, with a reaction temperature of 50°C to 100°C and a reaction time of 200 to 1200 s. Here, the concentration of the sodium hydroxide solution was 1% to 5%, and the concentration of the additive was 0.01% to 1%.

[0118] In some embodiments, the first holes may be formed during the texture formation process, or during the removal of either the first silicon-doped glass layer 227 or the second silicon-doped glass layer 235, or they may be formed by etching during both or all of these processes.

[0119] In some embodiments, the gap regions may be formed before, after, or during the texture formation process. The gap regions may have a surface morphology similar to a pyramidal structure.

[0120] As shown in Figure 13, the manufacturing method includes forming a passivation layer 213 and forming a plurality of electrodes arranged along a first direction. Here, the passivation layer 213 covers the surface of the doped semiconductor layer, filling the first holes and covering the texture structure. The electrodes penetrate the thickness of the passivation and make electrical contact with the doped semiconductor layer.

[0121] As shown in Figure 13, the manufacturing method includes forming a passivation layer 213 that covers the surfaces of the first sub-hole 2121, the second sub-hole 2122, the gap region, the first doping semiconductor layer 244, and the second doping semiconductor layer 254.

[0122] As shown in Figure 13, the manufacturing method includes forming a first passivation layer 203 that covers the first surface 21 of the substrate 200.

[0123] In some embodiments, the passivation layer 213 and the first passivation layer 203 are formed in the same manufacturing process.

[0124] As shown in Figure 13, the manufacturing method includes forming a first electrode 2141 and a second electrode 2142. Here, the first electrode 2141 penetrates the passivation layer 213 and makes electrical contact with the first doping semiconductor layer 244, and the second electrode 2142 penetrates the passivation layer 213 and makes electrical contact with the second doping semiconductor layer 254.

[0125] In some embodiments, the manufacturing method for the first electrode 2141 and the second electrode 2142 includes printing a metal paste onto a portion of the surface of the passivation layer 213 using a screen printing process. The metal paste may contain at least one of silver, aluminum, copper, tin, gold, lead, or nickel. A sintering process is then performed on the metal paste, which contains highly corrosive components such as glass powder. During the sintering process, the corrosive components corrode the passivation layer 213, causing the metal paste to penetrate the passivation layer 213 and come into electrical contact with the first doping semiconductor layer 244 to form the first electrode 2141, and also come into electrical contact with the second doping semiconductor layer 254 to form the second electrode 2142.

[0126] Accordingly, Figure 21 shows the structure of a stacked cell provided in one embodiment of the present invention. As shown in Figure 21, this embodiment provides a stacked cell (tandem solar cell) comprising a bottom cell 350 and a top cell 360, wherein the bottom cell 350 may be a solar cell as shown in one embodiment (Figures 1 to 10), and the top cell 360 is located on the surface of the emitter in the bottom cell 350 or on the surface of the doped semiconductor layer.

[0127] In some embodiments, the stacked cell comprises a first grid line 366 of first polarity and a second grid line 367 of second polarity, with the first grid line 366 electrically in contact with the top cell 360 and the second grid line 367 electrically in contact with the bottom cell 350.

[0128] In some embodiments, there is an interface layer 361 between the top cell and the bottom cell, and the interface layer 361 fills the first hole 1120.

[0129] It should be noted that the stacked battery in this embodiment only shows a two-layer solar cell; those skilled in the art can install a three-layer or more multilayer solar cell according to actual needs.

[0130] In some embodiments, the top cell 360 may be a perovskite solar cell, which includes a stacked first transport layer 362, a perovskite substrate 363, a second transport layer 364, a transparent conductive layer 365, and an anti-reflective layer (not shown). Here, the first transport layer faces the bottom cell.

[0131] In some embodiments, the first transport layer may be either an electron transport layer or a hole transport layer, and the second transport layer may be the other of the electron transport layer or a hole transport layer.

[0132] Figure 22 is a diagram showing the structure of a photovoltaic module provided in one embodiment of the present invention, and Figure 23 is a diagram showing the cross-sectional structure along the M1-M2 section of Figure 22.

[0133] In some embodiments, as shown in Figures 22 and 23, another aspect of this embodiment further provides a photovoltaic module comprising a cell string formed by connecting a plurality of solar cells of any of the above embodiments, a sealing adhesive film for covering the surface of the cell string, and a cover plate for covering the surface of the sealing adhesive film away from the cell string.

[0134] Specifically, in some embodiments, multiple battery cells may be electrically connected by connecting members 409, and the connection members 409 and the main grid 264 in the battery cell may be welded.

[0135] In some embodiments, there is no spacing between the battery cells; that is, the battery cells overlap each other.

[0136] In some embodiments, a connector is welded to a subgrid in the battery cell, and the subgrid includes a first electrode 2141 and a second electrode 2142. In some embodiments, a connector is welded to a busbar 264 in the battery cell, and the main grid includes a first main grid and a second main grid, the first main grid welded to the first electrode 2141 and the second main grid welded to the second electrode 2142.

[0137] In some embodiments, the sealing adhesive film comprises a first sealing adhesive film and a second sealing adhesive film, wherein the first sealing adhesive film covers either the front or back surface of the solar cell, and the second sealing adhesive film covers the other front or back surface of the solar cell. Specifically, at least one of the first or second sealing adhesive film may be an organic sealing adhesive film such as a polyvinyl butyral (PVB) adhesive film, an ethylene vinyl acetate copolymer (EVA) adhesive film, a polyethylene-octene copolymer (POE) adhesive film, or a polyethylene terephthalate (PET) adhesive film.

[0138] Before lamination, there is a boundary line between the first sealing adhesive film and the second sealing adhesive film. After lamination, when the photovoltaic module is formed, the concepts of the first sealing adhesive film and the second sealing adhesive film no longer exist; rather, the first sealing adhesive film and the second sealing adhesive film are integrated to form a single sealing adhesive film 47.

[0139] In some embodiments, the cover plate 48 may be a light-transmitting cover plate, such as a glass cover plate or a plastic cover plate. Specifically, the surface of the cover plate 48 facing the sealing adhesive film 47 may be an uneven surface, which can increase the utilization rate of incident light. The cover plate 48 includes a first cover plate and a second cover plate, wherein the first cover plate faces the first sealing adhesive film and the second cover plate faces the second sealing adhesive film, or the first cover plate faces one side of the solar cell and the second cover plate faces the other side of the solar cell.

[0140] Those skilled in the art will understand that while the embodiments described above are specific examples of realizing the present application, various modifications in form and detail are possible in practical terms without departing from the scope of the present application. Since any person skilled in the art can make changes and modifications as long as they do not deviate from the spirit and scope of the present application, the scope of protection of the present application should be limited to the scope defined in the claims.

Claims

1. A substrate comprising a first surface and a second surface arranged opposite each other, wherein a portion of the second surface has a textured structure, A doping semiconductor layer located on the second surface, wherein the doping semiconductor layer comprises a first hole penetrating the doping semiconductor layer, the first hole corresponding one-to-one with the texture structure, and the texture structure is exposed from the bottom of the first hole. A passivation layer covering the surface of the doped semiconductor layer, wherein the passivation layer fills the first hole and covers the texture structure, The dielectric layer is located between the substrate and the doping semiconductor layer, The first surface has a pyramidal structure, the pyramidal structure includes a plurality of pyramidal structures, the second surface has a textured structure, and the one-dimensional dimension of the base of the protruding structure of the textured structure is less than or equal to the one-dimensional dimension of the base of the pyramidal structure. A solar cell characterized by the following features.

2. The texture structure includes at least one protruding structure, and the number of protruding structures corresponding to one of the first holes is 1 to 5. The solar cell according to feature 1.

3. The one-dimensional dimension of the bottom surface of the protrusion structure is in the range of 1 μm to 20 μm, and the height of the protrusion structure is in the range of 1 μm to 20 μm. The solar cell according to feature 2.

4. The one-dimensional dimension range of the first hole is 5 μm to 20 μm. The solar cell according to feature 1.

5. The substrate is provided with grooves, the grooves correspond one-to-one with the first holes, and the texture structure is located within the grooves. The solar cell according to feature 1.

6. The depth of the groove is 0.1 μm to 4 μm. The solar cell according to feature 5.

7. The doped semiconductor layer includes at least one of the following: an amorphous silicon doped layer, a polycrystalline silicon doped layer, a microcrystalline silicon doped layer, a silicon carbide doped layer, or a crystalline silicon doped layer. The solar cell according to feature 1.

8. The present invention further includes a plurality of electrodes arranged along a first direction, wherein the electrodes penetrate the passivation layer and are in electrical contact with the doping semiconductor layer, and some of the electrodes are located in the first hole and cover the textured structure. The solar cell according to feature 1.

9. A solar cell comprising a bottom cell and a top cell, wherein the bottom cell is a solar cell according to any one of claims 1 to 7. The top cell is located on the side of the substrate in the bottom cell that is away from the electrodes of the bottom cell. A stacked battery characterized by the following features.

10. A cell string comprising a plurality of solar cells according to any one of claims 1 to 8, A sealing adhesive film for covering the surface of the cell string, Includes a cover plate for covering the surface of the sealing adhesive film away from the cell string, A photovoltaic module characterized by the following features.

11. A cell string formed by connecting the stacked batteries described in claim 9, A sealing adhesive film for covering the surface of the cell string, Includes a cover plate for covering the surface of the sealing adhesive film away from the cell string, A photovoltaic module characterized by the following features.

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