Compact silicon qubit cell with embedded readout

Abstract

A quantum device is disclosed having an LC resonator circuit for measuring or reading out a quantum bit. The device includes a silicon layer (601), a dielectric layer (603) disposed on the silicon layer (601) and forming a functional interface with the silicon layer (601), a first metal region (614) disposed on the dielectric layer (603), and a second metal region (624) disposed on the dielectric layer (603) and laterally separated from the first metal region (614). The first metal region (614) and the second metal region (624) are arranged to electrically connect a double quantum dot forming a quantum bit having a first state and a second state to the functional interface below the first metal region (614) and the second metal region (624). The double quantum dot includes a capacitor (C1) in the LC resonator circuit, the capacitance of which depends on the state of the quantum bit. The first metal region 614 comprises an inductor L1 in the LC resonator circuit, the resonant frequency of which depends on the state of the quantum bit, thereby enabling the state of the quantum bit to be measured or estimated.

Description

[Technical Field]

[0001] This invention relates to a quantum device including an LC resonator circuit. This device is suitable for measuring or reading out qubits. [Background technology]

[0002] In the near future, intermediate-scale quantum computing, or NISQ-era quantum bit processors, may utilize 50 to 100 qubits. These qubits are typically arranged in dense arrays to minimize the required processor size.

[0003] Quantum computation using qubit processors typically involves the execution of an operation sequence on the qubits, followed by the readout of each qubit's state. This readout can be performed by coupling a charge sensor to an LC resonator or by embedding the qubit within an LC resonator circuit. However, the circuitry required to read out the qubit's state occupies a significantly larger area compared to the area required for the qubit itself. While the size of each qubit depends on the properties of the material used, the area it occupies is typically around 100 × 100 nm. 2 From 1 × 1 μm 2 It can be up to [a certain range]. In contrast, the area occupied by the LC resonator is typically at least 100 × 100 μm. 2 This is several orders of magnitude larger than the area occupied by a qubit. [Overview of the project] [Problems that the invention aims to solve]

[0004] The relatively large area occupied by the LC resonator circuit significantly limits the scalability of this technology. Reducing the size of the readout circuit is desirable. [Means for solving the problem]

[0005] One aspect of the present invention provides a quantum device having an LC resonator circuit for measuring or reading out a qubit. The device comprises a semiconductor layer, a dielectric layer disposed on the semiconductor layer and forming a functional interface with the semiconductor layer, a first metallic region disposed on the dielectric layer, and a second metallic region disposed on the dielectric layer and laterally separated from the first metallic region. The first and second metallic regions are arranged to be electrically connected so as to enable the induction of a double quantum dot, which forms a qubit having a first state and a second state, to the functional interface beneath the first and second metallic regions. The double quantum dot comprises a capacitor in the LC resonator circuit, the capacitance of which depends on the state of the qubit. The first metallic region comprises an inductor in the LC resonator circuit. The resonant frequency of the LC resonator circuit depends on the state of the qubit, thereby enabling the measurement or estimation of the state of the qubit.

[0006] The first and second metal regions are arranged to be electrically connected so as to enable the induction of a double quantum dot at the functional interface beneath the first and second metal regions. This is achieved by applying a bias potential to the first and second metal regions, which modifies the potential landscape near the first and second metal regions to locally confine charge carriers. The interface between the semiconductor layer and the dielectric layer typically includes a functional portion and a non-functional portion. When a bias potential is applied to the first and / or second metal regions, the functional portion typically has a greater field effect than the field effect with respect to the non-functional portion, and as a result, it becomes possible to confine one or more charge carriers at the functional interface beneath the first and / or second metal regions. The charge carriers can be electrons or holes, depending on the polarity of the bias potential.

[0007] The first metal region is arranged to be electrically connected so as to be able to induce the first quantum dot to the functional interface under the first metal region. Similarly, the second metal region is arranged to be electrically connected so as to be able to induce the second quantum dot to the functional interface under the second metal region. The sizes of the first metal region and the second metal region affect the sizes of the first and second quantum dots, and thus their electrical properties such as their charging energy. The charging energy is inversely proportional to the size of the quantum dot, and it is possible to induce smaller quantum dots with larger charging energy using smaller metal regions.

[0008] Optionally, a bias potential can be applied to either the first metal region or the second metal region to induce a single quantum dot. However, preferably a bias potential is applied to both the first and second metal regions to induce a double quantum dot. The double quantum dot includes the first quantum dot and the second quantum dot. The spacing between the first metal region and the second metal region is made such that tunneling between the first and second quantum dots is possible.

[0009] The double quantum dot forms a qubit having a first state and a second state. For example, the first state can include electrons with an anti-parallel spin orientation, and the second state can include electrons with a parallel spin orientation. In this example, as a result of the spin dynamics of the double quantum dot, the capacitance of the first state is higher than the capacitance of the second state. When the electron spins are parallel, tunneling between the first and second quantum dots is suppressed or even zero due to spin blockade.

[0010] The state of the qubit can be read using an LC resonator circuit that includes an inductor and a capacitor. The LC resonator circuit may also be known as an LC tank circuit, an LC resonator, a tank circuit, or a resonant circuit. The LC resonator circuit has a resonant frequency ω0 that depends on the inductance L and the capacitance C and follows the formula: ω0 = 1 / √LC. At the resonant frequency, the forward power transfer is maximized. In the device described above, the double quantum dot includes a capacitor within the LC resonator circuit. The capacitance, and thus the resonant frequency, depends on the state of the qubit. Therefore, it is possible to estimate the state of the qubit.

[0011] In the quantum device described above, the first metal region functions doubly. First, the first metal region is arranged to be electrically connected so that it can induce a quantum dot to the functional interface under the first metal region. Second, the first metal region includes an inductor within the LC resonator circuit. Therefore, no additional inductor is required. Preferably, only the first metal region includes an inductor within the LC resonator circuit. Therefore, the device advantageously provides a compact qubit readout mechanism for measuring or estimating the state of the qubit.

[0012] The semiconductor layer of the device can be any suitable semiconductor such as gallium arsenide (GaAs), indium arsenide (InAs), silicon germanium (SiGe), silicon carbide (SiC), carbon, or silicon. Different carbon allotropes such as graphene or carbon nanotubes may also be used. Intrinsic silicon, isotopically pure silicon Si 28Alternatively, different forms of silicon, such as doped silicon, may be used. The semiconductor layer optionally forms a portion of a layer substrate that further includes an insulating layer beneath the semiconductor layer. The substrate may include additional layers beneath the insulating layer. In one example, the semiconductor layer is a silicon layer, which is placed on a buried oxide, and which is further placed on a silicon substrate. Alternatively, there may be no insulating layer beneath the semiconductor layer, and the semiconductor layer may form a portion of a bulk semiconductor substrate.

[0013] The dielectric layer, which is disposed on the semiconductor layer and forms a functional interface with the semiconductor layer, can be any suitable electrical insulating material such as silicon dioxide, aluminum oxide, or undoped aluminum gallium arsenide (AlGaAs), or a material with a high dielectric constant κ such as hafnium silicate, zirconium silicate, hafnium dioxide, and zirconium dioxide.

[0014] Preferably, the first metal region contains a conductor with high carrier mobility, such as a superconductor. For example, the first metal region can contain titanium nitride (TiN), niobium nitride (NbN), or titanium niobium nitride (NbTiN). These materials typically have high kinetic inductance. The inductance of the first metal region containing the inductor in the LC resonator circuit depends on the material properties and geometry of the first metal region. The inductance of the first metal region is typically between 10 and 100 nanohenries, preferably between 40 and 60 nanohenries. For example, the inductance of the first metal region can be 50 nanohenries. The inductance depends on the geometry of the first metal region. Conveniently, when the first metal region contains a material with high kinetic inductance, the inductor can be made smaller, resulting in a more compact device.

[0015] The kinetic inductance of the first metal region depends on its geometry. The kinetic inductance is inversely proportional to the thickness and length of the first metal region and proportional to the extended portion of the first metal region. Therefore, any reduction in thickness, a narrower region, or an increased extended portion will increase the kinetic inductance of the first metal region.

[0016] Preferably, the thickness of the first metal region is between 1 and 10 nanometers. A thinner first metal region has higher kinetic inductance, which conveniently results in a smaller area occupied by the first metal region, leading to the realization of a more compact device.

[0017] A superconducting material, such as a material capable of forming the first metallic region, has a critical temperature below which its electrical resistivity becomes zero, i.e., the material becomes superconducting. A superconductor can have a critical temperature lower than 70 Kelvin, preferably lower than 20 Kelvin, and more preferably lower than 10 Kelvin. This has the advantage that superconductors with lower critical temperatures typically have higher kinetic inductance. However, the critical temperature of a superconductor is not a limiting factor.

[0018] Accordingly, the first metal region comprises an inductor in the LC resonator circuit of the quantum device at extremely low temperatures, and the double quantum dot comprises a capacitor in the LC resonator circuit. Preferably, the device further comprises a power supply and a probe for measuring or estimating the state of the qubit. The power supply is typically configured to supply power at a frequency corresponding to the resonant frequency of the LC resonator circuit. The power supply may be connected to the first metal region. The probe may be connected to the first metal region and / or a second metal region and is typically configured to measure power transfer through the LC resonator circuit. Measurement of power transfer through the LC resonator circuit can be used to estimate the state of the qubit.

[0019] The measured power transfer can be, for example, the forward power transfer S 21 In this example, the power source is connected to the first metal region, and the probe is connected to the second metal region. S 21 is the S parameter or scattering parameter used to determine the relationship between the first and second ports. At the resonant frequency of the LC resonator circuit, the forward power transfer is high. The resonant frequency of the LC resonator circuit depends on the state of the qubit.

[0020] In another example, the measured power transfer can be the reflected power transfer S 11 In this example, the power source and the probe are connected to the first metal region. S 11 is a further S parameter and depends on the resonant frequency of the LC resonator circuit. At the resonant frequency of the LC resonator circuit, the reflected power transfer is low.

[0021] In a further example, the power source is connected to the first metal region and the probe is connected to the first and second metal regions. In this example, it is possible to measure both the forward power transfer S 21 and the reflected power transfer S 11 both.

[0022] The power source is optionally configured to supply power at the resonant frequency of the LC resonator circuit corresponding to the first state of the qubit. Thus, if the qubit is in the first state, the forward power transfer S 21 becomes high. If the qubit is in the second state, the forward power transfer becomes low. Instead, the power source can be configured to supply power at the resonant frequency of the LC resonator circuit corresponding to the second state of the qubit. In this example, the forward power transfer is high when the qubit is in the second state and low when the qubit is in the first state.

[0023] The power supply is optionally configured to supply power at the resonant frequency of the LC resonator circuit corresponding to the first state of the qubit, and the reflected power transfer S is used to estimate the state of the qubit. 11 The reflected power transfer is used. When the qubit is in the first state, the reflected power transfer is low. When the qubit is in the second state, the reflected power transfer is high. The spectrum of the reflected power transfer includes an inverted peak at the resonant frequency. In another example, the power supply is configured to supply power at the resonant frequency of the LC resonator circuit corresponding to the second state of the qubit, and the reflected power transfer is used to estimate the state of the qubit. The reflected power transfer is low when the qubit is in the second state and high when the qubit is in the first state.

[0024] Conveniently, the device allows for sensitive estimation of the state of the qubit based on measurements of the power transfer. Furthermore, the device provides a significantly more compact qubit readout mechanism compared to the prior art. A qubit unit cell comprising the first and second metal regions suitable for supporting the qubits of the dual qudot can be approximately 100 nanometers × 10 micrometers. This is roughly 1 / 10,000th the size of existing devices with similar functionality.

[0025] Typically, the LC resonator circuit has two resonant frequencies, the first resonant frequency corresponding to the first state of the qubit, and the second resonant frequency corresponding to the second state of the qubit. Preferably, the lower of the first and second resonant frequencies is the one at which the power supply is configured to provide power. The advantage of selecting a lower frequency is the reduction of parasitic losses.

[0026] The resonant frequency of the LC resonator circuit is determined by the inductor and capacitor in the circuit. Optionally, the first metal region comprises a first inductor in the LC resonator circuit, and the second metal region comprises a second inductor in the LC resonator circuit. Preferably, only the first and second metal regions comprise the inductors in the LC resonator circuit. This arrangement eliminates the need for an additional inductor for reading the qubits, and thus, conveniently, allows for a more compact device. Including the first and second inductors provided by the first and second metal regions provides the added flexibility of having only the first inductor provided by the first metal region, due to the fact that reading can be performed in either the first or second metal region. Furthermore, when both the first and second metal regions comprise the inductors in the LC resonator circuit, and their inductors are in series, it is possible to increase the overall inductance of the circuit. This has the advantage of allowing for further reduction of the device dimensions for a given inductance.

[0027] If the second metal region comprises a second inductor in the LC resonator circuit, the second metal region preferably has substantially the same characteristics as the first metal region. For example, the second metal region preferably encloses a highly mobile carrier conductor with high kinetic inductance, such as titanium nitride, niobium nitride, or titanium niobium nitride. The second metal region preferably has dimensions similar to those of the first metal region. This has the advantage of making it easier to manufacture such devices.

[0028] The first metal region and the second metal region are separated laterally. The lateral separation results in electrical isolation. Optionally, the dielectric layer disposed on the semiconductor layer and forming a functional interface with the semiconductor layer is the first dielectric layer, and the device further includes a second dielectric layer, the second dielectric layer disposed on at least the first metal region and the second metal region. The second dielectric layer can at least partially overlap the edges of the first metal region and the second metal region. The portion of the second dielectric layer covering the first metal region can be laterally separated from the portion of the second dielectric layer covering the second metal region. Alternatively, the portion of the second dielectric layer covering the first metal region can be connected to the portion of the second dielectric layer covering the second metal region so that a gap between the first and second metal regions is closed. The second dielectric layer can be, for example, silicon nitride (Si3N4), aluminum oxide (Al2O3), or silicon dioxide (SiO2). The use of the second dielectric layer conveniently improves the electrical isolation between the first and second metal regions and also protects the first and second metal regions from damage.

[0029] Optionally, the device further includes a masking layer covering the first metal region. The masking layer may be placed on top of the first metal region. The masking layer may optionally also cover the second metal region. The masking layer may include, for example, polysilicon, aluminum, silicon oxide, silicon nitride, or aluminum oxide. The advantage of including a masking layer is the protection of the first and second metal regions. If the masking layer is placed on both the first and second metal regions, the masking layer can protect the first and second metal regions from mechanical and electrical damage that may occur during the manufacturing process of the device and / or during the operation of the device.

[0030] The device is preferably manufactured using a complementary metal-oxide-semiconductor manufacturing process. This conveniently facilitates the manufacturing of the device.

[0031] In this embodiment of the present invention, the semiconductor layer encompasses a nanowire. The nanowire can be manufactured by selective etching of the substrate defining the nanowire. Alternatively, in some examples, the nanowire can be grown, for example, a carbon nanotube can be grown. The first and second metallic regions can be positioned on opposing sides of the nanowire such that each of the first and second metallic regions partially overlaps one edge of the nanowire, and each portion of the first and second metallic regions extends away from the nanowire. Each portion of the first and second metallic regions can extend substantially perpendicular to the nanowire. This conveniently facilitates the manufacturing process.

[0032] Alternatively, portions of the first and second metal regions can be extended in a nonlinear manner. The kinetic inductance of each metal region is proportional to its extended portion, and therefore, arranging portions of the first and second metal regions to be extended in a nonlinear manner, such as a meandering or curved winding manner, has the advantage of reducing the area occupied by the device. In another example, the extended portions of the first and second metal regions form an angle with respect to the nanowire, and the individual arrangement of the extended portions does not affect the electrical properties of the device. A dielectric layer is placed on the nanowire to provide electrical isolation between the semiconductor layer and the first and second metal regions.

[0033] Preferably, the first and second metal regions are positioned to allow induction of the first and second quantum dots at the corner of the nanowire. The dual quantum dots are enclosed beneath the first and second metal regions, respectively. This arrangement, which can be called a split-gate transistor, conveniently results in strong charge carrier confinement as a result of its geometry, where the charge carrier is confined two-dimensionally by the two sides of the nanowire forming the corner. The lengths of the extensions of the first and second metal regions are selected according to the desired inductance. This arrangement has the further advantage that it can be easily scaled up. Preferably, the extensions of the metal regions are made nonlinear or substantially perpendicular to the nanowire when the metal regions are positioned to allow support of a one-dimensional array of dual quantum dots / qubits along the nanowire. This has the advantage that adjacent metal regions can be left laterally and electrically isolated and do not reach contact at any point. Furthermore, this type of configuration is conveniently easier to design and manufacture.

[0034] To scale up the device, the device optionally further includes third and fourth metallic regions disposed on the dielectric layer. The third and fourth metallic regions correspond to the first and second metallic regions described above. The third and fourth metallic regions are positioned on opposing sides of the nanowire such that each of the third and fourth metallic regions partially overlaps one edge of the nanowire and includes portions that extend away from the nanowire (preferably in a direction perpendicular to the nanowire). The third and fourth metallic regions are preferably separated laterally from the first and second metallic regions along the longitudinal axis of the nanowire. Typically, the first and second metal regions are electrically connected to allow the first double quantum dot to be guided to the functional interface beneath the first and second metal regions, and the third and fourth metal regions are electrically connected to allow the second double quantum dot to be guided to the functional interface beneath the third and fourth metal regions.

[0035] In this way, the device can be scaled in one dimension. Additional qubit unit cells, each containing two metallic regions suitable for supporting a dual qubit dot qubit, can be positioned at intervals along the nanowire. The intervals can be regular or irregular. The scalable architecture is advantageous and aligns with research directions in quantum computing and quantum devices for qubit processing.

[0036] Optionally, the inductances of the third and fourth metal regions are greater than the inductances of the first and second metal regions, respectively. To achieve this, the third and fourth metal regions can be extended beyond the first and second regions and / or narrower. Alternatively, the third and fourth metal regions can be made thinner than the first and second regions, although achieving this in practice may be difficult. Preferably, the third and fourth metal regions extend beyond the first and second metal regions and have the same length. Optionally, the first and second metal regions extend substantially perpendicular to the nanowire in a linear manner, and the third and fourth metal regions extend nonlinearly such that they do not occupy areas beyond the extended portions of the first and second metal regions. In this way, the device can be made more compact and advantageous.

[0037] The first dual quantum dot forms a first qubit in a first qubit unit cell that encompasses the first and second metal regions and forms a first LC resonator circuit. The second dual quantum dot forms a second qubit in a second qubit unit cell that encompasses the third and fourth metal regions and forms a second resonator circuit. The effect of the difference in inductance between the first and second metal regions and the third and fourth metal regions is that the resonant frequencies of the first and second LC resonator circuits are different. This provides the advantage that the state of the first qubit and the state of the second qubit can be measured or estimated simultaneously using frequency domain multiplexing.

[0038] Typically, the device further includes a source electrode and a drain electrode. In the case of a device encompassing a one-dimensional array of qubit unit cells, the source and drain electrodes are preferably located at the first and second ends of the array, respectively. For example, the one-dimensional array may have n qubit unit cells arranged continuously from 1 to n along the longitudinal axis of a nanowire. In this case, the source electrode is preferably located in the nearest neighborhood to the first qubit unit cell, separated laterally along the longitudinal axis of the nanowire. Similarly, the drain electrode is preferably located in the nearest neighborhood to the nth qubit unit cell, separated laterally along the longitudinal axis of the nanowire. This may also apply to a device encompassing a single qubit unit cell, i.e., a device with n=1. Typically, the source and drain electrodes are arranged to be electrically connected so that a bias potential can be applied. The application of a bias potential to the source and / or drain electrodes can be used to modify the conductance of the semiconductor layer.

[0039] In another implementation of this aspect of the present invention, the semiconductor layer encompasses a nanowire, and the first and second metallic regions are separated laterally along the longitudinal axis of the nanowire. Each of the first and second metallic regions can overlap one or both edges of the nanowire. This has the advantage of being easy to manufacture.

[0040] The first and second metal regions typically extend substantially perpendicular to the nanowire. Alternatively, the first and / or second metal regions can extend at any angle without affecting the function of the device. In another example, the first and / or second metal regions can extend in a nonlinear manner, such as a crenelated manner. The extended portions of the first and second metal regions define their inductance, and their individual layouts can be selected according to design requirements without affecting the function of the device. For practical reasons, it is advantageous to make the extended portions of the first and second metal regions substantially perpendicular to each other to facilitate their arrangement without overlap.

[0041] Optionally, the main portion of the first metallic region extends to the same side of the nanowire as the main portion of the second metallic region. Alternatively, the main portions of the first and second metallic regions may extend to opposing sides of the nanowire. The device is typically designed to reduce its total area.

[0042] In this implementation, the source electrode is preferably positioned closer to the first metal region and separated laterally along the longitudinal axis of the nanowire. The drain electrode is preferably positioned closer to the second metal region and separated laterally along the longitudinal axis of the nanowire.

[0043] In a further implementation of an aspect of the present invention, the dielectric layer comprises a thin region and a thick region. The dielectric layer may comprise one or more thin regions and one or more thick regions. The thin and thick regions can be connected such that the dielectric layer forms a continuous layer with non-uniform thickness. The thickness of the dielectric layer in the thin region is typically at least half the thickness of the dielectric layer in the thick region. The thin region may have a thickness between 1 and 10 nanometers. The thick region of the dielectric layer electrically insulates the first metal region and the second metal region from the semiconductor layer. The functional interface is formed between the semiconductor layer and the thin region of the dielectric layer. Thus, when a bias potential is applied to the first metal region and / or the second metal region, it is possible to induce a confinement region beneath the thin region of the dielectric layer. This has the advantage that the device can be implemented in bulk technology.

[0044] The first metallic region is typically laid over the thin and thick regions of the dielectric layer. When a bias is applied to the first metallic region, one or more charge carriers can be confined beneath the thin region of the dielectric layer rather than the thick region, due to a reduction in the field effect beneath the thick region of the dielectric layer. The second metallic region is also typically laid over the thin and thick regions of the dielectric layer.

[0045] The device may encompass a substantially rectangular thin region of the dielectric layer surrounded by a thicker region of the dielectric layer. The rectangular thin region typically includes a first and second edge that are separated between 30 and 200 nanometers, or preferably between 30 and 150 nanometers, and can extend over several micrometers. Optionally, the first and second metallic regions are positioned on the first and second edges of the rectangular thin region, respectively, such that each of the first and second metallic regions partially overlaps one edge of the rectangular thin region and extends away from the thin region, including portions that overlap the thicker region. Typically, the first and second quantum dots can be guided to the edges of the rectangular thin region of the dielectric layer beneath the first and second metallic regions, respectively.

[0046] The layout of the extended portions of the first and second metal regions that overlay the thicker region can be linear or nonlinear. The layout is typically arranged to reduce the area occupied by the first and second metal regions. The layout is preferably arranged to facilitate the manufacturing process.

[0047] The device optionally further includes third and fourth metallic regions disposed on the dielectric layer. The third and fourth metallic regions can be positioned on the first and second edges of the rectangular thin region, respectively, such that each of the third and fourth metallic regions partially overlaps one edge of the rectangular thin region and includes a portion that extends away from the thin region. Each of the portions overlaps the thick region. The third and fourth metallic regions are preferably separated laterally from the first and second metallic regions along the longitudinal axis of the rectangular thin region.

[0048] The first and second metal regions are arranged to be electrically connected so as to enable the induction of the first double quantum dot to the functional interface beneath the first and second metal regions. The third and fourth metal regions are arranged to be electrically connected so as to enable the induction of the second double quantum dot to the functional interface beneath the third and fourth metal regions. The functional interface is typically formed between the thin region of the semiconductor layer and the dielectric layer. Optionally, the inductances of the third and fourth metal regions are greater than the inductances of the first and second metal regions, respectively.

[0049] In another example, the first and second metallic regions are separated laterally along the longitudinal axis of the rectangular thin region of the dielectric layer. Typically, the first and second quantum dots can be induced beneath the first and second metallic regions at the interface between the thin dielectric layer and the semiconductor layer, and this interface is called a functional interface. In this example, the first and second quantum dots can be formed at the substantial center of the rectangular thin region of the dielectric layer.

[0050] Another aspect of the present invention provides a method for measuring or reading out a qubit using the quantum device described above. The method comprises the steps of: inducing a dual quantum dot by applying first and second bias potentials to the first and second metal regions, respectively; forming a qubit having a first state and a second state at the functional interface beneath the first and second metal regions; applying a signal with a selected frequency to the first metal region; applying a bias difference between the first and second metal regions; and measuring power transfer in the first or second metal region, the measurement being used to measure or estimate the state of the qubit.

[0051] In this method, the first and second metal regions are used for both inducting the dual quantum dot and measuring or estimating the state of the qubit. Preferably, the first metal region is the sole inductor in the LC resonator circuit used for measuring or reading out the qubit. As a result of this dual function, it is conveniently possible to reduce the area occupied by the device. In some implementations, the second metal region comprises an additional inductor in the LC resonator circuit.

[0052] The first and second bias potentials can be made identical, for example, and applied using a single power supply. However, the first and second metal regions are electrically isolated regions.

[0053] The dual quantum dot forms a qubit having a first state and a second state. The qubit has a capacitance that depends on the state of the qubit. The qubit forms a capacitor in an LC resonator circuit, and the first metal region comprises an inductor in the LC resonator circuit. The resonant frequency of the LC resonator circuit depends on the state of the qubit. At the resonant frequency of the LC resonator circuit, the forward power transfer is maximized and the reflected power transfer is minimized.

[0054] Preferably, the selected frequency applied to the first metal region corresponds to the resonant frequency of the LC resonator circuit. Typically, the selected frequency is the resonant frequency of the LC resonator circuit when the capacitance of the double quantum dot is at its maximum. This can, for example, correspond to the first state of the qubit. A larger capacitance results in a lower resonant frequency. Applying a signal with a lower frequency usually has the advantage of resulting in lower parasitic losses.

[0055] The power transfer measured is forward power transfer S.21 or reflected power transfer S 11 This can be done. Preferably, if the power transfer being measured is the forward power transfer, the method includes measuring the forward power transfer in the second metal region. Preferably, if the power transfer being measured is the reflected power transfer, the method includes measuring the reflected power transfer in the first metal region. In one example, the frequency of the signal corresponds to the resonant frequency of the LC resonator circuit when the qubit is in the first state. In this example, the forward power transfer S when the qubit is in the first state 21 The reflected power transmission S increases, 11 The forward power transfer becomes lower. Conversely, when the qubit is in the second state, the forward power transfer becomes lower and the reflected power transfer becomes higher. In this way, the measurement of the power transfer in the first or second metallic region can be used to measure or estimate the state of the qubit.

[0056] The method described herein involves measuring one qubit. If the device includes additional qubits, the method may further involve a multiplexing method for reading the states of multiple qubits. In a device with multiple qubits, the method may include applying first and second bias potentials to the first and second metal regions, respectively, to induce a first double qubit, thereby forming a first qubit, and applying third and fourth bias potentials to the third and fourth metal regions, respectively, to induce a second double qubit, thereby forming a second qubit.

[0057] Optionally, the method includes time-domain multiplexing. The method may include applying a signal with a first selected frequency to the first metal region at a first time t0. The method may include applying a signal with a second selected frequency to the third metal region at a second time t1, i.e., t1 > t0, which is later than the first time. The second selected frequency may be the same as the first selected frequency. Measurements of the power transfer in each of the second and fourth metal regions are performed sequentially to estimate the states of the first and second qubits. The advantage of time-domain multiplexing is the scalability of both the device and the technique.

[0058] Optionally, as an alternative to or in combination with time-domain multiplexing, the method may include frequency-domain multiplexing. To perform frequency-domain multiplexing, the inductances of the first and / or second metal regions are different from those of the third and / or fourth metal regions. As a result, the resonant frequencies of each of the LC resonator circuits are different, and it becomes possible to simultaneously measure or estimate the states of the first and second qubits using measurements of the power transfer over a range of frequencies. The advantage of performing frequency-domain multiplexing is the increased processing speed resulting from the simultaneous readout of multiple qubits.

[0059] Preferably, the method is carried out at a temperature lower than 20 Kelvin, more preferably at a temperature lower than 10 Kelvin. Conveniently, at extremely low temperatures, the effect of thermal excitation on the occupation of the double quantum dots is reduced. Furthermore, the first metallic region has a critical temperature T c It can include superconductors that become superconducting below a certain temperature. The critical temperature depends on the material, but is usually low. Therefore, when the temperature of the first metal region is extremely low, the first metal region is usually superconducting. Conveniently, the first metal region is suitable for use as an inductor at extremely low temperatures.

[0060] Further aspects of the present invention provide a method for assembling the quantum device described above. The method comprises the steps of: arranging a dielectric layer on a semiconductor layer to form a functional interface; arranging a first metallic region on the dielectric layer; and arranging a second metallic region on the dielectric layer, laterally separated from the first metallic region. The first and second metallic regions are configured to be electrically connected so as to enable the induction of a double quantum dot, which forms a qubit having a first state and a second state, onto the functional interface beneath the first and second metallic regions. The double quantum dot comprises a capacitor in the LC resonator circuit, the capacitance of which depends on the state of the qubit. The first metallic region comprises an inductor in the LC resonator circuit. The resonant frequency of the LC resonator circuit depends on the state of the qubit, thereby making it possible to measure or estimate the state of the qubit.

[0061] Preferably, the first metal region comprises the only inductor in the LC resonator circuit. This method of assembling the quantum device conveniently results in a compact device suitable for reading out qubits.

[0062] Optionally, the arrangement of the first metal region is carried out in a different processing step than the arrangement of the second metal region. In this method, the first metal region and the second metal region can be formed from different materials such as titanium nitride and polysilicon, respectively.

[0063] Instead, the first and second metal regions are placed on the dielectric layer in the same processing step. This has the advantage of simplifying the manufacturing process. In this case, the first and second metal regions are typically made from the same material, such as niobium nitride or other material with high kinetic inductance.

[0064] The method may further include the placement of a masking layer on the first metal region. Optionally, the method may also include the placement of a masking layer on the second metal region. When the first and second metal regions are covered with masking layers, they are conveniently protected from damage. Potential damage may be caused by additional processing steps.

[0065] For example, the device typically includes source and drain electrodes. The method for assembling the device optionally includes performing a self-alignment injection process to define the ohmic contact of the source and drain. During this process, the first and second metal layers may be damaged unless they are covered.

[0066] Aspects of the present invention conveniently provide a compact device layout in which the qubit readout mechanism is embedded within the metal region of the device. The first metal region offers a dual function, as it can be used for inducting the quantum dot and as an inductor in the LC resonator circuit used to estimate the state of the qubit, which conveniently results in a reduction of up to four orders of magnitude in the size of the circuitry required for qubit support and readout compared to existing devices. The area occupied by the circuitry for qubit support and readout can be approximately 100 nanometers × 10⁻⁶ micrometers. Furthermore, aspects of the present invention are suitable for integration into scalable device architectures suitable for processing multiple qubits.

[0067] Embodiments of the present invention will be described below with reference to the following attached drawings. [Brief explanation of the drawing]

[0068] [Figure 1A] This is a cross-sectional view of a conventional quantum device. [Figure 1B] This is a cross-sectional view of a conventional quantum device. [Figure 2A] This is a cross-sectional view of a quantum device. [Figure 2B] This is a cross-sectional view of a quantum device. [Figure 3A] This is a cross-sectional view of a quantum device. [Figure 3B] This is a cross-sectional view of a quantum device. [Figure 4A] A plan view of a quantum device. [Figure 4B] A plan view of a quantum device. [Figure 5] This is a flowchart illustrating how to assemble a quantum device. [Figure 6] This is a cross-sectional view of a quantum device. [Figure 7] This is a cross-sectional view of a quantum device. [Figure 8] This is a flowchart illustrating a method for measuring or reading out qubits. [Figure 9] This is a circuit diagram illustrating a quantum device. [Figure 10A] This is a graph illustrating power transfer as a function of frequency with respect to the first capacitance. [Figure 10B] This is a graph illustrating power transfer as a function of frequency with respect to the second capacitance. [Figure 11A] A plan view of a quantum device. [Figure 11B] A plan view of a quantum device. [Modes for carrying out the invention]

[0069] Figures 1A and 1B schematically illustrate cross-sectional views of a conventional quantum device. The device shown in Figure 1A is an exemplary nanowire transistor. This nanowire transistor contains a silicon nanowire 1 placed on a silicon dioxide layer 2. The silicon dioxide layer 2 forms a substrate portion that further contains a silicon layer (not shown). A dielectric layer 3 containing silicon dioxide covers the silicon nanowire 1. The dielectric layer 3 is covered by a titanium nitride layer 4. The titanium nitride layer 4 is approximately 5 nanometers thick. A polysilicon layer 5 covers the titanium nitride layer 4. The polysilicon layer 5 is conductive and extends from the silicon nanowire 1 to the gate electrode 6. The gate electrode 6 is connected to a power supply (not shown) which can be used to apply a bias potential to the conductive polysilicon layer 5. In this method, one or more charge carriers can be confined within the silicon nanowire 1 to form a quantum dot.

[0070] The device shown in Figure 1B is an exemplary planar transistor. This planar transistor comprises a silicon layer 7 and a silicon dioxide layer 8 that partially covers the silicon layer 7. The device also comprises a dielectric layer 3 deposited on top of the silicon layer 7 within a gap in the silicon dioxide layer 8. In this example, the dielectric layer 3 is silicon dioxide. In another example of prior art, a silicon dioxide layer is deposited on top of a silicon layer, and the silicon dioxide layer has a variable thickness. The device shown in Figure 1B, similar to that shown in Figure 1A, further includes a titanium nitride layer 4 and a polysilicon layer 5 connected to a gate electrode 6. The titanium nitride layer 4 covers the dielectric layer 3, and the polysilicon layer 5 covers the titanium layer 4. The polysilicon layer 5 extends away from the dielectric layer 3 toward the gate electrode 6. Using this device, when a bias potential is applied to the conductive polysilicon layer 5, it is possible to confine one or more charge carriers beneath the dielectric layer 3 (or beneath a thin region of the variable-thickness silicon dioxide layer). The one or more charge carriers may be confined within a quantum dot.

[0071] In Figures 1A and 1B, the titanium nitride layer 4 can be used for threshold voltage engineering. Threshold voltage engineering is a technique used to offset the threshold voltage so that the operating value of a qubit can be set to an appropriate value. In examples of alternative conventional techniques, the thickness of the titanium nitride layer can vary, but is typically between 1 and 10 nanometers. Titanium nitride is a material with high kinetic inductance. The inductance of the titanium nitride layer 4 depends on the geometry, but in existing quantum devices, it is typically less than 1 nanohenryen.

[0072] Figures 2A and 2B schematically illustrate cross-sectional views of a quantum device according to an embodiment of the present invention.

[0073] The device shown in Figure 2A illustrates a semiconductor layer 201 placed on a thick dielectric layer 202. In this example, the semiconductor layer 201 contains silicon, and the thick dielectric layer 202 contains silicon dioxide (SiO2). In alternative examples, the semiconductor layer 201 can be any suitable semiconductor such as GaAs, InAs, SiGe, graphene, carbon nanotubes, or SiC, and the thick dielectric layer 202 can be any suitable electrical insulating layer such as silicon oxide, silicon nitride, or aluminum oxide. The thick dielectric layer 202 forms a substrate portion that contains a further support layer (not shown) made of silicon in this example, beneath the thick dielectric layer 202. In alternative examples, the thick dielectric layer is absent, and the semiconductor layer forms the substrate portion.

[0074] The silicon layer 201 in Figure 2A contains silicon nanowires that extend in the direction of penetrating the paper, as shown in Figure 2A. A thin dielectric layer 203 is placed on top of the silicon layer 201. The thin dielectric layer 203 covers the exposed side of the silicon layer 201 and contains thermally grown silicon dioxide (SiO2). A metallic region 204 is placed on top of the thin dielectric layer 203. The thin dielectric layer 203 provides an electrostatic barrier between the silicon layer 201 and the metallic region 204.

[0075] The metallic region 204 encompasses titanium nitride (TiN). In alternative examples, the metallic region can encompass niobium nitride or titanium niobium nitride. TiN is a superconducting material with high kinetic inductance. For example, the kinetic inductance of a thin film of TiN can exceed 200 picohrenries per square meter for a thickness of 10 nanometers. The inductance of the metallic region 204 depends on its dimensions. Its inductance is proportional to the elongated portion of the metallic region 204 and inversely proportional to its length. Therefore, the kinetic inductance is proportional to the ratio of the elongated portion to the length of the metallic region 204. For a TiN thin film with a constant thickness of 10 nanometers, the inductance of a region with equal length and elongated portion will exceed 200 picohrenries. The high kinetic inductance of TiN means that it is possible to provide an inductor with high inductance even with a relatively small metallic region. In this example, the thickness of the metallic region 204 is 20 nanometers. Inductance is inversely proportional to thickness, and therefore, in another example, inductance can be increased by reducing the thickness of the metal region.

[0076] The length of the metallic region 204 is measured along the longitudinal axis of the nanowire, which in this example is 22 nanometers, although it is not visible in this cross-sectional view. The metallic region 204 is electrically connected to allow the induction of quantum dots within the nanowire at the functional interface between the semiconductor layer 201 and the thin dielectric layer 203 beneath the metallic region 204. The length of the metallic region 204 affects the size and, therefore, the properties of the quantum dots, such as their charge energy. The inductance is inversely proportional to the length of the metallic region 204. In another example, the size of the quantum dots can be increased by increasing the length of the metallic region, which results in quantum dots with lower charge energy and a metallic region with reduced inductance.

[0077] The metallic region 204 extends in a first direction substantially perpendicular to the nanowire. In an alternative example, the metallic region extends from the nanowire, forming an acute angle between the metallic region and the nanowire. The metallic region 204 extends until it contacts the gate electrode 206. The extended portion of the metallic region 204 is the distance d between the gate electrode 206 and the silicon layer 201 when measured along the first direction. g The inductance is defined by the length through which current flows from the gate electrode 206 to the silicon layer 201, and the inductance of the metal region 204 is proportional to its extension. Therefore, in this example, to achieve an inductance of 50 nanohenries, the extension of the metal region 204 should be approximately 10.6 micrometers. In another example, the extension of the metal region can be increased to increase the inductance.

[0078] Alternatively, the metal region 204 can be extended in a nonlinear manner. For example, the metal region 204 can meander across the surface of the thick dielectric layer 202. As a result, the furthest point of the metal region 204 in this example is such that the extended portion of the metal region is d g Nevertheless, d g It becomes shorter. This can be used to design more compact device architectures.

[0079] The device shown in Figure 2B has the same structural features as the device shown in Figure 2A. However, in Figure 2B, the semiconductor layer 201 contains gallium arsenide (GaAs), and the thin dielectric layer 203 contains a thermally grown oxide. The support layer (not shown) contains GaAs, and the thick dielectric layer 202 contains silicon dioxide, silicon nitride, or aluminum oxide. In addition, the device in Figure 2B further contains a masking layer 205. The masking layer 205 covers the metal region 204. In this example, the masking layer 205 contains polysilicon. Alternatively, the masking layer could contain, for example, aluminum. The masking layer 205 is used to prevent damage to the metal layer 204. The masking layer 205 shown in Figure 2B is positioned between the metal layer 204 and the gate electrode 206. The masking layer 205 is conductive, and as a result, the metal layer 204 is electrically connected to the gate electrode 206.

[0080] Figures 3A and 3B schematically illustrate cross-sectional views of a quantum device according to an embodiment of the present invention. In Figure 3A, the device substrate comprises a semiconductor layer 307 containing indium arsenide (InAs). In alternative examples, any semiconductor material compatible with complementary metal-oxide-semiconductor manufacturing processes can be used. A thick dielectric layer 308 partially covers the semiconductor layer 307. This can be achieved by selectively depositing the thick dielectric layer 308 on the semiconductor layer 307, leaving a gap. Alternatively, the thick dielectric layer 308 can be deposited in a first processing step to completely cover the semiconductor layer 307, and then in a second processing step, a portion of the thick dielectric layer 308 can be removed to form a gap. In this example, the thick dielectric layer 308 contains aluminum oxide (Al2O3). In alternative examples, the thick dielectric layer contains silicon dioxide or silicon nitride.

[0081] A thin dielectric layer 303 containing aluminum oxide is placed on top of a semiconductor layer 307. In another example, the thin dielectric layer contains hafnium dioxide or any other material with a high dielectric constant. In this example, the thin dielectric layer 303 and the thick dielectric layer 308 are deposited in separate processing steps. Alternatively, the thin dielectric layer 303 can also be formed by selectively removing portions of the thick dielectric layer 308 using chemical or physical processes to form regions of the thin dielectric layer 303.

[0082] Similar to Figures 2A and 2B, a metallic region 304 is positioned on a thin dielectric layer 303. In Figures 3A and 3B, the metallic region 304 contains niobium nitride (NbN), a material with high kinetic inductance. In alternative examples, the metallic region 304 can contain titanium nitride or titanium niobium nitride. The metallic region 304 extends along a thick dielectric layer 308, reaching electrical contact with the gate electrode 306. In Figures 3A and 3B, applying a bias potential to the gate electrode 306 allows quantum dots to be guided to the functional interface between the semiconductor layer 307 beneath the metallic region 304 and the thin dielectric layer 303.

[0083] The device shown in Figure 3B has the same structural features as the device shown in Figure 3A, and further includes a masking layer 305. The masking layer 305 contains aluminum and is located on top of the metal region 304. In another example, the masking layer contains any conductive material such as polysilicon. In Figure 3B, the semiconductor layer 307 contains a double layer of graphene. The thick dielectric layer 308 contains aluminum dioxide selectively deposited on the semiconductor layer 307. The thin dielectric layer 303 contains graphene oxide deposited or grown following the deposition of the thick dielectric layer 308. The semiconductor layer 307 is supported on a substrate such as a silicon substrate. In an alternative example, the thin dielectric layer contains aluminum oxide or silicon oxide, which can be deposited using appropriate techniques such as chemical vapor deposition (CVD).

[0084] Figures 4A and 4B schematically illustrate plan views of quantum devices according to embodiments of the present invention. These devices each include a transistor comprising a source electrode 416 and a drain electrode 426 electrically connected to a nanowire 401. In this example, the nanowire is silicon. In alternative examples, the nanowire may be gallium arsenide, monowalled or multiwalled carbon nanotubes, silicon germanium, indium arsenide, graphene, or silicon carbide. The source and drain electrodes 416, 426 are electrically connected to a voltage source. The electrical properties of the silicon nanowire 401 can be modified by applying a bias difference between the source and drain electrodes 416, 426. The nanowire 401 includes a highly doped region 404 and an undoped region 405.

[0085] Furthermore, the device comprises a first metallic region 414 and a second metallic region 424 laterally separated from the first metallic region 414. An undoped region 405 of the nanowire 401 extends beneath the first and second metallic regions 414, 424 to the edge of the nanowire 401. The nanowire 401 is electrically isolated from the first and second metallic regions 414, 424 by a thin dielectric layer (not shown). The first metallic region comprises a first inductor in the LC resonator circuit, and the second metallic region comprises a second inductor in the LC resonator circuit. The first and second metallic regions comprise the only inductor in the LC resonator circuit. No additional on-chip or off-chip inductors are present. The first and second metallic regions 414, 424 are electrically isolated from the nanowire 401 by a thin dielectric layer (not shown) positioned at least between the first and second metallic layers 414, 424 and the nanowire 401. In an alternative example, the thin dielectric layer may cover the main portion of the nanowire or be positioned only beneath the first and second metallic layers. In this example, the thin dielectric layer is a thermally grown native oxide.

[0086] The first and second metallic regions 414, 424 are electrically connected to their respective gate electrodes (not shown) which are connected to an external voltage source. The voltage source can be used to apply a voltage to the first and second metallic regions 414, 424 so that a double quantum dot can be guided to a functional interface beneath the first and second metallic regions 414, 424. The functional interface is defined by the geometry of the device and the electrical properties of the layers within the device. In this example, the nanowire is provided superimposed on a thick dielectric layer supported by a further supporting layer containing silicon. The functional interface is between the outer surface of the nanowire and the thin dielectric layer superimposed on the nanowire. The thick dielectric layer beneath the nanowire reduces the field effect away from the nanowire. The double quantum dot guided to the functional interface forms a qubit having two states and a variable capacitance that changes according to the state of the qubit. The double quantum dot comprises a capacitor in an LC resonator circuit of the device which can be used to measure or estimate the state of the qubit.

[0087] In Figure 4A, the first and second metallic regions 414 and 424 are separated along the longitudinal axis of the nanowire 401. In the alternative example, the nanowire 401 is replaced with a grown carbon nanotube selected for its semiconductor properties. The distance S between the first and second metallic regions 414 and 424 gg The distance is typically between 10 and 100 nanometers. gg It is configured to be of sufficient size to allow for clear distinction between the first and second quantum dots formed beneath the first and second metal regions 414, 424 when a bias potential is applied. On the other hand, the distance S gg It is composed of components small enough to allow the first and second quantum dots to be tunnel-coupled to form a dual quantum dot qubit.

[0088] Each of the first and second metal regions 414 and 424 has a length L g and extended portion d gIt has the following characteristics. Typically, the length and extension of the first metal region are the same as those of the second metal region. However, this is not a requirement, and the dimensions of the metal regions can be selected according to the desired performance characteristics of the device. The inductance of the first and second metal regions 414, 424 is proportional to the extension and inversely proportional to the length. The kinetic inductance L per unit length K This is determined by the following formula: TIFF0007873674000001.tif3353 In this, μ0 is the permeability of vacuum, λ is the magnetic field penetration depth, and L g and t g These are the length and thickness of the metal region. Typically, the length L is... g It is between 7 and 100 nanometers, and the extension portion d g The thickness t of the first and second metallic regions is between 1 and 100 nanometers. g The thickness is typically between 1 and 20 nanometers. Thicker metal regions have lower inductance per square meter and therefore occupy a larger area. However, manufacturing thinner metal regions can result in lower yields due to manufacturing difficulties. In one example, the metal region contains TiN and is 40 nanometers long and 10 nanometers thick. In this example, the inductance is 5 nanohenries per micron of metal region extension.

[0089] In Figure 4A, the first and second metallic regions 414 and 424 are positioned superimposed on both edges of the nanowire 401. Applying a bias potential to the first and second metallic regions 414 and 424 makes it possible to induce the first and second quantum dots, respectively, within the nanowire 401 beneath the first and second metallic regions. Each of the first and second quantum dots is positioned substantially at its center, away from the edges of the nanowire. The confinement of the charge carrier in each of the first and second quantum dots is limited by the narrow width w of the nanowire 401 and the length L of each metallic region. gThis is achieved using a functional interface between the nanowire 401 and a thin dielectric layer (not shown). The width w of the nanowire 401 is typically between 30 and 140 nanometers. Preferably, w is less than 100 nanometers. In this example, the width w of the silicon nanowire 401 is about 60 nanometers. The narrower the nanowire, the stronger the confinement. The appropriate width of the nanowire depends on the properties of the semiconductor used in the device, such as the effective mass of the charge carrier.

[0090] In the alternative example, the first and second metallic regions are positioned overlapping on only one edge of the nanowire, and each of the first and second metallic regions overlaps on the same edge of the nanowire. The first and second metallic regions are separated laterally along the longitudinal axis of the nanowire. In this alternative example, the confinement of the charge carrier is along the length L between the corner of the nanowire and the metallic region. g This is achieved using [method / tool]. The width w of the nanowire is irrelevant in this alternative example and can be several micrometers or more.

[0091] In Figure 4B, the first and second metallic regions 414 and 424 are positioned on opposite sides of the nanowire 401. Each of the first and second metallic regions 414 and 424 partially overlaps one edge of the nanowire 401. The first and second metallic regions 414 and 424 are spaced S apart along the width of the nanowire 401. vv Only the separation S. vv The interval S is typically between 10 and 100 nanometers. vv The first and second quantum dots formed beneath the first and second metal regions 414 and 424 when a bias potential is applied are configured to be of sufficient size to allow for clear distinction between them. On the other hand, the spacing S vv It is composed of components small enough to allow the first and second quantum dots to be tunnel-coupled to form a dual quantum dot qubit.

[0092] The capacitance of a device depends on the device's geometry and the state of the qubits. The total capacitance consists of the dual qudo / qubit, geometric capacitance, and an indeterminate capacitance arising from parasitic capacitance. The resonant frequency of an LC resonator circuit depends on the capacitance.

[0093] A dual quantum dot qubit has a first state with a first capacitance and a second state with a second capacitance. The capacitance values ​​of the first and second qubits are different. In this example, the electron spin orientation is antiparallel in the first state of the qubit and parallel in the second state. In the first state, tunneling between the first and second quantum dots is possible. In the second state, tunneling is suppressed due to spin blockade. Therefore, the first capacitance is much larger than the second capacitance. The first capacitance can be within the range of femtofarads, but will depend on the characteristics of the qubit.

[0094] Geometric capacitance can be estimated using the following equation. TIFF0007873674000002.tif3078 In this case ε die L is the relative permittivity of a thin dielectric layer. g and t g These are the length and thickness of the metal region, respectively, and S vv L is the distance between the first and second metallic regions in a direction perpendicular to the longitudinal axis of the nanowire. Exemplary value, L g = 50 nanometers, t g =10 nanometers, and S vv Using a thickness of 10 nanometers, the geometric capacitance for a device using a thin dielectric layer of silicon dioxide is approximately 2 at-farads. This is far smaller than the first capacitance.

[0095] Parasitic capacitance can occur between any metal region and the electrical ground state. However, parasitic capacitance is usually small, for example, about 0.1 to 0.2 femtofarads. The value of parasitic capacitance is usually indicated by the manufacturer and can be incorporated into calculations to optimize qubit measurement parameters. Changes in capacitance have an effect on the resonant frequency of the LC resonator circuit and therefore must be taken into consideration when performing measurements.

[0096] In another example, the device includes an additional dielectric layer that covers the first and second metal layers and optionally completely or partially occupies the gap between the first and second metal layers. This additional dielectric layer can be made from silicon nitride (Si3N4) and is used to ensure electrical isolation between neighboring metal regions and to provide protection against electrical and / or physical damage. This additional dielectric layer can also be made from any electrical insulating material.

[0097] In a further example, the first metal region 414 contains TiN and the second metal region 424 contains polysilicon. In this example, the first metal region 414 comprises an inductor in an LC resonator. However, the second metal region 424 does not contribute to the inductance.

[0098] Figure 5 illustrates a method for assembling a quantum device according to an embodiment of the present invention. In step 501, a dielectric layer is placed on a semiconductor layer to form a functional interface. The dielectric layer comprises an electrically insulating layer. In one example, the semiconductor layer contains silicon and the dielectric layer contains a material such as silicon dioxide or hafnium dioxide with a high dielectric constant. In another example, the semiconductor layer contains any one of gallium arsenide, indium arsenide, silicon germanium, graphene, carbon nanotubes, or silicon carbide and the dielectric layer contains a high-k dielectric material deposited using thermally grown oxide or atomic layer deposition. In one example, the semiconductor layer is a nanowire with a width between 30 and 140 nanometers. In another example, the semiconductor layer is a flat plateau region and the dielectric layer contains a thin region and a thick region. The width of the thin region is between 30 and 140 nanometers.

[0099] In step 502, a first metallic region is placed on the dielectric layer. In step 503, a second metallic region is placed on the dielectric layer, separated laterally from the first metallic region. The lateral spacing is typically between 10 and 100 nanometers. The first and second metallic regions are arranged to be electrically connected so as to enable the induction of first and second confinement regions at the functional interface beneath the first and second metallic regions, respectively. The first and second confinement regions are coupled to form a qubit having a first state and a second state. The qubit comprises a capacitor in an LC resonator circuit having a variable capacitance, which can be used to measure or estimate the qubit state.

[0100] The first and second metallic regions comprise materials with high kinetic inductance, such as titanium nitride, niobium nitride, or titanium niobium nitride. The first and second metallic regions comprise the first and second inductors in the LC resonator circuit. In an alternative example, only the first metallic region comprises the inductor in the LC resonator circuit. The LC resonator circuit has first and second resonant frequencies that depend on the inductance value and the variable capacitance of the qubit.

[0101] The dimensions of the first and second metal regions affect their inductance. The lengths of the first and second metal regions are typically between 7 and 100 nanometers. The length affects the size and inductance of the first and second confinement regions; longer first and second metal regions result in larger confinement regions and lower inductance. The first and second metal regions are typically extended 1 to 100 micrometers away from the confinement region, depending on the desired inductance of the first and second metal regions. If greater inductance is required, the first and second metal regions are designed to extend further.

[0102] Table 1 shows the kinetic inductance per square meter for titanium nitride (TiN), niobium nitride (NbN), and titanium niobium nitride (NbTiN). The kinetic inductance values ​​were experimentally determined for the thicknesses given in Table 1 and normalized to provide a comparison of the kinetic inductance of the materials independently of thickness. Critical temperature T cThe values ​​for these three materials are also given. Experimental values ​​for TiN were published in Shearrow et al., *Applied Physics Letters*, Vol. 113, 212601 (2018). Experimental values ​​for NbN were published in Hayashi et al., *Journal of Physics*, Conference Series, Vol. 507, 042015 (2014). Experimental values ​​for NbTiN were published in Samkharadze et al., *Physical Review Applied*, Vol. 5, 044004 (2016).

[0103] TIFF0007873674000003.tif43154

[0104] It should be noted here that any material with high kinetic inductance is suitable for use as the first and / or second metal layer in the devices described herein. Some superconductors have high kinetic inductance. Generally, disordered superconductors have higher kinetic inductance per square meter. Furthermore, superconductors with lower critical temperatures generally have higher kinetic inductance.

[0105] The effect of the dimensions of the first and second metal regions on the inductance can be determined using the values ​​given in Table 2. Table 2 shows the respective thicknesses t of the first and second metal regions required to achieve an inductance of 50 nanohenries using titanium nitride. g Length L g , and extended portion d g The following are example values.

[0106] TIFF0007873674000004.tif50153

[0107] Following the placement of the first and second metal regions, another exemplary assembly method further includes the step of placing a masking layer covering the first and second metal layers. The masking layer comprises a conductive material such as polysilicon or aluminum. The manufacturing process of this device may involve a self-alignment injection process that defines the source and drain electrodes of the device. In this case, the masking layer protects the underlying metal regions.

[0108] Quantum devices according to embodiments of the present invention can be manufactured using industry-standard complementary metal-oxide-semiconductor manufacturing processes.

[0109] Figure 6 is an illustration of a cross-sectional side view of a quantum device according to an embodiment of the present invention. In Figure 6, the device includes a silicon substrate 600. The device includes silicon fins 601 that protrude from the substrate 600 to form a fin-type field-effect transistor (FinFET). In this example, the silicon substrate 600 is etched to form the fins 601 that protrude from the rest of the substrate.

[0110] A thin dielectric layer 603 containing silicon dioxide is placed on the fin 601. First and second metal regions 614 and 624 are placed and overlapped on two edges of the fin 601. The first and second metal regions 614 and 624 comprise the first and second inductors in the LC resonator within the device. The first and second metal regions 614 and 624 extend toward the first and second gate electrodes 616 and 626, respectively.

[0111] A functional interface is formed between a thin dielectric layer 603 and a fin 601. The thin dielectric layer 603 covers the substrate 600 and the fin 601, but the geometry of the fin 601 enhances the field effect of the fin 601 when a bias is applied to the first and / or second metal regions 614, 624. As a result, it becomes possible to support the first quantum dot 610 at the corner of the fin 601 at the functional interface between the silicon fin 601 and the thin dielectric layer 603 below the first metal region 614. Similarly, it is possible to support the second quantum dot 620 at the corner of the fin 601 at the functional interface below the second metal region 624. The first and second quantum dots 610, 620 can be tunnel-coupled to form a double quantum dot. The double quantum dot forms a qubit having two quantum states and comprises a capacitor in the LC resonator circuit of the device. The first and second quantum dots 610 and 620 can be induced by applying bias potentials to the first and second metal regions 614 and 624, respectively.

[0112] At extremely low temperatures, the first and second quantum dots 610 and 620 can each be used to confine a single electron in response to the application of an appropriate bias potential to the first and / or second metallic regions 614 and 624. Under certain conditions, electrons can tunnel back and forth between the quantum dots 610 and 620. However, under other specific conditions, tunneling is suppressed due to spin blockade. Therefore, the double quantum dots behave as a variable capacitor with high capacitance when tunneling is not quantum mechanically suppressed. The maximum capacitance of the double quantum dots in this example is between 1 and 10 femtofarads. The capacitance of the device depends on the device geometry and material properties, as well as the state of the qubit. Therefore, the resonant frequency of the LC resonator circuit also depends on the state of the qubit. The relationship between the state of the qubit and the resonant frequency of the LC resonator circuit can be used to estimate the state of the qubit through the measurement of frequency-dependent power transfer.

[0113] Figure 7 is an illustration of a cross-sectional view of a quantum device according to an embodiment of the present invention. In Figure 7, the device includes a substrate 700 containing silicon. Dielectric layers 702 and 703 having non-uniform thicknesses are laid on top of the substrate 700. Dielectric layers 702 and 703 include a thin region 703 and a thick region 702. In this example, dielectric layers 702 and 703 are continuous regions containing silicon dioxide.

[0114] The thin region 703 of the dielectric layer occupies a substantially rectangular area. This rectangular area has a first edge and a second edge. The device includes a first metallic region 714 that overlaps the thin region 703 and the thick region 702 of the dielectric layer at the first edge. The device also includes a second metallic region 724 that overlaps the thin region and the thick regions 702 and 703 of the dielectric layer at the second edge. In this example, the first and second metallic regions 714 and 724 contain NbTiN. In alternative examples, the first and second metallic regions contain TiN or NbN. When a bias is applied to the first and / or second metallic regions, the field effect in the thinner portion of the dielectric layer becomes stronger. As a result, a functional interface is formed between the thin dielectric layer 703 and the semiconductor layer 700 beneath the first and second metallic regions 714 and 724. The first and second quantum dots 710 and 720 can be guided to the functional interfaces beneath the first and second metallic regions 714 and 724, respectively.

[0115] In another example, the device, when shown in cross-section, comprises two thin regions and three thick regions. The thin regions can be connected to each other within different regions of the device, and the thick regions can also be connected to each other elsewhere. In this example, the first metallic region is laid over the first thick region and the first thin region, and optionally over a portion of the second thick region. The second metallic region is laid over the second thin region and the third thick region, and optionally over a portion of the second thick region. The first and second metallic regions are nevertheless electrically and physically separated.

[0116] The device shown in Figure 7 illustrates a single qubit containing a double quantum dot. This device can be scaled to support an array of qubits. Further metallic regions can be superimposed on the dielectric layer, at least within a thin region of the dielectric layer. For example, third and fourth metallic regions can be superimposed on a thin region of the dielectric layer, separated laterally from the first and second metallic regions.

[0117] Further modifications allow for arbitrary shapes in the thin regions of the dielectric layer. Typically, the shape of each thin region of the dielectric layer encompasses two parallel edges. However, the spacing between these edges can be varied along the length of the thin region of the dielectric layer. Furthermore, the thin regions can be made nonlinear to support a two-dimensional array of qubits.

[0118] Figure 8 illustrates a method for measuring or reading out a qubit according to an embodiment of the present invention. This method can be performed on any device according to the embodiments of the present invention described herein. The device is cooled to an extremely low temperature before performing the steps of the method described below. In this example, the device is cooled to below 4.2 Kelvin. However, in alternative examples, the operating temperature, i.e., the temperature at which the method can be performed, may differ.

[0119] The operating temperature depends on the material used for the first metal region. For the first metal region to exhibit the high kinetic inductance characteristics necessary to provide an inductor in the LC resonator, the first metal region must be at a critical temperature T c It must be cooled to a lower temperature. For example, the estimated critical temperature of titanium nitride is lower than 2 Kelvin, the estimated critical temperature of niobium nitride is between 13 and 15 Kelvin, and the estimated critical temperature of titanium niobium nitride is 9 Kelvin.

[0120] The operating temperature also depends on the size of the quantum dot. To confine a charge carrier within a quantum dot, the thermal energy must be significantly lower than the charge energy of the quantum dot. Larger quantum dots will have lower charge energies, and consequently, a lower operating temperature is required to confine the charge carrier.

[0121] In step 801, a first bias potential is applied to the first metal region, and a second bias potential is applied to the second metal region. The first and second metal regions may be arranged in series, for example, as shown in Figure 4A, or in parallel, for example, as shown in Figure 4B. The first and second bias potentials are set to values ​​such that the first quantum dot is guided to the functional interface between the semiconductor layer and the thin dielectric layer beneath the first metal region, and the second quantum dot is guided to the functional interface beneath the second metal region. In this example, the first and second bias potentials are substantially the same, approximately 0.5 volts. The appropriate values ​​for the first and second bias potentials will depend on the geometry of the device.

[0122] At extremely low temperatures, the magnitudes of the first and second bias potentials can be selected to confine a single electron or several electrons to each of the first and second quantum dots. In this example, a single electron is confined to each quantum dot.

[0123] The first and second quantum dots are tunnel-coupled to form a double quantum dot. Under certain conditions, it is possible to tunnel a single electron from the first quantum dot to the second quantum dot, and from the second quantum dot to the first quantum dot. The capacitance of the double quantum dot is relatively large when a single electron tunnels between the two quantum dots.

[0124] A dual quantum dot forms a qubit having two quantum states defined by the relative electron spin states within the first and second quantum dots. In this example, the qubit is in the first state when the electron spins are antiparallel, and in the second state when the electron spins are parallel. In the second state, tunneling is suppressed due to spin blockade, so the capacitance of the first qubit state is greater than that of the second qubit state.

[0125] In step 802, a high-frequency signal is applied to the first metal region using a power supply. The frequency of this high-frequency signal corresponds to the resonant frequency of the LC resonator circuit encompassing the double quantum dot and the first and second metal regions. The resonant frequency of the LC resonator circuit depends on the capacitance of the double quantum dot. The capacitance of the double quantum dot depends on the state of the qubit, as described above.

[0126] In this example, the frequency of the high-frequency signal corresponds to the resonant frequency of the LC resonator circuit when the qubit is in the first state. A larger capacitance corresponds to a lower resonant frequency. Applying a lower frequency signal results in less parasitic loss.

[0127] In step 802, the amplitude of the high-frequency excitation is equal to the tunnel coupling voltage V between the quantum dots. in It is selected so that it becomes smaller. Therefore, there is no electron tunneling between the first and second quantum dots. The tunnel coupling voltage is determined by the following equation: TIFF0007873674000005.tif2858 Here, e is the charge of the electron, α is the gate lever arm, Δ is the tunnel coupling energy, and Q is the quality factor of the LC resonator. The gate lever arm is defined as the difference between the ratio of the gate capacitances of the first and second quantum dots in the first metallic region to the total capacitance of each quantum dot. In one example, when α = 0.5, Δ = 10 μeV, and Q = 1000, the tunnel coupling voltage V in =10 nV is obtained.

[0128] In step 803, a bias difference is applied between the first and second metal regions. This bias difference is small compared to the first and second bias potentials applied in step 801. The bias difference is greater than the tunnel coupling voltage. Typically, the bias difference is a few millivolts. The bias difference is selected such that, when the selected bias difference exists between the first and second metal regions and a high-frequency signal is applied to the first metal region, if the qubit is in the first state, electrons will tunnel back and forth between the first and second quantum dots, resulting in a high capacitance state. Conversely, if the qubit is in the second state, tunneling is greatly suppressed, resulting in a low capacitance state.

[0129] In step 804, power transfer through the LC resonator circuit is measured using a probe connected to the first or second metal region. If the qubit is in the first state, the resonant frequency matches the frequency of the high-frequency signal, and power transfer is high. If the qubit is in the second state, power transfer is low. Reflected power transfer S is measured using a probe connected to the first metal region. 11 It is possible to measure the forward power transfer S using a probe connected to a second metal region. 21 It is possible to measure this.

[0130] In this example, power transfer is measured using a vector network analyzer. In an alternative example, power transfer can be measured using a high-frequency voltage source and a power sensor. The power sensor can be, for example, a diode.

[0131] In the alternative example, the high-frequency signal in step 802 corresponds to the resonant frequency of the second state of the qubit. In this example, when the qubit is in the first state, the resonant frequency of the circuit does not match the frequency of the high-frequency signal, resulting in low power transfer. When the qubit is in the second state, power transfer is high.

[0132] Figure 9 is a circuit diagram showing a quantum device according to an embodiment of the present invention. The device is shown within the dashed area A. The first metallic region comprises a first inductor L1 with a first inductance in an LC resonator circuit. The second metallic region comprises a second inductor L2 with a second inductance in an LC resonator circuit. The first and second inductors L1 and L2 are in series with a double quantum dot comprising a first capacitor C1 in an LC resonator circuit. It should be noted that the capacitance of the double quantum dot changes according to the state of the qubit.

[0133] The circuit diagram also illustrates the off-chip sensing electronics. It is possible to operate the circuit using additional components to adjust the circuit's operating frequency. The second and third capacitors C2 and C3 represent the parasitic capacitance of the off-chip sensing electronics. The second and third capacitors C2 and C3 represent the total parasitic capacitance, which in this example is approximately 200 femtofarads for each of the second and third capacitors C2 and C3. In alternative examples, the capacitance of the second capacitor C2 and the capacitance of the third capacitor C3 may be different.

[0134] The fourth and fifth capacitors C4 and C5 represent decoupling capacitors. In this example, the capacitances of the fourth and fifth capacitors C4 and C5 are each approximately 0.25 picofarads. These decoupling capacitors enable maximum power transfer to the device, which provides maximum sensitivity for measuring the qubit state. The fourth and fifth capacitors C4 and C5 can be used to adjust the maximum power transfer through the circuit at resonance.

[0135] Furthermore, the circuit may include first and second bias tees (not shown) that can be used to offset the DC bias of the first and second metal regions so that the device becomes a qubit operating point. Each bias tee may contain a resistor with a resistance greater than 1 megaohm and may be positioned between the decoupling capacitor and the device.

[0136] The resonant frequencies of the circuit illustrated in Figure 9 depend on the first and second inductors and the first, second, third, fourth, and fifth capacitors. Maximum power transfer occurs at the circuit's resonant frequency. Figures 10A and 10B show the forward power transfer S. 21 This is illustrated as a function of frequency for the two values ​​of the first capacitance. The circuit response is simulated.

[0137] Figure 10A illustrates the forward power transfer when the first capacitance is 10 femtofarads. Using these input values, the resonant frequency of the circuit is expected to be approximately 5.15 gigahertz. When the first capacitance is a second value, i.e., 5 femtofarads, the resonant frequency of the circuit is expected to be approximately 7.20 gigahertz, as shown in Figure 10B.

[0138] Figures 11A and 11B schematically illustrate plan views of quantum devices according to embodiments of the present invention. These devices each include a source electrode 1002 and a drain electrode 1003 that are electrically connected to an external power supply. These devices may include a high-frequency multiplexer to reduce the number of high-frequency sources and detectors required to read out multiple qubit states.

[0139] The illustrated device architecture depicts a single nanowire 1001 and multiple qubit unit cells 1021-1024 and 1041-1043. Figures 11A and 11B schematically show the highly doped region 1004 and the undoped region 1005. Figure 11A illustrates four qubit unit cells 1021-1024, and Figure 11B illustrates three qubit unit cells 1041-1043. For reference, Figures 4B and 6 illustrate a similar device with a single qubit unit cell.

[0140] In Figure 11A, the nanowires are silicon germanium (SiGe) nanowires. In the alternative example, the nanowires are indium arsenide (InAs) nanowires. Each qubit unit cell 1021-1024 contains two metallic regions 1011-1018 positioned on opposite sides of the SiGe nanowire 1001. The undoped region 1005 of the nanowire 1001 extends to both edges of the nanowire 1001 beneath the metallic regions 1011-1018, and the metallic regions 1011-1018 are electrically isolated from the nanowire 1001 by a thin dielectric layer (not shown). The first qubit unit cell 1021 contains the first and second metallic regions 1011, 1012. The second qubit unit cell 1022 contains the third and fourth metallic regions 1013, 1014. The third qubit unit cell 1023 encompasses the fifth and sixth metal regions 1015 and 1016. The fourth qubit unit cell 1024 encompasses the seventh and eighth metal regions 1017 and 1018. In alternative examples, the device may contain further or fewer qubit unit cells. The spacing between the source and drain electrodes 1002 and 1003 can be modified according to the number of qubit unit cells. Each metal region 1011-1018 is electrically connected to a gate electrode (not shown). The metal regions 1011-1018 contain the only inductors in the device. There are no external inductors.

[0141] In this example, each qubit unit cell has substantially the same geometric properties and, as a result, similar electronic properties. For example, each of the metallic regions 1011 to 1018 is substantially the same length and, as a result, has substantially the same inductance. Therefore, the resonant frequencies of each of the qubit unit cells 1021 to 1024 will be similar. The state of each qubit can be measured or estimated by sequentially measuring the qubit in the first qubit unit cell 1021, the qubit in the second qubit unit cell 1022, the qubit in the third qubit unit cell 1023, and the qubit in the fourth qubit unit cell 1024.

[0142] Furthermore, the spacing between each pair of metallic regions (i.e., the first and second metallic regions 10¹¹, 10¹², the third and fourth metallic regions 10¹³, 10¹⁴, the fifth and sixth metallic regions 10¹⁵, 10¹⁶, and the seventh and eighth metallic regions 10¹⁷, 10¹⁸) is substantially the same. This means that the dual quantum dot qubits that can be induced within each qubit unit cell 10²¹–10²⁴ have similar electronic properties to the extent that variations resulting from device imperfections are incorporated into the calculations. Device imperfections can arise, for example, from material defects or processing irregularities.

[0143] The qubit unit cells 1021-1024 are separated along the longitudinal axis of the nanowire 1001. The third and fourth metallic regions are separated laterally from the first and second metallic regions along the longitudinal axis of the nanowire. The lateral spacing between each adjacent metallic region is assumed to be such that there is no overlap. In this example, the spacing between the qubit unit cells is substantially the same. For example, the spacing between the first metallic region 1011 in the first qubit unit cell 1021 and the third metallic region 1013 in the second qubit unit cell 1022 is between 10 and 100 nanometers.

[0144] In alternative examples, the spacing between adjacent qubit unit cells may differ. For example, the spacing between the first and third metal regions 1011, 1013 can be greater than the spacing between the third and fifth metal regions 1013, 1015. However, the arrangement of metal regions along the nanowire is substantially symmetrical, and therefore the spacing between the first and third metal regions 1011, 1013 is the same as the spacing between the second and fourth metal regions 1012, 1014, within a range that allows for manufacturing tolerances.

[0145] In Figure 11B, nanowire 1001 encloses silicon. The first qubit unit cell 1041 encloses the first and second metal regions 1031 and 1032, the second qubit unit cell 1042 encloses the third and fourth metal regions 1033 and 1034, and the third qubit unit cell 1043 encloses the fifth and sixth metal regions 1035 and 1036. In alternative examples, the device encloses further or fewer qubit unit cells. Each metal region 1031-1036 is electrically connected to a gate electrode (not shown). The metal regions 1031-1036 are the only inductors in the LC resonator circuit of this device. The undoped region 1005 of the nanowire 1001 extends to both edges of the nanowire 1001 beneath the metallic regions 1031-1036, and the metallic regions 1031-1036 are electrically isolated from the nanowire 1001 by a thin dielectric layer (not shown).

[0146] In this example as well, as explained with respect to Figure 11A, the spacing between pairs of metallic regions within each qubit unit cell 1041-1043 is substantially the same, and the spacing between adjacent metallic regions along both edges of the nanowire is substantially the same. However, in the device shown in Figure 11B, each qubit unit cell 1041-1043 has a different resonant frequency due to the difference in the extension of the metallic regions 1031-1036. In this example, the metallic regions of each pair are extended by substantially the same distance. This can facilitate the manufacturing process and simplify data extraction. In this example, the extensions of the first and second metallic regions 1031, 1032 are the shortest. The third and fourth metallic regions 1033, 1034 extend slightly further than the first and second metallic regions 1031, 1032. The fifth and sixth metallic regions 1035, 1036 extend the furthest. Therefore, the inductances of the first and second metal regions 1031 and 1032 are smaller than the inductances of the third and fourth metal regions 1033 and 1034, while the inductances of the fifth and sixth metal regions 1035 and 1036 are the largest.

[0147] In the alternative example, the second, fourth, and sixth metal regions 1032, 1034, and 1036 may be extended by substantially the same amount, while only the first, third, and fifth metal regions 1031, 1033, and 1035 have different extended portions. In this configuration, the total inductance of each qubit unit cell is further modified.

[0148] In further examples, only the first, third, and fifth metal regions 1031, 1033, and 1035 contain the sole inductor within their respective qubit unit cells 1041, 1042, and 1043. The second, fourth, and sixth metal regions 1032, 1034, and 1036 contain polysilicon and can be of any size, and these sizes do not affect the inductance of the LC resonator circuit. Even in this case, it is possible for the first, third, and fifth metal regions 1031, 1033, and 1035 to be extended by different distances, resulting in diversity in the inductance between the LC resonator circuits.

[0149] Due to the different inductances of the first, second, and third qubit unit cells 1041-1043, and therefore their different resonant frequencies, the state of each qubit can be measured or estimated using frequency domain multiplexing.

[0150] Figure 8 describes a method for measuring or reading out a qubit for a device with a single qubit unit cell. For devices with multiple qubit unit cells, time-domain and / or frequency-domain multiplexing can be employed to measure or estimate the state of the qubits within each qubit unit cell.

[0151] For example, a time-domain multiplexing method can be used to measure the state of each qubit in the device shown in Figure 11A. In this example, a high-frequency signal is applied to a first metallic region, and subsequently, the state of the qubit in the first qubit unit cell is measured or estimated in a second metallic region. Then, a high-frequency signal is applied to a third metallic region, and the state of the qubit in the second qubit unit cell is measured or estimated in a fourth metallic region.

[0152] For the device shown in Figure 11B, the frequency domain multiplexing method can be used to measure the state of each qubit. In this example, it is possible to simultaneously measure or estimate the state of each qubit.

[0153] In alternative examples, a combination of time and frequency domain multiplexing methods can be employed. For example, a device may contain several qubit unit cells with the same dimensions and several with different dimensions. The specific implementation of the device and method used will depend on some practical constraints such as the desired device properties and geometry. For example, in the case of a device with 20 qubit unit cells, having 20 different extensions may be deemed inappropriate because the inductance of the smallest metal region may fall below the desired value, and the size of the largest metal region may result in a large parasitic capacitance and / or consequently geometric constraints.

[0154] As can be seen from the above, a quantum device having an LC resonator circuit for measuring or reading out qubits is disclosed, along with a method for measuring or reading out qubits using the device and a method for assembling the device. The LC resonator circuit in the device comprises a capacitor and an inductor. The inductor is provided by a metallic region containing a material with high kinetic inductance. The metallic region is also suitable for inducing a quantum dot that can be used to confine one or more electrons. A double quantum dot forming a qubit having two states can be induced using two neighboring metallic regions. The capacitor in the LC resonator circuit is provided by a double quantum dot qubit having a capacitance that varies depending on the state of the qubit. The resonant frequency of the LC resonator circuit depends on its capacitance. Power transfer through the LC resonator circuit is frequency-dependent and is maximum at the circuit's resonant frequency. The state of the qubit affects the capacitance, which in turn affects the resonant frequency. Therefore, it is possible to use a measurement of power transfer at the circuit's resonant frequency to estimate the state of the qubit. The dual function of the first metallic region, namely the induction of quantum dots and the provision of an inductor within the LC resonator, along with the use of a material with high kinetic inductance to form the first metallic region, results in a compact device with qubit readout capability. [Explanation of Symbols]

[0155] 1. Silicon nanowires 2. Silicon dioxide layer 3. Dielectric layer 4 Titanium nitride layer 5. Polysilicon layer 6. Food Service Centers 7 Silicon layer 8. Silicon dioxide layer 201 Semiconductor layer, silicon layer 202 Thick dielectric layer 203 Thin dielectric layer 204 Metal region, metal layer 205 Masking layer 206 Gate 303 Thin dielectric layer 304 Metal area 305 Masking layer 306 Post Office 307 Semiconductor layer 308 Thick dielectric layer 401 nanowire 404 High-doped region 405 Undoped area 414 First metallic region, metallic layer 416 Source electrodes 424 Second metallic region, metallic layer 426 Drain electrode 600 circuit boards 601 Silicone fins, fins 603 Thin dielectric layer 610 First quantum dot 620 Second quantum dot 614, 624 First and second metallic regions 616, 626 First and second gate electrodes 700 substrates, semiconductor layers 702 Thick region (dielectric layer) 703 Thin region (dielectric layer) 710 The first quantum dot 714 First Metallic Region 720 Second quantum dot 724 Second Metallic Region 1001 nanowires, SiGe nanowires 1002 Source electrode 1003 Drain electrode 1004 High-doped region 1005 Undoped area 1011~1018 Metal area 1021-1024 qubit unit cell 1031~1036 Metal area 1041-1043 qubit unit cell C1 First Capacitor C2 Second Capacitor C3 Third capacitor C4, the fourth capacitor C5, the fifth capacitor L1 First inductor L2 Second inductor

Claims

1. A quantum device having an LC resonator circuit for measuring or reading out qubits, Semiconductor layer, A dielectric layer disposed on the semiconductor layer and forming a functional interface with the semiconductor layer, A first metal region disposed on the dielectric layer, A second metal region is disposed on the dielectric layer and is separated laterally from the first metal region, It includes, The first metal region and the second metal region are arranged to be electrically connected so as to enable the induction of a double quantum dot, which forms a qubit having a first state and a second state, onto the functional interface beneath the first metal region and the second metal region. The double quantum dot comprises a capacitor in the LC resonator circuit, and the capacitance of the double quantum dot depends on the state of the qubit. The first metal region comprises an inductor in the LC resonator circuit. The resonant frequency of the LC resonator circuit depends on the state of the qubit, thereby making it possible to measure or estimate the state of the qubit. Quantum devices.

2. The quantum device according to claim 1, wherein the first metallic region includes a superconductor.

3. A power supply configured to supply power at a frequency corresponding to the resonant frequency of the LC resonator circuit, A probe for estimating the state of the qubit, connected to the first and / or second metal regions and configured to measure power transfer through the LC resonator circuit, The quantum device according to claim 1 or 2, further encompassing the above.

4. The quantum device according to any one of claims 1 to 3, wherein the first metal region comprises a first inductor in the LC resonator circuit, and the second metal region comprises a second inductor in the LC resonator circuit.

5. The quantum device according to any one of claims 1 to 4, further comprising a masking layer covering the first metallic region.

6. The quantum device according to any one of claims 1 to 5, wherein the semiconductor layer encompasses a nanowire, and the first metal region and the second metal region are arranged on opposing sides of the nanowire such that each of the first and second metal regions includes a portion that partially overlaps with one edge of the nanowire and extends away from the nanowire.

7. Further encompassing third and fourth metallic regions disposed on the dielectric layer, The third and fourth metallic regions are positioned on opposing sides of the nanowire such that each of the third and fourth metallic regions includes a portion that partially overlaps with one edge of the nanowire and extends away from the nanowire. The third and fourth metallic regions are separated laterally from the first and second metallic regions along the longitudinal axis of the nanowire. The first metal region and the second metal region are arranged to be electrically connected so as to enable the first double quantum dot to be guided to the functional interface beneath the first metal region and the second metal region. The third and fourth metallic regions are arranged to be electrically connected so as to enable the induction of a second double quantum dot on the functional interface beneath the third and fourth metallic regions. The quantum device according to claim 6.

8. The quantum device according to claim 7, wherein the inductances of the third and fourth metal regions are greater than the inductances of the first and second metal regions, respectively.

9. The quantum device according to any one of claims 1 to 5, wherein the semiconductor layer encompasses a nanowire, and the first metallic region and the second metallic region are separated laterally along the longitudinal axis of the nanowire.

10. The quantum device according to any one of claims 1 to 5, wherein the dielectric layer encompasses a thin region and a thick region, and the functional interface is formed between the semiconductor layer and the thin region of the dielectric layer.

11. A method for measuring or reading out a qubit using the device described in any one of claims 1 to 10, The steps include: applying first and second bias potentials to the first and second metal regions, respectively, to induce a double quantum dot; and forming a qubit having a first state and a second state on the functional interface beneath the first and second metal regions. This includes the first and second bias potentials, which are substantially identical, and furthermore, The steps include applying a signal with a selected frequency to the first metal region, The steps include applying a bias difference between the first metal region and the second metal region, A step of measuring power transfer in the first or second metal region, A method comprising, wherein the measurement is used to measure or estimate the state of the qubit.

12. The method according to claim 11, wherein the selected frequency is the resonant frequency of the circuit when the capacitance of the double quantum dot is at its maximum.

13. The method according to claim 11 or 12, wherein the method is carried out at a temperature lower than 20 Kelvin.

14. A method for assembling a quantum device according to any one of claims 1 to 10, The steps include: arranging a dielectric layer on top of a semiconductor layer to form a functional interface; The steps include placing a first metal region on the dielectric layer, The steps include: arranging a second metal region on the dielectric layer, separated laterally from the first metal region; It includes, The first metal region and the second metal region are electrically connected such that a double quantum dot forming a qubit having a first state and a second state can be guided to the functional interface beneath the first metal region and the second metal region. The double quantum dot comprises a capacitor in the LC resonator circuit, and the capacitance of the double quantum dot depends on the state of the qubit. The first metal region comprises an inductor in the LC resonator circuit. The resonant frequency of the LC resonator circuit depends on the state of the qubit, thereby making it possible to measure or estimate the state of the qubit. method.

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