Vertical trench-type capacitively coupled gate-controlled junction field-effect transistor and method for manufacturing the same

Abstract

To provide a vertical trench type capacitive coupling gate control junction type field effect transistor in which the current characteristic from a drain to a source is not affected, current does not flow to a gate, and the reliability is high, and a manufacturing method for the same.SOLUTION: A field effect transistor includes a substrate 1 functioning as a drain region of a first doping type, an epitaxial layer 2 existing on the substrate, and a plurality of repeating units. Each of the repeating units includes two source regions 4 of the first doping type provided in the epitaxial layer and apart from each other in a lateral direction, a trench formed downward from an upper surface of the epitaxial layer and existing between the source regions, a gate 6 of a second doping type formed at an inner wall and a bottom part of the trench and in a floating state, a dielectric layer 7 formed at least on an inner bottom of the gate, and a coupling capacitance upper electrode 8 formed on the dielectric layer. The gate is controlled indirectly by the coupling capacitance upper electrode through the dielectric layer.SELECTED DRAWING: Figure 3-1

Description

[Technical Field]

[0001] This application relates to the semiconductor technology field, and more specifically to a vertical trench capacitively coupled gate-controlled junction field-effect transistor and a method for manufacturing the same. [Background technology]

[0002] Silicon carbide (SiC) is a third-generation wide-bandgap semiconductor with a bandgap width of 3.2 eV, which is significantly larger than the 1.1 eV of conventional silicon materials. It also has advantages such as a critical breakdown field strength that is an order of magnitude higher than silicon materials, excellent resistance to high temperatures and pressures, and a fast saturation drift rate, making it suitable for manufacturing high-temperature, high-voltage power semiconductor devices that support fast response, such as VDMOS (Vertical Double-diffused MOSFET) and JFET (Junction Field-Effect Transistor).

[0003] A junction field-effect transistor (JFET) is a triode semiconductor device whose operating principle involves controlling the reverse bias of the pn junction between the gate electrode and the channel by applying a voltage to the gate electrode, thereby turning off the drain and source electrodes. When no voltage is applied to the gate electrode, a junction field-effect transistor is usually a normally-on device, and its conduction channel is located within the device. Due to its advantages such as low noise, small size, and high-frequency response, junction field-effect transistors are often applied to switching devices, power amplifier devices, and digital electronic circuits, meeting the requirements of various electronic devices.

[0004] The CN1238904C is a JFET device, and as shown in Figure 1, it comprises a single-crystal silicon SiC substrate 1, a p-type epitaxial layer 2, an n-type epitaxial layer 3, a p+-type semiconductor layer 4, an n+-type source region layer 5, a p+-type gate layer 7, an n+-type drain region layer 9, a source electrode 10, a gate electrode 11, and a drain electrode 12. The conduction channel of the JFET device is located inside the device, within the n-type epitaxial layer 3, and the conduction channel is located inside the semiconductor material, thus avoiding the problem of low surface mobility of the SiC material. The JFET device is a normally-on device, meaning that when no voltage is applied to the p+-type gate layer 7 (i.e., the gate electrode), the device is in a conduction state (shown as a dashed line representing current in Figure 1). Therefore, in order to turn off the device, a negative voltage must be applied to the p+-type gate layer 7 (i.e., the gate electrode), which limits its application as a power switch. Furthermore, since the p+ type gate layer 7 (i.e., the gate electrode) and the channel have a pn junction structure, it is not possible to apply a voltage exceeding 3V to the p+ type gate layer 7 (i.e., the gate electrode). In the case of SiC material, if a voltage of 3V or more is applied to the gate electrode, the gate electrode and the channel or source electrode conduct, resulting in a large on-current that affects the current characteristics from drain to source. Moreover, because high voltages cannot be applied to the gate electrode, its application as a power switch is limited.

[0005] Therefore, conventional JFET devices have a technical problem in that high voltage cannot be applied to the gate electrode, resulting in low reliability of the gate electrode, which limits their application as power switches.

[0006] The information disclosed in the background art is intended solely to enhance understanding of the background of the present application and therefore may contain information that does not constitute prior art known to those skilled in the art. [Overview of the project] [Problems that the invention aims to solve]

[0007] Embodiments of the present application provide a vertical trench capacitive-coupled gate-controlled junction field-effect transistor and a manufacturing method thereof to solve the technical problem existing in conventional JFET devices, namely, that a high voltage cannot be applied to the gate electrode, and the reliability of the gate electrode is low, thus restricting the application as a power switch.

Means for Solving the Problem

[0008] In a first aspect according to an embodiment of the present application, a vertical trench capacitive-coupled gate-controlled junction field-effect transistor is provided. The vertical trench capacitive-coupled gate-controlled junction field-effect transistor includes a first-doping-type substrate and an epitaxial layer, and a plurality of repeating units. The epitaxial layer is located on the substrate, and the substrate functions as a drain region. The repeating unit includes two first-doping-type source regions formed in the epitaxial layer and spaced apart in the horizontal direction, a trench formed downward from the upper surface of the epitaxial layer and located between the two first-doping-type source regions, a second-doping-type gate formed on the inner wall and bottom of the trench and in a floating state, a dielectric layer formed at least on the inner bottom of the gate, and a coupling capacitor upper electrode formed on the dielectric layer.

[0009] In a second aspect according to an embodiment of the present application, a manufacturing method of a vertical trench capacitive-coupled gate-controlled junction field-effect transistor is provided. The method includes forming a first-doping-type epitaxial layer on a first-doping-type substrate, and forming a plurality of repeating units. The step of forming the repeating units includes forming two first-doping-type source regions located in the epitaxial layer and spaced apart in the horizontal direction, The steps include forming a trench that is formed downward from the upper surface of the epitaxial layer and located between two first doping-type source regions, The steps include forming a second doping-type gate located on the inner wall and bottom of the trench, The steps include forming a dielectric layer on the inner bottom of the gate, The step includes forming a coupled capacitance upper electrode on the dielectric layer, The gate is indirectly controlled by the coupling capacitance upper electrode across the dielectric layer. [Effects of the Invention]

[0010] The embodiments of this application, by employing the above technical solutions, have the following technical effects.

[0011] In the vertical trench capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of the present application, the gate 6 is indirectly controlled by the coupling capacitance upper electrode 8 across the dielectric layer 7. The coupling capacitance upper electrode voltage applied to the coupling capacitance upper electrode 8 is coupled to the gate 6 by coupling. Furthermore, because the gate 6 is in a floating state and not directly connected to the gate electrode, even if the potential of the coupling capacitance upper electrode 8 rises to 3V or higher, the lower part located between the coupling capacitance upper electrode 8, the substrate 1, and the gate 6 in the epitaxial layer does not conduct. Compared to the JFET device described in CN1238904C, in the embodiment of the present application, even if a high voltage (above 3V, e.g., 4V, 5V) is applied to the coupling capacitance upper electrode 8, it does not conduct and does not affect the current characteristics from the drain electrode to the source electrode of the device. Because the gate 6 is indirectly controlled by the coupling capacitance upper electrode 8 across the dielectric layer 7, no current flows through the gate 6, resulting in higher reliability. [Brief explanation of the drawing]

[0012] The accompanying drawings shown herein are for further understanding of the present application and constitute part of the present application; the exemplary embodiments and descriptions thereof are for illustrative purposes of the present application and do not constitute an unreasonable limitation to the present application. [Figure 1] This is a schematic diagram showing a conventional JFET device. [Figure 2] This is a schematic diagram showing a conventional Trench VDMOS device. [Figure 3-1] This is a schematic diagram showing the first implementation form of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention. [Figure 3-2] This is a schematic diagram showing a second implementation form of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention. [Figure 3-3] This is a schematic diagram showing a third implementation form of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention. [Figure 3-4] This is a schematic diagram showing a fourth implementation configuration of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention. [Figure 3-5] This is a schematic diagram showing a fifth implementation configuration of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention. [Figure 3-6] This is a schematic diagram showing the sixth implementation form of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention. [Figure 3-7] This is a schematic diagram showing the seventh implementation form of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention. [Figure 3-8] This is a schematic diagram showing the eighth implementation form of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention. [Figure 3-9] This is a schematic diagram showing the ninth implementation form of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention. [Figure 3-10] This is a schematic diagram showing the tenth implementation configuration of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention. [Figure 4] This is a schematic diagram illustrating the formation of an epitaxial layer on a substrate in a method for manufacturing a vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to the second implementation embodiment of the present invention. [Figure 5]This is a schematic diagram based on Figure 4 illustrating the formation of the second doping type ohmic contact region, source region, and trench. [Figure 6] This is a schematic diagram of trench formation based on Figure 5. [Figure 7] This is a schematic diagram showing the formation of a gate based on Figure 6. [Figure 8] This is a schematic diagram illustrating the formation of a dielectric layer based on Figure 7. [Figure 9] This is a schematic diagram based on Figure 8, showing how the positions of the coupling capacitance upper electrode and source electrode are pre-determined on the dielectric layer. [Figure 10] This is a schematic diagram showing the formation of the coupling capacitance upper electrode and source electrode based on Figure 9. [Figure 11] This is a schematic diagram showing the formation of the drain electrode based on Figure 10. [Figure 12] This is an equivalent circuit diagram of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention. [Figure 13] This is a schematic diagram showing the current path when the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention is conducting. [Figure 14] This is a schematic diagram comparing the characteristics of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention with those of a conventional VDMOS device. [Figure 15] This is a schematic diagram showing the vertical trench type capacitively coupled gate-controlled junction field-effect transistor of the present invention. [Figure 16] This is the potential distribution of the structure of the coupling capacitance upper electrode of the vertical trench type capacitively coupled gate-controlled junction field-effect transistor of the present invention. [Figure 17-1] This figure shows the energy band distribution when different voltages are applied to the upper electrode 10 of the coupling capacitance of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention. [Figure 17-2] This figure shows the energy band distribution when different voltages are applied to the upper electrode 10 of the coupling capacitance of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention. [Figure 17-3] This figure shows the energy band distribution when different voltages are applied to the upper electrode 10 of the coupling capacitance of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention. [Figure 17-4] This figure shows the energy band distribution when different voltages are applied to the upper electrode 10 of the coupling capacitance of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention. [Figure 17-5] This figure shows the energy band distribution when different voltages are applied to the upper electrode 10 of the coupling capacitance of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention. [Figure 17-6] This figure shows the energy band distribution when different voltages are applied to the upper electrode 10 of the coupling capacitance of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention. [Figure 18-1] This figure shows the carrier concentration distribution in each region during device operation, as the hole concentrations in the gate 6, channel 5, and second-doped ohmic contact region 3 of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention are affected by the voltage applied to the coupling capacitance upper electrode 8. [Figure 18-2] This figure shows the carrier concentration distribution in each region during device operation, as the electron concentration in the gate 6, channel 5, and second-doped ohmic contact region 3 of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention is affected by the voltage applied to the coupling capacitance upper electrode 8. [Modes for carrying out the invention]

[0013] To further clarify the technical solutions and advantages of the embodiments of this application, exemplary embodiments of this application will be described in more detail below with reference to the drawings. However, it is clear that the embodiments described are only a selection of embodiments of this application and do not exhaustively represent all embodiments. Furthermore, the embodiments and features of the embodiments of this application may be combined with each other without contradiction.

[0014] Conventional semiconductor devices are often manufactured using silicon, a first-generation semiconductor material. However, in recent years, silicon carbide, a third-generation wide-bandgap semiconductor material, has shown significant performance advantages over silicon-based semiconductor devices due to its material advantages such as wide bandgap, high breakdown voltage, and high thermal conductivity. However, because the growth of current silicon carbide materials is still immature, silicon carbide-based semiconductor devices have performance and reliability issues. For example, silicon carbide materials have many defects near the surface, resulting in low surface mobility and seriously impacting device performance. Furthermore, silicon carbide devices have high quality requirements for gate oxides, but the quality of existing gate oxides cannot meet these reliability requirements. In conventional power devices of the same type, the conductive channels are located on the surface of the silicon carbide material and oxide. Due to the material properties of silicon carbide, there are many charges and defects on the surface of the silicon carbide and oxide, which affects the mobility of carriers in the channels. As a result, the carrier mobility in the channels is much lower than the bulk mobility of silicon carbide. The channel mobility, i.e., surface mobility, of silicon carbide MOSFETs is approximately 20-40 cm⁻¹. 2 While the value is / V·s, the bulk mobility of silicon carbide material is approximately 1000 cm². 2 The value is / V·s. Low channel mobility affects the current transmission characteristics and on-resistance of the device. Also, because the portion of the current flowing across the device surface is located beneath the gate oxide, unstable traps and defect centers affect the reliability of the gate electrode operation of the device.

[0015] In conventional power devices of the same type, under the high voltage of the drain electrode when the device is off (breakdown condition), the main breakdown voltage region is the vertical epitaxial layer-JFET region-dielectric layer. From the relationship D=ε·E between the electric displacement vector, electric field strength, and dielectric constant, the electric displacement vector within the semiconductor is D 半導体 =ε 半導体 ·E 半導体It is found that the electric displacement vector in the dielectric layer immediately adjacent to the semiconductor is D 誘電体 = ε 誘電体 · E 誘電体 At the interface between the semiconductor and the dielectric, the electric displacement vector D is continuous, that is, D 半導体 = D 誘電体 Therefore, ε 半導体 · E 半導体 = ε 誘電体 · E 誘電体 When the same dielectric material is adjacent to different semiconductor materials, if the substrates are silicon and silicon carbide, the dielectric constants ε of these two semiconductor materials are approximately the same (ε シリコン = 11.8, ε 炭化ケイ素 = 9.8), but the critical breakdown field strength of silicon carbide, which is a third-generation wide-bandgap semiconductor material, is much larger than that of the silicon material (E シリコン = 0.23 MV / cm, E 炭化ケイ素 = 2.2 MV / cm). From ε 半導体 · E 半導体 = ε 誘電体 · E 誘電体 it can be seen that the electric field strength in the dielectric layer corresponding to the silicon carbide material is much larger than that in the dielectric layer corresponding to the silicon material. Therefore, the dielectric layer (oxide layer or high-K dielectric) below the gate of a silicon carbide-based device in the breakdown state has a very high electric field strength with a typical value of about 2×10 6 V / cm, and the electric field strength is on the order of megavolts per centimeter. The high electric field strength in the dielectric layer affects the reliability of the operation of the gate electrode of the silicon carbide-based device.

[0016] As described above, in the prior art, not only is there a technical problem that a high voltage cannot be applied to the gate electrode in a conventional silicon carbide-based junction field-effect transistor, and the reliability of the gate is low, which limits the application of the junction field-effect transistor as a power switch, but there are also technical problems such as a decrease in the performance of the device due to the conductive channel being close to the surface of a material with low mobility, and a decrease in the reliability of the device due to a decrease in the quality of the gate dielectric layer.

[0017] Trench Vertical Double-Diffused MOSFET (Trench VDMOS) devices are an improved structure based on planar VDMOS, where the gate electrode is formed by etching trenches. This allows the gate electrode to penetrate deep into the device to control the on / off state of the channel, resulting in enhanced controllability of the gate electrode over the channel and achieving lower on-resistance Rsp and current Idsat compared to planar VDMOS devices.

[0018] As shown in Figure 2, the CN113363308A is a P-channel Trench VDMOS device structure. The polysilicon gate has a trench-type structure that penetrates deep into the device, and the MOS capacitance effect of the gate oxide layer attracts charge near the trench in the n-type base region, controlling whether the n-type base region inverts and thus controlling the on / off state of the channel. During device operation, the inverted channel in the n-type base region is controlled by the polysilicon gate and moves closer to the gate oxide layer, i.e., the boundary between the device trench and the gate oxide layer (the closer to the polysilicon gate, the greater the gate's influence). In other words, part of the conductive channel is located within the P-drift region, and the other part is along the surface of the trench near the gate oxide. Similar to planar VDMOS, where the location of the conduction channel on the device surface causes low mobility problems, trench VDMOS presents more serious issues due to trench etching, such as charge, defects, and surface scattering at the interface between the trench surface and the gate oxide layer. The low carrier mobility on the semiconductor trench surface results in a low device saturation current (Idsat), a high on-resistance (Rsp), and affects device performance, limiting the device's output power and switching speed. Trench VDMOS is a suitable vertical trench capacitively coupled gate-controlled junction field-effect transistor when applied to switching and linear applications, and is primarily used in electronic switches, adapters, drive band energy, and industrial control systems.

[0019] <Example 1> As shown in Figure 3-1, the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to the first implementation embodiment of the present invention (i.e., Example 1) comprises a first-doped substrate 1 and an epitaxial layer 2, and a plurality of repeating units, wherein the epitaxial layer 2 is located on the substrate 1, the substrate functions as a drain region, and the repeating units are Two first doping-type source regions 4 are formed within the epitaxial layer 2 and are spaced apart in the lateral direction, A trench is formed from the upper surface of the epitaxial layer 2 downwards and located between the two first doping-type source regions 4, A second doping-type gate 6, which is formed in the inner wall and bottom of the trench and is in a floating state, A dielectric layer 7 formed at least on the inner bottom of the gate 6, The device comprises a coupling capacitance upper electrode 8 formed on the dielectric layer 7.

[0020] Here, the second doped gate 6, the first doped epitaxial layer 2, and the second doped gate 6 of the adjacent repeating unit form a JFET region (i.e., the region located between the second doped gate 6 of the adjacent repeating unit and the adjacent second doped gate 6 of the epitaxial layer forms a JFET region), and the gate 6 of the JFET region is indirectly controlled by the coupling capacitance upper electrode 8 across the dielectric layer 7.

[0021] In the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of the present invention, the gate 6 of the JFET region is indirectly controlled by the coupling capacitance upper electrode 8 across the dielectric layer 7. The coupling capacitance upper electrode voltage applied to the coupling capacitance upper electrode 8 is coupled to the gate 6 by coupling. Furthermore, since the gate 6 is in a floating state and not directly connected to the gate electrode, even if the potential of the coupling capacitance upper electrode 8 rises to 3V or higher, the lower part of the epitaxial layer located between the coupling capacitance upper electrode 8, the substrate 1, and the gate 6 does not conduct. Compared to the JFET device described in CN1238904C, in the embodiment of the present invention, even if a high voltage (above 3V, e.g., 4V, 5V) is applied to the coupling capacitance upper electrode 8, it does not conduct and does not affect the current characteristics from the drain electrode to the source electrode of the device. Since the gate 6 is indirectly controlled by the coupling capacitance upper electrode 8 across the dielectric layer 7, no current flows through the gate 6, resulting in higher reliability.

[0022] Specifically, the dielectric layer 7 plays a role in preventing current injection by the coupled capacitance upper electrode from affecting the reliability of the device and improving the operating voltage.

[0023] The vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of the present invention is a vertical trench-type capacitively coupled gate-controlled junction field-effect transistor with a novel structure, and is neither a conventional JFET device nor a conventional Trench VDMOS device.

[0024] In the CN1238904C JFET device, the coupling capacitance upper electrode and the channel are connected via a pn junction, making it impossible to apply a voltage higher than 3V to the coupling capacitance upper electrode. When SiC is used as the substrate material, applying a voltage of 3V or higher to the coupling capacitance upper electrode causes conduction between the coupling capacitance upper electrode and the channel or source electrode, resulting in a large on-current that affects the current characteristics from the drain electrode to the source electrode. This prevents the application of high voltages to the coupling capacitance upper electrode, thus limiting its use as a power switch.

[0025] The vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of this application differs in essential ways from conventional JFET devices as follows:

[0026] The vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of the present invention utilizes the principle of capacitive coupling to indirectly control the upper electrode of the coupling capacitance, thereby avoiding current injection from the upper electrode of the coupling capacitance into the channel and enabling control of the channel by applying a higher voltage to the upper electrode of the coupling capacitance, making it applicable to a wider range of applications.

[0027] The vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of this application differs in essential ways from a JFET device as follows:

[0028] The vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of the present invention indirectly controls the on / off state of the channel by controlling the potential of the floating coupled capacitance upper electrode 8 across the dielectric layer 7, utilizing the principle of capacitive coupling.

[0029] In a typical JFET device, the top gate is directly connected to the electrodes, and when a high voltage is applied, the pn junction between the top gate and the channel turns on, causing current to flow from the top gate to the channel, resulting in a negative effect. In the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor structure according to the embodiment of the present invention, this problem can be avoided because of the isolation provided by the insulating gate dielectric layer.

[0030] In implementation, as shown in Figure 3-1, the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor is, A drain electrode 10 is provided on the lower surface of the substrate 1, The system further comprises two source electrodes 9 formed on each of the two source regions 4, The first doped substrate 1, the first doped epitaxial layer 2, and the two first doped source regions 4 form an internal conductive path from the drain electrode to the two source electrodes, located within the substrate 1 and the epitaxial layer 2.

[0031] In the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of the present invention, the first-doped epitaxial layer fabricates the main structure of the semiconductor device (the gate 6, source region 4, etc., are all parts of the semiconductor device). By providing the source region 4 on the upper part of the epitaxial layer, the source region 4 is provided from top to bottom within the epitaxial layer. This ensures that the substrate 1, the epitaxial layer 2, and the two source regions 4 are all of the first-doped type, and therefore the first-doped substrate, the first-doped epitaxial layer, and the two first-doped source regions 4 form an internal conduction path (shown by a dashed line in Figure 3-1) from the drain electrode 10 to the source electrode 9, located within the substrate and epitaxial layer, and this internal conduction path is entirely away from the surface of the trench. In other words, the internal conduction path is entirely away from the surface of the semiconductor material and the surface of the trench, and is internal conduction, thus avoiding the problem of low surface mobility. In the embodiment of the present invention, the internal conduction path of the vertical trench capacitively coupled gate-controlled junction field-effect transistor is located inside the vertical trench capacitively coupled gate-controlled junction field-effect transistor and is separated from the trench surface and the semiconductor material surface. As a result, the carriers always maintain a state of high mobility and fast drift rate, and the vertical trench capacitively coupled gate-controlled junction field-effect transistor has a large saturation current Idsat, a small on-resistance Rsp, and good performance.

[0032] In the trench-type VDMOS patent application CN116598356A, the conducting channel is partially located vertically inside the device, with the other part aligned along the surface of the trench. That is, part of the conducting channel is on the surface of the trench. Part of the conducting channel is on the surface of the trench because the P-drift region and the n-base region form a PN junction, and when no voltage is applied, the PN junction is off. When a voltage is applied to the polysilicon gate, the PN junction is most likely to invert to form a channel for conduction at the part closest to the polysilicon gate, i.e., the surface of the trench. Therefore, the conducting channel is located on the surface of the trench, i.e., along the surface of the trench. Trench etching exacerbates problems with charge, defects, and surface scattering at the interface between the trench surface and the gate oxide. This results in low carrier mobility on the semiconductor trench surface, leading to a low device saturation current (Idsat), high on-resistance (Rsp), and ultimately impacting device performance, limiting the device's output power and switching speed.

[0033] In the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of the present invention, the substrate 1, the epitaxial layer 2, and the two source regions 4 are all of the first doping type, and they are conductive even without the formation of a PN junction. As a result, an internal conduction path is formed within the substrate and epitaxial layer, from the drain electrode 10 to the source electrode 9. This internal conduction path is separated from the surface of the semiconductor material, and this internal conduction path is separated from the surface of the trench. In other words, all internal conduction paths are separated from the surface of the semiconductor material and the surface of the trench, resulting in internal conduction and avoiding the problem of low surface mobility.

[0034] In the implementation, as shown in Figure 3-1, the trench is a U-shaped trench, in which case the dielectric layer 7 covers the coupling capacitance upper electrode space surrounded by the inner surface of the gate 6, and the dielectric layer (7) covers the top of the gate. The coupling capacitance upper electrode 8 is formed in the coupling capacitance upper electrode space.

[0035] By etching a U-shaped trench, a U-shaped trench gate 6 is formed, allowing the gate 6 to penetrate deep into the device and control the on / off state of the JFET region, thereby enhancing the gate 6's control capability over the JFET region. Compared to planar VDMOS devices, lower on-resistance Rsp and current Idsat are achieved.

[0036] In the implementation, the substrate is a silicon carbide substrate, a silicon substrate, a diamond substrate, or a potassium oxide substrate. The dielectric layer is a dielectric layer made of a high dielectric constant material. The aforementioned coupling capacitance upper electrode 8 is a polysilicon electrode or a metal electrode.

[0037] Conventional diamond substrate MOSFETs have a problem with their dielectric layer; the dielectric layer formed on the diamond substrate by deposition methods, such as the oxide layer, is of poor quality and therefore performs poorly. In contrast, the diamond vertical trench capacitively coupled gate-controlled junction field-effect transistor using this device structure solves this problem because the conduction channel is located within the device. MOSFETs (metal oxide semiconductor field-effect transistors) are common semiconductor devices.

[0038] Potassium oxide is a fourth-generation semiconductor material that can be used in the manufacture of electronic elements and electronic devices, particularly new types of controllable semiconductor devices.

[0039] Specifically, silica or a high-K dielectric material may be used for the dielectric layer. Using a high-K dielectric helps control the coupling capacitance of the upper electrode to the P+ type top gate, thereby improving the performance of the device.

[0040] Specifically, gate 6 can employ P+ and N+ type high-concentration doped polysilicon, which reduces the contact resistance with the upper electrode metal of the coupling capacitance and the parasitic resistance of the upper electrode of the coupling capacitance, thereby improving the performance of the device.

[0041] High-K dielectrics refer to materials with a high dielectric constant (high relative permittivity).

[0042] Specifically, the first doped substrate 1 is highly doped, has a high doping concentration, and functions as the drain region of a vertical trench-type capacitively coupled gate-controlled junction field-effect transistor.

[0043] In practice, the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor is, The system further comprises a metal silicide layer (not shown in Figure 3-1) formed between the gate 6 and the dielectric layer 7.

[0044] A metal silicide layer (abbreviated as Silicide layer) may be added beneath the dielectric layer of the upper electrode of the coupling capacitance, that is, the metal silicide layer may be interposed between the dielectric layer 7 and the gate 6. In this way, the metal silicide layer beneath the dielectric layer 7 is a metal layer, and the electric field distribution within the metal layer is uniform, thereby optimizing the electric field on the surface of the gate 6 and improving the reliability of the device.

[0045] In the example, the doping concentration of gate 6 is 1 × 10⁻⁶ 16 cm -3 That's all.

[0046] The doping concentration at the gate is 1 × 10⁻⁶ 16 cm -3 As described above, this ensures that the top gate does not become depleted when the gate electrode voltage is applied, and that no strong electric field is generated within the gate.

[0047] In the implementation, the doping concentration of channel 5 is higher than the doping concentrations of the substrate and epitaxial layer. The doping concentration in the channel is higher than that of the substrate. This helps to reduce the on-resistance of the device and improve its performance.

[0048] The vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to Example 1 may be implemented as a normally-off device or a normally-on device.

[0049] To implement the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to Example 1 as a normally-off device, By controlling the doping of the second-doped gate 6 of two adjacent repeating units, when the voltage of the coupled capacitance upper electrode 8 is zero, the region sandwiched between the second-doped gate 6 of two adjacent repeating units in the epitaxial layer becomes depleted, and the vertical trench-type capacitive-coupled gate-controlled junction field-effect transistor is a normally-off device.

[0050] Here, by adjusting the doping position and doping concentration of the second doping type gate 6 of two adjacent repeating units, the vertical trench capacitively coupled gate-controlled junction field-effect transistor is implemented as a normally-off device.

[0051] When a vertical trench capacitively coupled gate-controlled junction field-effect transistor is a normally off device, If the first type of doping is N-type doping and the second type of doping is P-type doping, When no voltage is applied to a vertical trench capacitively coupled gate-controlled junction field-effect transistor, the vertical trench capacitively coupled gate-controlled junction field-effect transistor turns off. When a positive voltage is applied to a vertical trench capacitively coupled gate-controlled junction field-effect transistor, the vertical trench capacitively coupled gate-controlled junction field-effect transistor conducts.

[0052] Furthermore, if the first type of doping is P-type doping and the second type of doping is N-type doping, When no voltage is applied to a vertical trench capacitively coupled gate-controlled junction field-effect transistor, the vertical trench capacitively coupled gate-controlled junction field-effect transistor is turned off. When a negative voltage is applied to a vertical trench capacitively coupled gate-controlled junction field-effect transistor, the vertical trench capacitively coupled gate-controlled junction field-effect transistor conducts.

[0053] To implement the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to Example 1 as a normally-on device, By controlling the doping of the second-doped gate 6 of two adjacent repeating units, when the voltage of the coupled capacitance upper electrode 8 is zero, the region of the epitaxial layer sandwiched between the second-doped gate 6 of the two adjacent repeating units becomes conductive, and the vertical trench-type capacitive-coupled gate-controlled junction field-effect transistor is a normally-on device.

[0054] Here, by adjusting the doping position and doping concentration of the second doping type gate 6 of two adjacent repeating units, the vertical trench capacitively coupled gate-controlled junction field-effect transistor is implemented as a normally-on device.

[0055] If a vertical trench-type capacitively coupled gate-controlled junction field-effect transistor is a normally-on device, If the first type of doping is N-type doping and the second type of doping is P-type doping, When no voltage is applied to a vertical trench capacitively coupled gate-controlled junction field-effect transistor, the vertical trench capacitively coupled gate-controlled junction field-effect transistor conducts. When a negative voltage is applied to a vertical trench capacitively coupled gate-controlled junction field-effect transistor, the vertical trench capacitively coupled gate-controlled junction field-effect transistor turns off.

[0056] Furthermore, if the first type of doping is P-type doping and the second type of doping is N-type doping, When no voltage is applied to a vertical trench capacitively coupled gate-controlled junction field-effect transistor, the vertical trench capacitively coupled gate-controlled junction field-effect transistor conducts. When a positive voltage is applied to a vertical trench capacitively coupled gate-controlled junction field-effect transistor, the vertical trench capacitively coupled gate-controlled junction field-effect transistor turns off.

[0057] In other words, the region sandwiched between the second-doped gate 6 of two adjacent repeating units is the portion of the epitaxial layer sandwiched between the second-doped gate 6 of two adjacent repeating units.

[0058] <Example 2> The vertical trench capacitively coupled gate-controlled junction field-effect transistor according to the second implementation form (Example 2) of this application differs structurally from the vertical trench capacitively coupled gate-controlled junction field-effect transistor according to the first implementation form (i.e., Example 1) as follows. As shown in Figure 3-2, the vertical trench capacitively coupled gate-controlled junction field-effect transistor according to the second implementation form (Example 2) of this application is, It further comprises two first doping-type channels 5 located below each of the two source regions 4.

[0059] In this way, the second doped gate 6, the first doped channel 5, and the second doped gate 6 of the adjacent repeating unit form a JFET region, and the gate 6 of the JFET region is indirectly controlled by the coupling capacitance upper electrode 8 across the dielectric layer 7.

[0060] In this case, as shown in Figure 3-2, the first doped substrate 1, the first doped epitaxial layer 2, the two first doped channels 5, and the two first doped source regions 4 form an internal conductive path from the drain electrode to the two source electrodes, located within the substrate 1 and the epitaxial layer 2.

[0061] Specifically, channel 5 may be formed by ion implantation or by other methods utilizing the original substrate. As a result, the doping concentration of channel 5 is higher than the doping concentration of epitaxial layer 2.

[0062] Specifically, the doping concentration of channel 5 in the first doping type is higher than that of epitaxial layer 2, resulting in a lower resistance for channel 5 in the first doping type, and consequently a lower on-resistance Rsp of the vertical trench capacitively coupled gate-controlled junction field-effect transistor, thus improving the performance of the vertical trench capacitively coupled gate-controlled junction field-effect transistor.

[0063] In this case, the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to Example 2 may be implemented as a normally-off device or a normally-on device.

[0064] To implement the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to Example 2 as a normally-off device, By controlling the doping of the second-doped gate 6 of two adjacent repeating units, when the voltage across the coupled capacitance upper electrode 8 is zero, the channel 5 sandwiched between the second-doped gate 6 of the two adjacent repeating units becomes depleted, and the vertical trench-type capacitive-coupled gate-controlled junction field-effect transistor is a normally-off device.

[0065] Here, by adjusting the doping position and doping concentration of the second doping type gate 6 of two adjacent repeating units, the vertical trench capacitively coupled gate-controlled junction field-effect transistor may be implemented as a normally-off device.

[0066] To implement the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to Example 2 as a normally-on device, By controlling the doping of the second-doped gate 6 of two adjacent repeating units, when the voltage of the coupled capacitance upper electrode 8 is zero, the channel 5 sandwiched between the second-doped gate 6 of the two adjacent repeating units becomes conductive, and the vertical trench-type capacitive-coupled gate-controlled junction field-effect transistor is a normally-on device.

[0067] Here, by adjusting the doping position and doping concentration of the second doping type gate 6 of two adjacent repeating units, the vertical trench capacitively coupled gate-controlled junction field-effect transistor may be implemented as a normally-on device.

[0068] In other words, the region sandwiched between the second doping type gate 6 of two adjacent repeating units is the channel 5.

[0069] The CN1238904C JFET device is a normally-on device, meaning that when no voltage is applied to the gate electrode, the device conducts, and a negative voltage must be applied to the gate electrode to turn the device off. This limits the device's application as a power switch.

[0070] <Example 3> The vertical trench capacitively coupled gate-controlled junction field-effect transistor according to the third implementation form (Example 3) of this application differs structurally from the vertical trench capacitively coupled gate-controlled junction field-effect transistor according to the first implementation form (i.e., Example 1) as follows. As shown in Figure 3-3, the vertical trench capacitively coupled gate-controlled junction field-effect transistor according to the third implementation form of this application is, It further comprises two second doping-type ohmic contact regions 3 located outside each of the two source regions 4.

[0071] Here, the second doped gate 6, the region located between the second doped gate 6 and the second doped ohmic contact region 3 of the epitaxial layer, and the second doped ohmic contact region 3 form a JFET region, and the gate 6 of the JFET region is indirectly controlled by the coupling capacitance upper electrode 8 across the dielectric layer 7.

[0072] The second doping type ohmic contact region 3 plays a role in adjusting the electric field to improve the device's breakdown voltage BV and enhance the device's reliability.

[0073] In this case, as shown in Figure 3-3, the first doped substrate 1, the first doped epitaxial layer 2, and the two first doped source regions 4 form an internal conductive path from the drain electrode to the two source electrodes, located within the substrate 1 and the epitaxial layer 2.

[0074] The vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to Example 3 may be implemented as a normally-off device or a normally-on device.

[0075] To implement the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to Example 3 as a normally-off device, By controlling the doping of the second-doped gate 6 and the second-doped ohmic contact region 3, when the voltage of the coupled capacitance upper electrode 8 is zero, the region of the epitaxial layer sandwiched between the second-doped gate 6 and the second-doped ohmic contact region 3 becomes depleted, and the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor is a normally-off device.

[0076] Here, by adjusting the doping position and doping concentration of the adjacent second-doped gate 6 and second-doped ohmic contact region 3, the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor is implemented as a normal-off device.

[0077] To implement the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to Example 3 as a normally-on device, By controlling the doping of the second-doped gate 6 and the second-doped ohmic contact region 3, when the voltage of the coupled capacitance upper electrode 8 is zero, the region of the epitaxial layer sandwiched between the second-doped gate 6 and the second-doped ohmic contact region 3 becomes conductive, and the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor is a normally-on device.

[0078] Here, by adjusting the doping position and doping concentration of the adjacent second-doped gate 6 and second-doped ohmic contact region 3, the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor is implemented as a normally-on device.

[0079] In other words, the region sandwiched between the second-doped gate 6 and the second-doped ohmic contact region 3 is the region of the epitaxial layer sandwiched between the second-doped gate 6 and the second-doped ohmic contact region 3.

[0080] Specifically, the second doping type ohmic contact region 3 may be formed by ion implantation or by other methods using the original substrate.

[0081] <Example 4> The vertical trench capacitively coupled gate-controlled junction field-effect transistor according to the fourth implementation form (Example 4) of the present application differs structurally from the vertical trench capacitively coupled gate-controlled junction field-effect transistor according to the first implementation form (i.e., Example 1) as follows. As shown in Figure 3-4, the vertical trench capacitively coupled gate-controlled junction field-effect transistor according to the fourth implementation form (Example 4) of the present application is, Two first doping-type channels 5 are located below each of the two source regions 4, It further comprises two second doping-type ohmic contact regions 3 located outside the two source regions 4 and the channel 5, respectively. Here, the second doped gate 6, the first doped channel 5, and the second doped ohmic contact region 3 form a JFET region, and the gate 6 of the JFET region is indirectly controlled by the coupling capacitance upper electrode 8 across the dielectric layer 7. The gate 6, channel 5, source region 4, and second doping-type ohmic contact region 3 are formed within the epitaxial layer 2.

[0082] In this case, as shown in Figure 3-4, the first doped substrate 1, the first doped epitaxial layer 2, the first doped channel 5, and the two first doped source regions 4 form an internal conductive path from the drain electrode to the two source electrodes, located within the substrate 1 and the epitaxial layer 2.

[0083] Specifically, the first doped substrate 1, the first doped epitaxial layer 2, the first doped channel 5, and the two first doped source regions 4 are connected sequentially. Current flows from the drain electrode 10 through the first doped substrate 1 and the first doped epitaxial layer 2, through the first doped channels 5 on both the left and right sides, through the source regions 4 on both the left and right sides, and finally is collected by the two source electrodes 12 on both the left and right sides.

[0084] Specifically, channel 5 may be formed by ion implantation or by other methods using the original substrate. As a result, the doping concentration of channel 5 is higher than the doping concentration of epitaxial layer 2.

[0085] Specifically, the doping concentration of channel 5 in the first doping type is higher than that of epitaxial layer 2, resulting in a relatively low resistance of channel 5 in the first doping type, and consequently, a relatively low on-resistance Rsp of the vertical trench capacitively coupled gate-controlled junction field-effect transistor, leading to good performance of the vertical trench capacitively coupled gate-controlled junction field-effect transistor.

[0086] This application proposes a vertical trench-type capacitively coupled gate-controlled junction field-effect transistor, and in an embodiment of the device, the threshold voltage is 3.03V, the breakdown voltage is 1507V, and the on-resistance is 0.12Ω·mm. 2This allows for the realization of a device that meets the following criteria. According to the vertical trench capacitively coupled gate-controlled junction field-effect transistor of this invention, all conduction channels are located inside the device, making it less susceptible to the effects of interfacial charge and low interfacial mobility of the device, and the on-resistance is improved by 50% compared to ordinary silicon carbide-based VDMOS. Because the dielectric layer is protected by the gate, the area protecting the junction field effect of the coupled capacitance upper electrode can be reduced, further lowering the on-resistance. Due to the capacitive coupling effect of the channel, the current of this invention saturates under high gate voltage, improving the short-circuit resistance of the device. The coupled capacitance upper electrode of the vertical trench capacitively coupled gate-controlled junction field-effect transistor of this invention is a capacitively coupled gate, and operates using the capacitive coupling principle to control the operation of the device. The requirements for the work function of the capacitance electrode are low, and coupled capacitance dielectrics can be used flexibly. The typical electric field strength in the dielectric layer at the breakdown of the device is approximately 2 × 10⁻⁶. 5 With a voltage of V / cm, it is approximately an order of magnitude lower than conventional silicon carbide devices, has lower quality requirements for capacitively coupled dielectrics, and clearly offers higher reliability, robustness, and manufacturing advantages.

[0087] The following explanation will use the example where the first doping type is N-type and the second doping type is P-type.

[0088] The P+ type ohmic contact region 3, the N type channel 5, and the P+ type gate 6 form a JFET region, the P+ type ohmic contact region 3 and the N type channel 5 form a single PN junction, and the N type channel 5 and the P+ type gate 6 form a single PN junction. By controlling the voltage of the coupling capacitance upper electrode 8, depletion and pinch-off of channel 5 are achieved, control of the internal conduction path is realized, and ultimately, conduction and off-control of the vertical trench type capacitively coupled gate-controlled junction field-effect transistor is achieved.

[0089] The vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to Example 4 may be implemented as a normally-off device or a normally-on device.

[0090] To implement the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to Example 4 as a normally-off device, By controlling the doping of the second-doped gate 6 and the second-doped ohmic contact region 3, when the voltage of the coupling capacitance upper electrode 8 is zero, the channel 5 sandwiched between the second-doped gate 6 and the second-doped ohmic contact region 3 becomes depleted, and the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor is a normally-off device.

[0091] Here, by adjusting the doping position and doping concentration of the adjacent second-doped gate 6 and second-doped ohmic contact region 3, the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor is implemented as a normal-off device.

[0092] To implement the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to Example 4 as a normally-on device, By controlling the doping of the second-doped gate 6 and the second-doped ohmic contact region 3, when the voltage of the coupling capacitance upper electrode 8 is zero, the channel 5 sandwiched between the second-doped gate 6 and the second-doped ohmic contact region 3 becomes conductive, and the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor is a normally-on device.

[0093] Here, by adjusting the doping position and doping concentration of the adjacent second-doped gate 6 and second-doped ohmic contact region 3, the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor is implemented as a normally-on device.

[0094] In other words, the region sandwiched between the second doping type gate 6 and the second doping type ohmic contact region 3 is the channel 5.

[0095] The following explanation will use the example where the first doping type is N-type and the second doping type is P-type.

[0096] In the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of the present invention, the JFET region is connected to the depletion region formed by the coupling capacitance upper electrode 8 and the self-formed electric field of the N-type channel 5, and to the depletion region of the self-formed electric field formed by the PN junction. This enables self-depletion and pinch-off of the N-type channel 5, thereby realizing the normally-off function of the device. That is, when no voltage is applied to the coupling capacitance upper electrode 8, the connection between the drain electrode and the source electrode is off, and when a voltage is applied to the coupling capacitance upper electrode, the connection between the drain electrode and the source electrode is on.

[0097] The following describes a method for manufacturing a vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to an embodiment of the present invention, using the case where the first doping type is N-type and the second doping type is P-type as an example. This manufacturing method includes the following steps.

[0098] Referring to Figure 4, an N-type epitaxial layer 2 is epitaxially grown on a low-resistance SiC N+ type substrate 1. Subsequently, the N+ epitaxial layer 1 forms ohmic contact with the metal of the drain electrode 10 on the back surface. The N-type epitaxial layer 2 is then formed to become the main structure of the device by processes such as ion implantation, thermal annealing, etching, and deposition.

[0099] Referring to Figure 5, and based on the structure formed in Figure 4, a single cell of the device is fabricated using a photomask with photoresist as the mask material, and a P+ type ohmic contact region 3, an N+ type ohmic contact region 4, and an N type channel 5 are formed on the N- type epitaxial layer 2 by ion implantation. This device has a centrally symmetric structure and is a single cell; however, actual devices are composed of multiple similar cells arranged in an array.

[0100] Referring to Figure 6, based on the structure formed in Figure 5, a trench is formed by plasma etching by etching the SiC material at the intermediate position of the single cell, that is, in the intermediate portion between the two source electrodes on the left and right.

[0101] Referring to Figure 7, based on the structure formed in Figure 6, ion implantation is performed in the trench region, and the SiC material inside the trench, near the trench surface, is formed into a P+ type gate 6 by implantation. If the trench is deep, ion implantation with a slope may be used to form the vertical sidewall of the trench into a P type. The P+ type gate 6 is not connected to an external metal electrode and is a physically floating region. Subsequently, the potential is coupled to the P+ type gate 6 by applying a voltage to the coupling capacitance upper electrode 8 or by the principle of coupling capacitance due to the dielectric layer 7, and then the on / off of the N type channel 5 is controlled by the JEFT effect. After the implantation into the P+ type gate 6 is complete, the implantation into the entire active region of this trench-type vertical trench-type capacitively coupled gate-controlled junction field-effect transistor is completed, and each time the implanted ions are activated and diffused by thermal annealing to form each region.

[0102] Referring to Figure 8, based on the structure formed in Figure 7, a dielectric layer 7 is deposited on the trench and wafer surface by chemical vapor deposition, and the surface is polished flat by chemical mechanical polishing. An oxide layer or other high-K dielectric can be used as the dielectric layer, but a high-K dielectric is advantageous due to the control of the P+ type gate 6 and N type channel 5 by the coupling capacitance upper electrode. A high-K dielectric refers to a material with a high dielectric constant (high relative permittivity).

[0103] Referring to Figure 9, based on the structure formed in Figure 8, the coupling capacitance upper electrode and source region to be etched are defined by a method of forming a photoresist or hard mask by lithography, and the gate dielectric is etched by plasma etching to form a trench-type coupling capacitance upper electrode and source electrode on which metal needs to be deposited.

[0104] Referring to Figure 10, based on the structure formed in Figure 9, a metal is deposited to form a coupling capacitance upper electrode 8 in the trench region, and a source electrode 9 is formed in the boundary region between the P+ type ohmic contact region 3 and the N+ type ohmic contact region 4. The coupling capacitance upper electrode can also have a polysilicon gate formed by depositing polysilicon, which has the advantage of allowing adjustment of the control capability of the coupling capacitance upper electrode by the gate.

[0105] Referring to Figure 11, based on the structure formed in Figure 10, after the surface process of the device is completed, the entire back surface of the wafer is polished to make it thinner, and the back surface is metallized to fabricate the drain electrode 10 on the back surface of the device, thereby completing the entire device structure.

[0106] The operating principle of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of this application will be described in detail below.

[0107] The vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of this application utilizes the properties of SiC wide-bandgap semiconductors. Because the bandgap width of SiC is 3.4 electron volts, the Fermi level difference energy of P-type and N-type SiC brought about by doping exceeds 3 electron volts. Therefore, the SiC PN junction generates a built-in voltage exceeding 3 volts, establishing the physical foundation of the device by significantly adjusting the current in the junction field-effect transistor channel. Physically, this device is essentially different from the channel current brought about by channel doping, which is a physical property inherent to wide-bandgap semiconductor devices and has been discovered for the first time in this application. This will be explained in detail below with reference to the energy band diagram.

[0108] Conventional technologies include three common methods for modulating the channel. The first method is the inversion layer used in conventional Si MOSFETs, which, when combined with high-quality silicon dioxide grown using thermal-oxygen growth more suitable for silicon materials, enables large-scale production and application.

[0109] The second method involves heterojunction FETs, exemplified by GaAs / AlGaAs and GaN / AlGaN, abbreviated as HFETs. This device structure is difficult to fabricate in an enhanced form factor, a problem currently being addressed through methods such as embedded gate structures and fluoride ion implantation.

[0110] The third method is the JFET principle, but because silicon has a bandgap of only 1.1 eV, silicon-based JFET devices can only be fabricated as normally-on devices. Existing SiC-based JFET devices are also normally open and cannot be used directly as power electronics switching devices.

[0111] In the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of this invention, the normally-off function of the device is achieved by utilizing the high built-in voltage formed by the wide bandgap characteristics of SiC, in conjunction with the wide bandgap characteristics of SiC. However, the threshold voltage does not exceed 1V and the gate operating voltage does not exceed 3V, so it still cannot meet the requirements of power electronics switching devices. Based on this, this invention provides a capacitively coupled gate structure that can reach a threshold voltage of 3V or more and an operating voltage of 15V or more, thus fully meeting the requirements of existing power electronics devices.

[0112] The vertical trench capacitively coupled gate-controlled junction field-effect transistor of the present invention has a vertical device structure, and as shown in Figure 3-4, the drain electrode 10 is located below the substrate 1 at the bottom of the device, and the coupled capacitance upper electrode 8 and source electrode 9 are located at the top of the device. The coupled capacitance upper electrode employs a trench structure, with a dielectric layer 7 outside the coupled capacitance upper electrode 8 and a gate 6 outside the dielectric layer 7. The coupled capacitance upper electrode 8, dielectric layer 7, and gate 6 together constitute the coupled capacitance upper electrode structure of the vertical trench capacitively coupled gate-controlled junction field-effect transistor. The portion immediately adjacent to the gate 6 is the source region 4 and channel 5, and these two portions, together with the epitaxial layer 2 and substrate 1, constitute the conduction path of the vertical trench device structure. The other side of the source region 4 and channel 5 is a second-doped ohmic contact region 3, which is connected to the source electrode 9 together with the source region 4. The second-doped ohmic contact region 3, channel 5, and gate 6 form a JFET region.

[0113] The equivalent circuit diagram of the coupling capacitance upper electrode of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor device in Embodiment 4 of the present application (corresponding to Figures 3-4) is as shown in Figure 12, and has a structure in which a capacitor and the coupling capacitance upper electrode of the junction field-effect transistor are connected in series. In this circuit diagram, the capacitor is coupled with the semiconductor junction capacitor of the JFET to divide the voltage and control the on and off states of the junction field-effect transistor.

[0114] When the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention operates, as shown in Figure 3-4, a voltage is applied to the coupling capacitance upper electrode 8 and the drain electrode 10. The voltage applied to the coupling capacitance upper electrode 8 is coupled to the gate 6 via the dielectric layer 7. The potential coupled to the gate 6 forms a second doping-type ohmic contact region 3 connected to the source electrode and a region of the JFET device control channel, thereby controlling the on / off state of the intermediate channel.

[0115] When the applied voltage turns off the channel, the JFET region is in an off state, and channel 5 becomes depleted. In this depleted state, the number of carriers in the channel is small. If a voltage is then applied to the drain electrode 10, the device's channel is depleted and in an off state, so no current flows between the drain electrode 10 and the source electrode 9, or only a very small current flows.

[0116] When the applied voltage turns on the channel, the JFET region becomes conductive, channel 5 becomes conductive, and the drain electrode and source electrode are connected. At this time, if a voltage is applied to the drain electrode 10, the device's channel is conductive and in the ON state, so current flows from the drain electrode 10 to the source electrode 9, and the device operates.

[0117] The threshold voltage of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of this invention can be modulated according to doping. When doping is controlled to form a self-pinch-off JFET region, when no voltage is applied to the upper electrode of the device's coupling capacitance, the carriers in channel 5 are depleted due to the built-in electric field caused by the doping itself, forming a depletion region. At this time, the device is a normally-off device. Only by applying a positive voltage to the JFET region can the depletion region be eliminated and an effective channel for conduction be formed. The pn junction formed of silicon carbide material has a large built-in potential due to the wide bandgap characteristics of silicon carbide, enabling the realization of a normally-off device structure.

[0118] If the JFET region does not form a self-pinch-off state, the device itself has a channel and is a normally-on device. According to the operating principle of JFETs, a corresponding voltage must be applied to the control region of the JFET, causing the channel to form a depletion region and the device to turn off.

[0119] The on-resistance Rsp of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor device of the present invention is mainly determined by the resistance R1 of the JFET region and the resistance R2 of the epitaxial layer 2. The voltage applied to the drain electrode 10 of the device is divided by two resistors connected in series, reducing the resistance of each region and optimizing the on-resistance Rsp of the entire device.

[0120] The advantages of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor device of this application will be described below.

[0121] The coupling capacitance upper electrode of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of this invention employs a capacitance coupling method and has the following advantages compared to conventional wide-bandgap metal oxide semiconductor field-effect transistors.

[0122] Figure 13 is a schematic diagram showing the current path when the vertical trench capacitively coupled gate-controlled junction field-effect transistor of the present invention is conducting. Figure 14 is a schematic diagram comparing the characteristics of the vertical trench capacitively coupled gate-controlled junction field-effect transistor of the present invention with those of a conventional VDMOS device.

[0123] As shown in Figure 13, the dashed line with an arrow represents the current path when the field-effect transistor is conducting. As shown in Figure 13, the current path when the vertical trench capacitively coupled gate-controlled junction field-effect transistor of the present invention is conducting is located within the device and away from the surface of the semiconductor material, and is therefore not affected by the low interface mobility of the material. The performance of the vertical trench capacitively coupled gate-controlled junction field-effect transistor of the present invention is mainly influenced by the thickness of the capacitive dielectric, and the work function requirements of the electrodes are low. For example, if the coupled capacitive upper electrode 8 is made of polysilicon material, either N-type polysilicon or P-type polysilicon can play the role of capacitive coupling, and capacitive dielectrics such as ordinary oxide materials or HighK dielectrics can be flexibly used and also play the role of capacitance coupling.

[0124] Figure 14 is a schematic diagram comparing the characteristics of the vertical trench capacitively coupled gate-controlled junction field-effect transistor of the present invention with those of a conventional VDMOS technology device. As shown in Figure 14, when the area of ​​the active region is the same, the vertical trench capacitively coupled gate-controlled junction field-effect transistor of the present invention clearly has superior on-resistance Rsp.

[0125] The vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of this invention operates using the principle of capacitive coupling. Therefore, the dielectric acts as an insulating layer. When a voltage is applied to the upper electrode of the device's coupling capacitance, the potential is coupled to gate 6. However, due to the physical floating of gate 6, current does not flow through the dielectric layer 7 to gate 6, which is the main control region of the device's JFET region. As shown in Figure 13, since the device's current conduction path does not pass through gate 6, a large current is not generated at gate 6, resulting in relatively high reliability. Under high drain voltage (breakdown condition) when the device is turned off, the epitaxial layer-gate-dielectric layer becomes the main breakdown voltage region. Due to the presence of the semiconductor pn junction structure between the epitaxial layer and gate, a fixed negative charge exists in the depletion region within the gate. The electric field line starts from the positive charge in the epitaxial layer and ends at the negative charge in the gate. Therefore, the high electric field is shielded at the junction interface of the semiconductor junction. The electric field strength within the dielectric layer is reduced by the gate's shielding effect, and the typical dielectric electric field strength is approximately 2 × 10⁻⁶. 5 The electric field strength is V / cm, which is an order of magnitude lower than the dielectric layer electric field strength of conventional silicon carbide VDMOS devices. Low dielectric layer electric field strength plays an important role in protecting the dielectric layer and improving its reliability.

[0126] Figure 15 is a schematic diagram showing the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention.

[0127] Figure 16 shows the potential distribution of the structure of the coupling capacitance upper electrode of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention. As shown in Figure 16, the vertical axis represents the potential distribution, and the horizontal axis represents the horizontal position.

[0128] In Figure 15, the horizontal dashed lines represent the horizontal direction. The portion of the horizontal dashed lines to the right of the vertical dashed lines corresponds to the portion to the right of coordinate 0 on the horizontal axis in Figure 16, and the portion of the horizontal dashed lines to the left of the vertical dashed lines corresponds to the portion to the left of coordinate 0 on the horizontal axis in Figure 16.

[0129] In the operating device of the present invention, the current saturates at a high gate voltage due to the capacitive coupling effect of the channel. The voltage division principle of the coupling capacitance upper electrode of the device of the present invention is as shown in Figure 5, and the dielectric layer capacitance C is composed of the coupling capacitance upper electrode 8, dielectric layer 7, and gate 6. ゲート The junction capacitance C is formed by the semiconductor depletion region formed in gate 6 and channel 5. 半導体 The two capacitances, and , are connected in series to divide the voltage and control the on / off state of the channel. When the external gate voltage is Vgs, the dielectric capacitance C ゲート The voltage distributed is Vgs·C 半導体 / (C ゲート +C 半導体 ) and the junction capacitance C in the semiconductor depletion region 半導体 The voltage distributed is Vgs·C ゲート / (C ゲート +C 半導体 ) is the dielectric layer capacitance C. ゲート This is determined as a fixed value by the material and thickness of the dielectric layer 7, and when Vgs increases from 0, C ゲート And the junction capacitance C in the depletion region formed by the self-formed electric field of the semiconductor. 半導体 The voltages are divided, and a portion of the voltage Vgs applied to the upper electrode 8 is coupled to the semiconductor junction, and at this time the junction capacitance C in the semiconductor depletion region 半導体 The percentage C of the voltage coupled to it ゲート / (C ゲート +C 半導体 ) becomes maximum. The gate voltage Vgs rises and the junction capacitance C in the semiconductor depletion region increases. 半導体 As the voltage coupled to it increases, the semiconductor junction capacitance C 半導体 The depletion region becomes narrower, and the junction capacitance C 半導体 The junction capacitance C in the semiconductor depletion region becomes larger. 半導体 The percentage C of the voltage coupled to it ゲート / (Cゲート +C 半導体 The junction capacitance C in the semiconductor depletion region gradually decreases. When the semiconductor depletion region narrows to a certain extent, the area in close contact with the semiconductor junction interface cannot be narrowed further, and the junction capacitance C in the semiconductor depletion region decreases. 半導体 The voltage rises to a relatively large value and remains thereafter, and there is no further increase. At this point, the voltage Vgs applied to the upper electrode 8 of the coupling capacitance and the potential coupled to the gate 6 become maximum, and the device saturates.

[0130] Figures 17-1, 17-2, 17-3, 17-4, 17-5, and 17-6 show the energy band distribution when different voltages are applied to the coupling capacitance upper electrode 10 of the vertical trench type capacitively coupled gate-controlled junction field-effect transistor of the present invention, with the vertical axis representing the potential distribution and the horizontal axis representing the horizontal position.

[0131] In Figure 15, the vertical dashed lines represent the vertical direction. The portion of the horizontal dashed lines to the right of the vertical dashed lines corresponds to the portion to the right of coordinate 0 on the horizontal axis in Figures 17-1, 17-2, 17-3, 17-4, 17-5, and 17-6. The portion of the horizontal dashed lines to the left of the vertical dashed lines corresponds to the portion to the left of coordinate 0 on the horizontal axis in Figures 17-1, 17-2, 17-3, 17-4, 17-5, and 17-6.

[0132] As shown in Figures 17-1, 17-2, 17-3, 17-4, 17-5, and 17-6, the energy band distribution in the gate 6, channel 5, and second-doped ohmic contact region 3 of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention shows the relative changes in the conduction band, valence band, and Fermi levels of electrons and holes in each region when the coupling capacitance upper electrode of the device is operating. As shown in Figure 17-1, when the voltage Vgs applied to the coupling capacitance upper electrode 8 is 0V, taking channel 5 in a self-depleted state as an example, the Fermi level of channel 5 is located at the center of the band gap, the device is in a self-depleted state, and the concentrations of both electrons and holes in channel 5 are very low. The Fermi levels of gate 6 and second-doped ohmic contact region 3 are located near the valence band, with an extremely high concentration of holes and an extremely low concentration of electrons. As the voltage Vgs applied to the upper electrode 8 of the coupling capacitance increases, the distance between the conduction band and the Fermi level of electrons in the gate 6 and channel 5 gradually decreases, causing a low concentration of electrons to appear in the gate 6, and the conduction band in channel 5 to be close to the Fermi level of electrons, resulting in a very high electron concentration in channel 5, which contributes to conductivity and can form a conductive channel. Also, the distance between the valence band and the Fermi level of holes in channel 5 gradually decreases, causing a low concentration of holes to appear in channel 5.

[0133] Figure 18-1 shows the carrier concentration distribution in each region when the device is operating, as the hole concentration in the gate 6, channel 5, and second-doped ohmic contact region 3 of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention is affected by the voltage applied to the coupling capacitance upper electrode 8.

[0134] Figure 18-2 shows the carrier concentration distribution in each region when the device is operating, as the electron concentration in the gate 6, channel 5, and second-doped ohmic contact region 3 of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention is affected by the voltage applied to the upper electrode 8 of the coupling capacitance.

[0135] As shown in Figures 18-1 and 18-2, the electron and hole concentrations in the gate 6, channel 5, and second-doped ohmic contact region 3 of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention are affected by the voltage applied to the coupling capacitance upper electrode 8, and show the carrier concentration distribution in each region when the device is operating. When the voltage Vgs applied to the coupling capacitance upper electrode 8 is 0V, the hole concentration in the gate 6 is extremely high and the electron concentration is extremely low. When the channel 5 is modulated into a self-depleted state by doping, both the electron and hole concentrations are extremely low. As the voltage Vgs applied to the coupling capacitance upper electrode 8 increases, both the capacitor coupled to the dielectric layer 7 and the voltage on the semiconductor junction capacitor formed by the gate 6 and channel 5 increase due to the capacitive coupling principle. When the voltage on the semiconductor junction formed by the gate 6 and channel 5 increases, the depletion region in the channel 5 narrows, and the depleted state becomes a non-depleted state, so the electron concentration in the channel 5 increases rapidly, and a conductive channel is formed. Furthermore, the built-in potential at the semiconductor junction formed by gate 6 and channel 5 decreases, allowing some electrons from channel 5 to enter gate 6. As a result, the electron concentration in gate 6 changes from extremely low to extremely low, while some holes from gate 6 enter channel 5, increasing the hole concentration at the semiconductor junction of gate 6 and channel 5.

[0136] Due to the transfer characteristics of the vertical trench-type capacitive-coupled gate-controlled junction field-effect transistor of the present invention, a voltage is applied to both the upper electrode and the drain electrode of the coupling capacitance. When the voltage of the upper electrode of the coupling capacitance is low, the off-current of the device is small. As the voltage of the upper electrode of the coupling capacitance increases, the current at the drain electrode increases. When the voltage of the upper electrode of the coupling capacitance increases significantly, the magnitude of the semiconductor junction capacitance is stably maintained, and the device saturates. Current SiC MOSFET devices still do not exhibit current saturation characteristics even at Vgs 20V. Furthermore, in the device of the present invention, the bus through which the current flows is separated from the surface of the dielectric, thereby improving the short-circuit resistance capability of the device.

[0137] The vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of this invention clearly offers high reliability, high robustness, and manufacturing advantages.

[0138] <Example 5> Figure 3-5 is a schematic diagram showing a fifth mounting configuration of the vertical trench type capacitively coupled gate-controlled junction field-effect transistor of the present invention. In the fifth mounting configuration of the vertical trench type capacitively coupled gate-controlled junction field-effect transistor of the present invention, the shapes of the trench, dielectric layer 7, and coupling capacitance upper electrode 8 differ from those of the first mounting configuration (i.e., Example 1).

[0139] As shown in Figure 3-5, the trench is a trench with a rectangular cross-section, and in this case, the dielectric layer 7 covers only the inner bottom of the gate 6 and does not cover the side walls of the gate 6. The coupling capacitance upper electrode 8 is formed only on the dielectric layer 7.

[0140] The dielectric layer 7 does not completely cover the side walls of the trench, but is formed only at the inner bottom of the trench, and the coupling capacitance upper electrode 8 is located above the dielectric layer. Because this structure is planar, it has the advantage of being easy to process and easy to fabricate.

[0141] The operating principle is that the dielectric layer 7 is located at the bottom of the trench, and the coupling capacitance upper electrode 8 is located above the dielectric layer 7. The coupling capacitance upper electrode 8 controls the gate 6 via the dielectric layer, and further controls the on / off state of the channel 5.

[0142] Figure 3-6 is a schematic diagram showing the sixth mounting configuration of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention. In the sixth mounting configuration of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention, the shapes of the trench, dielectric layer 7, and coupling capacitance upper electrode 8 differ from those of the second mounting configuration (i.e., Example 2).

[0143] As shown in Figure 3-6, the trench is a trench with a rectangular cross-section, and in this case, the dielectric layer 7 covers only the inner bottom of the gate 6 and does not cover the side walls of the gate 6. The coupling capacitance upper electrode 8 is formed only on the dielectric layer 7.

[0144] Figure 3-7 is a schematic diagram showing the seventh mounting configuration of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention. In the seventh mounting configuration of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention, the shapes of the trench, dielectric layer 7, and coupling capacitance upper electrode 8 differ from those of the third mounting configuration.

[0145] As shown in Figure 3-7, the trench is a trench with a rectangular cross-section, and in this case, the dielectric layer 7 covers only the inner bottom of the gate 6 and does not cover the side walls of the gate 6. The coupling capacitance upper electrode 8 is formed only on the dielectric layer 7.

[0146] Figure 3-8 is a schematic diagram showing the eighth mounting configuration of the vertical trench type capacitively coupled gate-controlled junction field-effect transistor of the present invention. In the eighth mounting configuration of the vertical trench type capacitively coupled gate-controlled junction field-effect transistor of the present invention, the shapes of the trench, dielectric layer 7, and coupling capacitance upper electrode 8 differ from those of the fourth mounting configuration (i.e., Example 4).

[0147] As shown in Figure 3-8, the trench is a trench with a rectangular cross-section, and in this case, the dielectric layer 7 covers only the inner bottom of the gate 6 and does not cover the side walls of the gate 6. The coupling capacitance upper electrode 8 is formed only on the dielectric layer 7.

[0148] Figure 3-9 is a schematic diagram showing the ninth mounting configuration of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention. Figure 3-9 shows the metal silicide layer 11. As shown in Figure 3-9, the metal silicide layer 11 is formed between the gate 6 and the dielectric layer 7.

[0149] A metal silicide layer (abbreviated as Silicide layer) may be added below the dielectric layer of the upper electrode of the coupling capacitance; that is, the metal silicide layer may be interposed between the dielectric layer 7 and the gate 6. In this way, the metal silicide layer below the dielectric layer 7 is a metal layer, and the distribution of the electric field within the metal layer is uniform, thereby optimizing the electric field on the surface of the gate 6 and improving the reliability of the device.

[0150] Figure 3-10 is a schematic diagram showing a tenth mounting configuration of the vertical trench-type capacitively coupled gate-controlled junction field-effect transistor of the present invention. Figure 3-10 shows the metal silicide layer 11. As shown in Figure 3-10, the metal silicide layer 11 is formed between the gate 6 and the dielectric layer 7.

[0151] <Example 6> The method for manufacturing a vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to the embodiment of the present application is as follows: The steps include forming a first-doped epitaxial layer 2 on a first-doped substrate 1, The step of forming a plurality of repeating units includes, The steps include forming two first doping-type source regions 4 located within the epitaxial layer and spaced apart in the lateral direction, The steps include forming a trench that is formed downward from the upper surface of the epitaxial layer and located between two first doping-type source regions 4, The steps include forming a second doping-type gate 6 located on the inner wall and bottom of the trench, The steps include forming a dielectric layer 7 on at least the inner bottom of the gate 6, The process includes the step of forming a coupled capacitance upper electrode 8 on the dielectric layer 7.

[0152] In implementation, the step of forming a repeating unit is: The process further includes the step of forming two first doping-type channels 5, each located beneath one of the two source regions 4.

[0153] In implementation, the step of forming a repeating unit is: The steps include forming two first doping-type channels 5 located below each of the two source regions 4, The further step includes forming two second doping-type ohmic contact regions 3 located outside each of the two source regions 4.

[0154] In the description of this application and its embodiments, the orientations or positional relationships indicated by terms such as "peak," "base," and "height" are based on the orientations or positional relationships shown in the drawings and are merely for the purpose of facilitating and simplifying the description of this application. It should be understood that these terms do not indicate or imply that the referred devices or elements have a specific orientation, or must be constructed and operate in a specific orientation. Therefore, they should not be understood as limiting this application.

[0155] In this application and its embodiments, unless otherwise explicitly stated and limited, terms such as “to provide,” “to attach,” “to connect,” “to link,” and “to fix” should be understood broadly, and may, for example, be a fixed connection, a removable connection, or an integral connection; they may be a mechanical connection, an electrical connection, or a communication; they may be a direct connection, an indirect connection via an intermediate medium, an internal communication between two elements, or an interaction relationship between two elements. A person skilled in the art will be able to understand the specific meaning of the terms described herein depending on the specific circumstances.

[0156] In the present application and its embodiments, unless otherwise explicitly stated and limited, the presence of a first feature "above" or "below" a second feature may mean that the first and second features are in direct contact or indirectly in contact via an intermediate medium. Furthermore, the presence of a first feature "above," "above," and "on the top surface" of a second feature may mean that the first feature is directly above or diagonally above the second feature, or simply that the horizontal height of the first feature is greater than that of the second feature. The presence of a first feature "below," "below," and "on the bottom surface" of a second feature may mean that the first feature is directly below or diagonally below the second feature, or simply that the horizontal height of the first feature is lower than that of the second feature.

[0157] The above disclosure provides many different embodiments or examples for implementing different structures of the present application. For the sake of brevity of the disclosure, the components and settings of specific examples are described above. Of course, these are merely examples and are not intended to limit the present application. Furthermore, the present application may repeat reference numbers and / or reference letters in different examples for the purposes of simplification and clarity and are not in themselves to indicate relationships between the various embodiments and / or arrangements discussed. Furthermore, while the present application describes examples of various specific processes and materials, those skilled in the art may anticipate the application of other processes and / or the use of other materials.

[0158] While preferred embodiments of the present application have been described, those skilled in the art, knowing the basic inventive concept, may make additional changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as encompassing the preferred embodiments and all changes and modifications that should fall within the scope of the present application.

[0159] Clearly, a person skilled in the art can make various modifications and variations to this Application without departing from the spirit and scope of this Application. Thus, if such modifications and variations of this Application fall within the scope of the claims of this Application and their equivalents in the art, this Application also intends to include such modifications and variations. [Explanation of Symbols]

[0160] 1 circuit board 2. Epitaxial layer 3. Second doping type ohmic contact region 4. Source Area 5 channels Gate 6 7. Dielectric layer 8 Coupling capacitance upper electrode 9 Source electrodes 10 Drain electrode 11. Metallic silicide layer.

Claims

1. The invention comprises a first doping type substrate (1) and an epitaxial layer (2), and a plurality of repeating units, wherein the epitaxial layer is located on the substrate, the substrate functions as a drain region, and the repeating units are (a) Two first doping-type source regions (4) formed within the epitaxial layer and spaced apart in the lateral direction, (b) A trench formed from the upper surface downward of the epitaxial layer and located between the two first doping-type source regions (4), A second doping-type gate (6) is formed along the inner wall and bottom of the trench and is in a floating state not directly connected to the external electrode, (c) A dielectric layer (7) formed only on the inner bottom of the gate (6), A coupling capacitance upper electrode (8) that does not extend to the trench sidewall formed on the dielectric layer (7), (d) A metal silicide layer (11) formed only directly beneath the dielectric layer (7) between the dielectric layer (7) and the gate (6), The gate (6) is indirectly controlled by the coupling capacitance upper electrode (8) across the dielectric layer (7), The substrate (1), the epitaxial layer (2), and the channel (5) are positioned spaced apart from the surface of the semiconductor material and the surface of the trench. A vertical trench-type capacitively coupled gate-controlled junction field-effect transistor characterized by the following features.

2. The aforementioned vertical trench-type capacitively coupled gate-controlled junction field-effect transistor is, Two first doping-type channels (5) located below each of the two source regions (4), The system further comprises two second doping-type ohmic contact regions (3) located outside the two source regions (4) and channels (5), respectively. The second doped gate (6), the first doped channel (5), and the second doped ohmic contact region (3) form a JFET region, and the gate (6) of the JFET region is indirectly controlled by the coupling capacitance upper electrode (8) across the dielectric layer (7). The gate (6), channel (5), source region (4), and second doping type ohmic contact region (3) are formed within the epitaxial layer (2). The vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to feature 1.

3. The aforementioned vertical trench-type capacitively coupled gate-controlled junction field-effect transistor is, A drain electrode (10) provided on the lower surface of the substrate, The device further comprises two source electrodes (9) formed on each of the two source regions (4), The first doped substrate (1), the first doped epitaxial layer (2), and the two first doped source regions (4) form an internal conductive path from the drain electrode to the two source electrodes, located within the substrate (1) and the epitaxial layer (2). The vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to feature 1.

4. The aforementioned vertical trench-type capacitively coupled gate-controlled junction field-effect transistor is, A drain electrode (10) provided on the lower surface of the substrate, The device further comprises two source electrodes (9) formed on each of the two source regions (4), The first doped substrate (1), the first doped epitaxial layer (2), the two first doped channels (5), and the two first doped source regions (4) form an internal conductive path from the drain electrode to the two source electrodes, located within the substrate (1) and the epitaxial layer (2). A vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to claim 1 or 2.

5. The trench is a trench with a rectangular cross-section, and in this case, the dielectric layer (7) covers the inner bottom of the gate (6). The coupling capacitance upper electrode (8) is formed on the dielectric layer (7), A vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to claim 1 or 2.

6. The substrate (1) is a silicon carbide substrate, a silicon substrate, a diamond substrate, or a gallium oxide substrate. The dielectric layer (7) is a dielectric layer made of a high dielectric constant material. The coupling capacitance upper electrode (8) is a polysilicon electrode or a metal electrode. The vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to feature 1.

7. The doping concentration of the gate (6) is 1 × 10 １６ cm －３ That's all. The vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to feature 1.

8. The doping concentration of the channel (5) is higher than the doping concentrations of the substrate and the epitaxial layer. A vertical trench-type capacitively coupled gate-controlled junction field-effect transistor according to claim 1 or 2.

9. The steps include forming a first doping type epitaxial layer (2) on a first doping type substrate (1), The step of forming a plurality of repeating units includes, (i) Forming two first doping-type source regions (4) located within the epitaxial layer and spaced apart laterally, and forming first doping-type channels (5) below each source region (4) with a doping concentration higher than that of the epitaxial layer (2), (ii) Form a trench located between the two first doping type source regions (4), The steps include forming a second doping-type gate (6) located on the inner wall and bottom of the trench, (iii) The step of forming a metal silicide layer (11) only on the inner bottom of the gate (6), and then depositing a dielectric layer (7) on the metal silicide layer (11), (iv) The step of forming a coupling capacitance upper electrode (8) on the dielectric layer (7) that does not extend to the trench sidewall, (v) The step of forming a second doping-type ohmic contact region (3) outside each of the two source regions (4) and channels (5), The gate (6) is indirectly controlled by the coupling capacitance upper electrode (8) via the dielectric layer (7). A method for manufacturing a vertical trench-type capacitively coupled gate-controlled junction field-effect transistor, characterized by the following:

10. The trench has a rectangular cross-section, and the dielectric layer (7) is selectively formed only on the inner bottom of the gate (6). A method for manufacturing a vertical trench-type capacitively coupled gate-controlled junction field-effect transistor as described in feature 9.

11. The dielectric layer (7) is made of a high dielectric constant material, and the coupling capacitance upper electrode (8) is formed of polysilicon or metal. A method for manufacturing a vertical trench-type capacitively coupled gate-controlled junction field-effect transistor as described in feature 9.

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