Method for manufacturing a trench capacitor structure and trench capacitor

Abstract

To provide a concept for devices having dielectric, e.g., trench capacitors or RC snubbers or for dielectric layer structures for increasing a breakdown voltage with constant or increased integration density (capacitance).SOLUTION: A method for producing a trench capacitor structure includes the steps of: preparing a silicon substrate with a trench structure, the trench structure comprising a plurality of recesses in a main surface of the silicon substrate; forming a first silicon dioxide layer at least in the recesses of the silicon substrate; depositing a first silicon nitride layer on the first silicon dioxide layer; depositing a second silicon dioxide layer on the first silicon nitride layer by depositing a polycrystalline silicon layer and oxidizing the polycrystalline silicon layer; and depositing a second silicon nitride layer on the second silicon dioxide layer.SELECTED DRAWING: Figure 1a

Description

[Technical Field] 【0001】 Embodiments of the present invention relate to a method for manufacturing a trench capacitor structure and a trench capacitor, or a method for manufacturing a dielectric layer stack and a trench capacitor having a dielectric layer stack. [Background technology] 【0002】 The dielectric layer stack is preferably a dielectric (ON) for, for example, a Si-RC snubber device. x The stack is (x≧2), the silicon dioxide layer is denoted by O, and the silicon nitride layer is denoted by N. Different concepts are known for reducing substrate bending when manufacturing integrated capacitors. German Patent No. 102019204503 discloses the introduction of a stress-free nitride layer to increase the peak voltage intensity to 1200V and reduce disk bending, for example. However, with such a design, it is virtually impossible to further increase the voltage intensity without compromising integration density (e.g., by a thicker dielectric layer) or significantly increasing wafer bending (e.g., a thicker dielectric layer with a simultaneous increase in surface area due to deeper hole structuring). Considering this, there is a need for a device or dielectric layer structure, such as a trench capacitor or RC snubber, that has dielectric properties, or that takes into account the bending of the disk due to thermomechanical stress during and after deposition of the dielectric layer, in order to increase the dielectric breakdown voltage at a constant or increased integration density (capacitance). This objective is addressed by the subject matter of the independent claim. Further developments of the invention are defined in the dependent claims. [Overview of the project] 【0003】 According to one aspect of the present invention, the inventors recognized that a challenge in manufacturing trench capacitor structures is the difficulty in increasing voltage intensity without impairing integration density and without significantly increasing the bending of the silicon substrate. According to one aspect of the present invention, this difficulty is overcome by providing a dielectric layer stack of at least two silicon dioxide layers and at least two silicon nitride layers within the trench structure of the silicon substrate, with the silicon dioxide and silicon nitride layers arranged alternately in the upper and lower halves, thereby achieving a higher capacitance density in trench capacitors compared to planar capacitors. However, at the same time, it must be considered that manufacturing mechanisms for planar capacitors cannot be simply applied to trench capacitors, as the coating of the trench structure, in particular, must withstand different challenges than coating a flat surface, for example, in relation to uniform layer thickness and substrate bending. In this regard, the inventors recognized that by alternately forming silicon dioxide and silicon nitride layers within the trench structure, it is possible not only to control the bending of the substrate during the formation of the layer stack, but also to increase the pore depth and, therefore, the surface expansion of the capacitor. In particular, it was found that the layer stack formed within the trench structure must comprise at least two silicon dioxide layers and at least two silicon nitride layers in order to keep substrate bending as low as possible with a large hole depth. Furthermore, in relation to the trench structure, it was observed that the silicon dioxide layers can be formed on the silicon nitride layers particularly advantageously when the polycrystalline silicon layers are deposited and oxidized, i.e., with high quality, such as a uniform structure, uniform layer thickness, and / or a low defect method. This makes it possible to obtain a trench capacitor structure with a dielectric layer stack that has high dielectric breakdown strength. 【0004】 Therefore, one embodiment relates to a method for manufacturing a trench capacitor structure. The method comprises preparing a silicon substrate with a trench structure, the trench structure having a plurality of recesses on the main surface of the silicon substrate. Furthermore, the method comprises forming a first silicon dioxide layer in the recesses of the silicon substrate, depositing a first silicon nitride layer on the first silicon dioxide layer, depositing a second silicon dioxide layer on the first silicon nitride layer by depositing a polycrystalline silicon layer and oxidizing the polycrystalline silicon layer, and depositing a second silicon nitride layer on the second silicon dioxide layer. The first silicon dioxide layer is formed in at least the recesses of the silicon substrate. Optionally, the first silicon dioxide layer may be further formed on at least a portion of the main surface of the silicon substrate or on the entire main surface of the silicon substrate. The first silicon dioxide layer may be further formed, for example, on portions of the main surface of the silicon substrate connecting the recesses. Therefore, at least in the recesses of the silicon substrate, optionally further on the main surface of the silicon substrate, (ON) x A stack (x≧2) is formed, with the silicon dioxide layer represented by O and the silicon nitride layer represented by N. The index x indicates how many ON layer pairs are arranged on top of each other. 【0005】 According to one embodiment, an oxynitride layer is formed between the first silicon nitride layer and the second silicon dioxide layer during the oxidation of the polycrystalline silicon layer. This results in a clean interface between the silicon nitride layer and the silicon dioxide layer. The formation of the oxynitride layer reduces potential defects between the silicon nitride layer and the silicon dioxide layer, improving the electrical dielectric breakdown strength. 【0006】 According to one embodiment, during the oxidation of the polycrystalline silicon layer, the polycrystalline silicon layer is completely converted into a second silicon dioxide layer. The inventors have found that even if only a thin polycrystalline silicon layer remains, unpredictable electrical processes can occur in the trench capacitor structure, resulting in only low dielectric breakdown strength being achievable. This is based on the knowledge that the polycrystalline silicon layer is a semiconductor layer. However, the stack of alternately arranged silicon dioxide and silicon nitride layers functions as a dielectric in the trench capacitor structure, thus reducing the dielectric breakdown strength of the layer stack, even with a thin semiconductor layer between layers accompanied by insulating material. 【0007】 Optionally, after the polycrystalline silicon layer has been completely converted to a second silicon dioxide layer, oxidation is continued to partially oxidize the first silicon nitride layer to form an oxynitride layer between the first silicon nitride layer and the second silicon dioxide layer. As a result, a clean interface between the silicon nitride layer and the silicon dioxide layer and high electrical breakdown strength are achieved. The oxidation is continued for a period of, for example, at least 5 minutes, 20 minutes, or 1 hour. The period is, for example, in the range of 5 minutes to 5 hours, 20 minutes to 5 hours, or 1 hour to 5 hours, preferably in the range of 5 minutes to 1 hour. In a preferred embodiment, the oxidation is continued for about 20 minutes or about 1 hour. 【0008】 According to one embodiment, the polycrystalline silicon layer is not doped. This is based on the finding that, as a result, a high-quality silicon dioxide layer can be formed within the trench capacitor structure. In particular, the inventors have found that, as a result, a very pure silicon dioxide layer with low leakage current can be achieved. This improves the electrical properties of the trench capacitor structure. 【0009】 According to one embodiment, a polycrystalline silicon layer is deposited on a first silicon nitride layer by low-pressure deposition, i.e., using the LPCVD method. It is recognized that while direct deposition of a silicon oxide layer on a silicon nitride layer by the LPCVD method results in a defect-ridden interface and low electrical breakdown strength, LPCVD deposition of polycrystalline silicon and subsequent oxidation of polycrystalline silicon results in a clean interface and high electrical breakdown strength. 【0010】 According to one embodiment, the first silicon dioxide layer, the first silicon nitride layer, the second silicon dioxide layer and / or the second silicon nitride layer are deposited with respective layer thicknesses in the range of 100 nm to 1000 nm or 330 nm to 530 nm. The individual layers may have different layer thicknesses. It has been further found that a series of several thin silicon dioxide and silicon nitride layers achieve lower substrate bending and higher dielectric breakdown strength than a series of less thick silicon dioxide and silicon nitride layers. 【0011】 According to one embodiment, a first silicon dioxide layer is formed in a recess of a silicon substrate by thermal growth, a first silicon nitride layer is deposited on the first silicon dioxide layer by low-pressure deposition, i.e., LPCVD, and a second silicon nitride layer is deposited on the second silicon dioxide layer by low-pressure deposition, i.e., LPCVD. 【0012】 According to one embodiment, a silicon nitride layer forms a layer pair with a silicon dioxide layer, and the silicon nitride layer is positioned, for example, on the silicon dioxide layer as viewed from the silicon substrate in the stacking direction. In other words, the silicon dioxide layer and the silicon nitride layer on the silicon dioxide layer can be called a layer pair. A layer pair may also be referred to herein as a layer stack unit. A first silicon dioxide layer and a first silicon nitride layer form, for example, a first layer pair, and a second silicon dioxide layer and a second silicon nitride layer form, for example, a second layer pair. At least one further layer pair including a silicon dioxide layer and a silicon nitride layer can be deposited, i.e., on the second layer pair as viewed from the silicon substrate in the stacking direction. In this case, for example, the silicon dioxide layer of each further layer pair is deposited on the silicon nitride layer of the preceding layer pair. The deposition of layer pairs including silicon dioxide layers and silicon nitride layers is repeated several times. Therefore, at least within the recesses of the silicon substrate, optionally further on the main surface of the silicon substrate, (ON) x A stack is formed (x≧3), where the silicon dioxide layer is denoted by O and the silicon nitride layer is denoted by N. At least one further pair of layers is deposited, for example, on the second pair of layers, such that a layer structure is formed in which the silicon dioxide layers and silicon nitride layers are arranged alternately. Starting from the second pair of layers, the silicon dioxide layer of each pair of layers is deposited by depositing a polycrystalline silicon layer and oxidizing the polycrystalline silicon layer. The inventors have found that a thicker overall dielectric stack layer, i.e., even with more silicon dioxide and silicon nitride layers alternating vertically, can be obtained or even increased in density. It has been found that by stacking the silicon dioxide and silicon nitride layers alternately vertically, substrate bending can be kept low, and at the same time, layer stacks with large overall thicknesses, for example, of at least 1600 nm, 2000 nm, or 3000 nm can be realized within the recesses of a silicon substrate. As a result, layer stacks with high dielectric breakdown strengths of, for example, at least 1200V, 1400V, or 1500V can be achieved. Furthermore, it is particularly advantageous if an oxynitride layer is formed between each individual layer pair. 【0013】 According to one embodiment, the polycrystalline silicon layer described herein is oxidized by dry chemical oxidation or wet chemical oxidation. In other words, the silicon dioxide layer described herein is thermally grown. Dry chemical or wet chemical oxidation may also be referred to herein as dry chemical or wet chemical re-oxidation or up-oxidation. Wet chemical oxidation may also be referred to herein as wet chemical oxidation. The inventors have found that the formation of a silicon dioxide layer by dry chemical or wet chemical oxidation of polycrystalline silicon results in a cleaner interface and higher dielectric breakdown strength than when the silicon dioxide layer is directly deposited by LPCVD (low-pressure chemical vapor deposition) or PECVD (plasma chemical vapor deposition). As a result, a high-quality silicon dioxide layer is produced, improving the electrical properties of the trench capacitor structure. Wet chemical oxidation has the advantage of being able to form the silicon dioxide layer more quickly than dry chemical oxidation, and dry chemical oxidation has the advantage of being able to achieve higher dielectric breakdown strength of the layer stack formed in recesses of the silicon substrate than wet chemical oxidation. 【0014】 According to one embodiment, RC snubber elements are formed or manufactured by the method described herein. 【0015】 Further embodiments relate to a trench capacitor comprising a dielectric layer structure comprising a first silicon dioxide layer, a first silicon nitride layer, a second silicon dioxide layer, and a second silicon nitride layer. The trench capacitor includes, for example, a silicon substrate with a trench structure having a plurality of recesses on the main surface of the silicon substrate. The dielectric layer structure is arranged, for example, in the recesses of the silicon substrate. The first silicon dioxide layer, the first silicon nitride layer, the second silicon dioxide layer, and the second silicon nitride layer are arranged in this order. The layers can be directly adjacent to each other. Optionally, an oxynitride layer may be placed between the first silicon nitride layer and the second silicon dioxide layer, and the oxynitride layer may be considered as part of the first silicon nitride layer. The second silicon dioxide layer may be a polycrystalline silicon oxide layer. 【0016】 The trench capacitor is based on the same considerations as the method described above. The trench capacitor can be complemented with all the features and functions described also with respect to this method. Also, at least a part of the trench capacitor can be manufactured by the method described in this specification. 【Brief Description of the Drawings】 【0017】 Hereinafter, embodiments according to the present invention will be described in more detail with reference to the accompanying drawings. [Figure 1a] It is a block diagram of an embodiment of the present invention of a method for manufacturing a trench capacitor structure. [Figure 1b] It is a schematic diagram of method steps of an embodiment of the present invention of a method for manufacturing a trench capacitor structure. [Figure 2] It is a schematic diagram of method steps of an embodiment of the present invention of a method for manufacturing a dielectric layer structure with an oxynitride layer. [Figure 3] It is a schematic diagram of an embodiment of the present invention of a trench capacitor structure with a plurality of ON layer pairs. [Figure 4] It is a schematic diagram of an embodiment of the present invention of a trench capacitor structure with a plurality of ON layer pairs each further comprising an oxynitride layer. [Figure 5] It is a figure with the characteristic curves of an embodiment of the present invention of a snubber device in which the silicon dioxide layer is deposited by dry chemical oxidation and the characteristic curves of a snubber device in which the silicon dioxide layer is deposited by LPCVD deposition. [Figure 6] It is a figure with the characteristic curves of an embodiment of the present invention of a snubber device in which the silicon dioxide layer is deposited by dry chemical oxidation and the characteristic curves of an embodiment of the present invention of a snubber device in which the silicon dioxide layer is deposited by wet chemical oxidation. [Figure 7] It is a figure with the characteristic curves of an embodiment of the present invention of a snubber device in which the silicon dioxide layer is deposited by dry chemical oxidation and the characteristic curves of a snubber device having a stress-free nitride layer. 【Modes for Carrying Out the Invention】 【0018】 Detailed Description of the Embodiment Related to the Drawings Before explaining the embodiments of the present invention in more detail below with reference to the drawings, note that the same, functionally identical, or equal elements, objects, and / or structures are assigned the same or similar reference numbers in different drawings, and thus, the descriptions of these elements shown in different embodiments are interchangeable or compatible. To facilitate the description of various embodiments, some of the figures include a Cartesian coordinate system x, y, z, where the x-y plane corresponds to the first main surface region of the substrate (= reference plane = x-y plane), that is, is parallel to the first main surface region, and the direction perpendicular upward with respect to the reference plane (x-y plane) corresponds to the "+z" direction, and the direction perpendicular downward with respect to the reference plane (x-y plane) corresponds to the "-z" direction. In the following description, the term "lateral direction" means a direction parallel to the x direction and / or the y direction, that is, a direction parallel to the x-y plane, and the term "vertical" means a direction parallel to the z direction. 【0019】 FIG. 1a and FIG. 1b show a trench capacitor structure 200 or a method 100 for manufacturing a trench capacitor. Method 100 includes a step 110 of preparing a silicon (Si) substrate 210 with a trench structure. The trench structure includes a plurality of recesses 212 on the main surface 214 of the silicon substrate 210. The silicon substrate 210 can be, for example, a silicon wafer. In method 100, for example, a pre-manufactured silicon substrate 210 with an already integrated trench structure can be used. Alternatively, step 110 of preparing a silicon substrate 210 with a trench structure can include forming a trench structure on the main surface 214 of the silicon substrate 210. The trench structure is formed, for example, by patterning the silicon substrate. Forming a trench structure on the main surface 214 of the silicon substrate 210 can include one or more lithography steps and one or more etching steps. 【0020】 A further step of Method 100 relates to forming a first silicon dioxide (Si) layer 2201 at least within recesses 212 of the silicon substrate 210 (step 120). In Figure 1b, the first silicon dioxide layer 2201 is also formed, exemplary, on the main surface 214 of the silicon substrate 210. The first silicon dioxide layer 2201 is formed, exemplary, by thermal growth or thermal oxidation. For this purpose, for example, the silicon substrate 210 is oxidized dry chemically or wet chemically, in which case dry chemical oxidation is preferred. For example, the surfaces within a plurality of recesses 212, and optionally the main surface 214 or a portion of the main surface 214, are oxidized to form the first silicon dioxide layer 2201. The first silicon dioxide layer 2201 includes, for example, an SiO2 material or a thermal oxide. The thickness of the first silicon dioxide layer 2201 is, for example, in the range of 100 nm to 1000 nm, preferably in the range of 100 nm to 450 nm, for example, 330 nm. 【0021】 The first silicon nitride layer 2301 is deposited on the first silicon dioxide layer 2201 (step 130). The first silicon nitride layer 2301 is deposited, for example, by low-pressure deposition, i.e., using the LPCVD method. The first silicon nitride layer 2301 contains, for example, Si3N4 material. The thickness of the first silicon nitride layer 2301 is, for example, in the range of 100 nm to 1000 nm, preferably in the range of 100 nm to 550 nm, for example, 460 nm. A second silicon dioxide layer 2202 is deposited on the first silicon nitride layer 2301 (step 140). Here, a polycrystalline silicon layer 222, i.e., polysilicon, is deposited on the first silicon nitride layer 2301 (step 142) and oxidized (step 144). The polycrystalline silicon layer 222 is, for example, not doped. The polycrystalline silicon layer 222 is deposited, for example, by low-pressure deposition, i.e., using the LPCVD method. The oxidation 144 of the polycrystalline silicon layer 222 is carried out, for example, by dry chemical or wet chemical oxidation, in which case dry chemical oxidation is preferred. The thickness of the second silicon dioxide layer 2202 is, for example, in the range of 100 nm to 1000 nm, preferably in the range of 100 nm to 450 nm, for example, 330 nm. 【0022】 Method 100 further includes step 150 of depositing a second silicon nitride layer 2302 on a second silicon dioxide layer 2202. The second silicon nitride layer 2302 is deposited, for example, by low-pressure deposition, i.e., using the LPCVD method. The second silicon nitride layer 2302 comprises, for example, a Si3N4 material. The thickness of the second silicon nitride layer 2302 is, for example, in the range of 100 nm to 1000 nm, preferably in the range of 100 nm to 550 nm, for example, 530 nm. 【0023】 Therefore, referring to the trench capacitor structure 200, a dielectric layer structure 240 is formed or provided in the trench capacitor. The dielectric layer structure 240 comprises a first silicon dioxide layer 2201, a first silicon nitride layer 2301, a second silicon dioxide layer 2202, and a second silicon nitride layer 2302. Optionally, the dielectric layer structure 240 may include further silicon dioxide and silicon nitride layers, for example, see Figures 3 and 4. The dielectric layer structure 240 is disposed within at least a plurality of recesses 212, for example, on the surface of a plurality of recesses 212. Optionally, the dielectric layer structure 240 is further disposed on the main surface 214 of the silicon substrate 210 or on a portion of the main surface 214 of the silicon substrate 210. 【0024】 The first silicon dioxide layer 2201, the first silicon nitride layer 2301, the second silicon dioxide layer 2202, and the second silicon nitride layer 2302 are arranged adjacent to each other in this order, for example. The dielectric layer structure 240 can also be considered as a layer stack having dielectric layers, for which refer to layers 2201, 2202, 2301, and 2302. The first silicon dioxide layer 2201 is, for example, placed directly on the substrate 210 of the trench capacitor, and the first silicon nitride layer 2301, the second silicon dioxide layer 2202, and the second silicon nitride layer 2302 are arranged on the first silicon dioxide layer 2201 in this order, for example. The order of the dielectric layers of the dielectric layer structure 240 is shown, for example, in the stacking direction from the silicon substrate 210. Optionally, method 100 may include further steps, such as those described in relation to Figure 2. Similarly, the trench capacitor structure 200 may include further layers, such as those described in relation to Figure 2. The first silicon nitride layer 2301 may include, for example, an oxynitride layer 232, as described in relation to Figure 2. The oxynitride layer 232 of the first silicon nitride layer 2301 may be located, for example, at the interface between the first silicon nitride layer 2301 and the second silicon dioxide layer 2202. 【0025】 Figure 2 illustrates Method 100 with respect to a cross-section of a trench capacitor structure 200 formed by the method described above. In other words, one of the multiple recesses of the trench structure in the silicon substrate 210, recess 212, and the layer deposited therein are shown in schematic detail. That is, Figure 2 shows the method steps in detail with respect to one of the multiple recesses of the trench structure. Even though Figure 2 shows the method steps with respect to only one of the multiple recesses, recess 212, it is clear that the method steps can also be applied to the remaining recesses of the multiple recesses. 【0026】 Method 100 in Figure 2, similar to Method 100 in Figures 1a and 1b, includes the steps of: preparing a silicon substrate 210 (step 110); forming a first silicon dioxide layer 2201 in a recess 212 of the silicon substrate 210 (step 120); depositing a first silicon nitride layer 2301 on the first silicon dioxide layer 2201 (step 130); depositing a second silicon dioxide layer 2202 on the first silicon nitride layer 2301 (step 140); and depositing a second silicon nitride layer 2302 on the second silicon dioxide layer 2202 (step 150). 【0027】 As described in relation to Figures 1a and 1b, step 140, which involves depositing a second silicon dioxide layer 2202 on a first silicon nitride layer 2301, includes step 142, which involves depositing a polycrystalline silicon layer 222, and step 144, which involves oxidizing the polycrystalline silicon layer 222. The oxidation step 144 can be carried out, for example, by dry chemical or wet chemical processes. During step 144, which involves oxidizing the polycrystalline silicon layer 222, an oxynitride layer 232 is optionally formed between the first silicon nitride layer 2301 and the second silicon dioxide layer 2202, or in the first silicon nitride layer 2301 at the interface between the first silicon nitride layer 2301 and the second silicon dioxide layer 2202. The polycrystalline silicon layer 222 is, for example, completely converted into a second silicon dioxide layer 2202, i.e., completely oxidized, and optionally, the oxidation step 144 is continued to partially oxidize the first silicon nitride layer 2301, either within the first silicon nitride layer 2301 or at the interface between the first silicon nitride layer 2301 and the second silicon dioxide layer 2202, in order to form an oxynitride layer 232. The nitride surface of the first silicon nitride layer 2301 is oxidized to a depth of several nanometers by continuing the oxidation step 144 for longer than necessary, for example, to consume the polycrystalline silicon. This step is optional and is intended in particular to optimize the interface between the oxide and the nitride / to make the interface between the oxide and the nitride less defective. The first silicon nitride layer 2301 functions, for example, as an oxidation stop. The oxidation period in oxidation step 144 is, for example, within the range of 5 to 72 hours, 5 to 48 hours, or 5 to 32 hours, for example, 9, 75 hours, or 10 hours. Oxidation step 144 is carried out for at least 5 hours, 9 hours, or 24 hours, depending on the thickness of the second silicon dioxide layer 2202 to be formed, so that the polycrystalline silicon layer 222 is completely converted into the second silicon dioxide layer 2202 and the oxynitride layer 232 is formed. The thicker the second silicon dioxide layer 2202 to be formed or the polycrystalline silicon layer 222 to be oxidized, the longer oxidation step 144 should be performed. 【0028】 The oxynitride layer 232 contains, for example, a thermal oxide. The thickness of the oxynitride layer 232 is, for example, in the range of 1 nm to 12 nm or 1 nm to 11 nm. The maximum thickness of the oxynitride layer 232 is preferably 11 nm. The first silicon dioxide layer 2201, the first silicon nitride layer 2301, the oxynitride layer 232, the second silicon dioxide layer 2202, and the second silicon nitride layer 2302 form, for example, a dielectric layer structure 240. 【0029】 Optionally, a layer 250 with doped polysilicon material can be deposited on the second silicon nitride layer 2302 (step 160). The layer 250 with doped polysilicon material is deposited such that, for example, the doped polysilicon material fills at least the recesses 212 where the silicon dioxide and silicon nitride layers are located (step 160). The layer 250 with doped polysilicon material completes, for example, a number of recesses 212. The layer 250 with doped polysilicon material can be further deposited on the surface of the second silicon nitride layer 2302 facing away from the main surface of the silicon substrate 210 (opposite the main surface of the silicon substrate 210) (step 160). The layer 250 with the doped polysilicon material is deposited such that, for example, the surface parallel to the main surface 214 of the silicon substrate 210 faces away from the dielectric layer structure 240 (opposite side from the dielectric layer structure 240) (step 160). The layer 250 with the doped polysilicon material is deposited, for example, by low-pressure deposition, i.e., using the LPCVD method. The doped polysilicon material is, for example, an in situ-doped polycrystalline silicon material. The layer 250 with the doped polysilicon material forms, for example, an electrode of an RC snubber element (device) 300, such as a front electrode. 【0030】 Optionally, aluminum layers (see 2601 and 2602) can be deposited on the layer 250 with the doped polysilicon material and on the side of the silicon substrate 210 facing away from the dielectric layer structure 240 (opposite side from the dielectric layer structure 240) (step 170). The aluminum layers 2601 and 2602 are, for example, metallizations before and after the RC snubber element (device) 300. 【0031】 A trench capacitor or RC snubber element 300 comprises, for example, a silicon substrate 210 with a trench structure having a plurality of recesses 212, and a dielectric layer structure 240 located in at least the recesses 212 of the silicon substrate 210. The first silicon dioxide layer 2201 of the dielectric layer structure 240 is, for example, directly placed on the substrate 210 of the trench capacitor, and the first silicon nitride layer 2301 with an oxynitride layer 232, the second silicon dioxide layer 2202, and the second silicon nitride layer 2302 are, for example, placed on the first silicon dioxide layer 2201 in this order. The order of the dielectric layers of the dielectric layer structure 240 is, for example, shown in the stacking direction from the silicon substrate 210. Optionally, the trench capacitor comprises a doped polycrystalline silicon layer (see layer 250) on the surface of the dielectric layer structure 240 facing away from the silicon substrate 210 (opposite side from the silicon substrate 210). Furthermore, the trench capacitor may, for example, include a first aluminum layer 2601 on the surface of the silicon substrate 210 opposite to the main surface 214, and a second aluminum layer 2602 on the surface of the doped polycrystalline silicon layer facing away from the main surface 214 (opposite to the main surface 214). 【0032】 Figures 1a and 2 show the (ON) state at x=2. xThe snubber treatment is shown. However, methods 100 or trench capacitor structures 200 for trench capacitors or RC snubber elements 300, for example, are also possible, having more ON layer pairs, i.e., silicon dioxide-silicon nitride layer pairs. Figure 3 illustrates a trench capacitor structure 200 for x≧5, and Figure 4 illustrates a trench capacitor structure 200 for x=3. The silicon dioxide layer described herein may also be called an oxide layer or denoted by the letter O. The silicon nitride layer described herein may also be called a nitride layer or denoted by the letter N. 【0033】 As shown in Figures 3 and 4, the dielectric layer structure 240 described herein may comprise three or more silicon dioxide-silicon nitride layer pairs, i.e., ON layer pairs 242, for example, 242 in Figure 3. 1-5 and Figure 4, 242 1-3 See below. The silicon dioxide layer 220 and the silicon nitride layer 230 both form an ON layer pair 242. When viewed in the stacking direction from the silicon substrate 210, that is, in the direction of the dielectric layer structure 240, for example, within the ON layer pair 242, each silicon nitride layer 230 is positioned on top of each silicon dioxide layer 220. 【0034】 The ON layer pairs 242 are arranged vertically in the stacking direction. Starting with the second layer pair 2422, each silicon dioxide layer 220 is placed on top of the silicon nitride layer 230 of the preceding layer pair 242. The dielectric layer structure 240 comprises, for example, a layer stack in which silicon dioxide layers and silicon nitride layers are arranged alternately. Starting with the second layer pair 2422, each silicon dioxide layer 220 is deposited by depositing a polycrystalline silicon layer and oxidizing the polycrystalline silicon layer. Optionally, after each polycrystalline silicon layer has been completely converted to its respective silicon dioxide layer 220, the oxidation step can be continued to oxidize the nitride surface of each silicon nitride layer 2301 where each silicon dioxide layer 220 is located, in order to form the respective oxynitride layer 232. 【0035】 In the dielectric layer structure 240 with xON layer pairs 242, as illustrated in Figure 4, each of the first silicon nitride layers 230 up to the (x-1)th silicon nitride layer 230 may comprise an oxynitride layer 232, in which case x≧3. The oxynitride layers are each located, for example, at the interface with the subsequent layer pair 242. That is, when a new layer pair 242 is formed on a preceding layer pair 242, the nitride surface of the silicon nitride layer 230 of the preceding layer pair is oxidized to a depth of, for example, several nanometers to form the oxynitride layer 232, in which case the nitride surface is located facing the new layer pair 242. 【0036】 According to one embodiment, the oxynitride layer 232 can alternatively be considered as independent layers, each positioned between two consecutive ON layer pairs 242. Optionally, the trench capacitor structure 200 shown in Figures 3 and 4 may further comprise doped polycrystalline silicon layers 250 and / or aluminum layers 1601 and 2602 as described in relation to Figure 2. 【0037】 As described in German Patent No. 102019204503 at the beginning of this application, instead of relying on stress-free nitrides, silicon dioxide (thermally grown) and silicon nitride (deposited via LPCVD) (see German Patent Application Publication No. 102014223904) are again repeatedly generated on the underlying dielectric layer (silicon dioxide under silicon nitride) with layer thicknesses of 100 nm to 1000 nm, for any number of times more than two. Thus, opposite material voltages are continuously used to reduce or control wafer bending, and the dielectric breakdown voltage is significantly increased in the process. Due to the mechanical voltages acting on each other, the pore depth, and therefore the expansion of the capacitor surface, can be increased, and even if the entire dielectric stack layer is thicker, the integration density can be obtained or even increased. 【0038】 To maximize the quality of the silicon dioxide layer 220, the silicon dioxide layer is produced by thermal oxidation. Therefore, the first silicon dioxide layer 2201 is thermally grown on the silicon substrate 210, and further silicon dioxide layers 2202-220 are produced.x For (x≧3), each layer of undoped polycrystalline silicon (100~1000nm) is transformed by LPCVD into its respective silicon nitride layer 2301~230 x-1 (x≧3) The silicon is deposited on top and is thermally and completely dry chemically oxidized or re-oxidized. After each polycrystalline silicon layer 222 is completely converted to silicon dioxide 220, the polycrystalline silicon layer is further oxidized for a certain period of time, and as a result, silicon nitride 230 is also oxidized to some extent, forming an oxynitride layer 232. This results in a clean interface between the silicon nitride layer 230 and the silicon dioxide layer 220, where silicon nitride acts here as a pseudo-"growth stopper" and is also slightly oxidized due to the very low dry oxidation rate of silicon nitride itself (RLGuldi et al., 1989 J. Electrochem. Soc. 1363815, DOI 10.1149 / 1.2096555) and the partially thick silicon dioxide layer 220 (formerly polycrystalline silicon 222) on top of it, which slows down the diffusion of oxygen into silicon nitride. Due to the constant compensation of the mechanical voltage resulting from the opposing pressures of silicon nitride and silicon oxide, wafer bending can be kept as low as possible, thereby increasing the integration density by increasing the hole depth and simultaneously increasing the overall thickness of the dielectric stack, and therefore the dielectric breakdown strength. 【0039】 Using previously known materials and methods, it has been possible to achieve an increase in dielectric breakdown strength solely by increasing the total layer thickness. This, on the one hand, results in increased wafer bending, and on the other hand, a decrease in integration density. If integration density is to be increased, deeper holes must be created, which increases wafer bending. As a solution, the mutual mechanical pressure of the dielectrics used herein, namely the silicon dioxide layer 220 and the silicon nitride layer 230, is achieved by arranging at least two silicon dioxide layers 220 and at least two silicon nitride layers 230 alternately on top of each other. To combine this with the best possible electrical properties, instead of LPCVD or PECVD methods, dry chemical oxidation or oxidation or up-oxidation or re-oxidation of polysilicon is used to form the silicon dioxide layer 220 and create the layer stack. 【0040】 By directly depositing a silicon dioxide layer onto a silicon nitride layer, essentially similar stacks can be produced, for example, by LPCVD or PECVD methods. However, when using LPCVD or PECVD methods, the interface has more defects and the electrical breakdown strength is significantly lower (see Figure 5). Figure 5 shows the first characteristic curve 400 of a device with an equivalent oxide thickness of approximately 1175 nm, manufactured according to Figure 2. The silicon dioxide layer of the device on which characteristic curve 400 is based is deposited by dry chemical oxidation. Furthermore, Figure 5 shows the second characteristic curve 500 of an identically configured device, but the silicon dioxide layer is deposited by LPCVD deposition, rather than by dry chemical oxidation of the polysilicon layer. 【0041】 In addition, polycrystalline silicon can be re-oxidized wet chemically rather than dry chemically, which also functions more rapidly from the perspective of process technology but also has a lower dielectric breakdown strength (see FIG. 6). FIG. 6 shows a first characteristic curve 400 of a device having an equivalent oxide thickness of about 1175 nm, manufactured according to FIG. 2. The silicon dioxide layer of the device on which the characteristic curve 400 is based is deposited by dry chemical oxidation. Further, FIG. 6 shows a second characteristic curve 600 in a device also manufactured according to FIG. 2, where the silicon dioxide layer (e.g., the silicon dioxide layer starting at least from the second silicon dioxide layer 2202) is deposited by wet chemical or wet chemical oxidation of the polysilicon layer rather than dry chemical oxidation of the polysilicon layer. 【0042】 Furthermore, the device according to FIG. 2 has a higher dielectric breakdown strength compared to a device with a stress-free nitride layer, as known from the specification of German Patent No. 102019204503. FIG. 7 shows a first characteristic curve 400 of a device having an equivalent oxide thickness of about 1175 nm, manufactured according to FIG. 2. The silicon dioxide layer of the device on which the characteristic curve 400 is based is deposited by dry chemical oxidation. Further, FIG. 7 shows a second characteristic curve 700 for a device having a dielectric layer structure with 330 nm of SiO2, 550 nm of Si3N4, 500 nm of Si x N y and 500 nm of Si3N4 and having an equivalent oxide thickness of about 1085 nm. 【0043】 In the method 100 described herein, devices having a voltage class of at least 1000 V, 1200 V, or even at least 1500 V, such as RC snubber elements, can be provided. For example, a device according to FIG. 2 having a total oxide thickness of 680 nm and a total nitride thickness of 1000 nm can achieve a dielectric breakdown voltage of 1500 V at 10 mA. Whether a Si-RC snubber device was fabricated by one of the methods described herein can be determined by FIB cross-sectional analysis (focused ion beam with SEM imaging). The behavior of leakage current at nominal voltage can indicate the quality of the oxide used, i.e., the silicon dioxide layer 220, where a rough distinction can be made between PECVD, wet chemically grown oxides and dry chemically grown oxides (reducing leakage current from PECVD to wet oxides to dry oxides). Furthermore, TEM analysis can be used to investigate the formation (deposition vs. growth) of the oxide layer used. A further possibility is to investigate the difference in etching rates of the generated oxide layers. 【0044】 The method described herein allows for the fabrication of a snubber device for overvoltage attenuation within a power module. Using a snubber device, for example, a silicon carbide transistor in a conventional power module can be switched more rapidly without module-induced induction, which can result in high voltage peaks potentially harmful to all devices within the module. Here, a capacitor absorbs energy (in a few cycles), and through an integrated resistor, this energy is converted into heat and dissipated. Possible application areas for such modules include, for example, vehicle electronics (in charging modules or powertrains of e-mobility) or renewable energy (wind turbines, etc.). The possibility of faster switching leads to less power loss, thus increasing the overall efficiency of the power module. 【0045】 While several embodiments have been described in relation to the apparatus, it is understood that these embodiments also represent descriptions of corresponding methods, and therefore, blocks or devices of the apparatus should also be understood as corresponding method steps or features of method steps. Similarly, embodiments described in relation to or as method steps also represent descriptions of corresponding blocks, details, or features of the corresponding apparatus. Some or all of the method steps can be performed by (or using) hardware devices such as, for example, a microprocessor, a programmable computer, or an electronic circuit. In some embodiments, some or more of the most important method steps can be performed by such devices. 【0046】 The embodiments described above are merely illustrative of the principles of the present invention. It should be understood that modifications and changes to the configurations and details described herein will be obvious to those skilled in the art. Therefore, the present invention is intended to be limited only by the following claims and not by any specific details presented herein based on the description of the specification and embodiments.

Images