Manufacturing method for semiconductor devices

By employing optical exposure and thermal reflow with dummy openings, the method addresses the challenge of forming small etching apertures, achieving precise gate lengths in semiconductor devices.

JP7873803B2Active Publication Date: 2026-06-15NAT UNIV CORP TOKAI NAT HIGHER EDUCATION & RES SYST +1
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Patent Information

Application Number
JP2022155464
Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
Filing Date
2022-09-28
Publication Date
2026-06-15
Estimated Expiration
2042-09-28

AI Technical Summary

Technical Problem

Existing methods using optical lithography and thermal reflow struggle to form etching apertures with aperture widths smaller than the resolution limit, resulting in larger openings due to the shape of the resist layer after thermal reflow.

Method used

A method involving optical exposure and thermal reflow of a resist layer with dummy openings on both sides of the main opening to reduce the main opening width, followed by etching the underlying layer to form an etching aperture with a smaller width.

Benefits of technology

Enables the formation of etching apertures with smaller aperture widths using optical exposure, suitable for gate lengths of 0.15 μm or less, improving manufacturing precision and yield in semiconductor devices.

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Abstract

To form an etching opening with a smaller opening width using optical exposure.SOLUTION: A method for manufacturing a semiconductor device includes the steps of: forming a resist layer 14 on a specific layer 12; exposing and developing the resist layer 14 and forming dummy openings 14b and 14c having a dummy opening width Ld and a main opening 14a having a first opening width L1 larger than the dummy opening with Ld and provided between the dummy openings 14b and 14c on the resist layer 14; deforming the resist layer 14 formed with the main opening 14a and the dummy openings 14b and 14c by heating, contracting the main opening 14a to a second opening width L2 smaller than the first opening width L1, and blocking the dummy openings 14b and 14c; and forming an etching opening 12a having a third opening width L3 on the specific layer 12 by etching the specific layer 12 exposed in a main opening 14d.SELECTED DRAWING: Figure 1
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