Manufacturing method for semiconductor devices

Abstract

To form an etching opening with a smaller opening width using optical exposure.SOLUTION: A method for manufacturing a semiconductor device includes the steps of: forming a resist layer 14 on a specific layer 12; exposing and developing the resist layer 14 and forming dummy openings 14b and 14c having a dummy opening width Ld and a main opening 14a having a first opening width L1 larger than the dummy opening with Ld and provided between the dummy openings 14b and 14c on the resist layer 14; deforming the resist layer 14 formed with the main opening 14a and the dummy openings 14b and 14c by heating, contracting the main opening 14a to a second opening width L2 smaller than the first opening width L1, and blocking the dummy openings 14b and 14c; and forming an etching opening 12a having a third opening width L3 on the specific layer 12 by etching the specific layer 12 exposed in a main opening 14d.SELECTED DRAWING: Figure 1

Description

[Technical Field] 【0001】 This disclosure relates to a method for manufacturing a semiconductor device. [Background technology] 【0002】 5G mobile communication systems are expected to utilize millimeter-wave amplifiers. In field-effect transistors (FETs) used in millimeter-wave amplifiers, it is preferable to shorten the gate length to improve switching speed. For example, a gate length of about 0.15 μm can be achieved using a process using electron beam lithography. Since electron beam lithography has low throughput, it is preferable to achieve a fine gate structure using optical lithography such as i-line steppers, which are low-cost and enable mass production. 【0003】 Since the minimum resolution of an i-line stepper is approximately 0.4 μm, it is extremely difficult to form a resist layer with an aperture width of approximately 0.15 μm by exposure and development alone. As a method for forming a resist layer with an aperture width smaller than the resolution of optical exposure, a method has been proposed in which the resist aperture after exposure and development is reduced by thermal reflow. For example, a technique has been proposed to achieve a gate length of approximately 0.15 μm by reducing the resist aperture after reflow to approximately 0.15 μm. [Prior art documents] [Non-patent literature] 【0004】 [Non-Patent Document 1] Cheng-Guan Yuan et al., "0.15 micron gate 6-inch pHEMT technology by using i-line stepper," CS MANTECH Conference (May 18-21, 2009, Tampa, Florida, US). [Overview of the Initiative] [Problems that the invention aims to solve] 【0005】 The resist layer formed by thermal reflow has a shape in which the thickness gradually decreases towards the edges of the opening. Therefore, if the resist opening formed by thermal reflow is used to etch the lower layer of the resist layer to form an etched opening, the lower layer is also etched outside the resist opening, resulting in an etched opening with a larger opening width than the resist opening. Consequently, even if the opening width of the resist opening after reflow is about 0.15 μm, it is difficult to make the opening width of the etched opening about 0.15 μm. 【0006】 This disclosure has been made in view of these challenges, and one of its exemplary objectives is to provide a technique for forming etching apertures with smaller aperture widths using optical exposure. [Means for solving the problem] 【0007】 One aspect of the present disclosure is a method for manufacturing a semiconductor device. The method comprises the steps of: forming a specific layer made of a semiconductor or an insulator on a semiconductor substrate; forming a first resist layer on the specific layer; exposing and developing the first resist layer to form a first dummy opening and a second dummy opening having dummy opening widths, and a main opening having a first opening width larger than the dummy opening width and provided between the first dummy opening and the second dummy opening in the first resist layer; heating and deforming the first resist layer on which the main opening, the first dummy opening and the second dummy opening are formed to reduce the main opening to a second opening width smaller than the first opening width, and to close the first dummy opening and the second dummy opening; and etching the specific layer exposed by the main opening to form an etched opening having a third opening width in the specific layer. [Effects of the Invention] 【0008】 According to this disclosure, etching apertures with smaller aperture widths can be formed using optical exposure. [Brief explanation of the drawing] 【0009】 [Figure 1] Figs. 1(a) to 1(e) are cross-sectional views schematically showing a method of forming an etching opening according to the first embodiment. [Figure 2] It is a top view schematically showing a main opening, a first dummy opening, and a second dummy opening formed in the resist layer after development. [Figure 3] It is a graph showing an example of the relationship among a first opening width before reflow, a second opening width after reflow, and a third opening width after etching. [Figure 4] It is a plan view schematically showing an opening pattern of a mask used in a preliminary experiment. [Figure 5] It is a graph showing an example of the relationship between a mask opening width and opening widths of the resist layer before and after reflow. [Figure 6] It is a graph showing an example of the relationship between a mask opening width and pitch and a reduction amount of an opening width of the resist layer before and after reflow. [Figure 7] It is a plan view schematically showing an opening pattern of a mask according to an example. [Figure 8] It is a graph showing an example of the relationship between the number of dummy openings and the resist opening width after reflow. [Figure 9] It is a graph showing an example of the relationship between an exposure amount and the resist opening width after reflow. [Figure 10] It is a graph showing an example of the relationship between a reflow temperature and the resist opening width after reflow. [Figure 11] It is a graph showing an example of the relationship between a reflow time and an etching opening width. [Figure 12] It is a cross-sectional view schematically showing the structure of a semiconductor device according to the second embodiment. [Figure 13] Figs. 13(a) to 13(d) are cross-sectional views schematically showing a manufacturing process of a semiconductor device. [Figure 14] Figs. 14(a) to 14(b) are cross-sectional views schematically showing a manufacturing process of a semiconductor device. [Figure 15] It is a histogram showing the variation in the gate length of a semiconductor device. [Figure 16] It is a graph showing an example of the relationship between the main mask opening width and the maximum drain current of a semiconductor device. [Figure 17] It is a graph showing an example of the reverse breakdown voltage characteristic of a semiconductor device. [Figure 18] It is a graph showing an example of the relationship between the main mask opening width and the gate leakage current of a semiconductor device. [Figure 19] It is a cross-sectional view schematically showing the structure of a semiconductor device according to the third embodiment. [Figure 20] Figs. 20(a) to (c) are cross-sectional views schematically showing the manufacturing process of a semiconductor device. [Figure 21] It is a cross-sectional view schematically showing the structure of a semiconductor device according to the fourth embodiment. [Figure 22] Figs. 22(a) to (d) are cross-sectional views schematically showing the manufacturing process of a semiconductor device. 【Embodiments for Carrying Out the Invention】 【0010】 Hereinafter, embodiments for carrying out the present disclosure will be described in detail with reference to the drawings. In the description, the same reference numerals are assigned to the same elements, and redundant descriptions are omitted as appropriate. 【0011】 This embodiment will now be outlined. This embodiment relates to a method for forming an etching opening by etching a portion of a specific layer made of a semiconductor or insulator. The resist layer used to form the etching opening is patterned by optical exposure such as an i-line stepper, and then shaped by thermal reflow. After exposure and development, the resist layer has a main opening corresponding to the etching opening, as well as at least two dummy openings formed on both sides of the main opening. Therefore, the main opening is formed between the first dummy opening and the second dummy opening. The main opening is reduced by thermal reflow, and the first and second dummy openings are closed by thermal reflow. According to this embodiment, by forming dummy openings on both sides of the main opening, the amount of reduction of the main opening can be increased, and a resist opening with a smaller opening width can be formed. By etching a specific layer using such a resist opening, an etching opening with a smaller opening width can be formed. 【0012】 (First Embodiment) Figures 1(a) to 1(e) are schematic cross-sectional views illustrating the method for forming the etching aperture 12a according to the first embodiment. First, as shown in Figure 1(a), a semiconductor substrate 10 is prepared, and a specific layer 12 is formed on the semiconductor substrate 10. Next, a resist layer 14 is formed on the specific layer 12. 【0013】 The semiconductor substrate 10 is a substrate containing at least one semiconductor layer. The material of the semiconductor layer contained in the semiconductor substrate 10 is not particularly limited and may be a single-element semiconductor such as silicon (Si), or a compound semiconductor such as a III-V semiconductor or silicon carbide (SiC). An example of a material for the semiconductor layer contained in the semiconductor substrate 10 is a GaN-based nitride semiconductor, Al x Ga y In 1-x-y It can be represented by the chemical formula N(0≦x≦1, 0≦y≦1, 0≦x+y≦1). 【0014】 The specific layer 12 is a layer that includes at least a semiconductor layer or an insulating layer. The material of the semiconductor layer that may be included in the specific layer 12 is not particularly limited and may be a single-element semiconductor or a compound semiconductor, similar to the semiconductor substrate 10. The semiconductor layer included in the specific layer 12 may be an epitaxial layer formed by epitaxial growth on a semiconductor layer included in the semiconductor substrate 10. An example of a semiconductor layer included in the specific layer 12 is a GaN-based nitride semiconductor. The material of the insulating layer that may be included in the specific layer 12 is also not particularly limited and may be an oxide material such as SiO2 or a nitride material such as SiN. The specific layer 12 can be formed on the upper surface of the semiconductor substrate 10 using known methods such as metal-organic chemical vapor deposition (MOVPE) or plasma-excited chemical vapor deposition (PECVD). 【0015】 The resist layer 14 is formed by applying a photoresist for thermal reflow to the upper surface of a specific layer 12. The material of the resist layer 14 is not particularly limited, but for example, a novolac-based photoresist material can be used. The resist layer 14 may be a positive type in which the exposed areas are removed, or a negative type in which the exposed areas remain. In the examples shown in Figures 1(a) to (e), a positive type resist layer 14 is used. 【0016】 Next, as shown in Figure 1(b), a mask 16 is placed above the resist layer 14, and ultraviolet light 18 is irradiated from above the mask 16 to expose the resist layer 14. The wavelength of the ultraviolet light 18 is 300 nm or greater. In the exposure process shown in Figure 1(b), for example, an i-line stepper can be used. The wavelength of the ultraviolet light 18 used in the i-line stepper is approximately 365 nm, and the minimum resolution is approximately 400 nm. The mask 16 has a main mask aperture 16a, a first dummy mask aperture 16b, and a second dummy mask aperture 16c. The resist layer 14 is exposed by ultraviolet light 18 in the regions corresponding to the main mask aperture 16a, the first dummy mask aperture 16b, and the second dummy mask aperture 16c, respectively. 【0017】 Next, the resist layer 14 is developed. By developing the resist layer 14, the resist layer 14 in the exposed area is removed, as shown in Figure 1(c), and a main opening 14a, a first dummy opening 14b, and a second dummy opening 14c are formed in the resist layer 14. The main opening 14a is formed in the location corresponding to the main mask opening 16a. The first dummy opening 14b is formed in the location corresponding to the first dummy mask opening 16b. The second dummy opening 14c is formed in the location corresponding to the second dummy mask opening 16c. 【0018】 The main opening 14a has a first opening width L1. The first opening width L1 is substantially the same as the opening width of the main mask opening 16a. The first opening width L1 is, for example, 0.6 μm or more and 1 μm or less, preferably 0.7 μm or more and 0.9 μm or less. The first dummy opening 14b and the second dummy opening 14c have a dummy opening width Ld. The dummy opening width Ld is substantially the same as the opening width of the first dummy mask opening 16b and the second dummy mask opening 16c, respectively. The dummy opening width Ld is smaller than the first opening width L1. The dummy opening width Ld is, for example, 0.4 μm or more and 0.7 μm or less. The aperture pitch Lp from the center position of the main aperture 14a to the center positions of the first dummy mask aperture 16b and the second dummy mask aperture 16c is, for example, 1 μm or more and 2 μm or less, preferably 1.5 μm or more and 2.0 μm or less. 【0019】 Figure 2 is a schematic top view showing the main opening 14a, the first dummy opening 14b, and the second dummy opening 14c formed in the resist layer 14 after development. The main opening 14a has an elongated rectangular shape with its first opening width L1 in the shorter direction. Similarly, the first dummy opening 14b and the second dummy opening 14c have an elongated rectangular shape with their dummy opening width Ld in the shorter direction. The first dummy opening 14b and the second dummy opening 14c are positioned next to the main opening 14a in the shorter direction. In other words, the main opening 14a, the first dummy opening 14b, and the second dummy opening 14c are arranged in a line in the shorter direction. 【0020】 Next, the resist layer 14 is heated and deformed. In other words, the resist layer 14 is shaped by thermal reflow. As shown in Figure 1(d), the thermal reflow of the resist layer 14 reduces the size of the main opening 14a of the resist layer 14, forming a main opening 14d having a second opening width L2 that is smaller than the first opening width L1 before reflow. The second opening width L2 is, for example, 0.2 μm or less, preferably 0.1 μm or less. The first dummy opening 14b and the second dummy opening 14c of the resist layer 14 are closed by the thermal reflow of the resist layer 14, resulting in a state where no openings exist. That is, the opening widths of the first dummy opening 14b and the second dummy opening 14c after thermal reflow become 0. 【0021】 Next, as shown in Figure 1(e), the specific layer 12 is etched using the reflowed resist layer 14 as a mask to form an etched opening 12a in the specific layer 12 exposed at the main opening 14d. The etched opening 12a can be formed using known dry etching techniques such as reactive ion etching (RIE). The etched opening 12a may also be formed by wet etching. The etched opening 12a has a third opening width L3 that is larger than the second opening width L2. The third opening width L3 is, for example, 0.3 μm or less, and preferably 0.2 μm or less. 【0022】 The etching opening 12a shown in Figure 1(e) can be used, for example, to form a gate electrode including an embedded portion that is embedded in the etching opening 12a. In this case, the third opening width L3 of the etching opening 12a corresponds to the gate length. Therefore, by setting the third opening width L3 to 0.3 μm or less, the gate length in the embedded portion can be set to 0.3 μm or less. As an example, by setting the second opening width L2 of the main opening 14d after reflow to 0.1 μm or less, the gate length in the embedded portion can be set to approximately 0.15 μm. 【0023】 Figure 3 is a graph showing an example of the relationship between the first aperture width L1 before reflow, the second aperture width L2 after reflow, and the third aperture width L3 after etching. The example in Figure 3 shows the case where the dummy aperture width Ld = 0.5 μm, the aperture pitch Lp = 1.5 μm, the reflow temperature T = 150°C, and the reflow time t = 240 seconds (4 minutes). The material of the specific layer 12 is SiN. According to the example in Figure 3, the reduction amount of the main aperture 14a due to reflow, that is, the difference ΔL = L1 - L2 between the first aperture width L1 and the second aperture width L2, can be made to 0.6 μm or more. For example, if the first aperture width L1 is 0.7 μm, the second aperture width L2 of the main aperture 14d after reflow can be made to 0.1 μm or less, and the third aperture width L3 of the etched aperture 12a after etching can be made to about 0.15 μm. 【0024】 (Preliminary experiment) Figure 4 is a schematic plan view showing the aperture pattern of the mask 20 used in the preliminary experiment. In the preliminary experiment, instead of combining a main aperture and a dummy aperture, a mask 20 was used in which multiple mask apertures 22 had a common aperture width Lm. The number of multiple mask apertures 22 was 10. Multiple apertures were formed in the resist layer by exposure and development using an i-line stepper with the mask 20, and the aperture width of the resist layer was measured before and after reflow. Multiple masks 20 with different aperture widths Lm and pitches p of the mask apertures 22 were used, and the effects of changes in aperture width Lm and pitch p were investigated. 【0025】 Figure 5 is a graph showing an example of the relationship between the mask opening width Lm and the opening widths L1 and L2 of the resist layer before and after reflow. The example in Figure 5 shows the results when the mask opening width Lm of multiple mask openings 22 is varied, with a pitch p = 1.5 μm, a reflow temperature T = 150°C, and a reflow time t = 240 seconds. The opening width L1 of the resist layer before reflow is almost identical to the mask opening width Lm, indicating that the opening pattern of the mask 20 is directly developed on the resist layer. The opening width L2 of the resist layer after reflow is 0 when the mask opening width Lm is 0.7 μm or less (closing), and greater than 0 when the mask opening width Lm exceeds 0.7 μm (not closing). 【0026】 Figure 6 is a graph showing an example of the relationship between the mask opening width Lm and pitch p and the reduction in opening width ΔL before and after reflow of the resist layer. The example in Figure 6 shows the results when the pitch p (μm) of multiple mask openings 22 is changed to 1, 1.5, 2, 3, 4, and 7, at a reflow temperature T = 150°C and a reflow time t = 240 seconds. As shown in the figure, when the pitch p is between 1 μm and 2 μm, it can be seen that there are conditions under which the resist opening can be closed after reflow, under conditions where an i-line stepper is usable and a mask opening of 0.4 μm or larger is used. Here, the condition under which the resist opening can be closed corresponds to the case where the reduction in resist opening ΔL is greater than or equal to the mask opening width Lm, and corresponds to the shaded area in the upper left of Figure 6. In particular, when the pitch p is between 1.5 μm and 2 μm, the reduction in resist opening ΔL can be made to 0.6 μm or more, and a desirable reduction effect of the resist opening by reflow can be obtained. On the other hand, when the pitch p is 3 μm or larger, it can be seen that there are no conditions under which the resist openings can be closed after reflow when using a mask opening of 0.4 μm or larger. 【0027】 Figure 7 is a schematic plan view showing the opening pattern of the mask 24 according to the embodiment. The mask 24 in Figure 7 has a main mask opening 24a, a plurality of first dummy mask openings 24b, and a plurality of second dummy mask openings 24c. The plurality of first dummy mask openings 24b are arranged at equal intervals with a predetermined pitch p on one side of the main mask opening 24a (right side in Figure 7). The plurality of second dummy mask openings 24c are arranged at equal intervals with a predetermined pitch p on the other side of the main mask opening 24a (left side in Figure 7). The dummy mask opening width Lm2 of the plurality of first dummy mask openings 24b and the plurality of second dummy mask openings 24c is smaller than the main mask opening width Lm1 of the main mask opening 24a. Using the mask 24 in Figure 7, the opening width L2 of the main opening after reflow of the resist layer was measured when there were multiple dummy openings Nd on one side and the total number of dummy openings on both sides was 2Nd. 【0028】 Figure 8 is a graph showing an example of the relationship between the number of dummy openings Nd and the resist opening width L2 after reflow. Figure 8 shows the results when the number of dummy openings Nd on one side is changed to 1, 2, and 5, and the main mask opening width Lm1 is changed in the range of 0.7 μm to 1 μm, with a dummy mask opening width Lm2 = 0.5 μm, a mask opening pitch p = 1.5 μm, a reflow temperature T = 150 °C, and a reflow time t = 240 seconds. As shown in the figure, when the number of dummy openings Nd on one side is 1, that is, when mask 16 in Figure 1(b) is used, the resist opening width L2 after reflow was minimized. When Nd = 1, with a main mask opening width Lm1 = 0.85 μm, the resist opening width L2 after reflow was 0.07 μm. 【0029】 In Figure 8, the same results were obtained for the case with Nd=5 when the number of dummy openings on one side Nd=2. When the number of dummy openings on one side Nd is 2 or more, the reduction amount ΔL of the resist opening width before and after reflow tends to be smaller compared to the case with Nd=1. Furthermore, even if the number of dummy openings on one side Nd is multiple (i.e., 2 or more), the resist opening width L2 after reflow can be made to about 0.1 μm by setting the main mask opening width Lm1 to about 0.7 μm. 【0030】 Figure 9 is a graph showing an example of the relationship between exposure amount D and the resist aperture width L2 after reflow. Figure 9 shows the exposure amount D (mJ / cm²) when the number of dummy apertures Nd = 1 on one side, the dummy mask aperture width Lm² = 0.5 μm, the mask aperture pitch p = 1.5 μm, the reflow temperature T = 150°C, and the reflow time t = 240 seconds. 2 The results of varying the exposure amount D to 120, 170, and 220 are shown. The lower the exposure amount D, the smaller the resist aperture width L2 after reflow tended to be. Exposure amount D = 120 mJ / cm 2 When the main mask aperture width Lm = 0.8 μm, the resist aperture width L2 after reflow was 0.045 μm. 【0031】 Figure 10 is a graph showing an example of the relationship between the reflow temperature T and the resist aperture width L2 after reflow. Figure 10 is based on the following conditions: number of dummy apertures Nd=1, dummy mask aperture width Lm2=0.5μm, mask aperture pitch p=1.5μm, exposure D=170mJ / cm². 2 The results shown are obtained when the reflow temperature T (°C) is varied to 130, 140, and 150, with a reflow time t = 240 seconds. The higher the reflow temperature T, the smaller the resist opening width L2 after reflow tended to be. At a reflow temperature of T = 150°C and a main mask opening width Lm = 0.85 μm, the resist opening width L2 after reflow was 0.145 μm. 【0032】 Figure 11 is a graph showing an example of the relationship between reflow time t and the etching aperture width L3 after etching. Figure 11 shows the results when the reflow time t is 240 seconds (i.e., 4 minutes) or 270 seconds (i.e., 4.5 minutes) for the following conditions: number of dummy apertures Nd=1 on one side, dummy mask aperture width Lm2=0.5μm, mask aperture pitch p=1.5μm, and reflow temperature T=150℃. The material of the specific layer to be etched is SiN. When the main mask aperture width Lm is 0.85μm or less, the etching aperture width L3 became smaller as the reflow time t increased. For example, when the main mask aperture width Lm=0.7μm and the reflow time t=270 seconds, the etching aperture width L3 was 0.105μm. However, increasing the reflow time t tends to increase the variability of the etching aperture width L3. 【0033】 From the experimental results above, it can be seen that by forming dummy openings 14b and 14c on both sides of the main opening 14a in the resist layer 14, the amount of reduction of the main opening 14a after reflow can be increased, and a resist opening with a smaller second opening width L2 can be formed. By etching a specific layer 12 using such a resist opening, an etched opening 12a with a smaller third opening width L3 can be formed. According to one example of this embodiment, an etched opening 12a with a third opening width L3 of about 150 μm can be formed using an i-line stepper with a minimum resolution of about 400 nm. 【0034】 (Second Embodiment) Figure 12 is a schematic cross-sectional view showing the structure of a semiconductor device 30 according to the second embodiment. The semiconductor device 30 comprises a semiconductor substrate 32, a source electrode 34, a drain electrode 36, an insulating layer 38, and a gate electrode 40. The semiconductor device 30 is a field-effect transistor (FET), and more specifically, a high electron-mobility transistor (HEMT). 【0035】 The semiconductor substrate 32 includes a channel layer 50, an electron supply layer 52, and an element isolation region 54. The semiconductor substrate 32 is made of, for example, a GaN-based nitride semiconductor. The channel layer 50 is, for example, a GaN layer. The electron supply layer 52 is formed on the channel layer 50. The electron supply layer 52 is, for example, an AlGaN layer. The element isolation region 54 is formed outside the source electrode 34 and the drain electrode 36. The element isolation region 54 is a region with higher resistance than the channel layer 50 and the electron supply layer 52, and is formed by implanting ions such as boron (B), nitrogen (N), argon (Ar), and iron (Fe). 【0036】 The source electrode 34 and drain electrode 36 are provided on a semiconductor substrate 32. The source electrode 34 and drain electrode 36 are made of a metallic material that can make ohmic contact with the semiconductor substrate 32 (e.g., the electron supply layer 52). The source electrode 34 and drain electrode 36 are formed by depositing a multilayer structure such as Ti / Al / Ni / Au, Ti / Al / Nb / Au, or Mo / Al / Mo / Au, and then alloying it by high-temperature treatment at 600°C to 900°C. 【0037】 The insulating layer 38 covers the upper surface of the semiconductor substrate 32, the source electrode 34, and the drain electrode 36. The insulating layer 38 has a gate opening 42 that exposes the upper surface of the semiconductor substrate 32. The insulating layer 38 covers the upper surface of the semiconductor substrate 32 except for the gate opening 42. The insulating layer 38 may cover the entire source electrode 34 and the drain electrode 36, or it may cover only a portion of them. The insulating layer 38 may be provided so as not to cover the source electrode 34 and the drain electrode 36. The insulating layer 38 is made of, for example, silicon nitride (SiN). 【0038】 The gate electrode 40 has a field plate structure and includes an embedded portion 44 and a field plate portion 46. The embedded portion 44 is formed to fill the gate opening 42 and is in contact with the semiconductor substrate 32 (e.g., the electron supply layer 52). The field plate portion 46 is provided on the insulating layer 38 and is in contact with the upper surface of the insulating layer 38. The gate electrode 40 is made of a metallic material that makes Schottky contact with the semiconductor substrate 32 (e.g., the electron supply layer 52), and is, for example, made of a Ni / Au laminated structure. 【0039】 In the field plate structure, a Metal-Insulator-Semiconductor (MIS) junction consisting of a gate electrode 40, an insulating layer 38, and a channel layer 50 is formed at the gate end. This reduces electric field concentration between the gate and drain, improving the off-voltage of the semiconductor device 30. Furthermore, when an AC voltage is applied to the gate electrode 40, the carrier concentration directly beneath the field plate portion 46 is modulated, which also suppresses current collapse. 【0040】 The gate length Lg of the gate electrode 40 is determined by the opening width of the gate opening 42 formed in the insulating layer 38. The gate length Lg of the gate electrode 40 is, for example, about 0.15 μm. The gate opening 42 can be formed in the same manner as the etching opening 12a according to the first embodiment described above. The manufacturing method of the semiconductor device 30 will now be described. 【0041】 Figures 13(a) to 13(d) schematically show the manufacturing process of the semiconductor device 30, and illustrate the steps up to the formation of the gate opening 42. First, as shown in Figure 13(a), an electron supply layer 52 is formed on the channel layer 50. The electron supply layer 52 can be formed, for example, by the MOVPE method. Next, a source electrode 34 and a drain electrode 36 are formed on the electron supply layer 52. The source electrode 34 and the drain electrode 36 can be formed, for example, by the vapor deposition method or the sputtering method. Next, an insulating layer 38 is formed to cover the electron supply layer 52, the source electrode 34, and the drain electrode 36. The insulating layer 38 can be formed, for example, by the PECVD method. 【0042】 Next, as shown in Figure 13(b), ions 56 are injected outside the source electrode 34 and drain electrode 36 to form an element isolation region 54 in the channel layer 50 and the electron supply layer 52. 【0043】 Next, as shown in Figure 13(c), a first resist layer 60 is formed on the insulating layer 38. Subsequently, the first resist layer 60 is exposed and developed to form a main opening, a first dummy opening, and a second dummy opening in the first resist layer 60. The main opening of the first resist layer 60 has a first opening width L1, and the first dummy opening and the second dummy opening of the first resist layer 60 have a dummy opening width Ld. The exposure and development process of the first resist layer 60 is the same as shown in Figures 1(b) to (c) in the first embodiment described above. As the first resist layer 60, for example, a novolac-based positive resist material for thermal reflow can be used. An i-line stepper can be used to expose the first resist layer 60. 【0044】 Next, as shown in Figure 13(d), the first resist layer 60 is heated and deformed by thermal reflow to form a main opening 60d with a reduced second opening width L2. This thermal reflow process is the same as shown in Figure 1(d) in the first embodiment described above. The thermal reflow closes the first dummy opening and the second dummy opening, resulting in a state where no openings exist. 【0045】 Next, using the first resist layer 60 as a mask, the insulating layer 38 exposed at the main opening 60d is etched to form a gate opening 42 in the insulating layer 38. The opening width Lg of the gate opening 42 is larger than the second opening width L2 of the main opening 60d before etching. This etching process is the same as shown in Figure 1(e) in the first embodiment described above. In other words, the insulating layer 38 corresponds to the specific layer 12, and the gate opening 42 corresponds to the etched opening 12a. 【0046】 Figures 14(a) and 14(b) are schematic cross-sectional views illustrating the manufacturing process of the semiconductor device 30, showing the process of forming the gate electrode 40. First, the first resist layer 60 is peeled off and removed after the formation of the gate opening 42 shown in Figure 13(d). Next, as shown in Figure 14(a), a second resist layer 62 is formed on the insulating layer 38. The second resist layer 62 is a photoresist for lift-off and has an overhang shape. The second resist layer 62 is formed excluding the gate formation region Wg and has an opening 66 provided in the gate formation region Wg. The gate formation region Wg has an outer circumference defined to surround the gate opening 42, and is set so that the entire gate opening 42 is located inside the gate formation region Wg. 【0047】 Next, as shown in Figure 14(b), an electrode layer 58 is deposited using the second resist layer 62 as a mask. This deposits the electrode layer 58 inside the gate opening 42 exposed in the gate formation region Wg and on the insulating layer 38, forming a gate electrode 40 that includes an embedded portion 44 embedded in the gate opening 42 and a field plate portion 46 provided on the insulating layer 38. The gate formation region Wg corresponds to the formation area of ​​the field plate portion 46. Subsequently, the semiconductor device 30 shown in Figure 12 is completed by peeling off and removing the second resist layer 62. 【0048】 According to the second embodiment, since the gate electrode 40 includes the field plate portion 46, it is possible to relieve the current concentration at the gate end, improve the gate breakdown voltage, and suppress current collapse. Further, since the gate electrode 40 includes the embedded portion 44, the mechanical strength of the gate electrode 40 can be increased, and the manufacturing yield of the gate electrode 40 can be improved. 【0049】 FIG. 15 is a histogram showing the variation in the gate length Lg of the semiconductor device 30. FIG. 15 shows the variation in the gate length Lg of a plurality of semiconductor devices 30 formed on a 4-inch wafer by the manufacturing process of FIGS. 13(a) to 14(b). The main mask opening width Lm of the mask used for the exposure of the first resist layer 60 is 0.7 μm. In the example of FIG. 15, the average value of the gate length Lg is 0.187 μm, and the standard deviation is 0.03 μm. 【0050】 FIG. 16 is a graph showing an example of the relationship between the main mask opening width Lm and the maximum drain current I MAX of the semiconductor device 30. As shown in the figure, by reducing the main mask opening width Lm and thus reducing the gate length Lg, the maximum drain current I MAX was improved. This result indicates that it is possible to improve the electron velocity by shortening the gate length Lg. The reason for this is considered to be that the electric field strength at which the electron velocity of GaN constituting the channel layer 50 saturates is as high as about 200 kV / cm, and velocity saturation is unlikely to occur even at a high electric field. 【0051】 FIG. 17 is a graph showing an example of the reverse breakdown voltage characteristics of the semiconductor device 30, showing the cases where the main mask opening width Lm is 0.7 μm and 1.0 μm. As shown in the figure, by reducing the main mask opening width Lm and thus reducing the gate length Lg, the gate leakage current could be reduced. Also, when the main mask opening width Lm = 0.7 μm, the reverse breakdown voltage at which the gate leakage current becomes 10 -4 A / mm or more could be increased to 200 V or more. 【0052】 Figure 18 is a graph showing an example of the relationship between the main mask aperture width Lm and the gate leakage current of the semiconductor device 30. Figure 18 shows the gate-drain voltage V GD The gate leakage current when the voltage is set to -100V is shown. As shown in the figure, the gate leakage current can be reduced and the gate breakdown voltage can be improved by reducing the main mask opening width Lm and thus the gate length Lg. This is because, under the condition that the length of the field plate portion 46 of the gate electrode 40 is fixed, the gate length Lg was changed, and as the gate length Lg was reduced, the effective length of the field plate portion 46 increased, which is thought to have improved the gate breakdown voltage. 【0053】 For the semiconductor device 30 according to the second embodiment, the S-parameters were measured on the wafer when the gate length Lg was 0.15 μm and the gate width was 50 μm (finger length 25 μm × 2). Current gain shielding frequency f T The maximum oscillation frequency was 19 GHz when the drain voltage was 10 V. MAX The current gain shielding frequency f was 75 GHz when the drain voltage was 30 V. T and maximum oscillation frequency f MAX One possible reason for the relatively low capacitance is the large parasitic gate capacitance of the semiconductor device 30. The parasitic gate capacitance of the semiconductor device 30 arises from the electrical coupling of the gate electrode 40 with the channel layer 50 via the insulating layer 38. 【0054】 (Third embodiment) Figure 19 is a schematic cross-sectional view showing the structure of the semiconductor device 30A according to the third embodiment. The third embodiment differs from the second embodiment described above in that the gate electrode 40A is a so-called T-shaped gate. The third embodiment will be described below, focusing on the differences from the second embodiment, and the common points will be omitted from the explanation as appropriate. 【0055】 The semiconductor device 30A comprises a semiconductor substrate 32, a source electrode 34, a drain electrode 36, an insulating layer 38, and a gate electrode 40A. The gate electrode 40A includes an embedded portion 44 embedded in the gate opening 42 of the insulating layer 38 and a head portion 48 provided above the insulating layer 38 and separated from the insulating layer 38. 【0056】 Figures 20(a) to 20(c) are schematic cross-sectional views illustrating the manufacturing process of the semiconductor device 30A, showing the process of forming the gate electrode 40A. In the third embodiment, the process up to forming the gate opening 42 is the same as in the second embodiment shown in Figures 13(a) to 20(d). 【0057】 After the formation of the gate opening 42 shown in Figure 13(d), an electrode layer 58A is deposited inside the gate opening 42 and on the first resist layer 60, as shown in Figure 20(a), leaving the first resist layer 60 intact. Next, a second resist layer 62A is formed in the gate formation region Wg, as shown in Figure 20(b). The gate formation region Wg has an outer perimeter defined to surround the gate opening 42, and is set so that the entire gate opening 42 lies inside the gate formation region Wg. Therefore, the second resist layer 62A is positioned to overlap at least the entire gate opening 42. 【0058】 Next, as shown in Figure 20(c), the electrode layer 58A is etched away using the second resist layer 62A as a mask. This forms a gate electrode 40A, which includes an embedded portion 44 embedded in the gate opening 42 and a head portion 48 provided separately from the insulating layer 38. After the formation of the gate electrode 40A, the first resist layer 60 and the second resist layer 62A are peeled off and removed to produce the semiconductor device 30A shown in Figure 19. 【0059】 According to the third embodiment, the gate electrode 40A is provided away from the upper surface of the insulating layer 38, so the parasitic gate capacitance can be reduced compared to the second embodiment. As a result, the high-frequency gain can be improved in the third embodiment compared to the second embodiment. On the other hand, in the third embodiment, the area in contact between the gate electrode 40A and the insulating layer 38 is smaller compared to the second embodiment, so the gate electrode 40A is more prone to peeling, and the manufacturing yield of the gate electrode 40A decreases. 【0060】 (Fourth Embodiment) Figure 21 is a schematic cross-sectional view showing the structure of the semiconductor device 30B according to the fourth embodiment. The fourth embodiment differs from the embodiments described above in that the gate electrode 40B includes an embedded portion 44, a field plate portion 46, and a head portion 48, and is configured to combine the features of the gate electrodes 40 and 40A of the second and third embodiments. The fourth embodiment will be described below, focusing on the differences from the second and third embodiments, and the common points will be omitted as appropriate. 【0061】 The semiconductor device 30B comprises a semiconductor substrate 32, a source electrode 34, a drain electrode 36, an insulating layer 38, and a gate electrode 40B. The gate electrode 40B includes an embedded portion 44 embedded in the gate opening 42 of the insulating layer 38, a field plate portion 46 that contacts the upper surface of the insulating layer 38, and a head portion 48 provided above the insulating layer 38, away from the insulating layer 38. 【0062】 Figures 22(a) to (d) are schematic cross-sectional views illustrating the manufacturing process of the semiconductor device 30B, showing the process of forming the gate electrode 40B. In the third embodiment, the process up to forming the gate opening 42 is the same as in the second embodiment shown in Figures 13(a) to (d). 【0063】 After the formation of the gate opening 42 shown in Figure 13(d), the first resist layer 60 is peeled off and removed. Next, as shown in Figure 22(a), a second resist layer 62B is formed on the insulating layer 38. The second resist layer 62B is a photoresist for thermal reflow. The second resist layer 62B is formed excluding the first gate formation region Wg1 and has an opening 66B provided in the first gate formation region Wg1. The first gate formation region Wg has an outer perimeter defined to surround the gate opening 42, and is set so that the entire gate opening 42 is located inside the first gate formation region Wg1. The first gate formation region Wg1 is set to be a narrower area than, for example, the gate formation region Wg shown in Figure 14(a). 【0064】 The aperture width of the opening 66B of the second resist layer 62B is greater than the gate length Lg, for example, greater than the minimum resolution of the i-line stepper, which is 400 nm. Therefore, the mask used for exposure of the second resist layer 62B only needs to have a main mask opening corresponding to the opening 66B, and does not need to have a dummy mask opening. In other words, the second resist layer 62B can be patterned using a conventional general exposure mask. Alternatively, a mask having both a main mask opening and a dummy mask opening may be used for exposure of the second resist layer 62B. After exposure and development of the second resist layer 62B, the second resist layer 62B can be thermal reflowed to form a second resist layer 62B with a smooth shape at the edges of the opening 66B. 【0065】 Next, as shown in Figure 22(b), the electrode layer 58B is deposited using the second resist layer 62B as a mask. As a result, the electrode layer 58B is deposited inside the gate opening 42 exposed in the first gate formation region Wg1 and on the insulating layer 38, and the electrode layer 58B is deposited on the second resist layer 62B outside the first gate formation region Wg1. 【0066】 Next, as shown in Figure 22(c), a third resist layer 64B is formed in the second gate formation region Wg2. The second gate formation region Wg2 has an outer perimeter defined to surround the gate opening 42 and the first gate formation region Wg1, and is configured so that the entire gate opening 42 and the first gate formation region Wg1 are located inside the second gate formation region Wg2. Therefore, the third resist layer 64B is positioned to overlap at least the entire gate opening 42 and the first gate formation region Wg1. 【0067】 Next, as shown in Figure 22(d), the electrode layer 58B is etched away using the third resist layer 64B as a mask. This forms a gate electrode 40B, which includes an embedded portion 44 embedded in the gate opening 42, a field plate portion 46 that contacts the upper surface of the insulating layer 38, and a head portion 48 that is provided away from the insulating layer 38. After the formation of the gate electrode 40B, the second resist layer 62B and the third resist layer 64BA are peeled off and removed to produce the semiconductor device 30B shown in Figure 21. 【0068】 According to the fourth embodiment, the head portion 48 of the gate electrode 40B is provided away from the upper surface of the insulating layer 38, so the parasitic gate capacitance can be reduced compared to the second embodiment, and the high-frequency gain can be improved. According to the fourth embodiment, the field plate portion 46 of the gate electrode 40B is provided in contact with the upper surface of the insulating layer 38, so the mechanical strength of the gate electrode 40B can be improved compared to the third embodiment, and the manufacturing yield of the gate electrode 40B can be improved. 【0069】 For the semiconductor device 30B according to the fourth embodiment, the S-parameters were measured on-wafer when the gate length Lg was 0.15 μm and the gate width was 50 μm (finger length 25 μm × 2). Current gain shielding frequency f T The maximum oscillation frequency was 40 GHz when the drain voltage was 10 V. MAX The current gain shielding frequency f was 106 GHz when the drain voltage was 30 V. According to the fourth embodiment, compared to the second embodiment, the current gain shielding frequency f T and maximum oscillation frequency f MAXThis improves performance and allows for a reduction in parasitic gate capacity. 【0070】 In the above-described embodiment, the method for forming the etching opening 12a according to the first embodiment was shown in its application to the formation of a gate opening in a planar HEMT. The method for forming the etching opening 12a according to this embodiment can be applied to any etching process in the manufacturing process of a semiconductor device. 【0071】 This embodiment can be applied, for example, to the formation of gate openings in a recessed HEMT. In this case, in the etching process to form a recess for gate embedding in the electron supply layer, a resist layer 14 that has been exposed and developed using a mask 16 having a main mask opening 16a and dummy mask openings 16b, 16c, and then shaped by thermal reflow, can be used. In this case, at least a portion of the specific layer 12 to be etched becomes the electron supply layer, which is a semiconductor layer. 【0072】 This embodiment can be applied to the formation of gate trenches in a trench-structured transistor. In this case, in the etching process for forming gate trenches in a semiconductor layer, a resist layer 14 can be used that has been exposed and developed using a mask 16 having a main mask opening 16a and dummy mask openings 16b, 16c, and then shaped by thermal reflow. In this case, at least a portion of the specific layer 12 to be etched becomes a semiconductor layer. 【0073】 The present disclosure has been described above based on embodiments. Those skilled in the art will understand that the present disclosure is not limited to the above embodiments, that various design changes are possible, and that various modifications are possible, and that such modifications are also within the scope of the present disclosure. [Explanation of Symbols] 【0074】 10...Semiconductor substrate, 12...Specific layer, 12a...Etching aperture, 14...Resist layer, 14a...Main aperture, 14b...First dummy aperture, 14c...Second dummy aperture, 16...Mask, 16a...Main mask aperture, 16b...First dummy mask aperture, 16c...Second dummy mask aperture, 20...Mask, 30, 30A, 30B...Semiconductor equipment, 32...Semiconductor substrate, 34...Source electrode, 36...Dray Electrode, 52...electron supply layer, 38...insulating layer, 40, 40A, 40B...gate electrode, 42...gate opening, 44...embedded part, 46...field plate, 48...head part, 50...channel layer, 52...electron supply layer, 54...element isolation region, 58, 58A, 58B...electrode layer, 60...first resist layer, 60d...main opening, 62, 62A, 62B...second resist layer, 64B...third resist layer.

Claims

[Claim 1] A process of forming a specific layer composed of a semiconductor or an insulator on a semiconductor substrate, The steps include forming a first resist layer on the specified layer, A step of exposing and developing the first resist layer to form a first dummy opening and a second dummy opening having dummy opening widths, and a main opening having a first opening width larger than the dummy opening width and provided between the first dummy opening and the second dummy opening in the first resist layer, A step of heating and deforming the first resist layer on which the main opening, the first dummy opening, and the second dummy opening are formed, thereby reducing the main opening to a second opening width smaller than the first opening width, and closing the first dummy opening and the second dummy opening, A step of etching the specific layer exposed at the main opening to form an etched opening having a third opening width in the specific layer, A method for manufacturing a semiconductor device, comprising the step of forming a gate electrode including an embedded portion that is embedded in the etching opening. [Claim 2] The method for manufacturing a semiconductor device according to claim 1, wherein the aperture pitch from the center position of the main aperture to the respective center positions of the first dummy aperture and the second dummy aperture is 1 μm or more and 2 μm or less. [Claim 3] The method for manufacturing a semiconductor device according to claim 1, wherein the dummy aperture width is 0.4 μm or more and 0.7 μm or less. [Claim 4] The method for manufacturing a semiconductor device according to claim 1, wherein the first aperture width is 0.6 μm or more and 1 μm or less. [Claim 5] The method for manufacturing a semiconductor device according to claim 1, wherein the wavelength of the exposure is 300 nm or more, and the third aperture width is 0.3 μm or less. [Claim 6] The gate electrode further includes a field plate provided on the specific layer, The step of forming the gate electrode is, A step of removing the first resist layer after the formation of the etching opening, A step of forming a second resist layer on the specific layer from which the first resist layer has been removed, excluding a gate formation region having an outer periphery defined to surround the etching opening, A step of depositing an electrode layer in the etching opening exposed in the gate formation region and on the specific layer to form the embedded portion and the field plate, A method for manufacturing a semiconductor device according to any one of claims 1 to 5, comprising the step of removing the second resist layer after the deposition of the electrode layer. [Claim 7] The gate electrode further includes a head portion provided away from the specific layer, The step of forming the gate electrode is, A step of forming an electrode layer in the etching opening and on the first resist layer while leaving the first resist layer intact after the etching opening is formed, A step of forming a second resist layer on the electrode layer in a gate formation region having an outer periphery defined to surround the etching opening, The process involves etching away the electrode layer using the second resist layer as a mask to form the embedded portion and the head portion, A method for manufacturing a semiconductor device according to any one of claims 1 to 5, comprising the step of removing the first resist layer and the second resist layer after etching off the electrode layer. [Claim 8] The gate electrode further includes a field plate provided on the specific layer and a head portion provided away from the specific layer, The step of forming the gate electrode is, A step of removing the first resist layer after the formation of the etching opening, A step of forming a second resist layer on the specific layer from which the first resist layer has been removed, excluding a first gate formation region having an outer periphery defined to surround the etching opening, A step of forming an electrode layer in the etching opening exposed in the first gate formation region and on the specific layer and on the second resist layer, A step of forming a third resist layer in a second gate formation region having an outer periphery defined to surround the first gate formation region on the electrode layer, The process involves etching away the electrode layer using the third resist layer as a mask to form the embedded portion, the field plate, and the head portion. A method for manufacturing a semiconductor device according to any one of claims 1 to 5, comprising the step of removing the second resist layer and the third resist layer after etching off the electrode layer.

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