semiconductor devices

Abstract

To provide a semiconductor device that forms a gate dielectric layer with higher reliability as a buffer layer by using a heteroepitaxial layer of a semiconductor, to prevent formation of carbon clusters in the gate dielectric layer.SOLUTION: A semiconductor device includes a semiconductor layer 100, a trench gate structure 150, and a buffer layer 190. The semiconductor layer has a first surface and a second surface facing each other. At least part of the trench gate structure is located in a trench 102 of the first surface of the semiconductor layer, and includes a source region 130, a drift region 101, and a body region 110. The buffer layer is a heteroepitaxial layer of the semiconductor layer, covers an inner surface of the trench and the first surface of the semiconductor layer, and is located between a gate dielectric layer 151 and the semiconductor layer. A gate dielectric layer with higher reliability is formed as the buffer layer by using the heteroepitaxial layer of the semiconductor, to prevent formation of carbon clusters in the gate dielectric layer and improve the reliability of the device.SELECTED DRAWING: Figure 1

Description

【Technical Field】 【0001】 The present disclosure relates to the field of semiconductor device technology, and more particularly, to semiconductor devices having a trench gate structure. 【Background Art】 【0002】 Silicon carbide (SiC) semiconductor devices have advantages such as high switching speed and high power density. Compared with the planar transistor structure, the vertical transistor structure facilitates the trade-off between blocking voltage and on-resistance over the same area. The reliability of the gate dielectric layer is one of the important indicators of the vertical transistor structure. However, when the gate dielectric layer is formed by an oxidation process on the semiconductor layer, due to the preferential oxidation of Si in SiC, carbon clusters (C clusters) are formed in the gate dielectric layer, thus deteriorating the uniformity of the gate dielectric layer and the film quality, and reducing the stability and reliability of the device. 【Summary of the Invention】 【Problems to be Solved by the Invention】 【0003】 In view of the above problems, an object of the present disclosure is to provide a semiconductor device that forms a more reliable gate dielectric layer using a heteroepitaxial layer of a semiconductor layer as a buffer layer, thereby suppressing the formation of carbon clusters in the gate dielectric layer. 【Means for Solving the Problems】 【0004】 The semiconductor device provided by an embodiment of the present disclosure includes a semiconductor layer having opposing first and second surfaces, a trench gate structure, and a buffer layer, and at least a part of the trench gate structure is located in a trench on the first surface of the semiconductor layer. Here, the semiconductor layer a source region extending in a direction from the first surface toward the second surface, The drift region and the body region are located at least in part between the body region and the second surface of the semiconductor layer, The first portion of the body region is located between the source region and the drift region along the direction from the first surface to the second surface, and both the first portion of the body region and the source region are adjacent to the first side wall of the trench. Here, the buffer layer is a heteroepitaxial layer of the semiconductor layer, the buffer layer covers the inner surface of the trench and the first surface of the semiconductor layer, and the buffer layer is located between the gate dielectric layer and the semiconductor layer of the trench gate structure. Here, the source region and the drift region are of the first conductivity type, the body region is of the second conductivity type, and the first conductivity type is the opposite of the second conductivity type. 【0005】 Selectively, the semiconductor layer includes a silicon carbide semiconductor layer, and the buffer layer includes one or more of a Si layer, a SiGe layer, a GaN layer, and a GaAs layer. 【0006】 The thickness of the buffer layer may optionally include the thickness of one or more atomic layers. 【0007】 Selectively, the first, second, and third portions of the body region are sequentially adjacent along the width direction of the trench gate structure. The first and second portions of the body region are located between the two trench gate structures, the first portion is adjacent to the first side wall of the trench, the second portion is close to the second side wall of the trench, and the first and second side walls face each other. The third portion and the second portion are adjacent to the same trench, and the third portion is located between the bottom surface of the trench and the second surface, and the third portion and the first portion are separated by the drift region. Here, the second portion is adjacent to the second side wall, or the second portion and the second side wall are separated by the drift region. 【0008】 Selectively, the third portion of the body region extends from the bottom surface of the trench toward the second surface, or At least a portion of the bottom surface of the trench and the third portion of the body region are separated by the drift region along the direction from the first surface to the second surface. 【0009】 Selectively, the second portion of the body region includes a connected first subregion and a second subregion, Along the width direction of the trench gate structure, the first sub-region is adjacent to the first portion of the body region, and the second sub-region is adjacent to the third portion of the body region. Here, the distance from the edge of the first portion of the body region toward the second surface to the first surface is the first distance, the distance from the edge of the first sub-region toward the second surface to the first surface is the second distance, and the distance from the edge of the second sub-region toward the second surface to the first surface is the third distance. The third distance is greater than the second distance, and the second distance is greater than the first distance. 【0010】 Selectively, the distance from the bottom of the trench to the first surface is the fourth distance, and the second distance is greater than or equal to the fourth distance. 【0011】 Selectively, the distance at which the third portion of the body region and the bottom surface of the trench are separated by the drift region along the direction from the second surface to the first surface is the fifth distance, The sum of the fourth distance and the fifth distance is equal to the second distance. 【0012】 Selectively, the edges of the second and third portions of the body region toward the second surface direction are connected, or The edge of the third portion toward the second surface is closer to the second surface than the edge of the second portion toward the second surface. 【0013】 Selectively, the semiconductor layer further includes a channel drain region located between the first portion of the body region and the drift region, thereby the source region, the first portion of the body region and the channel drain region are sequentially adjacent along the direction from the first surface to the second surface and are all adjacent to the first sidewall of the trench. The channel drain region is further adjacent to the drift region and the second portion of the body region, respectively, and the channel drain region and the third portion of the body region are separated by the drift region. In this case, the channel drain region is of the first conductivity type. 【0014】 Selectively, the doping concentration in the channel drain region is greater than the doping concentration in the drift region. 【0015】 Selectively, the distance from the edge of the channel drain region toward the second surface to the first surface is not greater than the distance from the bottom of the trench to the first surface, or The distance from the edge of the channel drain region toward the second surface to the first surface is greater than the distance from the bottom surface of the trench to the first surface, and the channel drain region is adjacent to a part of the bottom surface of the trench. 【0016】 Selectively, the semiconductor layer further includes a channel drain region located between the first portion of the body region and the drift region, thereby the source region, the first portion of the body region and the channel drain region are sequentially adjacent along the direction from the first surface to the second surface, and all are adjacent to the first sidewall of the trench. The channel drain region is further adjacent to the drift region and the second portion of the body region, respectively, and the channel drain region and the third portion of the body region are separated by the drift region. Here, the channel drain region is of the first conductivity type, The distance from the edge of the channel drain region facing the second surface direction to the first surface is the sixth distance, The sixth distance is greater than the second distance, and the third distance is greater than the sixth distance, whereby the channel drain region and the second sub-region are separated by the drift region along the width direction of the trench gate structure. 【0017】 Optionally, the semiconductor layer further includes a body contact region extending in a direction from the first surface toward the second surface, and the body contact region is adjacent to the body region, The body contact region is adjacent to the source region or is separated by the body region, Here, the body contact region is of the second conductivity type. 【0018】 Optionally, along the extending direction of the trench gate structure, a part of the body contact region is adjacent to the second sidewall, there is a gap between another part of the body contact region and the second sidewall, and the adjacent part of the body contact region and the second sidewall and the part having the gap are alternately provided along the extending direction of the trench gate structure, Or, the body contact region and the second sidewall are both separated by the body region. 【0019】 Optionally, the trench gate structure includes the gate dielectric layer and the gate conductor, The gate dielectric layer covers the buffer layer located on the inner surface of the trench and covers a part of the buffer layer located on the first surface adjacent to the trench. The trench extends in a direction from the first surface toward the second surface, A part of the gate conductor is located in the trench, and another part extends outside the trench and covers the gate dielectric layer, Here, the gate dielectric layer is located between the gate conductor and the buffer layer to separate the gate conductor and the buffer layer. 【0020】 The semiconductor device is selectable to be a metal-oxide semiconductor field-effect transistor or an insulated-gate bipolar transistor. 【0021】 Selectively, between the two trench gate structures, the source region extends in a direction from the first side wall of one trench toward the second side wall of the other trench, adjacent to the second portion of the body region. 【0022】 One of the above proposed technologies has the following beneficial effects. 【0023】 By forming a heteroepitaxial layer between the inner surface of the trench in the semiconductor layer and the first surface of the semiconductor layer, the heteroepitaxial layer of the semiconductor layer is used as a buffer layer to form a more reliable gate dielectric layer, thereby suppressing the formation of carbon clusters in the gate dielectric layer. 【0024】 In some embodiments, a portion of the body region is placed below the bottom surface of the trench, and the bottom surface of the trench is separated from the portion of the body region by a drift region, thereby adjusting the electric field distribution near the bottom and corners of the trench and mitigating the problem of damage to the gate dielectric layer due to excessive electric field concentration at the bottom and corners of the trench. 【0025】 In some embodiments, the channel drain region, the first portion of the body region, and the source region are sequentially positioned adjacent to the first sidewall of the same trench in the vertical direction. This allows the channel length to be controlled by the position of the channel drain region, improving the uniformity of the channel length, the uniformity of the overlap between the channel and the drain region, and the uniformity of the concentration in the drain region, thereby improving the overall performance of the device. 【0026】 In some embodiments, the second portion of the body region is divided horizontally into a first sub-region and a second sub-region, and the first portion of the body region, the first sub-region, and the second sub-region are sequentially adjacent. By adjusting the distance from the bottom edge of the first sub-region to the first surface, the distance from the first sidewall of the trench to the body region gradually increases in the direction from the first surface to the second surface. In the ON state of the device, after the current flows through the source region and channel, the current path to the second surface gradually widens, thereby reducing the on-resistance and further improving the performance of the device. 【0027】 In some embodiments, the gate dielectric layer extends from the inner surface of the trench to the first surface of the semiconductor layer, protecting the portion of the buffer layer adjacent to the trench located on the first surface of the semiconductor layer. 【0028】 Please note that the general descriptions above and the detailed descriptions below are for illustrative and illustrative purposes only and do not limit this disclosure. [Brief explanation of the drawing] 【0029】 The drawings of the embodiments described below will be briefly explained in order to more clearly illustrate the technical concepts of the embodiments of this disclosure. However, it should be clear that the drawings in the following description relate only to some embodiments of this disclosure and do not limit this disclosure. 【0030】 [Figure 1] This is a schematic perspective view of a semiconductor device according to the first embodiment of this disclosure. [Figure 2] This is a schematic cross-sectional view along line AA in Figure 1. [Figure 3] This is a schematic cross-sectional view of some steps in the manufacturing method of a semiconductor device according to the first embodiment of this disclosure. [Figure 4] This is a schematic cross-sectional view of some steps in the manufacturing method of a semiconductor device according to the first embodiment of this disclosure. [Figure 5] This is a schematic cross-sectional view of some steps in the manufacturing method of a semiconductor device according to the first embodiment of this disclosure. [Figure 6] This is a schematic cross-sectional view of some steps in the manufacturing method of a semiconductor device according to the first embodiment of this disclosure. [Figure 7] This is a schematic cross-sectional view of some steps in the manufacturing method of a semiconductor device according to the first embodiment of this disclosure. [Figure 8] This is a schematic cross-sectional view of some steps in the manufacturing method of a semiconductor device according to the first embodiment of this disclosure. [Figure 9] This is a schematic diagram of a semiconductor device according to a second embodiment of the present disclosure. [Figure 10] This is a schematic diagram of a semiconductor device according to a third embodiment of the present disclosure. [Figure 11] This is a schematic diagram of a semiconductor device according to the fourth embodiment of this disclosure. [Figure 12] This is a schematic diagram of a semiconductor device according to the fifth embodiment of this disclosure. [Figure 13] This is a schematic diagram of a semiconductor device according to the sixth embodiment of this disclosure. [Figure 14] This is a schematic diagram of a semiconductor device according to the seventh embodiment of this disclosure. [Figure 15] This is a schematic diagram of a semiconductor device according to the eighth embodiment of this disclosure. [Figure 16] This is a schematic diagram of a semiconductor device according to the ninth embodiment of this disclosure. [Figure 17] This is a schematic cross-sectional view of a certain step in the manufacturing method of a semiconductor device according to the ninth embodiment of this disclosure. [Figure 18] This is a schematic cross-sectional view of a certain step in the manufacturing method of a semiconductor device according to the ninth embodiment of this disclosure. [Figure 19] This is a schematic cross-sectional view of a certain step in the manufacturing method of a semiconductor device according to the ninth embodiment of this disclosure. [Modes for carrying out the invention] 【0031】 The present disclosure will be described in more detail below with reference to the drawings. In each drawing, similar elements are given the same reference numerals. For clarity, the parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For brevity, a semiconductor structure obtained through several steps can be shown in a single figure. 【0032】 When describing the structure of a device, if one layer or region is said to be located "above" or "above" another layer or region, it can mean that it is directly above the other layer or region, or that there is another layer or region between it and the other layer or region. Also, if the device is inverted, that layer or region will be located "below" or "below" the other layer or region. 【0033】 To describe cases where a layer or region is directly located on top of another layer or region, this specification uses expressions such as "directly located on..." or "located on and adjacent to...". 【0034】 Power devices typically include an active element region, an edge termination region, and a crack stop or shield region. The active element region includes an array of active elements. This disclosure relates to the active element structure. The dimensions of the active elements vary depending on product requirements, and body regions may exist between the active elements in the active element region. 【0035】 To better understand this disclosure, many specific details of this disclosure, such as the device structure, materials, dimensions, processing steps, and technology, are described below. However, as will be understood by those skilled in the art, this disclosure may be implemented without adhering to these specific details. 【0036】 Figure 1 shows a schematic perspective view of a semiconductor device according to the first embodiment of this disclosure, and Figure 2 shows a schematic cross-sectional view along line AA in Figure 1. Note that in Figure 1, the structure above the buffer layer and part of the trench gate structure are omitted in order to more clearly show the positional relationships between each structure. 【0037】 As shown in Figures 1 and 2, a semiconductor device according to a first embodiment of the present disclosure includes a semiconductor layer 100, a buffer layer 190, a plurality of trench gate structures 150, an interlayer dielectric layer 160, and a source metal layer 170. The semiconductor layer 100 includes opposing first surfaces 10 and second surfaces 20 and a plurality of trenches 102, the trenches 102 extending inward into the semiconductor layer 100 in the direction from the first surface 10 to the second surface 20. The trenches 102 have a first sidewall 102a, a second sidewall 102b, and a bottom surface 102c, where the first sidewall 102a faces the second sidewall 102b. The plurality of trenches 102 extend in the Y-axis direction and are distributed at intervals in the X-axis direction (which can also be considered as the width direction of the trenches 102). Selectively, the X, Y, and Z axis directions (directions from the second surface 20 toward the first surface 10) are orthogonal to each other in pairs. Selectively, the X axis direction is either the <11-20> direction or the <1-100> direction, and the planes of the first sidewall 102a and the second sidewall 102b are either the (11-20) plane or the (1-100) plane. Multiple trench gate structures 150 are located within the corresponding trenches 102, and the extension direction of the trench gate structures 150 is the same as the extension direction of the trenches 102. Here, the semiconductor layer 100 is, for example, a SiC substrate or a laminated structure consisting of a SiC substrate and an epitaxial layer. However, the embodiments of this disclosure are not limited thereto, and those skilled in the art can, as needed, make other settings for the material and number of layers of the semiconductor layer 100. 【0038】 The semiconductor layer 100 includes a drift region 101, a body region 110, a source region 130, a body contact region 140, and a drain contact region 180. Here, the source region 130 and the drift region 101 are of a first conductivity type, the body region 110 and the body contact region 140 are of a second conductivity type, and the doping concentration of the body contact region 140 is greater than the doping concentration of the body region 110. The first conductivity type is the opposite of the second conductivity type. The first conductivity type is either P-type or N-type, and the second conductivity type is either P-type or N-type. 【0039】 The semiconductor device in this embodiment may be a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). For example, the conductivity type of the drain contact region 180 is set in correspondence with the first conductivity type or the second conductivity type. However, the embodiments of this disclosure are not limited thereto, and those skilled in the art may set the conductivity types of each region in the semiconductor layer 100 as needed to operate the semiconductor device as a MOSFET or an IGBT. 【0040】 The buffer layer 190 covers the inner surface of the trench 102 and the first surface 10 of the semiconductor layer 100. Here, the buffer layer 190 is a crystal-form heteroepitaxial layer of the semiconductor layer 100, and optionally, the semiconductor layer 100 may be a semiconductor layer containing C and Si elements, for example, a SiC semiconductor layer, or the semiconductor layer 100 may be a semiconductor layer containing other elements, and the buffer layer 190 may contain one or more of the Si layer, SiGe layer, GaN layer, and GaAs layer. The heteroepitaxial layer may be other semiconductor crystalline material or a crystalline material that is hardly doped with in situ impurities. The thickness of the buffer layer 190 is at the atomic layer level, for example, the thickness of the buffer layer 190 is 1 atomic layer or 2-3 atomic layers, thereby not creating a large barrier to the carrier flow. 【0041】 The trench gate structure 150 includes a gate dielectric layer 151 and a gate conductor 152. The gate dielectric layer 151 covers a buffer layer 190 located on the inner surface of the trench 102, and the gate conductor 152 is located inside the trench 102. The gate dielectric layer 151 is located between the buffer layer 190 and the gate conductor 152 and is used to separate the buffer layer 190 and the gate conductor 152. 【0042】 In this embodiment, a buffer layer 190, which is a heteroepitaxial layer of the semiconductor layer 100, is formed on the inner surface of the trench 102 of the semiconductor layer 100 and on the first surface 10 of the semiconductor layer 100. The buffer layer 190 separates the gate dielectric layer 151 from the semiconductor layer 100, thereby suppressing the formation of carbon clusters in the gate dielectric layer 151. 【0043】 The body region 110 includes a first portion 111, a second portion 112, and a third portion 113 that are sequentially connected in the X-axis direction. The first portion 111 is adjacent to the first side wall 102a of the trench 102, the second portion 112 is adjacent to the second side wall 102b of the trench 102, and the third portion 113 is located between the bottom surface 102c of the trench 102 and the second surface 20, and is adjacent to the bottom surface 102c. The second portion 112 is substantially flush with the edge of the third portion 113 in the direction of the second surface 20. Selectively, the doping concentrations of the first portion 111, the second portion 112, and the third portion 113 are different. 【0044】 The source region 130 extends from the first surface 10 to the second surface 20 of the semiconductor layer 100. The source region 130 and the drift region 101 are separated by the first portion 111 of the body region 110 along the Z-axis direction. Between the two trench gate structures 150, the source region 130 and the first portion 111 are adjacent to the first side wall 102a of the same trench 102. 【0045】 Selectively, between two trench gate structures 150, the source region 130 extends from the first side wall 102a of one trench 102 to the second side wall 102b of the other trench 102, thereby adjoining the second portion 112 of the body region 110. When the joint depth of the source region 130 is deep, increasing the width of the source region 130 helps to reduce the contact diffusion resistance of the source region 130. 【0046】 The body contact region 140 extends from the first surface 10 to the second surface 20 of the semiconductor layer 100 and is adjacent to the body region 110. Along the X-axis, between two adjacent trench gate structures 150, one end of the body contact region 140 is adjacent to the source region 130, and the other end is adjacent to the second sidewall 102b of the trench 102, but is not connected to the second sidewall 102b, where the body contact region 140 and the second sidewall 102b are separated by the body region 110. Optionally, the body contact region 140 and the source region 130 are separated by the body region 110. 【0047】 Selectively, along the Y-axis, a portion of the body contact area 140 is adjacent to the second side wall 102b, and the remaining portion of the body contact area 140 and the second side wall 102b are separated by the body area 110, creating a gap. Along the Y-axis, the body contact area 140 and portions adjacent to the second side wall 102b and portions with gaps are alternately arranged. 【0048】 The gate-to-source capacitance consists of three parts: the capacitance from the gate conductor 152 to the body region 110, the capacitance from the gate conductor 152 to the body contact region 140, and the capacitance from the gate conductor 152 to the source region 130. Here, the source region 130 is electrically connected to the body region 110. The body contact region 140 has a higher doping concentration and therefore a higher capacitance per unit area than the body region 110. By adjusting the area of ​​direct contact between the second sidewall 102b and the body contact region 140, the total gate-to-source capacitance can be adjusted. Depending on different applications and system requirements, the requirements for the gate charge or the ratio of the gate-to-drain capacitance / (gate-to-drain capacitance + gate-to-source capacitance) also differ. For example, during the turn-off process of a hard-switched transistor, the drain voltage suddenly rises, and capacitive coupling causes the gate to self-turn on. If there is no margin for gate self-turn-on, the margin can be improved by increasing the gate-to-source capacitance. 【0049】 The source metal layer 170 is located on the first surface 10 of the semiconductor layer 100 and adjacent to the buffer layer 190, where the source metal layer 170 is electrically connected to the source region 130, body region 110, and body contact region 140, respectively, via the buffer layer 190. The interlayer dielectric layer 160 is located between the buffer layer 190 and the source metal layer 170, is installed in correspondence with the gate structure 150, and is used to isolate the source metal layer 170 from the trench gate structure 150. The source metal layer 170 and the interlayer dielectric layer 160 may be multilayer structures of different materials. As an example of a multilayer source metal layer 170, the source metal layer 170 includes a tungsten (W) layer directly coated on the buffer layer 190 and an aluminum copper (AlCu) layer directly coated on the tungsten layer. Furthermore, the embodiment may optionally include parts not shown, for example, a gate contact region opening directly above the gate conductor 152 so that the gate conductor 152 is connected to the gate metal layer, the gate contact region being directly located on the gate conductor 152, and the gate conductor 152 being separated from the source metal layer 170 via the interlayer dielectric layer 160. 【0050】 At least a portion of the drift region 101 is located between the body region 110 and the second surface 20, adjacent to the second portion 112 and the third portion 113 of the body region 110, the bottom surface 102c of the trench 102, and the drain contact region 180, respectively, where the drain contact region 180 extends in the direction from the second surface 20 to the first surface 10 of the semiconductor layer 100. 【0051】 Furthermore, the semiconductor device of this embodiment further includes a drain metal layer (not shown) located on the second surface 20 of the semiconductor layer 100 and connected to the drain contact region 180. 【0052】 Figures 3 to 8 are schematic cross-sectional views of some steps in the manufacturing method of a semiconductor device according to the first embodiment of this disclosure. 【0053】 As shown in Figure 3, a buffer layer 201 is formed on the first surface 10 of the semiconductor layer 100, a first doping region 110-1 is formed by an ion implantation process, and then the buffer layer 201 is removed. 【0054】 Furthermore, a buffer layer 202 is formed on the first surface 10 of the semiconductor layer 100, a mask layer 203 is formed on the buffer layer 202, and a plurality of second doping regions 110-2 are formed by an ion implantation process, as shown in Figure 4. Here, the plurality of second doping regions 110-2 are adjacent to the first doping region 110-1, located between the first doping region 110-1 and the second surface 20, and distributed with spacing in the X-axis direction. 【0055】 Furthermore, the buffer layer 202 and the mask layer 203 are removed, and the body region 110 is constructed with the first doping region 110-1 and the second doping region 110-2, as shown in Figure 5. 【0056】 Furthermore, a mask layer 204 is formed on the first surface 10 of the semiconductor layer 100, and a plurality of trenches 102 are formed by an etching process, as shown in Figure 6. Here, the body region 110 includes a first portion 111, a second portion 112, and a third portion 113 that are sequentially adjacent along the extension direction of the X axis, the first portion 111 being adjacent to the first side wall 102a of the trench 102, the second portion 112 being adjacent to the second side wall 102b of the trench 102, and the third portion 113 being adjacent to the bottom surface 102c of the trench 102. 【0057】 Furthermore, the mask layer 204 is removed, and a buffer layer 190 is formed on the inner surface of the trench 102 and on the first surface 10 of the semiconductor layer 100 by an epitaxial process, as shown in Figure 7. Here, the buffer layer 190 is a heteroepitaxial layer of the semiconductor layer 100 and includes one or more of the following: a Si layer, a SiGe layer, a GaN layer, and a GaAs layer. The heteroepitaxial layer may be another semiconductor crystalline material or a material that is hardly doped with in situ impurities. In this embodiment, the body region 110 is formed before the buffer layer 190 is formed, so that the impurities injected when forming the body region 110 do not remain on the surface of the buffer layer 190, which helps to improve the reliability of the device. 【0058】 Furthermore, as shown in Figure 8, a gate dielectric layer 151 is formed on the buffer layer 190. Here, for example, the gate dielectric layer 151 is formed by a thermal oxidation process, during which a portion of the buffer layer 190 is consumed. After the formation of the gate dielectric layer 151, the thickness of the buffer layer 190 is at the atomic layer level, which continues to suppress the formation of defective carbon cluster structures at the interface between the gate dielectric layer and the semiconductor layer. Also, because the thickness of the buffer layer 190 is thin, it does not create a significant barrier to the carrier flow. In a subsequent process, the gate dielectric layer 151 located on the first surface 10 is removed. 【0059】 Figure 9 is a schematic diagram of a semiconductor device according to a second embodiment of this disclosure. 【0060】 As shown in Figure 9, the same aspects of the semiconductor device according to the second embodiment of this disclosure as the first embodiment are omitted from this description, and the explanations in Figures 1 to 8 can be found. The difference is that in this embodiment, in the Z-axis direction, at least a portion of the bottom surface 102c of the trench 102 is separated from the third portion 113 of the body region 110 by a drift region 101. Optionally, the third portion 113 is adjacent to the bottom surface 102c near the corner between the second side wall 102b and the bottom surface 102c. Optionally, the third portion 113 and the bottom surface 102c are completely separated by the drift region 101. Optionally, the second portion 112 of the body region 110 and the second side wall 102b of the trench 102 are separated by the drift region 101. 【0061】 In this embodiment, the drift region 101 separates the bottom surface 102c of the trench 102 from the third portion 113 of the body region 110, thereby adjusting the electric field distribution near the bottom and corners of the trench 102 and mitigating the problem of damage to the gate dielectric layer 151 due to excessive electric field concentration at the bottom and corners of the trench 102. 【0062】 Figure 10 is a schematic diagram of a semiconductor device according to a third embodiment of this disclosure. 【0063】 As shown in Figure 10, the similarities between the semiconductor device according to the third embodiment of this disclosure and the first embodiment will not be explained here, but you can refer to the explanation in Figures 1 to 8. The difference is that the semiconductor layer 100 of this embodiment further includes a channel drain region 120 which is a first conductivity type, and the doping concentration of the channel drain region 120 is greater than the doping concentration of the drift region 101. 【0064】 The channel drain region 120 is located between the first portion 111 of the body region 110 and the drift region 101, such that the channel drain region 120 is sequentially adjacent to the source region 130 and the first portion 111 of the body region 110 in the direction from the first surface 10 to the second surface 20. Here, between the two trench gate structures 150, the first portion 111, the channel drain region 120, and the source region 130 are all adjacent to the first side wall 102a of the same trench 102. The channel drain region 120 is close to the bottom surface 102c of the trench 102 and adjacent to the second portion 112. The channel drain region 120 and the third portion 113 of the body region 110 are separated by the drift region 101. Selectively, the distance from the edge of the channel drain region 120 in the direction toward the second surface 20 to the first surface 10 is less than or equal to the distance from the bottom surface 102c of the trench 102 to the first surface 10. Selectively, the distance from the edge of the channel drain region 120 toward the second surface 20 to the first surface 10 is greater than the distance from the bottom surface 102c of the trench 102 to the first surface 10, and the channel drain region 120 is adjacent to a portion of the bottom surface 102c of the trench 102. 【0065】 In this embodiment, when the semiconductor device is in the ON state, the conductivity type is reversed in the portion of the body region 110 adjacent to the first side wall 102a of the trench 102, thereby forming a channel. By providing a channel drain region 120 close to the bottom surface 102c of the trench 102, the channel length can be controlled relatively accurately, thereby improving the uniformity of multiple channel lengths in the semiconductor device. Furthermore, by providing a channel drain region 120, the uniformity of the overlapping portion of the channel and drain region, as well as the uniformity of the concentration in the drain region, can be improved, thereby improving the overall performance of the device. 【0066】 In some specific embodiments, the channel drain region 120 is formed in the same process steps as the source region 130 to more precisely control the channel length and further improve the uniformity of the channel length. 【0067】 Figure 11 is a schematic diagram of a semiconductor device according to the fourth embodiment of this disclosure. 【0068】 As shown in Figure 11, the similarities between the semiconductor device according to the fourth embodiment of this disclosure and the third embodiment are omitted from this description, and can be referred to in the description of Figure 10. The difference is that in this embodiment, in the Z-axis direction, at least a portion of the bottom surface 102c of the trench 102 is separated from the third portion 113 of the body region 110 by a drift region 101. Optionally, the third portion 113 is adjacent to the bottom surface 102c near the corner between the second side wall 102b and the bottom surface 102c. Optionally, the third portion 113 and the bottom surface 102c are completely separated by the drift region 101. Optionally, the second portion 112 of the body region 110 and the second side wall 102b of the trench 102 are separated by the drift region 101. 【0069】 In this embodiment, the drift region 101 separates the bottom surface 102c of the trench 102 from the third portion 113, thereby adjusting the electric field distribution near the bottom and corners of the trench 102 and mitigating the problem of damage to the gate dielectric layer 151 due to excessive electric field concentration at the bottom and corners of the trench 102. 【0070】 Figure 12 is a schematic diagram of a semiconductor device according to the fifth embodiment of this disclosure. 【0071】 As shown in Figure 12, the similarities between the semiconductor device according to the fifth embodiment of this disclosure and the second embodiment will not be explained here, but can be seen in the explanation in Figure 9. The difference is that in this embodiment, the second portion 112 of the body region 110 includes connected first sub-regions 112a and second sub-regions 112b. Along the X-axis, the first sub-region 112a is adjacent to the first portion 111 of the body region 110, and the second sub-region 112b is adjacent to the third portion 113 of the body region 110. 【0072】 The distance from the edge of the first part 111 in the direction toward the second surface 20 to the first surface 10 is the first distance d1, the distance from the edge of the first sub-region 112a in the direction toward the second surface 20 to the first surface 10 is the second distance d2, and the distance from the edge of the second sub-region 112b in the direction toward the second surface 20 to the first surface 10 is the third distance d3, where the third distance d3 is greater than the second distance d2, and the second distance d2 is greater than the first distance d1. 【0073】 In this embodiment, the distance d2 from the bottom edge of the first sub-region 112a to the first surface is adjusted so that the edge of the body region 110 adjacent to the first side wall 102a is stepped. As a result, the distance from the first side wall 102a to the second portion 112 of the body region 110 gradually increases in the direction from the first surface 10 to the second surface 20. When the device is on, the current path to the second surface 20 gradually widens after flowing through the source region 130 and the channel, thereby reducing the on-resistance and further improving the performance of the device. 【0074】 Selectively, the distance from the bottom surface 102c of the trench 102 to the first surface 10 is the fourth distance d4, where the second distance d2 is greater than or equal to the fourth distance d4, thereby reducing the influence of a high electric field on the bottom of the trench 102. 【0075】 Selectively, in the Z-axis direction, the distance at which the third portion 111 of the body region 110 and the bottom surface 102c of the trench 102 are separated by the drift region 101 is the fifth distance d5, and the sum of the fourth distance d4 and the fifth distance d5 is equal to the second distance d2, thereby the bottom surface 112-1 of the second sub-region 112b is substantially flush with the separation surface 113-1 of the third portion 113 of the body region 110. Thus, the depth of the second sub-region 112b is controlled to an appropriate degree, avoiding limiting the help of charge compensation to reduce turn-on resistance by having the second distance d2 be too large. 【0076】 Figure 13 is a schematic diagram of a semiconductor device according to the sixth embodiment of this disclosure. 【0077】 As shown in Figure 13, the semiconductor device according to the sixth embodiment of this disclosure and the third embodiment are the same, but the explanation is omitted here; refer to the explanation in Figure 10. The difference is that in this embodiment, the second portion 112 of the body region 110 includes connected first sub-regions 112a and second sub-regions 112b. Along the X-axis, the first sub-region 112a is adjacent to the first portion 111 of the body region 110, and the second sub-region 112b is adjacent to the third portion 113 of the body region 110. 【0078】 The distance from the edge of the first part 111 in the direction toward the second surface 20 to the first surface 10 is the first distance d1, the distance from the edge of the first sub-region 112a in the direction toward the second surface 20 to the first surface 10 is the second distance d2, and the distance from the edge of the second sub-region 112b in the direction toward the second surface 20 to the first surface 10 is the third distance d3, where the third distance d3 is greater than the second distance d2, and the second distance d2 is greater than the first distance d1. 【0079】 In this embodiment, the distance d2 from the bottom edge of the first sub-region 112a to the first surface is adjusted so that the edge of the body region 110 adjacent to the first side wall 102a is stepped. As a result, the distance from the first side wall 102a to the second portion 112 of the body region 110 gradually increases in the direction from the first surface 10 to the second surface 20. When the device is on, the current path to the second surface 20 gradually widens after flowing through the source region 130 and the channel, thereby reducing the on-resistance and further improving the performance of the device. 【0080】 Selectively, the distance from the edge of the channel drain region 120 toward the second surface 20 to the first surface 10 is the sixth distance d6, where the sixth distance d6 is greater than the second distance d2, and the third distance d3 is greater than the sixth distance d6, thereby separating a portion of the channel drain region 120 and the second sub-region 112b in the X-axis direction by the drift region 101. 【0081】 Figure 14 is a schematic diagram of a semiconductor device according to the seventh embodiment of this disclosure. 【0082】 As shown in Figure 14, the similarities between the semiconductor device according to the seventh embodiment of this disclosure and the sixth embodiment will not be explained here, but can be seen in the explanation in Figure 13. The difference is that in this embodiment, in the Z-axis direction, at least a portion of the bottom surface 102c of the trench 102 is separated from the third portion 113 of the body region 110 by a drift region 101. Optionally, the third portion 113 is adjacent to the bottom surface 102c near the corner between the second side wall 102b and the bottom surface 102c. Optionally, the third portion 113 and the bottom surface 102c are completely separated by the drift region 101. Optionally, the second portion 112 of the body region 110 and the second side wall 102b of the trench 102 are separated by the drift region 101. 【0083】 In this embodiment, the drift region 101 separates the bottom surface 102c of the trench 102 from the third portion 113, thereby adjusting the electric field distribution near the bottom and corners of the trench 102 and mitigating the problem of damage to the gate dielectric layer 151 due to excessive electric field concentration at the bottom and corners of the trench 102. 【0084】 Figure 15 is a schematic diagram of a semiconductor device according to the eighth embodiment of this disclosure. 【0085】 As shown in Figure 15, the similarities between the semiconductor device according to the eighth embodiment of this disclosure and the first embodiment will not be explained here, but the explanations in Figures 1 to 8 can be found. The difference is that in this embodiment, a part of the trench gate structure 150 is located inside the trench 102, and the other part is located on the first surface 10. Specifically, the gate dielectric layer 151 covers the buffer layer 190 located on the inner surface of the trench 102 and also covers a part of the buffer layer 190 on the first surface 10 adjacent to the trench 102, a part of the gate conductor 152 is located inside the trench 102, and the other part extends into the trench 102 and covers the gate dielectric layer 151 located on the first surface 10. 【0086】 The trench gate structure 150 in this embodiment extends from inside the trench 102 to above the first surface 10, protecting the portion of the first surface 10 and the buffer layer 190 adjacent to the trench 102, and reducing damage to the portion of the first surface 10 and the buffer layer 190 adjacent to the trench 102 during the manufacturing process. 【0087】 Optionally, the semiconductor device according to the eighth embodiment of the present disclosure may be configured such that at least a portion of the bottom surface 102c of the trench 102 is separated from the third portion 113 in the Z-axis direction by a drift region 101, as in the second, fourth, fifth, and seventh embodiments of the present disclosure. 【0088】 Optionally, the semiconductor device according to the eighth embodiment of the present disclosure may be provided with a channel drain region 120, as in the third, fourth, sixth, and seventh embodiments of the present disclosure. 【0089】 Optionally, the semiconductor device according to the eighth embodiment of the present disclosure may include a first sub-region 112a and a second sub-region 112b, as in the fifth, sixth, and seventh embodiments of the present disclosure. 【0090】 Figure 16 is a schematic diagram of a semiconductor device according to the ninth embodiment of this disclosure. 【0091】 As shown in Figure 16, the similarities between the semiconductor device according to the ninth embodiment of this disclosure and the first embodiment will not be explained here, but you can refer to the explanation in Figures 1 to 8. The differences are that in this embodiment, the distance from the edge of the body region 110 in the direction toward the second surface 20 from the first portion 111 is d1, the distance from the edge of the body region 110 in the direction toward the second surface 20 from the second portion 112 is d7, the distance from the edge of the body region 110 in the direction toward the second surface 20 from the first surface 10 is d8, and the distance from the bottom surface 102c of the trench 102 to the first surface 10 is d4, where d8>d7>d4>d1. 【0092】 In this embodiment, the third portion 113 plays a role in charge compensation, and increasing the depth of the third portion 113 (increasing the distance d8) can improve the breakdown voltage of the device. 【0093】 Optionally, the semiconductor device according to the ninth embodiment of the present disclosure may be configured such that at least a portion of the bottom surface 102c of the trench 102 is separated from the third portion 113 in the Z-axis direction by a drift region 101, as in the second, fourth, fifth, and seventh embodiments of the present disclosure. 【0094】 Optionally, the semiconductor device according to the ninth embodiment of the present disclosure may be provided with a channel drain region 120, as in the third, fourth, sixth, and seventh embodiments of the present disclosure. 【0095】 Optionally, the semiconductor device according to the ninth embodiment of the present disclosure may be provided with a trench gate structure 150, as in the eighth embodiment of the present disclosure. 【0096】 Figures 17 to 19 are schematic cross-sectional views of some steps in the manufacturing method of a semiconductor device according to the ninth embodiment of this disclosure. 【0097】 First, referring to Figure 3 and the textual explanation, a first doping region 110-1 is formed by an injection process, then a mask layer 301 is formed on the first surface 10 of the semiconductor layer 100, and multiple trenches 102 are formed by an etching process, as shown in Figure 17. After that, the mask layer 301 is removed. 【0098】 Furthermore, a mask layer 302 is formed on the first surface 10 of the semiconductor layer 100 and within the trench 102, and a second doping region 110-2 is formed by an injection process, as shown in Figure 18. Subsequently, the mask layer 302 is removed. 【0099】 Furthermore, as shown in Figure 19, a buffer layer 190 is formed on the inner surface of the trench 102 and on the first surface 10 of the semiconductor layer 100 by an epitaxial process. Here, the buffer layer 190 is a heteroepitaxial layer of the semiconductor layer 100 and includes one or more of the following: a Si layer, a SiGe layer, a GaN layer, and a GaAs layer. The heteroepitaxial layer may be another semiconductor crystalline material or a material that is hardly doped with in situ impurities. 【0100】 In this embodiment, since the second doping region 110-2 is formed after the formation of the trench 102, the structure of the trench 102 makes it easier to increase the depth of the third portion 113 of the body region 110. Since the body region 110 is formed before the formation of the buffer layer 190, impurities injected when forming the body region 110 do not remain on the surface of the buffer layer 190, which helps to improve the reliability of the device. 【0101】 Embodiments of the present disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the present disclosure, and such substitutions and modifications should fall within the scope of the present disclosure.

Claims

[Claim 1] A semiconductor device comprising a semiconductor layer having opposing first and second surfaces, a trench gate structure, and a buffer layer, wherein at least a portion of the trench gate structure is located in a trench of the first surface of the semiconductor layer. Here, the semiconductor layer is A source region extending in the direction from the first surface toward the second surface, The system includes a drift region and a body region, wherein at least a portion of the drift region is located between the body region and the second surface of the semiconductor layer. The first portion of the body region is located between the source region and the drift region along the direction from the first surface to the second surface, and both the first portion of the body region and the source region are adjacent to the first side wall of the trench. Here, the buffer layer is a heteroepitaxial layer of the semiconductor layer, the buffer layer covers the inner surface of the trench and the first surface of the semiconductor layer, and the buffer layer is located between the gate dielectric layer and the semiconductor layer of the trench gate structure. The source region and the drift region are of a first conductivity type, the body region is of a second conductivity type, and the first conductivity type is opposite to the second conductivity type. The first, second, and third portions of the body region are sequentially adjacent to each other along the width direction of the trench gate structure. The body region and the second surface are separated by the drift region. The first and second portions of the body region are located between the two trench gate structures, the first portion is adjacent to the first side wall of the trench, the second portion is close to the second side wall of the trench, and the first and second side walls face each other. The third portion and the second portion are adjacent to the same trench, and the third portion is located between the bottom surface of the trench and the second surface, and the third portion and the first portion are separated by the drift region. The third portion of the body region extends from a part of the bottom surface of the trench toward the second surface, or A semiconductor device in which at least a portion of the bottom surface of the trench and a third portion of the body region are separated by the drift region along the direction from the first surface to the second surface. [Claim 2] The semiconductor device according to claim 1, wherein the semiconductor layer includes a SiC semiconductor layer, and the buffer layer includes one or more of a Si layer, a SiGe layer, a GaN layer, and a GaAs layer. [Claim 3] The semiconductor device according to claim 1, wherein the thickness of the buffer layer includes the thickness of one or more atomic layers. [Claim 4] The semiconductor device according to claim 1, wherein the second portion is adjacent to the second sidewall, or the second portion and the second sidewall are separated by the drift region. [Claim 5] The second portion of the body region includes a first subregion and a second subregion that are connected, Along the width direction of the trench gate structure, the first sub-region is adjacent to the first portion of the body region, and the second sub-region is adjacent to the third portion of the body region. Here, the distance from the edge of the first portion of the body region toward the second surface to the first surface is the first distance, the distance from the edge of the first sub-region toward the second surface to the first surface is the second distance, and the distance from the edge of the second sub-region toward the second surface to the first surface is the third distance. The semiconductor device according to claim 1, wherein the third distance is greater than the second distance, and the second distance is greater than the first distance. [Claim 6] The semiconductor device according to claim 5, wherein the distance from the bottom surface of the trench to the first surface is the fourth distance, and the second distance is greater than or equal to the fourth distance. [Claim 7] Along the direction from the second surface toward the first surface, the distance from the bottom of the trench to the first surface is the fourth distance, and the distance at which the third portion of the body region and the bottom of the trench are separated by the drift region is the fifth distance. The semiconductor device according to claim 5, wherein the sum of the fourth distance and the fifth distance is equal to the second distance. [Claim 8] The edges of the second and third portions of the body region, in the direction of the second surface, are connected, or The semiconductor device according to any one of claims 4 to 7, wherein the edge of the third portion toward the second surface is closer to the second surface than the edge of the second portion toward the second surface. [Claim 9] The semiconductor layer further includes a channel drain region located between the first portion of the body region and the drift region, thereby the source region, the first portion of the body region and the channel drain region are sequentially adjacent along the direction from the first surface to the second surface, and all are adjacent to the first sidewall of the trench. The channel drain region is further adjacent to the drift region and the second portion of the body region, respectively, and the channel drain region and the third portion of the body region are separated by the drift region. The semiconductor device according to any one of claims 1 to 7, wherein the channel drain region is of the first conductivity type. [Claim 10] The semiconductor device according to claim 9, wherein the doping concentration in the channel drain region is greater than the doping concentration in the drift region. [Claim 11] The distance from the edge of the channel drain region toward the second surface to the first surface is not greater than the distance from the bottom surface of the trench to the first surface, or The semiconductor device according to claim 9, wherein the distance from the edge of the channel drain region toward the second surface to the first surface is greater than the distance from the bottom surface of the trench to the first surface, and the channel drain region is adjacent to a part of the bottom surface of the trench. [Claim 12] The semiconductor layer further includes a channel drain region located between the first portion of the body region and the drift region, thereby the source region, the first portion of the body region and the channel drain region are sequentially adjacent along the direction from the first surface to the second surface, and all are adjacent to the first sidewall of the trench. The channel drain region is further adjacent to the drift region and the second portion of the body region, respectively, and the channel drain region and the third portion of the body region are separated by the drift region. Here, the channel drain region is of the first conductivity type, The distance from the edge of the channel drain region toward the second surface to the first surface is the sixth distance. The semiconductor device according to claim 5, wherein the sixth distance is greater than the second distance, and the third distance is greater than the sixth distance, thereby separating the channel drain region and the second sub-region by the drift region along the width direction of the trench gate structure. [Claim 13] The semiconductor layer further includes a body contact region extending in the direction from the first surface toward the second surface, and the body contact region is adjacent to the body region. The body contact region is adjacent to the source region or separated from it by the body region. The semiconductor device according to any one of claims 1 to 7, wherein the body contact region is of the second conductivity type. [Claim 14] Along the extending direction of the trench gate structure, a portion of the body contact area is adjacent to the second side wall of the trench, and there is a gap between the other portion of the body contact area and the second side wall, and the adjacent portion between the body contact area and the second side wall and the portion having the gap are alternately arranged along the extending direction of the trench gate structure. Alternatively, the semiconductor device according to claim 13, wherein both the body contact region and the second side wall are separated by the body region. [Claim 15] The trench gate structure includes the gate dielectric layer and the gate conductor, The gate dielectric layer covers the buffer layer located on the inner surface of the trench and also covers a portion of the buffer layer located on the first surface adjacent to the trench, and the trench extends in a direction from the first surface toward the second surface. A portion of the gate conductor is located in the trench, and the other portion extends outside the trench and covers the gate dielectric layer. Herein, the semiconductor device according to any one of claims 1 to 7, wherein the gate dielectric layer is located between the gate conductor and the buffer layer in order to separate the gate conductor and the buffer layer. [Claim 16] The semiconductor device according to any one of claims 1 to 7, wherein the semiconductor device is a metal-oxide semiconductor field-effect transistor or an insulated-gate bipolar transistor. [Claim 17] The semiconductor device according to any one of claims 4 to 7, wherein the source region extends between the two trench gate structures in a direction from the first side wall of one trench toward the second side wall of the other trench and is adjacent to the second portion of the body region.

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