Circuit board design method and circuit board

JP7873893B1Active Publication Date: 2026-06-15ITABASHI SEIKI CO LTD

Patent Information

Authority / Receiving Office: JP · JP
Patent Type: Patents
Current Assignee / Owner: ITABASHI SEIKI CO LTD
Filing Date: 2025-02-07
Publication Date: 2026-06-15

AI Technical Summary

⚠Technical Problem

Existing substrate designs face challenges in ensuring reliable interlayer circuit connections due to issues with through-hole plating and residue accumulation, leading to potential connection failures and substrate warping.

⚗Method used

The design method involves calculating overlapping regions on multiple layers and positioning interlayer circuits within these regions, using rolled conductors to increase connection area and volume, and eliminating direct connections to prevent peeling and warping, while utilizing electrolytic conductors for additional electrical conductivity.

🎯Benefits of technology

This approach enhances the strength and reliability of interlayer connections, improves heat dissipation, and reduces the risk of connection failures by increasing the connection area and volume of interlayer circuits, thereby improving the overall performance of electronic components.

✦ Generated by Eureka AI based on patent content.

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Abstract

This invention provides a substrate design method and substrate for suppressing interlayer circuit connection failures. [Solution] The present invention provides a method for designing a substrate 1A and a substrate, comprising an upper planar circuit 21 extending in the planar direction, a lower planar circuit 31 having the same potential as the upper planar circuit 21 extending in the planar direction, and an interlayer circuit 41 connecting the upper planar circuit 21 and the lower planar circuit 31 and consisting of a block extending in the planar direction, the method for designing a substrate 1A comprising: an overlapping region calculation step of calculating the overlapping region portion where the upper planar circuit 21 and the lower planar circuit 31 overlap when the substrate 1A is viewed from above; and an interlayer circuit design step of arranging and designing the interlayer circuit 41 in the overlapping region portion.

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