Robust half bridge

Abstract

A semiconductor transistor including a drain region, a plurality of source regions, and a plurality of gate regions interleaved with the source regions.

Description

[Technical Field] 【0001】 Related applications This application asserts the interests under § 119(e) of U.S. Patent Application No. 63343348, filed on 18 May 2022, and this disclosure is incorporated herein by reference. 【0002】 field Embodiments of the present invention relate to providing a half-bridge circuit with improved resistance to shoot-through. [Background technology] 【0003】 A common element in many circuits, especially high-power conversion circuits, is a half-H-bridge or half-bridge. A half-bridge comprises a first switch and a second switch, which are typically MOSFET transistors, connected in series at the junction that functions as the output node of the half-bridge. 【0004】 During operation, a first MOSFET transistor, conventionally called a high-side (HS) transistor or switch, is connected to the high-voltage terminal of the power source, and a second MOSFET transistor, conventionally called a low-side (LS) transistor or switch, is connected to the low-voltage terminal of the power source. Dedicated HS and LS gate drivers are connected to the gates of the HS and LS transistors, respectively, to control the transistors to be ON (closed) and conductive, or OFF (open) and non-conductive. A load is connected between the output node of the half-bridge and the low-voltage terminal of the power source. When the HS gate driver controls the HS transistor to ON and the LS driver controls the LS transistor to OFF, the output node of the half-bridge is connected to the voltage "V" at the high-voltage terminal. HSThe voltage rises to "V", and we can say that the half-bridge is ON, the load is connected to the HS terminal of the power supply, and the power supply supplies current and power to the load. When the gate driver controls the HS transistor to OFF and the LS transistor to ON, the half-bridge node is at the voltage of the low voltage terminal of the power supply "V". LS When it drops to "", we can say that the half-bridge is OFF, and the power supply stops supplying current and power to the load. To prevent a shoot-through rush of current flowing through the half-bridge, which could short out and damage the power supply and / or components of the circuit that has the power supply, the HS and LS gate drivers are controlled synchronously so that when one transistor is ON, the other is OFF. 【0005】 Because the switching time of the HS and LS transistors is always affected by jitter, the gate drive is synchronized before switching the half-bridge between the ON and OFF states to help protect the power supply from short circuits. This controls both transistors to be OFF for a short period called a dead time period or simply dead time. However, even when protected by dead time pause, when switching the half-bridge between the dead time and the ON state, a voltage surge in the LS transistor of the half-bridge may generate a voltage at the gate of the LS transistor, causing the LS transistor to turn ON while the HS transistor is ON, resulting in a half-bridge shoot-through. [Overview of the Initiative] 【0006】 One embodiment of the present disclosure relates to providing a half-bridge with improved immunity to shoot-through. To provide enhanced immunity, according to an embodiment of the present disclosure, the LS transistor is formed to have a gate region and a plurality of interleaved source regions that are operable to control the current to the same drain region. When the source regions are electrically connected in parallel to form a composite source and the gate region is electrically connected in parallel to form a composite gate, the interleaved source and gate regions provide the LS transistor with a relatively large built-in gate-source capacitance connected between the composite gate and composite source by a relatively low impedance current channel. The large built-in capacitance mitigates the voltage amplitude between the gate and source and operates to reduce the probability of shoot-through when the half-bridge switches from dead time to ON. 【0007】 This summary is provided to introduce, in a simplified form, a selection of concepts that will be further described in the detailed description below. This summary is not intended to identify any major or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. [Brief explanation of the drawing] 【0008】 Non-limiting examples of embodiments of the present invention are described below with reference to the drawings accompanying the invention, which are listed later in this paragraph. Identical structures, elements, or parts appearing in more than one drawing are generally given the same number in all drawings in which they appear. In the drawings of embodiments of this disclosure, labels displaying icons representing a given feature may be used to refer to that feature. The dimensions of components and features shown in the drawings have been selected for convenience and clarity of presentation and are not necessarily shown to scale. 【0009】 [Figure 1] Figure 1 schematically shows a half-bridge using prior art. [Figure 2] Figures 2A - 2D schematically show the operation of the half - bridge shown in FIG. 1 when cycling between the dead - time according to the prior art and the interleaved ON and OFF states. [Figure 3A] FIG. 3A schematically shows an enlarged view of the half - bridge shown in FIG. 2A after switching from the dead - time state to the ON state according to the prior art. [Figure 3B] FIG. 3B schematically shows the half - bridge shown in FIG. 3A with a shunt capacitor for reducing the probability of shoot - through according to the prior art. [Figure 4] FIG. schematically shows the half - bridge shown in FIG. 3A with a low - side transistor having a relatively large built - in capacitance to reduce the probability of shoot - through according to an embodiment of the present disclosure. [Figure 5] Figures 5A - 5B schematically show modifications added to the structure of the LS transistor optionally used in the half - bridge to reduce the probability of shoot - through according to an embodiment of the present disclosure. [Figure 6] Figures 6A - 6B schematically show a transistor having a source region and a gate region that completely surround the drain region of the transistor according to an embodiment of the present disclosure. [Figure 7] Figures 7A - 7D schematically show a transistor switching die including a plurality of transistors according to an embodiment of the present disclosure. 【Mode for Carrying Out the Invention】 【0010】 In the description, unless otherwise specified, adjectives such as “substantially” and “about” modifying the condition or relational characteristics of one or more features of the embodiments of the Disclosure are understood to mean that the condition or characteristic is defined within the permissible limits of the operation of the embodiments in the intended use. Whenever a general term in the Disclosure is illustrated by reference to an exemplary example or a list of exemplary examples, the one or more examples referenced are by non-exclusive exemplary examples of the general term, and the general term is not intended to be limited to the specific exemplary one or more examples referenced. The phrase “in one embodiment” is used to introduce consideration of configurations that are illustrative of possible embodiments of the Disclosure, but are not necessarily essential, whether or not they are associated with permissives such as “may,” “optionally,” or “as an example.” Each of the verbs “comprise,” “include,” and “have,” as well as their conjugations, is used to indicate that one or more objects of a verb are not necessarily a complete list of components, elements, or parts of one or more subjects of a verb. Unless otherwise indicated, the word “or” in this specification and in the claims is considered to be inclusive rather than exclusive, indicating at least one item, or any combination of two or more items to which it is joined. 【0011】 Figure 1 schematically shows a conventional half-bridge 10 common to many conversion circuits. The half-bridge 10 comprises a high-side switch QHS-12 and a low-side switch QLS-13, which are generally MOSFET transistors, connected in series at a junction 15 that functions as the output node of the half-bridge 10. Each transistor has a source S, a drain D, and a gate G. A high-side gate driver HS_driver 16 is connected between the gate G and source S of transistor QHS-12 and controls the voltage difference between the source and gate to control QHS-12 to be ON (closed) and conductive, or OFF (open) and non-conductive. Similarly, a low-side gate driver LS_driver 17 is connected between the source S and gate G of low-side transistor QLS-13 and controls the low-side transistor to be ON or OFF. In this figure, it is shown that the half-bridge 10 is connected to a load L and the high-voltage terminal 20 of a high-voltage power supply VS, which supplies voltage HV+ to the high-voltage terminal 20 and voltage HV- to the low-voltage terminal 25. As an example, it is assumed that transistors QHS-12 and QLS-13 are n-channel transistors, with the drain D of transistor QHS-12 connected to the high-voltage terminal 20 supplying voltage HV+, and the source S of transistor QLS-13 connected to the low-voltage terminal 25 supplying voltage HV-. The load L is connected between the output node 15 of the half-bridge 10 and the low-voltage terminal 25 of the power supply VS. 【0012】 Figure 1 shows the halfbridge 10 ON when the high-side gate driver HS-16 controls transistor QHS-12 to ON (switch closed) and the low-side driver LS-17 controls transistor QLS-13 to OFF (switch open). As a result of the halfbridge 10 being ON, output node 15 is set to the voltage HV+ supplied by terminal 20, and power supply VS drives the current represented by the dashed arrow 45 through load L. 【0013】 Figures 2A to 2D schematically illustrate how the HS-driver 16 and LS-driver 17 control transistors QHS-12 and QLS-13 to turn the halfbridge 10 ON and OFF, alternatingly connecting and disconnecting the load L to voltage HV+ through a sequence of conventional halfbridge ON and OFF states with a dead time period, thereby powering the load L with pulses of current. The timeline 47 along the bottom of Figure 2A shows the ON state of the halfbridge 10 and the current 45 driving through the load L, as also shown in Figure 1. Figure 2B shows the halfbridge 10 during a dead time period in which both QHS-12 and QLS-12 are OFF, following the ON state of the halfbridge 10 shown in Figure 2A. When switching to the dead time, a transient decaying current, represented by the dashed line 50 supported by parasitic inductance and capacitance, flows through the load L for a limited time. Figure 2C schematically shows that the halfbridge is turned OFF by gate drivers 16 and 17, which control transistor QHS-12 to OFF and transistor QLS-13 to ON, respectively, and the dead time shown in Figure 2D continues. In the OFF state, the halfbridge node 15 drops to the low voltage HV- of terminal 25 of the power supply VS, there is no voltage drop across the load L, and the power supply VS stops supplying current and power to the load. 【0014】 Figure 3A schematically shows the details of the half-bridge 10 related to the operation of the half-bridge and illustrates the behavior of the half-bridge that can cause harmful current shoot-through and ringing of the voltage applied to the load L when the half-bridge switches from dead time (Figure 2D) to ON (Figure 2A). 【0015】 Transistor QHS-12 has parasitic capacitance CdgHS, C gsCharacterized by HS and CdsHS, the QHS-package-51 has internal impedances ZgIN / H and ZkIN / H, through which electrical connections can be made from outside the die to the gate G and source S of the transistor, respectively. The HS-driver 16 is connected to the gate G and source S of transistor QHS-12 via the respective impedances ZgEx / H and ZkEx / H located outside the QHS-package-51. ZgEx / H and ZkEx / H generally have the characteristics of conductive traces connecting the HS-driver and transistor QHS-12 on the printed circuit board (PCB) on which the HS-driver and transistor QHS-12 are mounted. Similarly, transistor QLS-13 has parasitic capacitances CdgLS, C gs Characterized by LS and CdsLS, the LS-driver 17 is contained within a QLS-package-52 having internal impedances ZgIN / L and ZkIN / L, through which electrical connections can be made to the gate G and source S of transistor QLS-13, respectively. The LS-driver 17 is connected to transistor QLS-13 via ZgEx / L and ZkEx / L located outside the QLS-package-51. 【0016】 When transistor QHS-12 is turned ON to switch between the dead time of half-bridge 10 (Figure 2D) and the ON state of the half-bridge (Figure 2A), a transient current represented by block arrow 70 flows from power supply VS through transistor QHS-12 to QLS-13. Transient current 70 branches into transient currents represented by dashed lines 71 and 72, and the parasitic capacitances CdgLS and C of transistor QLS-13 are affected. gs The currents LS and CdsLS are charged and flow toward the low-voltage terminal 25 of the power supply VS. A portion of the current 71 73 flows to the power supply VS through the impedances ZgIN / L, ZgEx / L, ZkEx / L, and ZkIN / L. The transient current 70 and its transient tributary currents 71, 72, and 73 flow through the parasitic capacitor C gsA voltage that raises LS causes a voltage to occur at the gate G of QLS-13, creating a voltage difference between the gate G and the source S of transistor QLS-12, operating to turn on the transistor and causing a potentially harmful shoot-through current. 【0017】 Prior art attempts to prevent shoot-through and / or slight ringing at output node 15 generally involve providing capacitor 75 in parallel with transistor QLS-13, as schematically shown in FIG. 3B. As a result of structural constraints, capacitor 75 is implemented outside of QLS-package-52 and operates as a low impedance that shorts external impedances ZgEX / L and ZkEx / L. When switching between dead time and ON, transient currents 70’, 71’, 72’ and 73’ occur, but as schematically shown in FIG. 3B, substantially no current flows through ZgEX / L and ZkEx / L. Capacitor 75 reduces the overall impedance between the gate G and the source S of QLS-13 to an impedance generated by the impedance inside QLS-package 52 in parallel with capacitor 75. When the impedance is reduced, the voltage generated between the gate G and the source S of transistor QLS-13 is advantageously limited when half-bridge 10 switches from dead time to the ON state. gs A capacitor 75 is provided in parallel with LS. As a result of structural constraints, capacitor 75 is implemented outside of QLS-package-52 and operates as a low impedance that shorts external impedances ZgEX / L and ZkEx / L. When switching between dead time and ON, transient currents 70’, 71’, 72’ and 73’ occur, but as schematically shown in FIG. 3B, substantially no current flows through ZgEX / L and ZkEx / L. Capacitor 75 reduces the overall impedance between the gate G and the source S of QLS-13 to an impedance generated by the impedance inside QLS-package 52 in parallel with capacitor 75. When the impedance is reduced, the voltage generated between the gate G and the source S of transistor QLS-13 is advantageously limited when half-bridge 10 switches from dead time to the ON state. 【0018】 FIG. 4 schematically shows a half-bridge 80 configured to exhibit relatively robust immunity to shoot-through according to an embodiment of the present disclosure. Half-bridge 80 includes a transistor QLS-85 having a “built-in” capacitor 90 that shorts not only external impedances ZgEX / L and ZkEx / L but also internal impedances ZgIN / L and ZkIN / L of QLS package 52. When switching between dead time and ON, transient currents 70 * , 71 * and 72 * and 73 *Although this occurs, as schematically shown in Figure 4, virtually no transient current flows through the series impedances ZgIN / L, ZgEx / L, ZkEx / L, and ZkIN / L. The internal capacitor 90 has ratio C gs By increasing LS / CgdLS, the impedance between the gate G and source S of the transistor QLS-85 is increased by the parasitic impedance C gs The impedance is effectively reduced to that of the capacitor 90 in parallel with LS. gs The increase in LS / CgdLS and the reduction in impedance favorably limit the voltage between the gate G and source S of transistor QLS-85 when the half-bridge 10 switches from dead time to ON state to a substantially lower voltage than that provided by the prior art configuration shown in Figure 3B. gs LS also enables faster switching, thus improving overall efficiency. 【0019】 Figures 5A and 5B schematically illustrate the differences between a conventional transistor such as QLS-13 included in the half-bridge 10 and a transistor QLS-85 according to an embodiment of the disclosure, which may be included in the half-bridge 80 of Figure 4 to mitigate or prevent shoot-through current within the half-bridge. 【0020】 The conventional transistor QLS-13 shown in Figure 5A has a source region and a drain region superimposed by source electrodes and gate electrodes labeled S and D, respectively, and a gate region superimposed by a gate electrode G for controlling the resistance between the source and drain regions and the current I indicated by the block arrow. For convenience of presentation, in Figures 5A and 5B, the source, drain, and gate regions are not explicitly shown or distinguished from their respective electrodes, and are referred to by the same labels S, D, and G as the electrodes. Parasitic capacitance C gs Cdg and Cdg connect the source region S to the gate region G, and the gate region G to the drain region D, respectively. The parasitic capacitance Cds connects the drain region D to the source region S. 【0021】 On the other hand, the transistor QLS-85, as shown in Figure 5B, is configured according to one embodiment of the present disclosure to have a plurality (optionally three) of source regions S interleaved with three gate regions G that are operable to control resistance between the source region S and the same drain region D and thereby current. Each source region S has an internal parasitic capacitance C gs * It is coupled to the adjacent gate region G. The three source regions are electrically connected in parallel to form a composite source S. C The three gate regions are electrically connected in parallel to form a composite gate G C This forms the composite source S shown in Figure 5B. C and composite gate G C Five internal parasitic capacities C are arranged in parallel between them. gs * Assuming that all parasitic capacitances are substantially the same size, the dashed line represents the capacitor C. GS All internal parasitic capacities, as roughly represented by the composite source S C and composite gate G C Bridge the transistor QLS-85 and apply approximately 5 × C gs * It provides a relatively large internal parasitic capacitance equal to . The large internal parasitic capacitance shorts the internal impedance of the transistor, operating to provide a half-bridge 80 with enhanced protection against shoot-through. 【0022】 As schematically shown in Figure 5B, in QLS-85, N gate-source pairs generally have an internal parasitic capacitance C GS Approximately (2N-1)C gs * Note that it may be approximated as equal to C. GS The magnitude of C may be adjusted as needed for a given circuit and the surrounding stray capacitance and / or inductance to which the circuit may be exposed, by selecting an appropriate number N of gate-source pairs. GSThe size of the internal capacity may also be adjusted by forming gate-source pairs having different sizes and / or distances between the gate and source regions of different gate-source pairs, or distances between different gate-source pairs. For example, if the first gate-source pair has a lateral range Lgs substantially parallel to the y-axis of the coordinate system shown in Figure 5B, and an additional N' gate-source pairs have, optionally, a lateral range αLgs on the same y-axis, where 0 ≤ α ≤ 1, then C GS is, equation C GS ~C gs * +2N'αC gs * It may also be approximated by the following equation. The last equation also assumes that the distance along the x-axis between all gate regions and the source regions adjacent to each of them is the same for all gate regions. 【0023】 Figures 6A and 6B schematically show top views of transistors 100 and 120, respectively, according to one embodiment of the present disclosure, which have relatively large built-in parasitic capacitance and may be advantageously functioning as low-side switch transistors in a half-bridge. Transistors 100 and 120 are characterized by a source-gate pair having a substantially rounded rectangular shape that optionally completely encloses the drain of the transistor. Transistor 100 shown in Figure 6A has a single drain 106 surrounded by a source-gate pair comprising a peripheral source 102 and a nested peripheral gate 104 inside the peripheral source 102. Ignoring the rounded edges of the peripheral 102 and peripheral gate 104, one side of the peripheral source-gate pair is approximately C gs * Assuming it has a "one-sided" stray capacitance equal to C, the built-in parasitic capacitance of transistor 100 is C. GS The total is approximately 2C gs * It may be estimated to be equal to . 【0024】 Similarly, transistor 120 shown in Figure 6B has two peripheral source-gate pairs and is approximately (2 × 3)C. gs* Total parasitic capacity C equal to GS It may be presumed that it has a built-in stray capacitance C. Generally, a transistor having N periphery source-gate pairs surrounding a single drain according to embodiments of the present disclosure has a built-in stray capacitance C. GS =2(2N-1)C gs * It may be assumed that it has the following: The surrounding function of a peripheral source-gate pair generally operates at about twice the built-in stray capacitance of a source-gate pair that is similar in structure and shape to one side of the peripheral source-gate pair. 【0025】 Figures 7A to 7D show schematic diagrams of a composite switching device, also called a switching die, comprising a plurality of transistors 100 (Figure 6A) or 120 (Figure 6B), according to an embodiment of the present disclosure. 【0026】 Figure 7A shows a schematic diagram of a switching die 200 having an array 202 having multiple transistors 100. In addition to the array 202, the switching die 200 has an array 204 of built-in capacitors 206 along the underside of the array 202, each capacitor 206 having a central electrode 208 surrounded by a peripheral electrode 207. Conductive traces 221 connect the peripheral electrodes 207 of all capacitors 206 and the sources 102 of all transistors 100 in parallel. Conductive traces 222 connect the central electrodes 208 of all capacitors 206 and the gates 104 of all transistors 100 in parallel. Conductive traces 223 connect the drains 106 of all transistors 100 in parallel. 【0027】 Figure 7B shows a schematic diagram of a switching die 250 comprising an array 252 of internal capacitors 206 and multiple interleaved transistors 100. Conductive traces 271 connect the peripheral electrodes 207 of all capacitors 206 and the sources 102 of all transistors 100 in parallel. Conductive traces 272 connect the central electrodes 208 of all capacitors 206 and the gates 104 of all transistors 100 in parallel. Conductive traces 273 connect the drains 106 of all transistors 100 in parallel. 【0028】 Figure 7C shows a schematic diagram of a switching die 300 having an array 302 with multiple transistors 100. In addition to the array 302, the switching die 200 has an array 304 of built-in capacitors 306 along the underside of the array 302, each capacitor 306 having a central electrode 308 that is surrounded by a peripheral electrode 307 and extends along its entire length along the underside. Conductive traces 321 connect the peripheral electrodes 307 of all capacitors 306 and the sources 102 of all transistors 100 in parallel. Conductive traces 322 connect the central electrode 308 of all capacitors 306 and the gates 104 of all transistors 100 in parallel. Conductive traces 323 connect the drains 306 of all transistors 100 in parallel. 【0029】 Figure 7D shows a schematic diagram of a switching die 350 comprising a plurality of transistors 120 (Figure 6B) according to one embodiment of the present disclosure. Conductive trace 371 connects the sources 102 of all transistors 120 in parallel. Conductive trace 373 connects the drains 106 of all transistors 120 in parallel. 【0030】 The descriptions of embodiments of the present invention in this application are provided for illustrative purposes only and are not intended to limit the scope of the invention. The described embodiments have different features, and not all of them are required in all embodiments of the invention. Some embodiments utilize only some of the features or possible combinations of features. Modifications of the described embodiments of the invention, and embodiments of the invention including different combinations of features shown in the described embodiments, will be conceivable to those skilled in the art. The scope of the invention is limited solely by the claims.

Claims

[Claim 1] A drain electrode placed on the drain region, Multiple source electrodes, each overlapping the source region, Multiple gate electrodes interleaved alternately with the source electrode The gate electrodes of the plurality of gate electrodes are located between one of the plurality of source electrodes and the drain electrode. A lateral semiconductor transistor in which the number of gate electrodes is equal to the number of source electrodes so as to form a plurality of gate-source pairs, and each gate-source pair comprises a gate electrode and a source electrode adjacent to the gate electrode on the far side of the gate electrode with respect to the drain electrode. [Claim 2] The lateral semiconductor transistor according to claim 1, wherein all of the source electrodes are electrically connected together. [Claim 3] The transverse semiconductor transistor according to claim 2, wherein all of the gate electrodes are electrically connected together. [Claim 4] The built-in internal gate-source capacitance C of the aforementioned semiconductor transistor ＧＳ The transverse semiconductor transistor according to claim 1, wherein the sum of the gate-source pairs is an increasing function of the number of gate-source pairs. [Claim 5] The lateral semiconductor transistor according to claim 4, wherein at least two gate-source pairs have different lateral ranges. [Claim 6] The lateral semiconductor transistor according to claim 4, wherein the distance between the source electrode and the gate electrode is different for at least two of the plurality of gate-source pairs. [Claim 7] The transverse semiconductor transistor according to claim 4, wherein the distance between the gate electrode and the source electrode is the same for all of the gate-source pairs of the plurality of gate-source pairs. [Claim 8] The transverse semiconductor transistor according to claim 7, wherein the gate-source pairs are equally spaced. [Claim 9] N is equal to the number of gate-source pairs, and the capacitance between the gate electrode and the source electrode is C. ｇｓ ＊ When represented by C ＧＳ However, approximately (2N-1)C ｇｓ ＊ A lateral semiconductor transistor according to claim 8, which is equal to the one described above. [Claim 10] The semiconductor transistor according to claim 1, wherein the source electrodes of the plurality of source electrodes are peripheral source electrodes that completely surround the drain electrode. [Claim 11] The lateral semiconductor transistor according to claim 10, wherein the gate electrodes of the plurality of gate electrodes are peripheral gate electrodes that completely surround the drain electrode. [Claim 12] Drain electrode and A plurality of peripheral source electrodes, each of which completely surrounds the drain electrode, The aforementioned peripheral source electrode and a plurality of peripheral gate electrodes interleaved alternately A lateral semiconductor transistor comprising, wherein each peripheral gate electrode completely surrounds the drain electrode and is located in a region surrounded by one of the plurality of peripheral source electrodes. [Claim 13] A semiconductor switching die comprising a plurality of lateral semiconductor transistors as described in claim 1. [Claim 14] The semiconductor switching die according to claim 13, wherein the source electrodes of the plurality of lateral semiconductor transistors are electrically connected in parallel. [Claim 15] The semiconductor switching die according to claim 13, wherein the gate electrodes of the plurality of lateral semiconductor transistors are electrically connected in parallel. [Claim 16] The semiconductor switching die according to claim 13, wherein the drain electrodes of the plurality of lateral semiconductor transistors are electrically connected in parallel. [Claim 17] A half-bridge having a low-side switch comprising a lateral semiconductor transistor as described in claim 1. [Claim 18] A semiconductor switching die comprising a plurality of lateral semiconductor transistors as described in Claim 12.

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