Semiconductor devices, electronic equipment

Abstract

To provide a semiconductor device that is fine, consumes less power, has high reliability, and has a small off-state current.SOLUTION: A manufacturing method of a semiconductor device, includes steps of: forming a second insulation body 302 onto a first insulation body 301; forming a third insulation body 303 onto the second insulation body; forming an open part reached to the second insulation body on the third insulation body and forming a first conductor 310 in the open part and onto the third insulation body; removing a second conductor 311 and the first conductor that are positioned at a position higher than an upper surface of the third insulation body by performing a grinding processing after the second conductor onto the first conductor is formed; and further forming a third conductor 312 onto the second conductor. An end part of the first conductor is the same of or lower than a height of the end part of the open part at the end part of the open part. The height of the upper surface of the second conductor is the same of or higher than the end part of the first conductor. A wiring layer prevents an oxidation of the second conductor by having the first and third conductors that surround and cover a bottom surface, a side surface, and the upper surface of the second conductor.SELECTED DRAWING: Figure 1

Description

[Technical Field] 【0001】 This invention relates to a product, a method, or a method of manufacturing; or to a process, a machine , relating to manufacture or composition of matter. In particular One aspect of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, an imaging device, and a memory device. The present invention relates to a method for driving them, or a method for manufacturing them. In particular, one aspect of the present invention relates to an acid This invention relates to semiconductor devices, display devices, or light-emitting devices having a crystalline semiconductor. 【0002】 In this specification and other documents, a semiconductor device refers to a device that can function by utilizing semiconductor properties. This refers to all types of equipment, including display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic devices. The device may contain semiconductor equipment. [Background technology] 【0003】 The silicon used in transistor semiconductors is either amorphous silicon or polycrystalline silicon, depending on the application. The terms "recon" and "converter" are used interchangeably. For example, transistors that make up large display devices are used in different applications. It is preferable to use amorphous silicon for which film deposition technology on large-area substrates has been established. The transistors that make up a high-performance display device, which integrates the drive circuit and the pixel section, are high power transistors. It is preferable to use polycrystalline silicon that can be used to fabricate transistors with field effect mobility. Polycrystalline silicon is produced by heat treatment at high temperatures or laser treatment of amorphous silicon. Methods for forming it are known. 【0004】 In recent years, transistors using oxide semiconductors (typically In-Ga-Zn oxide) have been developed. Development is becoming more active. Transistors using oxide semiconductors are being developed using amorphous silicon. It has characteristics that differ from transistors and transistors using polycrystalline silicon. For example, a display device that uses an oxide semiconductor transistor has low power consumption. It is known. 【0005】 Furthermore, transistors using oxide semiconductors exhibit extremely low leakage current in the non-conductive state. It is known that the leakage current of transistors using oxide semiconductors is low. Low-power CPUs that utilize this characteristic have been disclosed (see Patent Document 1). . 【0006】 To reduce power consumption through power gating, transistors using oxide semiconductors are used. It is preferable that the zista has normally-off electrical characteristics. One method for controlling the threshold voltage of an inverter to achieve normally-off electrical characteristics is as follows: A floating gate is placed in the region overlapping with the oxide semiconductor, and the floating gate A method for injecting negative fixed charges is disclosed (see Patent Document 2). 【0007】 Oxide semiconductors can be formed into thin films using methods such as sputtering, making them suitable for use in large-scale display devices. It can be used in transistors. Furthermore, transistors using oxide semiconductors are... Because it has high field-effect mobility, a high-performance display device is formed by integrating the drive circuit and the pixel section. It can be achieved. Furthermore, transistors using amorphous silicon, or using polycrystalline silicon... Since it is possible to modify and utilize some of the transistor production equipment, capital investment is possible. There are also advantages to being able to control it. 【0008】 The history of oxide semiconductors is long, with the synthesis of crystalline In-Ga-Zn oxide being reported in 1985. (See Non-Patent Document 1.) Also, in 1995, In-Ga-Zn oxide was It adopts a homologous structure, InGaO3(ZnO) m Described using the empirical formula (where m is a natural number). It has been reported that this is the case (see Non-Patent Document 2). 【0009】 Furthermore, in 1995, a transistor using oxide semiconductors was invented, and its electrical... The characteristics are disclosed (see Patent Document 3). 【0010】 Furthermore, in 2014, a report was published on transistors using crystalline oxide semiconductors. (See Non-Patent Documents 3 and 4.) Here, it is possible to mass-produce and excellent CAAC-OS (C-Axis Aligned C) has superior electrical characteristics and reliability. Transistors using rystalline oxide semiconductor A case has been reported. 【0011】 With the miniaturization of integrated circuits, the resistance and multi-layering of wiring layers are progressing, making the planarization of wiring layers essential. It has become indispensable. To solve these problems, a deceptive method of embedding the wiring layer in the interlayer insulating film is used. The N method is widely used (see Non-Patent Document 5). [Prior art documents] [Patent Documents] 【0012】 [Patent Document 1] Japanese Patent Publication No. 2012-257187 [Patent Document 2] Japanese Patent Publication No. 2013-247143 [Patent Document 3] Special Publication No. 11-505377 【Non-licensed literature】 【0013】 [Non-licensed document 1] N. Kimizuka, and T. Mohri: Journal of Solid State Chemistry, 1985, volume 60, p.382-p.384 【Non-licensed Document 2】 N. Kimizuka, M. Isobe, and M. Nakamura: Journal of Solid State Chemistry, 1995, volume 116, p.170-p.178 [Non-licensed document 3] S. Yamazaki, T. Hirohashi, M. Takahashi, S. Adachi, M. Tsubuku, J. Koezuka, K. Okazaki, Y. Kanzaki, H. Matsukizono, S. Kaneko, S. Mori, and T. Matsuo: Journal of the Society for Information Display, 2014, Volume 22, issue 1, p.55-p.67 【Non-licensed Document 4】 S. Yamazaki, T. Atsumi, K. Dairiki, K. Okazaki, and N. Kimizuka: ECS Journal of Solid State Science and Technology, 2014, volume 3, Issue 9, p.Q3012-p.Q3022 【Non-licensed Document 5】 CW Kaanta, SG Bombardier, WJ Cote, WR Hill, G. Kerszykowski, HS Landis, DJ Poinchexter, CW Pollard, GH Ross, JG Ryan, S. Wolff and JE Cronin: ``Dual Damascene: A ULSI Wiring Technology'', VMIC Conference, (1991), p.144-p.152 [Overview of the Initiative] [Problems that the invention aims to solve] 【0014】 One aspect of the present invention aims to provide a miniature semiconductor device. Or, one aspect of the present invention aims to provide a miniature semiconductor device. The objective of this invention is to provide a semiconductor device with low power consumption. Alternatively, one aspect of this invention The object of this embodiment is to provide a highly reliable semiconductor device. Or, one embodiment of the present invention. The objective is to provide a semiconductor device with low off-current. Or, one aspect of the present invention. The objective is to provide a semiconductor device that can retain data over a long period of time. Alternatively, one aspect of the present invention aims to provide a novel semiconductor device. One aspect of the present invention aims to provide an eye-friendly display device. One aspect of this invention aims to provide a semiconductor device having a transparent semiconductor. 【0015】 Furthermore, the description of these problems does not preclude the existence of other problems. The embodiment does not need to solve all of these problems. Other problems are addressed in the specification. This will become clear from the description in the drawings, claims, etc., and the specification, drawings, claims Based on these descriptions, it is possible to identify other issues besides those mentioned above. [Means for solving the problem] 【0016】 (1) One aspect of the present invention involves forming a second insulator on a first insulator, and forming a third insulator on the second insulator. A film is formed on the edge, and an opening is formed in the third insulator that reaches the second insulator, and on the third insulator and After forming the opening and a first conductive film, and then forming a second conductive film on the first conductive film, By performing the polishing process, the second conductor and the first conductor, which are located higher than the upper surface of the third insulator, are polished. The conductor and the end of the first conductor are removed, and the end of the opening is at the end of the opening The height of the upper surface of the second conductor is the same as or lower than the height of the edge of the first conductor. This is a method for manufacturing a wiring layer characterized by the following: (2) Alternatively, in one aspect of the present invention, a second insulator is formed on a first insulator, and on the second insulator A third insulator is formed, and an opening is formed in the third insulator that reaches the second insulator. A first conductive film is formed on the edge and the opening, and a second conductive film is formed on the first conductive film. Afterward, by performing a polishing process, the second conductor, which is located higher than the upper surface of the third insulator, Then, the first conductor and the third conductor are removed, and the second conductor and the third insulator are formed on top of the third conductor. The film is applied, and the third conductor is polished until it reaches the third insulator, and the end of the first conductor At the edge of the opening, the height is the same as or lower than the height of the edge of the opening, and the height of the upper surface of the second conductor. The height of the third conductor is the same as or lower than the height of the end of the first conductor, and the upper surface of the second conductor is The wiring layer is characterized by being in contact with the end of the first conductor at the end of the opening. This is the manufacturing method. (3) Alternatively, one aspect of the present invention has a second insulator on a first insulator, and the second insulator has a second insulator on it. It has three insulators, the third insulator having an opening that reaches the second insulator, the opening is open It comprises a first conductor in contact with the side and bottom surfaces of the opening, and a second conductor on the first conductor. Furthermore, the end of the first conductor is at the same height as or lower than the height of the end of the opening. The height of the upper surface of the second conductor is the same as or lower than the height of the edge of the first conductor. This is the wiring layer. (4) Alternatively, one aspect of the present invention has a second insulator on a first insulator, and the second insulator has a second insulator on it. It has three insulators, the third insulator having an opening that reaches the second insulator, the opening is open A first conductor in contact with the side and bottom surfaces of the opening, a second conductor on the first conductor, and a second A third conductor is located on the conductor, and the end of the first conductor is at the end of the opening. The height of the top surface of the second conductor is the same as or lower than the height of the edge of the opening, and the height of the top surface of the first conductor is the same as the height of the edge of the first conductor. The third conductor is the same height as or lower than the second conductor, and is in contact with the upper surface of the second conductor, at the end of the opening. The wiring layer is characterized by being in contact with the end of the first conductor. (5) Alternatively, in one aspect of the present invention, the first conductor is less permeable to oxygen than the second conductor. The wiring layer described in (3) is characterized by the following. (6) Alternatively, in one aspect of the present invention, the first and third conductors are more acidic than the second conductor. The wiring layer described in (4) is characterized by being difficult for elements to pass through. [Effects of the Invention] 【0017】 We can provide miniature semiconductor devices, or semiconductor devices with low power consumption. It is possible to do so. Or, it is possible to provide highly reliable semiconductor devices. Or, We can provide semiconductor devices with low current, or devices that can retain data over long periods of time. We can provide semiconductor devices that can be used. Or, we can provide novel semiconductor devices. It can be provided. Or, it can provide an eye-friendly display device. Or, transparent A semiconductor device having a bright semiconductor can be provided. 【0018】 Furthermore, the description of these effects does not preclude the existence of other effects. The embodiment does not need to have all of these effects. Other effects are described in the specification. This will become clear from the descriptions in the drawings and claims, and the specification, drawings, and claims will be clear from the description, drawings, and claims. It is possible to extract other effects from any of these descriptions. [Brief explanation of the drawing] 【0019】 [Figure 1] A cross-sectional view of a wiring layer according to one aspect of the present invention. [Figure 2] A diagram illustrating a method for creating a wiring layer according to one aspect of the present invention. [Figure 3] A top view and a cross-sectional view of a transistor according to one aspect of the present invention. [Figure 4] A diagram showing a top view, a cross-sectional view, and an example of a band of a transistor according to one aspect of the present invention. [Figure 5] High-resolution TEM image with Cs correction in cross-section of CAAC-OS, and schematic cross-sectional diagram of CAAC-OS. [Figure 6] High-resolution TEM image with Cs correction in the plane of CAAC-OS. [Figure 7] A diagram illustrating the XRD structural analysis of CAAC-OS and single-crystal oxide semiconductors. [Figure 8] A figure showing the electron diffraction pattern of CAAC-OS. [Figure 9]A diagram showing the changes in the crystalline structure of In-Ga-Zn oxide due to electron irradiation. [Figure 10] Circuit diagram and cross-sectional view of a semiconductor device according to one aspect of the present invention. [Figure 11] A cross-sectional view of a semiconductor device according to one aspect of the present invention. [Figure 12] A cross-sectional view of a semiconductor device according to one aspect of the present invention. [Figure 13] A top view showing a semiconductor device according to one aspect of the present invention. [Figure 14] Block diagram showing a semiconductor device according to one aspect of the present invention. [Figure 15] A cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 16] A cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 17] A perspective view and a cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 18] An example of the configuration of an RF tag according to one aspect of the present invention. [Figure 19] Block diagram of a semiconductor device according to one aspect of the present invention. [Figure 20] A circuit diagram illustrating a storage device according to one aspect of the present invention. [Figure 21] A circuit diagram, a top view, and a cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 22] A circuit diagram and a cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 23] A figure showing an example of an electronic device according to one aspect of the present invention. [Figure 24] An example of the use of an RF tag according to one aspect of the present invention. [Figure 25] Cross-sectional STEM image of the example. [Figure 26] Figure showing the Id-Vg characteristics of the example. [Modes for carrying out the invention] 【0020】 Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Without departing from the spirit and scope of the present invention, its form and details may be changed in various ways. Those skilled in the art will readily understand that further improvements are possible. Therefore, the present invention can be implemented as follows: It is not to be interpreted as being limited to the description of the form. 【0021】 In the configuration of the invention described below, the same part or part having a similar function is included. The same reference numeral may be used consistently across different drawings, and explanations of its repetition may be omitted. Furthermore, when referring to similar functions, the hatch pattern is the same, and no specific designation is given. There is. 【0022】 Furthermore, the "source" and "drain" functions of a transistor are related to transistors with different polarities. When adopting a circuit, or when the direction of current changes during circuit operation, the configuration may be reversed. Therefore, in this specification, the terms "source" and "drain" are interchangeable. It may be used in this manner. 【0023】 In this specification, ordinal numbers such as "the first," "the second," etc., are used to avoid confusion of constituent elements. It should be noted that this is added for the purpose of providing a numerical limit, and is not intended to limit the number of items. 【0024】 In each figure described herein, the size, layer thickness, or area of ​​each component is clearly indicated. It may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. . 【0025】 A transistor is a type of semiconductor device that amplifies current and voltage, and controls conduction or non-conductivity. This enables switching operations and the like. The transistors used in this specification are IGFET(Insulated Gate Field Effect Transi) Storr) and Thin Film Transistor (TFT) Includes. 【0026】 Note that the words "membrane" and "layer" may differ in some cases or depending on the situation. Therefore, they can be interchanged. For example, the term "conductive layer" can be replaced with "conductive film." In some cases, it may be possible to change the term to "insulating film". Alternatively, for example, the term "insulating film" may be used. In some cases, it may be possible to change the term to "insulating layer." 【0027】 Furthermore, unless otherwise specified in this specification, off-current refers to the state in which a transistor is off. This refers to the drain current when the device is in a non-conductive state or interrupted state. The off state is: Unless otherwise specified, in an n-channel transistor, the voltage between the gate and source is Vgs When the threshold voltage Vth is lower than the gate and source of a p-channel transistor, This refers to a state where the voltage Vgs between the two is higher than the threshold voltage Vth. For example, an n-channel type The off-current of a transistor is the voltage between the gate and source, Vgs, and the threshold voltage Vth. Sometimes it refers to the drain current when it is even lower. 【0028】 The off-current of a transistor may depend on Vgs. Therefore, the off-current of the transistor The statement that the current is less than or equal to I means that there exists a value of Vgs such that the transistor's off-current is less than or equal to I. It is sometimes said that the off-current of a transistor is the off-state at a given Vgs. An off state within a predetermined Vgs range, or a sufficiently reduced off current, can be obtained. This can sometimes refer to the off-current in the off state of Vgs, etc. 【0029】 As an example, the threshold voltage Vth is 0.5 V, and the drain current when Vgs is 0.5 V is 1×10 -9 A, and the drain current when Vgs is 0.1 V is 1×10 -13 A, and the drain current when Vgs is -0.5 V is 1×10 -19 A, and when Vgs is -0.8 V, the drain current is 1×10 -22 A. Assume an n-channel transistor. The drain current of the transistor is, when Vgs is -0.5 V, or, when Vgs is in the range of -0.5 V to -0.8 V, 1×10 A or less -19 because of this, in some cases, the off-current of the transistor is 1×10 A or less. Since there exists a Vgs for which the drain current of the transistor becomes 1×10 -19 A or less, in some cases, the off-current of the transistor is 1×10 A or less. -22 For this reason , in some cases, the off-current of the transistor is 1×10 -22 A or less. 【0030】 In this specification, the off-current of a transistor having a channel width W may be represented by the current value flowing per channel width W. Also, it may be represented by the current value flowing per a predetermined channel width (for example, 1 μm). In the latter case, the unit of the off-current may be represented by a unit having the dimension of current / length (for example, A / μm). 【0031】 The off-current of a transistor may depend on temperature. In this specification, the off-current represents, when there is no particular description, the off-current at room temperature, 60 °C, 85 °C, 95 °C, or 125 °C. Or, the reliability of a semiconductor device or the like including the transistor is guaranteed [[ID=,50]] ​​​The temperature at which the transistor is used, or the temperature at which the semiconductor device containing the transistor is used (for example) In some cases, it may represent the off-current at any one temperature between 5°C and 35°C. The off-current of the zista is less than or equal to I, meaning that at room temperature, 60°C, 85°C, 95°C, 125°C, etc. The temperature at which the reliability of the semiconductor device, etc., containing the transistor is guaranteed, or the transistor The temperature at which semiconductor devices containing DISTROs are used (for example, any one temperature between 5°C and 35°C) At a given temperature, there exists a value of Vgs such that the transistor's off-current is less than or equal to I. It may refer to something. 【0032】 The off-current of a transistor may depend on the voltage Vds between the drain and source. In this specification, unless otherwise specified, the off-current is defined as Vds of 0.1V, 0.8V, and 1 V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or This may represent the off-current at 20V, or the semiconductor containing the transistor. Vds that guarantees the reliability of the device, or semiconductor device containing the transistor. It can sometimes represent the off-current at Vds used in a transistor. The current is less than or equal to I, meaning that Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2V. 0.5V, 3V, 3.3V, 10V, 12V, 16V, 20V, the transistor in question is included. The reliability of the semiconductor device, etc., is guaranteed by Vds, or the semiconductor containing the transistor. In devices such as body equipment, the off-current of the transistor at Vds is less than or equal to I. This can sometimes refer to the existence of a value for gs. 【0033】 In this specification, the term "leakage current" may be used interchangeably with "off current." 【0034】 In this specification, off-current refers to, for example, the current when a transistor is in the off state. It can sometimes refer to the current flowing between the valve and the drain. 【0035】 In this specification, "parallel" means that two straight lines are positioned at an angle of -10° or more and 10° or less. This refers to a state where the temperature is in a certain condition. Therefore, it also includes cases where the temperature is between -5° and 5°. A "row" refers to a state where two straight lines are positioned at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are positioned at an angle of 80° to 100°. Therefore, it also includes cases where the angle is between 85° and 95°. Also, "approximately perpendicular" means two This refers to a state in which two straight lines are arranged at an angle between 60° and 120°. 【0036】 Furthermore, in this specification, if a crystal is trigonal or rhombohedral, it will be represented as a hexagonal crystal system. . 【0037】 (Embodiment 1) In this embodiment, the method for fabricating the wiring layer will be explained using Figures 2(A), (B), and (C). do. 【0038】 First, an insulator 302 is deposited on the insulator 301, and then an insulator 303 is deposited on the insulator 302. (See Figure 2(A)). Next, grooves are formed in the insulator 303 that reach the insulator 302. Grooves include, for example, holes and openings (see Figure 2(B)). Groove formation is wet. Etching can be used, but dry etching is preferable for microfabrication. Furthermore, the insulator 302 is an etching strip when etching the insulator 303 to form grooves. It is preferable to select an insulator that functions as a frosted film. For example, an insulator 3 that forms grooves. If a silicon oxide film is used for 03, the insulator 302 is a silicon nitride film or aluminum oxide film. A titanium film is recommended. 【0039】 In this embodiment, an insulator 302 is used, but depending on the application, the insulator 302 may be replaced with another material. Conductors or semiconductors may also be used. 【0040】 After forming the grooves, a conductive film 310 is deposited. The conductive film 310 has the function of being impermeable to oxygen. It is desirable that the conductor 311 has a function that makes it less permeable to oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used. The conductor 310 can be deposited using methods such as sputtering, CVD, and ALD. Next, a conductive film 311 is formed on the conductive film 310 (see Figure 2(C)). Conductive film 31 1. Low resistivity is desirable. For example, tantalum, tungsten, titanium, molybdenum. Butene, aluminum, copper, molybdenum-tungsten alloy, etc. can be used. The method for forming the electrolytic body 311 can be the same as the method used for forming the conductive body 310. 【0041】 Next, Chemical Mechanical Polishing By performing CMP (Chemical Purification), the conductors 311 and 310 on the insulator 303 are removed. As a result, the conductors 311 and 310 remain only in the grooves, as shown in Figure 1(A). The wiring layer shown can be formed. 【0042】 The end of the conductor 310 is at the same height as or lower than the groove at the end of the groove, but it is conductive. The upper surface of body 311 is at the same height as, or lower than, the edge of the conductor 310. This is formed by the difference in polishing speed between the electrolytic body 310 and the conductor 311. In this example, the polishing speed of conductor 311 is faster than that of conductor 310. 【0043】 When using a conductive material as a wiring layer or electrode layer, the surrounding oxide film, for example, silica oxide Care must be taken regarding the oxidation of conductors caused by oxygen contained in the film, etc. This can lead to an increase in resistivity, potentially reducing the functionality of the wiring layer or electrode layer. Alternatively, peeling or cracking of the conductor's own film due to volume increase, or peeling of the film around the conductor. This can cause crumbling and cracking, so it is important to prevent this. 【0044】 According to the present invention, as shown in Figure 1(A), the conductor 310 is located on the bottom surface and side surface of the conductor 311. This creates a structure that covers the oxide film, preventing direct contact with it. This prevents oxygen from entering the conductor 311. This can suppress heavy damage such as film peeling due to volume increase associated with oxidation of the conductor 311. This can prevent major malfunctions from occurring. 【0045】 In this embodiment, the substrate is not shown, but for example, a simple material such as silicon or germanium could be used. Semiconductor substrates, or silicon carbide, silicon germanium, gallium arsenide, phosphate Compound semiconductor substrates made from materials such as zinc oxide and gallium oxide can be used. Yes, it is possible. Alternatively, an insulating substrate such as quartz or glass can be used, and the present implementation can be carried out on top of it. A wiring layer fabricated in this form can be used. Alternatively, elements such as transistors and capacitors can be used. The above-mentioned substrate having the above-mentioned features can be used. 【0046】 This embodiment can be appropriately combined with other embodiments described herein, at least in part. They can be implemented together. 【0047】 (Embodiment 2) In this embodiment, a method for fabricating a wiring layer as shown in Figure 1(B) will be described. 【0048】 In Embodiment 1, CMP is performed, and the bottom surface and sides of the conductor 311 are covered with the conductor. Although a conductive material was fabricated, in this embodiment, a conductive material 312 is further deposited on the conductive material 311. It is desirable that the conductive material 312 has the same function as the conductor 310 in that it is impermeable to oxygen. Alternatively, it is desirable that the conductor 312 has a function that makes it less permeable to oxygen than the conductor 311. For example, tantalum nitride, tungsten nitride, titanium nitride, etc., can be used. Alternatively, the same conductor as conductor 310 may be used. 【0049】 Next, CMP is performed on the conductor 312 until it reaches the insulator 303, as shown in Figure 1(B). A wiring layer having a structure in which conductors 310, 311, and 312 are embedded in grooves. It can be formed. 【0050】 The wiring layer shown in Figure 1(B) consists of conductor 310 and conductor 312, with the bottom surface of conductor 311 and The structure surrounds and covers the sides and top, preventing oxidation of the conductor 311. Furthermore, in this embodiment, compared to Embodiment 1, CMP is performed one more time. Therefore, the top surface of the wiring layer becomes flatter, and the coverage of the film above the wiring layer becomes greater. This is a positive development. 【0051】 In this embodiment, as in Embodiment 1, the substrate is not shown, but for example, silicon Single-component semiconductor substrates such as germanium, or silicon carbide, silicon germanium, etc. Compound semiconductors made from materials such as gallium oxide, indium phosphide, zinc oxide, and gallium oxide. A substrate can be used. Alternatively, an insulating substrate such as quartz or glass can also be used. This can be done, and the wiring layer made in this embodiment can be used above it. Alternatively, The above-mentioned substrate having elements such as a zista and a capacitor can be used. 【0052】 This embodiment can be appropriately combined with other embodiments described herein, at least in part. They can be implemented together. 【0053】 (Embodiment 3) This embodiment shows an example in which the transistor uses the wiring layer described in Embodiment 1. Figure 3(A) is a top view of the transistor according to the present invention. The dashed line X in Figure 3(A) Figure 3(B) shows a cross-section of 1-X2, which is a cross-sectional view of the transistor in the channel length direction, and is a single-point chain. Figure 3(C) shows a cross-sectional view along the line Y1-Y2, which corresponds to a cross-sectional view of the transistor in the channel width direction. ru. 【0054】 The substrate 300 is, for example, a single semiconductor substrate such as silicon or germanium, or silicon carbide Cone, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide Compound semiconductor substrates made from materials such as crystalline silica or glass can be used. Insulating substrates such as those mentioned above can also be used. 【0055】 An insulator 301 is formed on the substrate 300. The insulator 301 is a silicon oxide film, an oxide film, etc. Silicon nitride film, silicon nitride oxide film, silicon nitride film, aluminum oxide film, aluminum nitride A nium film, hafnium oxide film, etc., can be used. The film deposition method is thermal oxidation, CV Methods such as D-method, sputtering, ALD method, plasma oxidation, and plasma nitriding can be used. ru. 【0056】 Next, an insulating film 302 is formed on the insulating film 301. Then, a conductive film 3 is formed in the same manner as in Embodiment 1. 10 deposits a wiring layer that covers the bottom and sides of the conductor 311. A wiring layer consisting of conductor 310 and conductor 311 is used as the gate electrode. 【0057】 An insulator 304 is formed on the conductor 311 and on the insulator 303. The same film as the insulator 301 described above can be used, and the same film formation method can be used. Yes, it is possible. Preferably, an insulator with properties that make it difficult for oxygen to permeate should be used. For example. Aluminum oxide films or aluminum nitride films can be used. This allows for the use of conductive materials. The bottom and sides of 11 are wrapped in a conductor 310, and the top surface is covered with an insulator 304. This suppresses oxidation of the conductor 311, and the volume increase associated with oxidation is reduced in the conductor 311. This can prevent serious problems such as membrane lifting or delamination of the surrounding membrane. 【0058】 An insulator 305 is deposited on the insulator 304. Note that the insulator 305 is an insulator containing excess oxygen. It would be preferable if this were the case. 【0059】 For example, an insulator containing excess oxygen is an insulator that has the function of releasing oxygen through heat treatment. For example, a silicon oxide film containing excess oxygen can release oxygen through heat treatment, etc. It is a silicon oxide film that allows oxygen to move through the film. Therefore, the insulator 305 allows oxygen to move through the film. It is a capable insulator. That is, insulator 305 should be an insulator that has oxygen permeability. For example Therefore, the insulator 305 should be an insulator with higher oxygen permeability than the semiconductor 320. 【0060】 An insulator containing excess oxygen may have the function of reducing oxygen deficiencies in semiconductor 320. In semiconductor 320, oxygen vacancies can become hole traps, etc. Also, at the site of the oxygen vacancy... The presence of hydrogen can generate electrons, which act as carriers. Therefore, semiconductors By reducing oxygen deficiency in the body, stable electrical characteristics are imparted to the transistor. It is possible. 【0061】 Here, insulators that release oxygen through heat treatment are identified by TDS analysis as having a temperature of 100°C or higher and 70°C. 1 × 10⁻¹⁰ 18 atom / cm 3 The above is 1 x 10 19 atoms / cm 3 or more, or 1 x 10 20 atoms / cm 3 It may also release the above amount of oxygen (calculated in terms of the number of oxygen atoms). 【0062】 The method for measuring oxygen release using TDS analysis is described below. 【0063】 The total amount of gas released when a sample is subjected to TDS analysis is proportional to the integral value of the ionic intensity of the released gas. For example, by comparing it with a standard sample, the total amount of gas released can be calculated. 【0064】 For example, the TDS analysis results of a silicon substrate containing hydrogen at a predetermined density, which is a standard sample, and From the TDS analysis results of the measured sample, the amount of oxygen molecules released from the measured sample (N O2 ) is the formula shown below This can be determined by the following: Here, the gas detected with a mass-to-charge ratio of 32 obtained by TDS analysis Assume that all of these originate from oxygen molecules. The mass-to-charge ratio of CH3OH is 32, but the existence of We will not consider this here as it has a low probability. Also, the isotope of the oxygen atom with mass number 17 Regarding oxygen atoms and oxygen molecules containing oxygen atoms with a mass number of 18, the abundance in nature The rate is so small that it will not be considered. 【0065】 N O2 =N H2 / S H2 ×S O2 It becomes ×α. 【0066】 N H2 This value represents the density of hydrogen molecules detached from the standard sample. H2 The standard test This is the integral value of the ionic intensity when the material is analyzed by TDS. Here, the reference value of the standard sample is N H2 / S H2 Let's assume that. S O2 This is the integral value of the ionic intensity when the sample is subjected to TDS analysis. Yes, it exists. α is a coefficient that affects the ionic strength in TDS analysis. For details of the formula shown above, see below. For further information, please refer to Japanese Patent Publication No. 6-275697. The amount of oxygen released is determined by the Electronics Science Using the EMD-WA1000S / W temperature-controlled desorption analyzer manufactured by Gaku Corporation, the standard sample was: For example, 1 x 10 16 atoms / cm 2 Measurements were taken using a silicon substrate containing hydrogen atoms. . 【0067】 Furthermore, in TDS analysis, some oxygen is detected as oxygen atoms. Oxygen molecules and oxygen atoms The ratio of these can be calculated from the ionization rate of oxygen molecules. Note that α above represents the oxygen component. Because it includes the ionization rate of the oxygen atom, by evaluating the amount of oxygen molecule released, the amount of oxygen atom released can be determined. Even if it's there, it can still be estimated. 【0068】 Note N O2 This is the amount of oxygen molecules released. The amount released when converted to oxygen atoms is the amount of oxygen molecules. This will be twice the amount released. 【0069】 Alternatively, insulators that release oxygen through heat treatment may contain peroxide radicals. Specifically, the spin density caused by peroxide radicals is 5 × 10⁻⁶ 17 spins / cm 3 This means the above. Furthermore, for insulators containing peroxide radicals, the g value in ESR is 2. It may also have asymmetrical signals in the vicinity of 01. 【0070】 Alternatively, an insulator containing excess oxygen is silicon oxide (SiO₂) with excess oxygen. X (X>2) It may be present. Silicon oxide (SiO₂) with excess oxygen. X (X>2)) represents the number of silicon atoms It contains more than twice the amount of oxygen atoms per unit volume. The number of electrons and oxygen atoms can be determined by Rutherford backscattering (RBS). These are values ​​measured by scalar-scattering spectrometry. 【0071】 Insulator 305 functions as a gate insulator for the transistor. Insulator 305 is above A film similar to the insulator 301 described above, and a similar film formation method, can be used. Figure 3(B) In (C), the insulator 305 is a single layer, but a multilayer film may also be used. For example, A hafnium oxide film is deposited on a silicon oxide film, and then silicon oxide is deposited on the hafnium oxide film. A three-layer structure with an oxide film can also be formed. The hafnium oxide film is used as an electron trapping layer. The threshold voltage of the transistor may be controlled. Alternatively, it can be made into a multilayer structure. The film combinations can be arbitrarily selected from those similar to those for the insulator 301 described above. ru. 【0072】 A semiconductor 320 is deposited on the insulator 305, and a conductive film is deposited on the semiconductor 320, and then... The conductive material in the channel formation region is etched to form the channel formation region. Next, the conductive material is etched. The semiconductor 320 is etched to form a pair of source or drain electrodes 312. A stacked island-like region is formed, consisting of a, 312b, and semiconductor 320. 【0073】 Alternatively, the conductor and semiconductor 320 may be etched before the formation of the channel formation region. After forming a stacked island-like region consisting of an electroluminescent body and a semiconductor 320, the channel formation region portion The conductive material is etched to form a channel region and a pair of source or drain electrodes. A combination of 312a and 312b may be formed. 【0074】 Source electrode or drain electrode 312a and source electrode or drain electrode 312b Tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum tungsten Stainless steel alloys, tungsten nitride, titanium nitride, tantalum nitride, etc., can be used. Alternatively, a multilayer structure can be used. Film deposition methods include sputtering, CVD, and AL. Method D or similar methods can be used. 【0075】 Next, source electrode or drain electrode 312a and source electrode or drain electrode 3 An insulator 306 is deposited so as to cover 12b and the channel formation region. The insulator 306 is a transistor It functions as the second gate insulator of the Zistor. Insulator 306 is described in the same way as insulator 305. To pour a drink. 【0076】 By placing semiconductors above and below semiconductor 320, the electrical characteristics of the transistor can be improved. In some cases, this is possible. Below, we will discuss semiconductor 320 and the semiconductors arranged above and below it. This will be explained in detail using Figures 4(A) and 4(B). 【0077】 Figure 4(A) shows the semiconductor 32 in the channel length direction of the transistor shown in Figure 3(B). This is a magnified cross-sectional view of the vicinity of 0. Figure 4(B) shows the transistor shown in Figure 3(C). This is an enlarged cross-sectional view of the vicinity of semiconductor 320 in the channel width direction. 【0078】 In the transistor structure shown in Figures 4(A) and 4(B), the insulator 305 and semiconductor 32 A semiconductor 320a is placed between 0 and 0. Also, the drain electrode or source electrode A semiconductor 320c is placed between 312a and 312b and the insulator 306. 【0079】 Semiconductor 320 is, for example, an oxide semiconductor containing indium. Furthermore, when indium is included, the carrier mobility (electron mobility) increases. Also, semiconductor 32 0 preferably contains element M. Element M is preferably aluminum, gallium, or y. This may include thorium or tin. Other elements that can be applied to element M include boron. Silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum These include cerium, neodymium, hafnium, tantalum, and tungsten. However, elements In some cases, element M can be a combination of multiple elements as mentioned above. Element M can be, for example, acid It is an element with a high bonding energy with oxygen. For example, indium has a high bonding energy with oxygen. It is an element with a higher energy gap than [another element]. Alternatively, element M is, for example, the energy gap of an oxide semiconductor. It is an element that has the function of increasing [the value]. Furthermore, it is preferable that semiconductor 320 contains zinc. Oxide semiconductors can sometimes crystallize more easily when zinc is present. 【0080】 However, semiconductor 320 is not limited to indium-containing oxide semiconductors. For example, zinc tin oxide, gallium tin oxide, etc., do not contain indium and contain zinc. These include oxide semiconductors containing gallium, oxide semiconductors containing tin, and so on. That's fine too. 【0081】 Semiconductor 320 uses, for example, an oxide with a large energy gap. The energy gap is, for example, between 2.5 eV and 4.2 eV, preferably 2.8 eV. The voltage should be 3.8 eV or less, and more preferably 3 eV to 3.5 eV. 【0082】 For example, semiconductor 320a and semiconductor 320c are composed of elements other than oxygen that make up semiconductor 320. It is an oxide semiconductor composed of one or more elements, or two or more elements. Semiconductor 320a and semiconductor 320c are composed of one or more elements other than oxygen, or two or more elements. Therefore, the interface between semiconductor 320a and semiconductor 320, and the interface between semiconductor 320 and semiconductor Defect levels are less likely to form at the interface with 320c. 【0083】 Semiconductors 320a, 320, and 320c contain at least indium. This is preferable. Furthermore, when semiconductor 320a is an In-M-Zn oxide, the sum of In and M is 1 When set to 00 atomic%, preferably In is less than 50 atomic and M is 50%. Higher than tomic%, and more preferably In is less than 25atomic% and M is 75at Assume it is higher than omic%. Also, when semiconductor 320 is In-M-Zn oxide, In is When the sum of M is 100 atomic%, preferably In is 25 atomic. The M is higher, M is less than 75 atomic%, and more preferably In is more than 34 atomic%. The concentration is high, and M is less than 66 atomic%. Also, semiconductor 320c is In-M-Zn oxidation. When the sum of In and M is 100 atomic%, preferably In is 50 Less than atomic%, M is higher than 50 atomic%, and more preferably In is 25a The tomic percentage should be less than 75, and M should be higher than 75 atomic percent. Note that semiconductor 320c is semi-atomic. You may use the same type of oxide as conductor 320a. However, semiconductor 320a or / There are cases where semiconductor 320c does not need to contain indium. For example, semiconductor 32 0a and / or semiconductor 320c may be gallium oxide. The number of atoms of each element contained in semiconductor 20a, semiconductor 320, and semiconductor 320c are in simple integer ratios. It's okay if it doesn't become that. 【0084】 Semiconductor 320 is an oxide with a higher electron affinity than semiconductors 320a and 320c. For example, semiconductor 320 is used if it is more electrically charged than semiconductor 320a and semiconductor 320c. Child affinity between 0.07 eV and 1.3 eV, preferably between 0.1 eV and 0.7 eV. Furthermore, an oxide with a voltage of 0.15 eV or more and 0.4 eV or less is used. Affinity is the energy difference between the vacuum level and the lower end of the conduction band. 【0085】 Furthermore, indium gallium oxide has low electron affinity and high oxygen blocking properties. Therefore, it is preferable that semiconductor 320c contains indium gallium oxide. The ratio of particles [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more, and further Preferably, it should be 90% or more. 【0086】 When a gate voltage is applied at this time, semiconductors 320a, 320, and 320c Of these, a channel is formed in semiconductor 320, which has a high electron affinity. 【0087】 Here, between semiconductor 320a and semiconductor 320, It may have a mixed region. Also, between semiconductor 320 and semiconductor 320c, It may have a mixed region of 320 and semiconductor 320c. In the mixed region, the defect level density is It becomes lower. Therefore, the laminate of semiconductor 320a, semiconductor 320, and semiconductor 320c is Near each interface, the energy changes continuously (also called a continuous junction). This is the diagram (see Figure 4(C)). Note that semiconductor 320a, semiconductor 320 and semiconductor In some cases, 320c may not allow for clear identification of each interface. 【0088】 At this time, the electrons are in semiconductor 320, not in semiconductor 320a and semiconductor 320c. It mainly moves along the interface between semiconductor 320a and semiconductor 320. The defect level density at the interface between semiconductor 320 and semiconductor 320c is reduced. This reduces the obstruction of electron movement in semiconductor 320, and transistor The on-current can be increased. 【0089】 The on-current of a transistor can be increased as the factors that hinder electron movement are reduced. Yes, it is possible. For example, if there are no factors hindering electron movement, it is estimated that electrons will move efficiently. Electron movement is inhibited, for example, when the physical irregularities of the channel-forming region are large. It will be done. 【0090】 To increase the on-current of the transistor, for example, the top or bottom surface of the semiconductor 320 ( The root mean square of the surface to be formed, in this case semiconductor 320a), in a 1 μm × 1 μm area. (RMS: Root Mean Square) Roughness is less than 1 nm, preferably 0.6 nm. The wavelength should be less than m, more preferably less than 0.5 nm, and more preferably less than 0.4 nm. Furthermore, the average surface roughness (also called Ra) in a 1 μm × 1 μm area is less than 1 nm. More preferably less than 0.6 nm, more preferably less than 0.5 nm, and more preferably 0.4 nm It should be less than [value]. Also, the maximum height difference (also called PV) within a 1 μm × 1 μm area. ) is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, more preferably The size should be less than 7 nm. RMS roughness, Ra, and PV are measured by SII Nanotech. Measurements are taken using a scanning probe microscope system such as the SPA-500 manufactured by Nology Corporation. It is possible. 【0091】 Alternatively, for example, if the defect level density in the region where the channel is formed is high, electron transfer may occur. Movement is inhibited. 【0092】 For example, semiconductor 320 has an oxygen deficiency (V O Also written as: ) If present, oxygen deficiency site Hydrogen can enter and form a donor level. Below, water is used at oxygen-deficient sites. The state in which the element is incorporated is V O It is sometimes written as H. O H scatters electrons, so This is a factor that reduces the on-current of the inverter. Also, hydrogen will enter the oxygen-deficient site. It is more stable when oxygen is present. Therefore, by reducing the oxygen deficiency in semiconductor 320... This can sometimes increase the on-current of the transistor. 【0093】 Furthermore, a high defect level density in the channel formation region can affect the electrical characteristics of the transistor. It can be caused to fluctuate. For example, if a defect level becomes a carrier source, the transistor The threshold voltage may be varied. 【0094】 To reduce oxygen deficiencies in semiconductor 320, for example, excess oxygen contained in insulator 305 One method involves moving the semiconductor to semiconductor 320 via semiconductor 320a. In this case, semiconductor Body 320a is preferably an oxygen-permeable layer (a layer that allows oxygen to pass through or permeate). It seems so. 【0095】 Furthermore, in order to increase the on-current of the transistor, the thickness of the semiconductor 320c should be as small as possible. Preferably, less than 10 nm, preferably 5 nm or less, and even more preferably 3 nm or less. The semiconductor 320c has the region. On the other hand, the semiconductor 320c has channel formation To the semiconductor 320, elements other than oxygen that constitute the adjacent insulator (hydrogen, silicon, etc.) It has a function to block the entry of ) to a certain extent. Therefore, semiconductor 320c is It is preferable to have a thickness of 0.3 nm or more, preferably 1 nm or more. More preferably, the semiconductor 320c has a region with a thickness of 2 nm or more. The conductor 320c suppresses the outward diffusion of oxygen released from the insulator 305, etc. It is preferable that it has the property of blocking elements. 【0096】 Furthermore, in order to increase reliability, semiconductor 320a should be thick and semiconductor 320c should be thin. Preferred. For example, 10 nm or more, preferably 20 nm or more, and more preferably 40 nm. More preferably, the semiconductor 320a has a region with a thickness of 60 nm or more. By increasing the thickness of semiconductor 320a, the interface between the adjacent insulator and semiconductor 320a The distance to the semiconductor 320 where the channel is formed can be increased. However, the semiconductor equipment Because the productivity of the installation may decrease, for example, 200 nm or less, preferably 120 nm. More preferably, the semiconductor 320a has a region with a thickness of 80 nm or less. . 【0097】 For example, between semiconductor 320 and semiconductor 320a, for example, secondary ion mass spectrometry (SI In MS (Secondary Ion Mass Spectrometry), 1 x 10 16 atoms / cm 3 The above 1 x 10 19 atoms / cm 3 The following are preferred 1 x 10 16 atoms / cm 3 The above 5 x 10 18 atoms / cm 3 The following are further preferred Or 1 x 10 16 atoms / cm 3 The above 2 x 10 18 atoms / cm 3 The following series It has a region where the concentration is high. Also, between semiconductor 320 and semiconductor 320c, SIMS In this case, 1 × 10 16atoms / cm 3 The above 1 x 10 19 atoms / cm 3 below, Preferably 1 × 10 16 atoms / cm 3 The above 5 x 10 18 atoms / cm 3 below, More preferably 1 × 10 16 atoms / cm 3 The above 2 x 10 18 atoms / cm 3 It has a region with the following silicon concentrations. 【0098】 Furthermore, in order to reduce the hydrogen concentration of semiconductor 320, semiconductor 320a and semiconductor 320c It is preferable to reduce the hydrogen concentration. Semiconductors 320a and 320c are used in SIMS. Let 1 x 10 16 atoms / cm 3 The above 2 x 10 20 atoms / cm 3 Below is good Mashiku is 1 x 10 16 atoms / cm 3 The above 5 x 10 19 atoms / cm 3 The following, Preferably 1 x 10 16 atoms / cm 3 The above 1 x 10 19 atoms / cm 3 below More preferably 1 × 10 16 atoms / cm 3 The above 5 x 10 18 atoms / cm 3 It has a region with the following hydrogen concentrations. Also, in order to reduce the nitrogen concentration of semiconductor 320 It is preferable to reduce the nitrogen concentration of semiconductor 320a and semiconductor 320c. a and semiconductor 320c are 1 × 10 in SIMS. 15 atoms / cm 3Above 5 ×10 19 atoms / cm 3 Below, preferably 1×10 15 atoms / cm 3 Above 5 ×10 18 atoms / cm 3 Below, more preferably 1×10 15 atoms / cm 3 Above Above 1×10 18 atoms / cm 3 Below, even more preferably 1×10 15 atoms / c m 3 Above 5×10 17 atoms / cm 3 It has a region with a nitrogen concentration below the above. 【0099】 The above three-layer structure is an example. For example, a two-layer structure without semiconductor 320a or semiconductor 320c is also acceptable. Or, on or under semiconductor 320a, or on or under semiconductor 320c, a four-layer structure having any one of the semiconductors exemplified as semiconductor 320a, semiconductor 320, and semiconductor 320c is also acceptable. Or, on any two or more of the above, under, above, and under semiconductor 320a, a semiconductor exemplified as semiconductor 320a, semiconductor 320, and semiconductor 320c having any one of them, an n-layer structure (n is an integer of 5 or more) is also acceptable. ​​​​​​​​​​​​​​​​​​Crystalline Oxide Semiconductor, Polycrystalline Oxide Semiconductor Examples include conductors, microcrystalline oxide semiconductors, and amorphous oxide semiconductors. 【0102】 From another perspective, oxide semiconductors include amorphous oxide semiconductors and other crystalline oxide semiconductors. They can be divided into conductors and crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single-crystal oxide semiconductors and CAAC-O Examples include S, polycrystalline oxide semiconductors, and microcrystalline oxide semiconductors. 【0103】 First, let's explain CAAC-OS. Note that CAAC-OS is referred to as CANC(CA This is called an oxide semiconductor having xis (aligned nanocrystals). It's also possible. 【0104】 CAAC-OS is an oxide semiconductor having multiple c-axis oriented crystalline portions (also called pellets). It is a type of conductor. 【0105】 Transmission Electron Microscope (TEM) A composite analysis image of the bright-field image and diffraction pattern of CAAC-OS (high-frequency analysis) is obtained using the scope. Also called a resolving TEM image.) When observing this image, multiple pellets can be identified. In high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries, are visible. It cannot be clearly confirmed that CAAC-OS occurs at the grain boundaries. This means that a decrease in electron mobility due to this is less likely to occur. 【0106】 The following describes CAAC-OS observed by TEM. Figure 5(A) shows the results. This shows a high-resolution TEM image of a cross-section of CAAC-OS observed from a direction approximately parallel to the material surface. For observing high-resolution TEM images, spherical aberration correction is necessary. The Corrector function was used. High-resolution TEM images using spherical aberration correction function were obtained. This is called a Cs-corrected high-resolution TEM image. Acquisition of Cs-corrected high-resolution TEM images is, for example, in Japan. This is done using an atomic-resolution analytical electron microscope such as the JEM-ARM200F manufactured by Denshi Co., Ltd. It is possible. 【0107】 Figure 5(B) shows a magnified Cs-corrected high-resolution TEM image of region (1) in Figure 5(A). Figure 5 (B) confirms that in the pellet, metal atoms are arranged in layers. The arrangement of atoms in each layer is determined by the surface (also called the surface to be formed) or above the CAAC-OS film. It reflects the surface irregularities and is parallel to the surface or top surface of the CAAC-OS. 【0108】 As shown in Figure 5(B), CAAC-OS has a characteristic atomic arrangement. Figure 5(C) shows The characteristic atomic arrangement is shown with auxiliary lines. From Figures 5(B) and 5(C), The size of each pellet is approximately 1 nm to 3 nm, and the inclination between pellets is It can be seen that the size of the resulting gap is about 0.8 nm. Therefore, the pellet They can also be called nanocrystals (nc). 【0109】 Here, based on the Cs-corrected high-resolution TEM image, the pellets of CAAC-OS on substrate 5120 are... The arrangement of the To 5100 can be schematically represented as a structure resembling stacked bricks or blocks. (See Figure 5(D).) The inclination between the pellets observed in Figure 5(C) is The area where this is occurring corresponds to region 5161 shown in Figure 5(D). 【0110】 Further, FIG. 6(A) shows a Cs-corrected high-resolution TEM image of the plane of CAAC-OS observed from a direction substantially perpendicular to the sample surface. The Cs-corrected high-resolution TEM images of regions (1), (2), and (3) in FIG. 6(A) are shown in FIGS. 6(B), 6(C), and 6(D), respectively. From FIGS. 6(B), 6(C), and 6(D), it can be confirmed that the metal atoms in the pellet are arranged in a triangular, square, or hexagonal shape. However, no regularity is observed in the arrangement of the metal atoms between different pellets. Next, CAAC-OS analyzed by X-ray diffraction (XRD) will be described. For example, when performing a structural analysis of CAAC-OS having a crystal of InGaZnO4 by the out-of-plane method, as shown in FIG. 7(A), a peak may appear near a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the crystal of InGaZnO4, it can be confirmed that the crystal of CAAC-OS has c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. In the structural analysis of CAAC-OS by the out-of-plane method, in addition to the peak near 2θ of 31°, a peak may also appear near 2θ of 36°. The peak near 2θ of 36° indicates that a part of CAAC-OS contains crystals without c-axis orientation. A more preferable CAAC-OS shows a peak near 2θ of 31° and does not show a peak near 2θ of 36° in the structural analysis by the out-of-plane method. On the other hand, for CAAC-OS, when X-rays are incident from a direction substantially perpendicular to the c-axis, in-plane 【0111】 【0112】 【0113】 ​ Structural analysis using the e method reveals a peak near 2θ = 56°. This peak corresponds to In It is attributed to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is 56 The sample is fixed in the vicinity of °, and the analysis is performed while rotating the sample around the normal vector of the sample surface as the axis (φ axis). Even after performing a φ scan, no clear peak appears, as shown in Figure 7(B). For a single-crystal oxide semiconductor of InGaZnO4, if 2θ is fixed to around 56°, the φ gap When this occurs, the peaks are attributed to the crystal plane equivalent to the (110) plane, as shown in Figure 7(C). Six of these are observed. Therefore, from structural analysis using XRD, CAAC-OS is a-axis. Furthermore, it can be confirmed that the orientation of the b-axis is irregular. 【0114】 Next, we will explain CAAC-OS analyzed by electron diffraction. For example, InGaZ For CAAC-OS having nO4 crystals, a probe with a diameter of 300 nm is placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern like the one shown in Figure 8(A) (limited field transmission electron diffraction pattern) is produced. (Also called a turn.) A diffracted pattern may appear. This diffraction pattern is due to the bonding of InGaZnO4. The crystal contains spots originating from the (009) plane. Therefore, electron diffraction also reveals C The pellets contained in AAC-OS have c-axis orientation, and the c-axis is approximately perpendicular to the surface being formed or the upper surface. It can be seen that it is facing in a straight direction. On the other hand, for the same sample, the probe diameter is perpendicular to the sample surface. Figure 8(B) shows the diffraction pattern when a 300 nm electron beam is incident on the device. A ring-shaped diffraction pattern is observed. Therefore, CAA can also be detected by electron diffraction. It can be seen that the a-axis and b-axis of the pellets contained in C-OS do not have any orientation. In Figure 8(B), the first ring is the (010) plane and (10) plane of the InGaZnO4 crystal. 0) This is thought to be caused by surfaces, etc. Also, the second ring in Figure 8(B) is (110) This is thought to be due to factors such as surface characteristics. 【0115】 Furthermore, CAAC-OS is an oxide semiconductor with a low defect level density. Examples include defects caused by impurities and oxygen deficiencies. Therefore, CAA C-OS can also be described as an oxide semiconductor with a low impurity concentration. Also, CAAC-OS It can also be described as an oxide semiconductor with few oxygen vacancies. 【0116】 Impurities contained in oxide semiconductors can act as carrier traps or carrier sources. In some cases, oxygen vacancies in oxide semiconductors can act as carrier traps, or water Capturing a primal can sometimes lead to the generation of a carrier. 【0117】 Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metals. There are elements, for example. For instance, oxygen is more abundant than the metallic elements that make up oxide semiconductors such as silicon. Elements with strong bonding forces can alter the atomic arrangement of oxide semiconductors by removing oxygen from them. It disrupts the crystallinity and causes a decrease in its properties. Also, heavy metals such as iron and nickel, argon, and nickel... Because carbon oxides and other elements have a large atomic radius (or molecular radius), they affect the atomic arrangement of oxide semiconductors. This disrupts the crystallinity and reduces its properties. 【0118】 Furthermore, oxide semiconductors with a low defect level density (few oxygen vacancies) have a low carrier density. Such oxide semiconductors can be processed using high-purity intrinsic or substantially high-purity intrinsic acid. It is called a monoxide semiconductor. CAAC-OS has a low impurity concentration and a low defect level density. That is, It is likely to become a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Therefore, CAA Transistors using C-OS exhibit an electrical characteristic where the threshold voltage is negative (normally). Also called "on." ) It rarely becomes [unclear]. Also, high-purity intrinsic or substantially high-purity intrinsic acid. Ion semiconductors have fewer carrier traps. Carriers are trapped in the carrier traps of oxide semiconductors. The charged particles take a long time to release, behaving almost like fixed charges. Yes, there is. Therefore, transients using oxide semiconductors with high impurity concentrations and high defect level densities are used. The sta may have unstable electrical characteristics. On the other hand, the transistor using CAAC-OS This results in a transistor with minimal fluctuations in electrical characteristics and high reliability. 【0119】 Furthermore, because CAAC-OS has a low defect level density, it is less susceptible to defects generated by light irradiation, etc. The rear is rarely captured by the defect level. Therefore, the tracer using CAAC-OS The radiator exhibits minimal changes in electrical properties due to irradiation with visible or ultraviolet light. 【0120】 Next, we will explain microcrystalline oxide semiconductors. 【0121】 Microcrystalline oxide semiconductors are regions where crystalline parts can be observed in high-resolution TEM images. It has regions where a clear crystalline structure cannot be identified. It is contained in microcrystalline oxide semiconductors. The crystalline portion is between 1 nm and 100 nm in size, or between 1 nm and 10 nm in size. This is often the case. In particular, microcrystals between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor having nanocrystals is called nc-OS (nanocrystalline It is called Oxide Semiconductor. nc-OS is, for example, high resolution. In TEM images, grain boundaries may not be clearly visible. Note that the nanocrystals are CAAC. -It may share the same origin as pellets in OS. Therefore, nc-O The crystalline portion of S is sometimes called a pellet. 【0122】 nc-OS is used in minute regions (for example, regions between 1 nm and 10 nm, especially between 1 nm and 3 nm). The atomic arrangement has periodicity in the region of less than nm. In addition, nc-OS has different pellets. No regularity in crystal orientation is observed between the layers. Therefore, no orientation is observed throughout the entire film. Therefore, depending on the analysis method, nc-OS may be indistinguishable from amorphous oxide semiconductors. For example, an XRD device that uses X-rays with a larger diameter than pellets compared to nc-OS. When structural analysis is performed using this method, the out-of-plane method shows that the crystal planes are visible. No peak is detected. Also, for nc-OS, the probe diameter is larger than the pellet (e.g. For example, when electron diffraction (also called limited-field electron diffraction) is performed using an electron beam of 50 nm or more, A diffraction pattern resembling a halo pattern is observed for nc-OS. Nanobeam electron diffraction using an electron beam with a probe diameter close to or smaller than the pellet size. When this is done, a spot is observed. Also, when nanobeam electron diffraction is performed on nc-OS In some cases, a region of high brightness can be observed in a circular (ring-shaped) pattern. Furthermore, phosphorus Multiple spots may be observed within a circular area. 【0123】 Thus, since there is no regularity in the crystal orientation between pellets (nanocrystals), nc- The OS has RANC (Random Aligned nanocrystals) Oxide semiconductors, or NANCs (Non-Aligned nanocrystals) It can also be called an oxide semiconductor having ). 【0124】 nc-OS is an oxide semiconductor with higher orderliness than amorphous oxide semiconductors. Therefore, nc-OS has a lower defect level density than amorphous oxide semiconductors. However, nc-OS There is no regularity in crystal orientation between different pellets. Therefore, nc-OS is CA Compared to AC-OS, the defect level density is higher. 【0125】 Next, we will explain amorphous oxide semiconductors. 【0126】 Amorphous oxide semiconductors are oxides in which the atomic arrangement in the film is irregular and which do not have crystalline regions. It is a semiconductor. One example is an oxide semiconductor that has an amorphous state, such as quartz. 【0127】 In amorphous oxide semiconductors, crystalline regions cannot be observed in high-resolution TEM images. 【0128】 When structural analysis of amorphous oxide semiconductors is performed using an XRD device, out-of-pl Analysis using the ANE method does not detect any peaks indicating crystal planes. Furthermore, amorphous oxide semiconductors... When electron diffraction is performed on a material, a halo pattern is observed. Furthermore, amorphous oxide semiconductors... In contrast, when nanobeam electron diffraction is performed, no spots are observed, and only a halo pattern is visible. It is measured. 【0129】 Various views have been expressed regarding amorphous structures. For example, some argue that the atomic arrangement has absolutely no order. A structure that does not have a completely amorphous structure It is sometimes called a cture. Also, although it does not have long-range order, it is close to the nearest atom. A structure that may have order within the range of atoms or up to the second nearest neighbor atoms is called an amorphous structure. It is sometimes called this. Therefore, according to the strictest definition, even a slight order in the atomic arrangement An oxide semiconductor possessing this property cannot be called an amorphous oxide semiconductor. Furthermore, at least, Oxide semiconductors exhibiting distance order cannot be called amorphous oxide semiconductors. Therefore, Because they have crystalline parts, for example, CAAC-OS and nc-OS are amorphous oxide semi-crystalline. It cannot be called a conductor or a complete amorphous oxide semiconductor. 【0130】 Furthermore, oxide semiconductors may have a structure between nc-OS and amorphous oxide semiconductors. Such an oxide semiconductor having such a structure is called an amorphous-like oxide semiconductor (a-li ke OS:amorphous-like Oxide Semiconductor ) is called. 【0131】 a-like OS exhibits porosity (also called voids) in high-resolution TEM images. In some cases, the crystalline region can be clearly identified in high-resolution TEM images. It has a region where the crystalline part cannot be identified, and a region where the crystalline part cannot be identified. 【0132】 Because it has porosity, a-like OS has an unstable structure. Below, a-like To demonstrate that the OS has a less stable structure compared to CAAC-OS and nc-OS. This shows the structural changes caused by electron irradiation. 【0133】 The samples to be irradiated with electrons are a-like OS (referred to as sample A) and nc-OS ( Prepare Sample B (referred to as Sample B) and CAAC-OS (referred to as Sample C). The sample is also an In-Ga-Zn oxide. 【0134】 First, high-resolution cross-sectional TEM images are obtained for each sample. It can be seen that all of them have crystalline parts. 【0135】 The determination of which part should be considered a single crystal can be made as follows. For example, The unit cell of an InGaZnO4 crystal has three In-O layers and a Ga-Zn-O layer. It is known to have a structure in which 6 layers, totaling 9 layers, are stacked in layers along the c-axis. The spacing between adjacent layers is approximately the same as the spacing between grid planes (also called the d value) of the (009) plane. Yes, and its value has been determined to be 0.29 nm from crystal structure analysis. Therefore, the lattice fringes Areas with a spacing of 0.28 nm or more and 0.30 nm or less are considered to be the crystalline regions of InGaZnO4. This can be done. Note that the lattice patterns correspond to the ab-plane of the InGaZnO4 crystal. 【0136】 Figure 9 shows an example of investigating the average size of the crystalline regions (22 to 45 locations) in each sample. However, the length of the lattice fringes mentioned above is used as the size of the crystal portion. From Figure 9, a-like It can be seen that the crystalline portion of OS grows in proportion to the cumulative amount of electron irradiation. Specifically, As shown in (1) in Figure 9, the size is about 1.2 nm in the initial stages of TEM observation. The prominent crystalline region (also called the initial nucleus) is formed when the cumulative irradiation dose reaches 4.2 × 10⁻⁶ 8 e - / nm 2 odor It can be seen that it has grown to a size of about 2.6 nm. On the other hand, nc-OS and CAAC-OS shows that there is no change in the size of the crystalline part within the range from the start of electron irradiation until the cumulative electron irradiation dose reaches 4.2×10 8 e - / nm 2 Specifically, as shown in (2) and (3) in Fig. 9, regardless of the cumulative electron irradiation dose, the sizes of the crystalline parts of nc-OS and CAA C-OS are about 1.4 nm and about 2.1 nm, respectively, as can be seen . 【0137】 Thus, crystal growth of a-like OS may be observed upon electron irradiation . On the other hand, it can be seen that nc-OS and CAAC-OS hardly show crystal growth due to electron irradiation . That is, it can be seen that a-like OS has an unstable structure compared to nc-OS and CAAC-O S 【0138】 In addition, since a-like OS has voids, it has a lower density structure compared to nc-OS and CAAC-OS . Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal of the same composition . Also, the density of nc-OS and CAAC -OS is 92.3% or more and less than 100% of the density of a single crystal of the same composition . An oxide semiconductor with a density less than 78% of that of a single crystal is difficult to form a film 【0139】 For example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of a single crystal InGaZnO4 having a rhombohedral crystal structure is 6.357 g / cm . Therefore 3 , for example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio] , the density of a-like OS is 5.0 g / cm 3 ​​More than 5.9g / cm 3 It will be less than. For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of nc-OS and CAAC-OS is 5.9 g / cm³. 3 More than 6.3g / cm 3 It will be less than. 【0140】 Note that single crystals with the same composition may not exist. In that case, crystals with different compositions in arbitrary proportions may be found. By combining single crystals, the density equivalent to that of a single crystal at a desired composition can be estimated. This is possible. The density corresponding to a single crystal of the desired composition can be obtained by combining single crystals of different compositions. The proportion can be estimated using a weighted average. However, the density should be as small as possible. It is preferable to estimate by combining different types of single crystals. 【0141】 As described above, oxide semiconductors can take on various structures, each possessing a variety of properties. Oxide semiconductors include, for example, amorphous oxide semiconductors, a-like OS, and microcrystalline oxides. The film may be a multilayer film containing two or more types of semiconductors and CAAC-OS. 【0142】 A conductive film is deposited on the insulator 306, and the unnecessary parts of the conductive film are etched, and the second gate A first electrode 331 is formed. The second gate electrode is made of tantalum, tungsten, titanium, and molybdenum. Butene, aluminum, copper, molybdenum tungsten alloy, tungsten nitride, titanium nitride Materials such as tantalum nitride can be used. Alternatively, a multilayer structure can be used. For film deposition methods, sputtering, CVD, ALD, etc., can be used. 【0143】 Next, the insulator 307 is deposited so as to cover the insulator 306 and the second gate electrode 331. The edge body 307 can use the same film as the insulator 305 described above, and the same film formation method can be used. It is possible to use an insulator that has the function of being impermeable to oxygen. For example, an aluminum oxide film can be used. 【0144】 An insulator 308 is formed on the insulator 307. The insulator 308 is the same as the insulator 301 described above. A film can be used, and a similar film formation method can be used. After forming the insulator 308 film CMP is performed to flatten the insulator 308. 【0145】 Next, insulators 308, 307, and 306 are connected to the source electrode or drain electrode. A contact hole is formed that reaches the upper surface of certain 312a and 312b. 【0146】 Next, a conductive film 314 is formed, and a conductive film 315 is formed on the conductive film 314. Furthermore, the conductor 315 is made of tantalum, tungsten, titanium, molybdenum, aluminum, Copper, molybdenum tungsten alloy, tungsten nitride, titanium nitride, tantalum nitride, etc. It can be used. Film deposition methods include sputtering, CVD, and ALD. It is possible. 【0147】 Next, CMP is performed until it reaches the upper surface of the insulator 308, and from the conductors 314 and 315 It forms a plug. 【0148】 Next, a conductive film 316 is formed on the conductive film 315 and the insulator 308. Conductive film 316 It is tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum Gusten alloys, tungsten nitride, titanium nitride, tantalum nitride, etc. can be used. Alternatively, it can be a multilayer film. Film deposition methods include sputtering, CVD, and AL. Method D or similar methods can be used. Next, the unnecessary parts of the conductor 316 are etched to make the conductive An electrode consisting of body 316 is formed. 【0149】 By the above steps, a semiconductor device having a transistor according to one aspect of the present invention can be manufactured. can. 【0150】 This embodiment can be appropriately combined with other embodiments described herein, at least in part. They can be implemented together. 【0151】 (Embodiment 4) In this embodiment, the oxidation-prevented back gate electrode and wiring described in Embodiment 3 are used. An example of a semiconductor device utilizing a transistor with layers will be described. 【0152】 Figure 10(A) shows an example of a memory device circuit, and Figure 10(B) shows a cross-sectional view. 【0153】 The substrate 350 is a single-crystal semiconductor substrate made of silicon, silicon carbide, etc., and a polycrystalline semiconductor substrate. Body substrate, compound semiconductor substrate made of silicon germanium, etc., SOI (Silic It is also possible to use boards such as an on-in-sulator board. 【0154】 A transistor 100 is formed on the substrate 350. The transistor 100 is shown in Figure 10. Thus, a planar transistor having a sidewall of 355 can be used. The transistor is an STI351 (Shallow Trench Isolation). A fin was formed to isolate the element. Also, transistor 100 is formed as shown in Figure 11. A type transistor may also be used. Furthermore, transistor 100 is a p-channel type transistor. You may use a t-type transistor, or you may use an n-channel transistor. Or you may use both. good. 【0155】 In this embodiment, transistor 100 uses a silicon single crystal in the channel formation region. However, for example, an oxide semiconductor may be used in the channel formation region, or a silicon single crystal may be used. It is not limited to this. Also, as an insulator 354 that has the function of a gate insulator For example, silicon oxide obtained by thermally oxidizing a silicon single crystal can be used. Silicon film, silicon oxide nitride film, silicon nitride oxide film, silicon nitride film, aluminum oxide Aluminum film, aluminum nitride film, hafnium oxide film, etc. can be used. Thermal oxidation, CVD, sputtering, ALD, plasma oxidation, plasma nitriding, etc. This can be used. Alternatively, a laminated film can be formed by selecting from the above-mentioned films as appropriate. . 【0156】 An insulator 360 is deposited on the transistor 100, on the STI 351, and on the diffusion layer 353. CMP is performed to planarize the surface of the insulator 360. The insulator 360 is a silicon oxide film. silicon oxide nitride film, silicon nitride oxide film, silicon nitride film, aluminum oxide film, nitrile Aluminum oxide films, hafnium oxide films, etc., can be used. The film deposition method is thermal oxidation. Using methods such as CVD, sputtering, ALD, plasma oxidation, and plasma nitriding. This can be done. Planarization may be performed using other processes. Alternatively, CMP and etching (dry Etching (wet etching) and plasma treatment may be combined. 【0157】 Contact holes in the insulator 360 that reach the upper surface of the gate electrode 330 of the transistor 100 Then, a contact hole is formed that reaches the upper surface of the diffusion layer 353, and the conductor is made into a contact hole It is embedded inside the tube, and CMP is performed until the top surface of the insulator 360 is exposed, then plug 370, plug Plug 371 and plug 372 are formed. Plugs 370, 371, and 372 are For example, tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum Tungsten alloys and the like can be used. Alternatively, multiple materials can be appropriately selected from the above to form a multilayer film. A film may be formed. Film formation methods include sputtering, CVD, ALD, plating, etc. This is possible. The deposition of the laminated film may be carried out using multiple formation methods from the above. 【0158】 Next, a conductive film is deposited on the insulator 360 to form wiring layers 373, 374, and 375. The wiring layers 373, 374, and 375 are connected to the plug 370 mentioned above. The same film and film formation method as for G371 and PLA372 can be used. 【0159】 An insulator 361 is formed on the insulator 360 and on the wiring layers 373, 374, and 375. The film is then coated and CMP is performed to planarize the surface of the insulator 361. The insulator 361 is the insulator described above. The same film and film deposition method as for 360 can be used. 【0160】 The insulator 361 reaches the upper surfaces of the wiring layers 373, 374, and 375, respectively. Form contact holes and grooves, and embed the conductive material in the contact holes and grooves. Next CMP is performed until the upper surface of the insulator 361 is exposed, and the plug and the wiring layer which also serves as the wiring layer 376, wiring layer 377, wiring layer 378 are formed. 378 is a film and film deposition method similar to those described above for plugs 370, 371, and 372. You can use it. 【0161】 Next, an insulator 362 is placed on the insulator 361 and on the wiring layers 376, 377, and 378. After forming the film, a wiring layer 37, which serves as both a plug and a wiring layer, is formed in the same manner as the insulator 361 described above. 9. Wiring layers 380 and 381 are formed. The insulator 362 is formed with the insulator 360 described above. Similar films and film formation methods can be used. Wiring layer 379, wiring layer 380, wiring layer 38 1 uses the same film and film deposition method as described above for plugs 370, 371, and 372. It is possible. This plug and the formation of the wiring layer, which also serves as the wiring layer, can be done as needed. Since the described method can be repeated to form the semiconductor device, a semiconductor device with a high degree of integration can be manufactured. . 【0162】 Next, an insulator 363 is placed on the insulator 362, and on the wiring layers 379, 380, and 381. A film is formed. The insulator 363 uses the same film and film formation method as the insulator 360 described above. This is possible. Preferably, the insulator 363 has the property of being impermeable to hydrogen. Alternatively, the insulator 363 does not need to be film-formed. 【0163】 An insulator 302 is formed on the insulator 363, and a transistor 1 is formed using the method described in Embodiment 3. Form 10. 【0164】 Next, an insulator 308 is deposited to form plugs 382, ​​383, and 384. On plug 382, ​​on plug 383, and on plug 384, respectively, there is a wiring layer 385. Wiring layers 386 and 387 are formed. 【0165】 Next, on the insulator 308, on the wiring layer 385, on the wiring layer 386, and on the wiring layer 387, The edge material 364 is deposited, and CMP is performed to planarize the surface of the insulator 364. A film and film formation method similar to that used for the insulator 360 described above can be used. 【0166】 Contact holes are formed in the insulator 364 that reach the upper surfaces of the wiring layers 386 and 387. Then, embed the conductor in the contact hole and CMP until the upper surface of the insulator 364 is exposed. This process is performed to form plug 388 and plug 389. Plug 388 and plug 389 are Using the same film and film deposition method as described above for plugs 370, 371, and 372. It is possible. 【0167】 Next, a conductive film is formed on the insulator 364, and one electrode 341 of the capacitive element 130 and the wiring layer 390 is formed. The electrode 341 and the wiring layer 390 are the plug 370 and plug 3 described above. 71. The same film and film deposition method as for plug 372 can be used. Next, capacitive element 130 Next, the other electrode 342 is formed to overlap the first electrode 341 via an insulator. Next, an insulator 365 is deposited, and CMP is performed to planarize the surface of the insulator 365. For 5, the same film and film formation method as described above for the insulator 360 can be used. 【0168】 A contact hole is formed in the insulator 365 that reaches the upper surface of the other electrode 342 of the capacitive element 130. On the other hand, a contact hole is formed that reaches the upper surface of the wiring layer 390, and a conductor is made to contact Embed in the hole, perform CMP until the top surface of insulator 365 is exposed, plug 391 This forms plug 392. Plug 391 and plug 392 are connected to plug 37 as described above. 0, the same film and film deposition method as for plug 371 and plug 372 can be used. 【0169】 Next, a conductive film is deposited on the insulator 365 to form wiring layers 393 and 394. The wire layer 393 and the wiring layer 394 are the plugs 370, 371, and 372 mentioned above. The same film and film formation method can be used. 【0170】 Furthermore, the planar capacitive element 130 shown in Figure 10 is replaced with the cylindrical type shown in Figure 12. It may be formed as a capacitive element 140. The cylindrical capacitive element 140 is a planar type This is preferable because it allows for the fabrication of a capacitive element in a smaller area than the capacitive element 130. 【0171】 By following the above steps, a semiconductor device according to one aspect of the present invention can be manufactured. 【0172】 This embodiment can be appropriately combined with other embodiments described herein, at least in part. They can be implemented together. 【0173】 (Embodiment 5) <Imaging device> The following describes an imaging device according to one aspect of the present invention. 【0174】 Figure 13(A) is a plan view showing an example of an imaging device 200 according to one aspect of the present invention. The unit 200 includes a pixel unit 210, a peripheral circuit 260 for driving the pixel unit 210, and a peripheral circuit It has a path 270, a peripheral circuit 280, and a peripheral circuit 290. The pixel section 210 has p rows and q columns. It has multiple pixels 211 arranged in a matrix (where p and q are integers greater than or equal to 2). Peripheral circuits 260, 270, 280, and 290 are each multiple It has the function of connecting to a number of pixels 211 and supplying signals to drive multiple pixels 211. Furthermore, in this specification, peripheral circuits 260, 270, and 280 are used. The term "peripheral circuit" or "drive circuit" is sometimes used to refer to all of these components, including peripheral circuitry 290. For example, peripheral circuit 260 can be considered part of the peripheral circuitry. 【0175】 Furthermore, it is preferable that the imaging device 200 has a light source 291. The light source 291 is a detection light P It can emit 1. 【0176】 Furthermore, the peripheral circuits include at least logic circuits, switches, buffers, amplification circuits, or converters. It has one of the circuits. Furthermore, the peripheral circuits may be fabricated on the substrate forming the pixel section 210. Furthermore, semiconductor devices such as IC chips may be used in part or all of the peripheral circuits. The peripheral circuits are peripheral circuit 260, peripheral circuit 270, peripheral circuit 280 and peripheral circuit 290. You may omit one or more of the following: 【0177】 Furthermore, as shown in Figure 13(B), in the pixel section 210 of the imaging device 200, Pixels 211 may be arranged at an angle. By arranging pixels 211 at an angle, the row direction and The pixel spacing (pitch) in the column direction can be shortened. This allows the imaging device 200 to This allows for a further improvement in the quality of the images being captured. 【0178】 <Example of pixel configuration 1> The imaging device 200 has one pixel 211 which is composed of multiple sub-pixels 212, and each sub A filter (color filter) that transmits light in a specific wavelength range is combined with pixel 212. This allows us to obtain the information necessary to display color images. 【0179】 Figure 14(A) is a plan view showing an example of pixels 211 for acquiring a color image. The pixel 211 shown in 14(A) is provided with a color filter that transmits the red (R) wavelength band. Sub-pixel 212 (hereinafter also referred to as "sub-pixel 212R") transmits the green (G) wavelength band. Sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G") equipped with a color filter and Sub-pixel 212 (hereinafter referred to as "sub-pixel") is provided with a color filter that transmits the blue (B) wavelength band. It has a sub-pixel (also called "pixel 212B"). The sub-pixel 212 is used to function as a photosensor. It is possible. 【0180】 Sub-pixels 212 (sub-pixels 212R, 212G, and 212B) are connected to wiring 23 1. It is electrically connected to wires 247, 248, 249, and 250. Pixel 212R, sub-pixel 212G, and sub-pixel 212B are each connected by independent wiring 25 It is connected to 3. Also, in this specification, for example, it is connected to pixel 211 of the nth row. Wires 248 and 249 are denoted as wire 248[n] and wire 249[n], respectively. To include. Also, for example, the wiring 253 connected to the pixel 211 in the mth column is defined as wiring 253[m] This is stated. Note that in Figure 14(A), the subpixel 212R of pixel 211 in the mth column Wiring 253[m]R is connected to the sub-pixel 212G, and wiring 253 is connected to the sub-pixel 212G. Wiring 253 connected to line 253[m]G and sub-pixel 212B is connected to wiring 253[m]B As described above, the sub-pixel 212 is electrically connected to the peripheral circuitry via the above wiring. 【0181】 Furthermore, the imaging device 200 transmits color filters of adjacent pixels 211 that transmit the same wavelength band. The sub-pixels 212, each equipped with a t-axis, are electrically connected to each other via a switch. In 14(B), arrange in n rows (where n is an integer between 1 and p) and m columns (where m is an integer between 1 and q). The sub-pixel 212 of the pixel 211, and the sub-pixel 212 located in the n+1 row and m column adjacent to the pixel 211. An example of the connection of sub-pixels 212 of the pixel 211 is shown. In Figure 14(B), n rows m Sub-pixels 212R located in a column and sub-pixels 212R located in row n+1 and column m are switched. It is connected via 201. Also, the subpixels 212G arranged in n rows and m columns, and n+1 Sub-pixels 212G, arranged in row m column, are connected via switch 202. Also, n Sub-pixel 212B located in row m and column m and sub-pixel 212B located in row n+1 and column m are It is connected via switch 203. 【0182】 Furthermore, the color filters used for sub-pixel 212 are limited to red (R), green (G), and blue (B). Color film that transmits cyan (C), yellow (Y), and magenta (M) light respectively. A LUTA may be used. A sub-pixel detects light of three different wavelength bands in one pixel 211. By adding 212, it is possible to acquire a full-color image. 【0183】 Alternatively, color filters that transmit red (R), green (G), and blue (B) light, respectively, are provided. In addition to the sub-pixels 212 that have been cut off, a sub-pixel with a color filter that transmits yellow (Y) light is provided. A pixel 211 having pixel 212 may be used. Alternatively, cyan (C) and yellow (Y) may be used, respectively. In addition to sub-pixels 212 equipped with a color filter that transmits ) and magenta (M) light, A pixel 21 has a sub-pixel 212 that is provided with a color filter that transmits blue (B) light. 1 may be used. Sub-pixels 2 detect light of four different wavelength bands in one pixel 211. By adding 12, the color reproduction accuracy of the acquired image can be further improved. 【0184】 Furthermore, for example, in Figure 14(A), sub-pixel 212 detects the red wavelength band, and the green wavelength The ratio of the number of sub-pixels 212 that detect the bandwidth and the sub-pixels 212 that detect the blue wavelength bandwidth ( The pixel ratio (or light-receiving area ratio) does not have to be 1:1:1. For example, the pixel ratio (light-receiving area ratio) Alternatively, a Bayer array with red:green:blue = 1:2:1 may be used. Or, the pixel ratio (received The light area ratio can also be set to red:green:blue = 1:6:1. 【0185】 Note that while one sub-pixel 212 may be provided in pixel 211, two or more are preferable. By providing two or more sub-pixels 212 that detect the same wavelength band, redundancy is increased, and the imaging device This can improve the reliability of the 200 unit. 【0186】 Furthermore, IR (Infrared) absorbs or reflects visible light and transmits infrared light. By using a filter, an imaging device 200 that detects infrared light can be realized. 【0187】 Also, an ND (Neutral Density) filter (light-reducing filter) is used. This is because when a large amount of light is incident on a photoelectric conversion element (light-receiving element), the output saturation occurs. This can prevent this. By using a combination of ND filters with different light reduction amounts, the imaging device This allows for a wider dynamic range in the image. 【0188】 In addition to the filter mentioned above, a lens may also be provided at pixel 211. Here, Figure 15 An example of the arrangement of pixels 211, filter 254, and lens 255 will be explained using a cross-sectional diagram. By providing the 255 element, the photoelectric conversion element can efficiently receive incident light. Specifically, as shown in Figure 15(A), a lens 255 and a filter 25 are formed on the pixel 211. 4 (filters 254R, 254G, and 254B), and pixel circuit 2 The structure can be configured to allow light 256 to be incident on the photoelectric conversion element 220 through 30, etc. 【0189】 However, as shown in the area enclosed by the dashed line, a portion of the light 256 indicated by the arrow is connected to wiring 257. It may be partially blocked by something. Therefore, as shown in Figure 15(B), the photoelectric The lens 255 and filter 254 are placed on the side of the conversion element 220, and the photoelectric conversion element 220 A structure that efficiently receives light 256 is preferred. Light 256 is received from the photoelectric conversion element 220 side. By injecting the photoelectric conversion element 220, an imaging device 200 with high detection sensitivity is provided. It is possible. 【0190】 As shown in Figure 15, the photoelectric conversion element 220 has a pn-type junction or a pin-type junction formed on it. Photoelectric conversion elements may also be used. 【0191】 Furthermore, the photoelectric conversion element 220 uses a material that has the function of absorbing radiation and generating electric charge. It may be formed by absorbing radiation and generating an electric charge. Len, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy These include: 【0192】 For example, if selenium is used in the photoelectric conversion element 220, in addition to visible light, ultraviolet light, and infrared light, Photoelectric conversion element 2 having an optical absorption coefficient across a wide wavelength range, including X-rays and gamma rays. We can achieve 20. 【0193】 Here, one pixel 211 of the imaging device 200 is, in addition to the sub-pixel 212 shown in Figure 14, Furthermore, it may have a sub-pixel 212 having a first filter. 【0194】 <Example of pixel configuration 2> Below, we will discuss transistors using silicon and transistors using oxide semiconductors. An example of how pixels are constructed using this method will be explained. 【0195】 Figures 16(A) and 16(B) are cross-sectional views of the elements constituting the imaging device. Figure 16(A) The imaging device shown has a silicon transistor 55 provided on a silicon substrate 500. 1. Transistor 55 using oxide semiconductors stacked on top of transistor 551 2 and transistor 553, and photodiode provided on silicon substrate 500 Includes 560. Each transistor and photodiode 560 is plugged into various plugs 570. and has electrical connections with wiring 571. Also, the anode 5 of photodiode 560 61 has an electrical connection with plug 570 via a low-resistance region 563. 【0196】 The imaging device also includes a transistor 551 and a photodie provided on the silicon substrate 500. A layer 510 having an electrode 560, and a layer 5 provided in contact with the layer 510 and having wiring 571 20 is provided in contact with layer 520 and has transistors 552 and 553. A layer 530 and a layer 5 provided in contact with the layer 530 and having wiring 572 and wiring 573 It has 40. 【0197】 In the example cross-sectional view in Figure 16(A), the transistor 55 is located on the silicon substrate 500. The configuration includes a photodiode 560 with a light-receiving surface on the side opposite to the surface on which 1 is formed. This configuration ensures that the optical path is not affected by various transistors, wiring, etc. This allows for the formation of pixels with a high aperture ratio. The light-receiving surface of 560 can also be the same as the surface on which transistor 551 is formed. 【0198】 Furthermore, when constructing pixels using transistors made of oxide semiconductors, layer 530 Alternatively, a layer containing transistors may be used. Alternatively, layer 510 may be omitted, and an oxide semiconductor may be used. Pixels may be constructed using only transistors. 【0199】 When constructing pixels using silicon transistors, layer 530 is omitted. That's all you need to do. An example of a cross-sectional view with layer 530 omitted is shown in Figure 16(B). 【0200】 Furthermore, the silicon substrate 500 may be an SOI substrate. Replace with germanium, silicon germanium, silicon carbide, gallium arsenide, arsenide Using a substrate having gallium dioxide, indium phosphide, gallium nitride, or an organic semiconductor. It is possible to stay there. 【0201】 Here, layer 510 has transistor 551 and photodiode 560, and An insulator 580 is provided between the layer 530 having the diast 552 and the transistor 553. It can be kicked. However, the position of the insulator 580 is not limited. 【0202】 Hydrogen in the insulator located near the channel formation region of transistor 551 is a silicon d This terminates the ring bond and improves the reliability of transistor 551. , hydrogen in an insulator provided near transistors 552 and 553, etc. This is one of the factors that generate carriers in oxide semiconductors. Therefore, transistor 5 This can be a factor that reduces the reliability of transistors such as 52 and 553. So, a transistor using an oxide semiconductor on top of a silicon-based semiconductor transistor... When stacking the elements, an insulator 580 having the function of blocking hydrogen is placed between them. It is preferable to provide it. By confining hydrogen in the layer below the insulator 580, the transistor The reliability of 551 can be improved. Furthermore, from below the insulator 580, the insulator Because hydrogen diffusion to the layer above 580 can be suppressed, transistors 552 and 580 This can improve the reliability of devices such as the 553. 【0203】 For example, refer to the description of insulator 363 for insulator 580. 【0204】 Furthermore, in the cross-sectional view of Figure 16(A), the photodiode 560 provided in layer 510 and layer The transistor located at 530 can be formed to overlap with it. In that case, the pixels This allows for an increase in the integration density, that is, an increase in the resolution of the imaging device. 【0205】 Furthermore, as shown in Figures 17(A1) and 17(B1), part or all of the imaging device It may be curved. Figure 17(A1) shows the imaging device in the direction of the dashed line X1-X2 in the figure. This shows the curved state. Figure 17(A2) is the same as the dashed line X1-X in Figure 17(A1). This is a cross-sectional view of the area indicated in 2. Figure 17(A3) is the dashed line Y1- in Figure 17(A1). This is a cross-sectional view of the area indicated by Y2. 【0206】 Figure 17(B1) shows the imaging device curved in the direction of the dashed line X3-X4 in the figure, and The diagram shows the curved state in the direction of the dashed line Y3-Y4. Figure 17(B2) is a diagram. This is a cross-sectional view of the area indicated by the dashed line X3-X4 in 17(B1). Figure 17(B3) is This is a cross-sectional view of the area indicated by the dashed line Y3-Y4 in Figure 17(B1). 【0207】 By curving the imaging device, image field curvature and astigmatism can be reduced. This facilitates the optical design of lenses and other components used in combination with imaging devices. For example, This allows for a reduction in the number of lenses required for aberration correction, thus enabling miniaturization of electronic devices using imaging equipment. This allows for weight reduction and improves the quality of captured images. . 【0208】 (Embodiment 6) In this embodiment, the RF includes the transistor or memory device exemplified in the above embodiment. Tags will be explained using Figure 18. 【0209】 The RF tag in this embodiment has a memory circuit inside, and stores the necessary information in the memory circuit. Furthermore, it uses non-contact means, such as wireless communication, to exchange information with the outside world. Due to its characteristics, RF tags are used to identify items by reading individual information about those items. It can be used in body recognition systems, etc. However, in order to use it for these purposes, For the first time, a high level of reliability is required. 【0210】 The configuration of an RF tag will be explained using Figure 18. Figure 18 shows an example of the configuration of an RF tag. This is a lock diagram. 【0211】 As shown in Figure 18, the RF tag 800 is connected to the communicator 801 (also known as an interrogator, reader / writer, etc.). Antenna 8 receives a radio signal 803 transmitted from antenna 802 connected to ( It has 04. In addition, the RF tag 800 has a rectifier circuit 805, a constant voltage circuit 806, and a demodulation circuit. It has 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Furthermore, the reverse current in the rectifying transistor included in the demodulation circuit 807 is sufficiently suppressed. A configuration in which a material that can be controlled, such as an oxide semiconductor, may be used. This suppresses the decrease in rectification due to reverse current and prevents the output of the demodulation circuit from saturating. This can be prevented. In other words, the output of the demodulation circuit can be made more linear with respect to the input of the demodulation circuit. It is possible. Furthermore, the data transmission format involves a pair of coils positioned opposite each other and communicating through mutual induction. Electromagnetic coupling methods, electromagnetic induction methods that use induced electromagnetic fields for communication, and methods that use radio waves for communication. They can be broadly classified into three types of radio wave methods. The RF tag 800 shown in this embodiment uses any of these methods. It can also be used for this purpose. 【0212】 Next, the configuration of each circuit will be explained. Antenna 804 is connected to the communication device 801. This is for transmitting and receiving wireless signals 803 with Tenor 802. Also, a rectifier circuit 8 05 rectifies the input AC signal generated by receiving a wireless signal with antenna 804. For example, half-wave voltage doubling rectification is performed, and the rectified signal is smoothed by a capacitive element provided in the subsequent stage. This is a circuit for generating input potential by converting it. Furthermore, the input side of the rectifier circuit 805 is also A limiter circuit may be provided on the output side. A limiter circuit is a circuit that limits the amplitude of the input AC signal. When the internally generated voltage is large, do not input power exceeding a certain level to the subsequent circuit. This is a circuit for controlling sea urchins. 【0213】 The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. This is a circuit. Note that the constant voltage circuit 806 may also have an internal reset signal generation circuit. The reset signal generation circuit utilizes the stable rise of the power supply voltage to generate the logic circuit 80 This is a circuit for generating a reset signal for number 9. 【0214】 The demodulation circuit 807 demodulates the input AC signal by detecting its envelope and generates a demodulated signal. This is a circuit for that purpose. Furthermore, the modulation circuit 808 responds to the data output from the antenna 804. This is a circuit for performing modulation. 【0215】 Logic circuit 809 is a circuit for analyzing and processing demodulated signals. Memory circuit 810 is This is a circuit that holds the input information, and includes a row decoder, column decoder, memory area, etc. It has. Furthermore, ROM811 stores unique numbers (IDs), etc., and outputs them according to the processing. This is a circuit for that purpose. 【0216】 Furthermore, the circuits described above can be selected or omitted as needed. 【0217】 Here, the memory circuit described in the previous embodiment can be used in the memory circuit 810. A memory circuit according to one aspect of the present invention can retain information even when the power supply is cut off, It can be suitably used in RF tags. Furthermore, a memory circuit according to one aspect of the present invention is a memory for writing data. Because the power (voltage) required for writing is significantly lower than that of conventional non-volatile memory, data It is also possible to avoid any difference in the maximum communication distance between reading and writing. Furthermore, To prevent malfunctions or incorrect data writing that may occur due to insufficient power during data writing. It is possible. 【0218】 Furthermore, a memory circuit according to one aspect of the present invention can be used as a non-volatile memory. Therefore, it can also be applied to ROM811. In that case, the manufacturer will provide data to ROM811. A separate command is provided for writing data, preventing users from freely rewriting it. It is preferable that the producer writes a unique number on the product before shipping it. Therefore, instead of assigning a unique number to every RF tag produced, we assign one to each good product that is shipped. It becomes possible to assign a unique number, and the unique numbers of products after shipment will not be discontinuous. This eliminates the need for post-shipment product management, making customer management easier. 【0219】 This embodiment can be appropriately combined with other embodiments described herein, at least in part. They can be implemented together. 【0220】 (Embodiment 7) In this embodiment, at least the transistors described in the embodiments can be used. Next, we will describe a CPU including the storage device described in the previous embodiment. 【0221】 Figure 19 shows a CPU that uses at least some of the transistors described in the previous embodiment. This is a block diagram showing the example configuration. 【0222】 The CPU shown in Figure 19 is an ALU1191 (ALU: Arithmet) mounted on board 1190. IC logic unit, arithmetic circuit, ALU controller 1192, instruction Timing decoder 1193, interrupt controller 1194, timing controller 1195, Register 1196, Register Controller 1197, Bus Interface 1 198 (Bus I / F), rewritable ROM1199, and ROM interface It has a ROM I / F (S1189). The substrate 1190 is a semiconductor substrate, SOI substrate , a glass substrate is used. ROM1199 and ROM interface1189 are separate. It may also be provided on the chip. Of course, the CPU shown in Figure 19 is a simplified representation of its configuration. This is just one example; actual CPUs have a wide variety of configurations depending on their application. For example, A configuration including the CPU or arithmetic circuit shown in Figure 19 is considered one core, and a configuration including multiple such cores is also included. The configuration may also involve each core operating in parallel. Furthermore, the CPU may have internal arithmetic circuits. The number of bits that can be handled by the data bus is, for example, 8 bits, 16 bits, 32 bits, 64 bits. It can be written as "t", etc. 【0223】 Instructions input to the CPU via the bus interface 1198 are instructions The signal is input to decoder 1193, decoded, and then processed by ALU controller 1192, interface Raptor controller 1194, register controller 1197, timing controller It is entered into 1195. 【0224】 ALU controller 1192, interrupt controller 1194, register controller R1197 and timing controller 1195 control various commands based on the decoded instructions. To perform the operation. Specifically, the ALU controller 1192 controls the operation of the ALU 1191. It generates a signal for that purpose. Also, the interrupt controller 1194 is the CPU programmer. During execution, interrupt requests from external input / output devices and peripheral circuits are prioritized and masked. The state is judged and processed. The register controller 1197 adds register 1196 It generates a response and reads or writes to register 1196 depending on the CPU state. 【0225】 Furthermore, the timing controller 1195 is connected to the ALU 1191 and the ALU controller 119 2. Instruction decoder 1193, interrupt controller 1194, and It generates a signal that controls the timing of the operation of the zista controller 1197. For example, The ming controller 1195 generates an internal clock signal based on the reference clock signal. It is equipped with an internal clock generation unit that supplies the internal clock signal to the various circuits mentioned above. 【0226】 In the CPU shown in Figure 19, a memory cell is located in register 1196. The transistors shown in the previous embodiment can be used as the 1196 memory cells. ru. 【0227】 In the CPU shown in Figure 19, the register controller 1197 receives information from the ALU 1191. Following the instructions, select the hold operation in register 1196. That is, register 11 In the memory cell of 96, data is retained by a flip-flop, or capacity Select whether to retain data using an element. Data retention using a flip-flop is If selected, power voltage is supplied to the memory cells in register 1196. If data retention in the capacitive element is selected, data rewriting to the capacitive element will occur. This process can be performed to stop the supply of power voltage to the memory cells in register 1196. . 【0228】 Figure 20 is an example of a circuit diagram of a memory circuit that can be used as register 1196. The memory circuit 1200 consists of a circuit 1201 in which the stored data is lost when the power is cut off, and a circuit 1201 in which the stored data is lost when the power is cut off. A circuit 1202 that prevents data from volatilizing, a switch 1203, a switch 1204, and a logic element It comprises a sub-element 1206, a capacitive element 1207, and a circuit 1220 having a selection function. 1202 consists of the capacitive element 1208, transistor 1209, and transistor 1210. It has a diode, a resistor, an inductor, etc., as needed. It may further have other elements such as a t. 【0229】 Here, the memory device described in the previous embodiment can be used in circuit 1202. When the power supply voltage to the memory circuit 1200 is stopped, the transistor 120 of circuit 1202 The gate of transistor 9 is input to the ground potential (0V) or the potential that turns off transistor 1209. The configuration will continue to be such that the gate of transistor 1209 is connected via a load such as a resistor. The structure will be as follows. 【0230】 Switch 1203 uses a single-conductivity (e.g., n-channel) transistor 1213. The switch 1204 is configured to have a conductivity type opposite to that of a single-conductivity type (for example, a p-channel type). An example using transistor 1214 is shown. Here, the first terminal of switch 1203 The child corresponds to one of the source and drain of transistor 1213, and the second of switch 1203. The terminals correspond to the source and drain of transistor 1213, and switch 1203 is The control signal RD input to the gate of transistor 1213 controls the first terminal and the second terminal. Continuity or non-conductivity between terminals (i.e., the on or off state of transistor 1213) ) is selected. The first terminal of switch 1204 is the source and drain of transistor 1214. Corresponding to one side of the input, the second terminal of switch 1204 is the source of transistor 1214. Corresponding to the other side of the drain, switch 1204 is input to the gate of transistor 1214. The control signal RD determines whether the first terminal and the second terminal are conductive or non-conductive (i.e., The ON or OFF state of the Rangista 1214 is selected. 【0231】 One of the sources and drains of transistor 1209 is connected to the pair of electrodes of capacitive element 1208. One side of this is electrically connected to the gate of transistor 1210. Here, the connection part Let this be node M2. One of the sources and drains of transistor 1210 is at a low power supply potential. It is electrically connected to a power supply (e.g., a GND wire), and the other is switch 1 Electrically connected to the first terminal of 203 (one of the source and drain of transistor 1213). The second terminal of switch 1203 (in addition to the source and drain of transistor 1213) is used. (One side) is the first terminal of switch 1204 (one side of the source and drain of transistor 1214). ) is electrically connected to the second terminal of switch 1204 (the saw of transistor 1214). The other end of the line (the drain) is electrically connected to wiring capable of supplying the power potential VDD. The second terminal of switch 1203 (the other end of the source and drain of transistor 1213) And the first terminal of switch 1204 (one of the source and drain of transistor 1214) The input terminal of logic element 1206 and one of the pair of electrodes of capacitive element 1207 are Electrically connected. Here, the connection point is referred to as node M1. A pair of capacitive elements 1207 The other electrode can be configured to receive a constant potential input. For example, a low power supply. The system can be configured to receive either an electrical potential (such as GND) or a high power supply potential (such as VDD) as input. The other electrode of the pair of electrodes of the capacitive element 1207 is a wire capable of supplying a low power supply potential. It is electrically connected to (for example, the GND wire). The other of the pair of electrodes of the capacitive element 1208 This can be configured to receive a constant potential input. For example, a low power supply potential (GND, etc.) Alternatively, a configuration can be used in which a high power supply potential (such as VDD) is input. Capacitive element 1208 The other of the pair of electrodes is a wire capable of supplying a low power potential (e.g., a GND wire). ) is electrically connected to it. 【0232】 Furthermore, capacitive elements 1207 and 1208 accumulate parasitic capacitances of transistors and wiring, etc. It was possible to omit it by using it to its fullest extent. 【0233】 The control signal WE is input to the first gate (first gate electrode) of transistor 1209. Switches 1203 and 1204 are configured to receive a different control signal RD than control signal WE. Therefore, a conductive or non-conductive state is selected between the first terminal and the second terminal, and one of the switches When there is electrical conductivity between the first and second terminals of one switch, the first and second terminals of the other switch... The area between the terminals becomes non-conductive. 【0234】 The source and drain of transistor 1209 are connected to the data held in circuit 1201. The corresponding signal is input. In Figure 20, the signal output from circuit 1201 is the transistor. An example is shown where the source and drain of switch 1209 are input. The signal output from the second terminal (the other end of the source and drain of transistor 1213) is: The logic element 1206 inverts its logic value, resulting in an inverted signal, which is then transmitted via circuit 1220. This is then input to circuit 1201. 【0235】 Note that in Figure 20, the second terminal of switch 1203 (source and terminal of transistor 1213) The signal output from the other side of Rain is transmitted through logic element 1206 and circuit 1220 to the circuit An example of input to 1201 is shown, but it is not limited to this. The second terminal of switch 1203 ( The signals output from the source and drain (the other side) of transistor 1213 invert the logic value. It may be input to circuit 1201 without being forced to do so. For example, input into circuit 1201 If there is a node that holds a signal inverted from the logical value of the signal input from the power terminal, , the second terminal of switch 1203 (the other of the source and drain of transistor 1213) The signal output from can be input to the node in question. 【0236】 Furthermore, in Figure 20, among the transistors used in the memory circuit 1200, Transistors other than TA1209 are made of a layer or substrate 119 made of a semiconductor other than an oxide semiconductor. A transistor can be formed where a channel is formed at 0. For example, a silicon film or It can be a transistor in which a channel is formed on a silicon substrate. Also, a memory circuit All transistors used in the 1200 are transistors whose channels are formed from oxide semiconductors. It can also be a zista. Alternatively, the memory circuit 1200 may have transistors other than transistor 1209. However, it may also include a transistor whose channel is formed of an oxide semiconductor, and the remaining transistor The radiator has channels formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. It can also be used as a transistor. 【0237】 In Figure 20, circuit 1201 can be, for example, a flip-flop circuit. Furthermore, logic elements such as inverters and clocked inverters can be used as logic elements 1206. It is possible. 【0238】 In one aspect of the present invention, in a semiconductor device, when the power supply voltage is not supplied to the memory circuit 1200 The data stored in circuit 1201 is transferred to the capacitive element 120 provided in circuit 1202. It can be held by 8. 【0239】 Furthermore, transistors with channels formed in oxide semiconductors exhibit extremely low off-currents. For example, the off-current of a transistor in which a channel is formed in an oxide semiconductor is crystalline. It is significantly lower than the off-current of a transistor in which a channel is formed in silicon. By using the transistor as transistor 1209, the memory circuit 120 The signal held by the capacitive element 1208 is maintained for a long period of time even when no power supply voltage is supplied to 0. It drips. In this way, the memory circuit 1200 retains its stored contents (data) even when the power supply voltage is interrupted. It is possible to hold ). 【0240】 Furthermore, by providing switches 1203 and 1204, pre-charge operation Because it is a memory circuit characterized by performing the following, after the power supply voltage is restored, the circuit 1201 returns to its original state. This can shorten the time it takes to re-store the data. 【0241】 Furthermore, in circuit 1202, the signal held by the capacitive element 1208 is transmitted to the transistor The signal is input to gate 1210. As a result, the power supply voltage to memory circuit 1200 is restored. After that, the signal held by the capacitive element 1208 is controlled by the state of transistor 1210 ( It can be converted to an ON state or an OFF state and read from circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitive element 1208 fluctuates slightly, the original signal It is possible to read it accurately. 【0242】 Such a memory circuit 1200 is used in the registers and cache memory of the processor. By using it in a storage device, it prevents the loss of data in the storage device due to a power supply interruption. This is possible. Furthermore, after the power supply voltage is restored, the system will quickly return to the state it was in before the power supply was interrupted. Therefore, the entire processor, or one of the components of the processor, This allows for power-off even for short periods in multiple logic circuits, thus reducing power consumption. It can be suppressed. 【0243】 In this embodiment, although the memory circuit 1200 was described as an example in which the CPU is used, the memory circuit 1 200 is a DSP (Digital Signal Processor), custom L LSIs such as SIs and PLDs (Programmable Logic Devices), R It can also be applied to F tags (Radio Frequency Identification). It is Noh. 【0244】 This embodiment can be appropriately combined with other embodiments described herein, at least in part. They can be implemented together. 【0245】 (Embodiment 8) 【0246】 In the following, a display device according to one aspect of the present invention will be described with reference to Figures 21 and 22. ru. 【0247】 Display elements used in display devices include liquid crystal elements (also called liquid crystal display elements) and light-emitting elements. (Also called light-emitting display elements) can be used. Light-emitting elements respond to current or voltage. Therefore, elements whose brightness is controlled are included in that category, specifically inorganic EL (Electric Light). This includes luminescence (OLED), organic EL, etc. The following is an example of a display device. Display devices using EL elements (EL display devices) and display devices using liquid crystal elements (liquid crystal display devices) This section will explain the display device. 【0248】 The display device described below comprises a panel in which the display elements are sealed, and a panel with This includes modules with ICs, controllers, and other components mounted on them. 【0249】 Furthermore, the display devices described below refer to image display devices or light sources (including lighting devices). Also, a connector, such as an FPC, a module with TCP attached, and a preamplifier at the end of the TCP. A module or display element having a circuit board has an IC (integrated circuit) directly connected to it using the COG method. All mounted modules are also included in the display device. 【0250】 Figure 21 shows an example of an EL display device according to one aspect of the present invention. Figure 21(A) shows an EL display The circuit diagram of the device's pixels is shown. Figure 21(B) is a top view showing the entire EL display device. Furthermore, Figure 21(C) is a cross-section of MN, which corresponds to a portion of the dashed line MN in Figure 21(B). . 【0251】 Figure 21(A) is an example of a circuit diagram of a pixel used in an EL display device. 【0252】 In this specification, active elements (transistors, diodes, etc.), passive elements ( For all terminals of capacitive elements, resistive elements, etc., the destination of their connection is not specified. However, a person skilled in the art may be able to constitute one aspect of the invention. In other words, connection Even without specifying the destination, one aspect of the invention can be said to be clear. And the connection destination is specified. If the content is described in this specification, etc., then one aspect of the invention that does not specify the connection destination is described in this specification. In some cases, it can be determined that this is stated in the document or other documentation. In particular, multiple terminals are used as connection destinations. If multiple locations are anticipated, it is not necessary to limit the connection destination of the terminal to a specific location. Therefore, active elements (transistors, diodes, etc.), passive elements (capacitors, resistive elements) By specifying the connection destination for only some of the terminals that children (etc.) have, In some cases, it may be possible to constitute one aspect of clarity. 【0253】 Furthermore, in this specification, etc., if a certain circuit is specified, then at least the connection destination is identified, and this applies to our business. If you are an expert, you may be able to identify the invention. Or, regarding a certain circuit, However, if the function is specified, a person skilled in the art may be able to specify the invention. In other words, if the function is specified, it can be said that one aspect of the invention is clear. It may be possible to determine that one aspect of the invention is described in this specification, etc. Therefore, even without specifying the function of a certain circuit, if the connection destination is specified, it constitutes an invention. It is disclosed as such and can constitute one aspect of the invention. Regarding a certain circuit, even if the connection destination is not specified, if the function is specified, it can be considered as one aspect of the invention. This has been disclosed and can constitute one aspect of the invention. 【0254】 The EL display device shown in Figure 21(A) includes a switch element 743, a transistor 741, and It has a light-emitting element 742 and a light-emitting element 719. 【0255】 Note that Figure 21(A), etc., is just one example of a circuit configuration, and further transistors can be added. It is possible to do so. Conversely, at each node in Figure 21(A), transistors, switches It is also possible to avoid adding passive components, etc. 【0256】 The gate of transistor 741 is connected to one end of switch element 743 and one end of capacitive element 742. The electrodes are electrically connected. The source of transistor 741 is connected to the other electrode of capacitive element 742. It is electrically connected to and electrically connected to one electrode of the light-emitting element 719. The drain of 741 is supplied with the power supply potential VDD. The other end of the switch element 743 is connected to signal line 7 It is electrically connected to 44. A constant potential is applied to the other electrode of the light-emitting element 719. The constant potential is set to the ground potential (GND) or a potential lower than that. 【0257】 It is preferable to use a transistor as the switching element 743. This allows for a reduction in pixel area, resulting in a high-resolution EL display device. As the switching element 743, a transistor was manufactured using the same process as transistor 741. Using transistor 74 can increase the productivity of EL display devices. 1 and / or, as the switching element 743, for example, the transistor described above can be applied. It is possible. 【0258】 Figure 21(B) is a top view of the EL display device. The EL display device consists of a substrate 700 and a substrate 7 50, seal material 734, drive circuit 735, drive circuit 736, pixel 737, FP C732 and, have, the sealing material 734, pixel 737, drive circuit 735 and drive circuit It is positioned between circuit boards 700 and 750 so as to surround 736. Note that the drive circuit 735 Alternatively, the drive circuit 736 may be placed outside the sealant 734. 【0259】 Figure 21(C) is a cross-sectional view of an EL display device, corresponding to a portion of the dashed line MN in Figure 21(B). That is the case. 【0260】 Figure 21(C) shows that transistor 741 is represented by an insulator 708 on substrate 700 and an insulator The insulator 708 and the conductor 704a are embedded in 708. The upper insulator 712a, the insulator 712b on the insulator 712a, and the insulator 712b The semiconductor 706 overlapping the conductor 704a, and the conductor 716a and conductor in contact with the semiconductor 706. The conductive body 716b and the insulators 7 on the semiconductor 706, the conductive body 716a, and the conductive body 716b. 18a, insulator 718b on insulator 718a, and insulator 718c on insulator 718b The structure includes a conductive material 714a that is located on an insulator 718c and overlaps with a semiconductor 706. Note that the structure of transistor 741 is just one example, and may differ from the structure shown in Figure 21(C). It may be so. The conductor 704a has a wiring layer formed by the method described in Embodiment 1. You may use it. 【0261】 Therefore, in the transistor 741 shown in Figure 21(C), the conductor 704a is the gate Having the function of an electrode, insulators 712a and 712b function as gate insulators. It has a function, with conductor 716a functioning as a source electrode and conductor 716b being a drain It functions as an electrode, and insulators 718a, 718b, and 718c are The electrode has the function of an insulator, and the conductor 714a has the function of a gate electrode. Oh, the electrical properties of semiconductor 706 may change when exposed to light. Therefore, One or more of the electric element 704a, conductor 716a, conductor 716b, and conductor 714a are shielded. It is preferable that it is photosensitive. 【0262】 Note that the interface between insulator 718a and insulator 718b is shown with a dashed line; this represents the boundary between the two. This indicates that there may be cases where it is not clear. For example, consider insulator 718a and insulator 718b. Therefore, when using the same type of insulator, it may be impossible to distinguish between the two depending on the observation method. 【0263】 Figure 21(C) shows that the capacitive element 742 consists of an insulator 708 on the substrate and embedded in the insulator 708. The embedded conductor 704b, the insulator 708, and the insulator 712a on the conductor 704b , an insulator 712b on insulator 712a, and an insulator 712b that overlaps with conductor 704b A conductor 716a, an insulator 718a on the conductor 716a, and an insulator on the insulator 718a 718b, an insulator 718c on the insulator 718b, and a conductor 71 on the insulator 718c It has a conductor 714b that overlaps with 6a, and the overlapping of conductor 716a and conductor 714b The region shows a structure in which a portion of insulators 718a and 718b has been removed. The conductive material 704b may be a wiring layer formed by the method described in Embodiment 1. 【0264】 In the capacitive element 742, the conductors 704b and 714b function as one of the electrodes. The conductor 716a functions as the other electrode. 【0265】 Therefore, the capacitive element 742 is fabricated using a film common to the transistor 741. This is possible. Furthermore, it is preferable to use the same type of conductor for conductors 704a and 704b. In that case, the conductor 704a and the conductor 704b can be formed through the same process. It is possible. Furthermore, it is preferable to use the same type of conductor for conductors 714a and 714b. In this case, the conductor 714a and the conductor 714b can be formed through the same process. . 【0266】 The capacitive element 742 shown in Figure 21(C) is a capacitive element with a large capacitance per unit area. Therefore, Figure 21(C) is an EL display device with high display quality. The capacitive element 742 shown is designed to thin the overlapping region of the conductors 716a and 714b. Therefore, although it has a structure in which a portion of the insulators 718a and 718b are removed, the present invention Capacitive elements relating to one embodiment are not limited thereto. For example, conductor 716a and In order to thin the overlapping region of the conductor 714b, a structure was created in which a portion of the insulator 718c was removed. It's okay to have it. 【0267】 An insulator 720 is placed on the transistor 741 and the capacitive element 742. Here, The insulator 720 reaches the conductor 716a, which functions as the source electrode of the transistor 741. It may have an opening. A conductor 781 is placed on the insulator 720. 1 may be electrically connected to transistor 741 through an opening in insulator 720. 【0268】 A partition wall 784 having an opening that reaches the conductor 781 is placed on the conductor 781. A light-emitting layer 782 is positioned on the wall 784, in contact with the conductor 781 at the opening of the partition wall 784. A conductor 783 is placed on the light-emitting layer 782. Conductor 781, light-emitting layer 782 and The overlapping region of the conductor 783 becomes the light-emitting element 719. 【0269】 Up to this point, we have explained examples of EL displays. Next, we will explain examples of liquid crystal displays. do. 【0270】 Figure 22(A) is a circuit diagram showing an example of the pixel configuration of a liquid crystal display device. The pixels shown in Figure 22 are , a transistor 751, a capacitive element 752, and an element (liquid crystal) filled between a pair of electrodes. It has a crystal element 753. 【0271】 In transistor 751, either the source or the drain is electrically connected to the signal line 755. The gate is electrically connected to scan line 754. 【0272】 In the capacitive element 752, one electrode supplies electricity to the source and the other to the drain of the transistor 751. They are connected to each other, and the other electrode is electrically connected to a wiring that supplies a common potential. 【0273】 In the liquid crystal element 753, one electrode supplies electricity to the source and the other to the drain of the transistor 751. They are connected to each other, and the other electrode is electrically connected to a wiring that supplies a common potential. The common potential applied to the wiring to which the other electrode of the capacitive element 752 described above is electrically connected, The common potential applied to the other electrode of the liquid crystal element 753 may be at a different potential. 【0274】 Furthermore, the top view of the liquid crystal display device will be explained in the same way as that of the EL display device. Figure 21(B) Figure 22(B) shows a cross-sectional view of the liquid crystal display device corresponding to the dashed line MN. Furthermore, FPC732 is connected to wiring 733a via terminal 731. 3a is a conductor of the same type as either a conductor or semiconductor that constitutes transistor 751. Alternatively, semiconductors may be used. 【0275】 Transistor 751 refers to the description of transistor 741. Also, capacitive elements Reference 752 refers to the description of the capacitive element 742. Note that Figure 22(B) is shown in Figure 21. The structure of the capacitance element 752 corresponding to the capacitance element 742 in (C) is shown, but it is not limited to this. stomach. 【0276】 Furthermore, when an oxide semiconductor is used for the semiconductor of transistor 751, the off-current is extremely small. It can be made into a transistor. Therefore, the charge held in the capacitive element 752 It is less prone to cracking and can maintain the voltage applied to the liquid crystal element 753 over a long period of time. Therefore, when displaying videos or still images with little movement, transistor 751 is turned off. This eliminates the need for power to operate transistor 751, resulting in a low-power liquid crystal. It can be used as a crystal display device. Also, the occupied area of ​​the capacitive element 752 can be reduced, This makes it possible to provide liquid crystal display devices with a high aperture ratio or high-resolution liquid crystal display devices. 【0277】 An insulator 721 is placed on the transistor 751 and the capacitive element 752. Here, The insulator 721 has an opening that reaches the transistor 751. On the insulator 721, The conductive body 791 is positioned. The conductive body 791 passes through the opening of the insulator 721 to the transistor. Connect electrically to 751. 【0278】 An insulator 792, which functions as an alignment film, is placed on the conductor 791. A liquid crystal layer 793 is placed there. An insulator 7 that functions as an alignment layer is placed on top of the liquid crystal layer 793. 94 is placed. Spacer 795 is placed on insulator 794. Spacer 795 And a conductor 796 is placed on the insulator 794. On the conductor 796, a substrate 79 A 7 is placed. 【0279】 The above-described structure provides a display device having a capacitive element with a small occupied area. It is possible to do so, or to provide a display device with high display quality. Or, high definition A display device can be provided. 【0280】 For example, in this specification, etc., display element, display device having a display element, light-emitting element A light-emitting device, which is a device having a sub-element and a light-emitting element, can be used in various forms or It can have various elements. A display element, display device, light-emitting element, or light-emitting device may be, for example, EL elements (EL elements including organic and inorganic materials, organic EL elements, inorganic EL elements), LE D (white LED, red LED, green LED, blue LED, etc.), transistor (current-dependent) Transistors that emit light, electron-emitting elements, liquid crystal elements, electronic inks, electrophoretic elements, etc. Rating light bulbs (GLV), plasma displays (PDP), MEMS (microwave-mediated displays) Display elements using a micro-electromechanical system, digital micromirror - Device (DMD), DMS (Digital Micro Shutter), IMOD (Interface -Fairness Modulation element, shutter-type MEMS display element, optical interference MEMS display elements, electrowetting elements, piezoelectric ceramic displays These include at least one of the following: a display element using carbon nanotubes. In addition, electrical or magnetic effects can alter contrast, brightness, reflectivity, transmittance, etc. It may also have a display medium that converts to a digital display. 【0281】 An example of a display device using EL elements is an EL display. An example of a display device using this is a field emission display (FED). This is a SED type flat-panel display (SED: Surface-conduction E Examples include lectron-emitter displays. Examples of devices include liquid crystal displays (transmissive liquid crystal displays, semi-transmissive liquid crystal displays). (Play, reflective LCD display, direct-view LCD display, projection LCD display) These include: display devices using electronic ink, electronic powder fluid (registered trademark), or electrophoretic elements. Examples include electronic paper. Furthermore, semi-transmissive liquid crystal displays and reflective liquid crystal displays are also examples. In realizing a crystal display, some or all of the pixel electrodes are used as reflective electrodes. The function should be such that it has the following properties. For example, some or all of the pixel electrodes are made of aluminum. It would be good to have silver, etc. Furthermore, in that case, below the reflective electrode, SRAM Any memory circuit can be installed. This further reduces power consumption. It is possible. 【0282】 Furthermore, when using LEDs, graphene or graphite is placed under the LED electrodes or nitride semiconductor. Threads may be placed. Graphene and graphite can be layered to form multilayer films. This is also good. In this way, by providing graphene or graphite, nitrides can be placed on top of it. Semiconductors, such as n-type GaN semiconductors having a crystalline structure, can be easily deposited as thin films. Furthermore, an LED can be constructed by providing a p-type GaN semiconductor with crystals on top of it. Yes, it is possible. Furthermore, between graphene or graphite and the crystalline n-type GaN semiconductor, An AlN layer may be provided. The GaN semiconductor in the LED is deposited by MOCVD. This is also acceptable. However, by providing graphene, the GaN semiconductor of the LED becomes spa It is also possible to deposit the film using the tarting method. 【0283】 (Embodiment 9) A semiconductor device according to one aspect of the present invention comprises a display device, a personal computer, and a recording medium. Image playback devices (typically DVDs: Digital Versatile Discs) To be used in a device that has a display capable of playing back recording media such as the above and displaying the images thereof. This is possible. In addition, electronic devices that can use a semiconductor device according to one aspect of the present invention This includes mobile phones, game consoles including portable models, mobile data terminals, e-readers, and video cameras. , cameras such as digital still cameras, goggle-type displays (head-mounted displays) (Ray), navigation systems, sound reproduction devices (car audio, digital audio) Players, photocopiers, fax machines, printers, multifunction printers, ATMs Examples include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 23. vinegar. 【0284】 Figure 23(A) shows a portable game console, consisting of a casing 901, casing 902, display unit 903, and display unit. 904, Microphone 905, Speaker 906, Control Keys 907, Stylus 908 It has the following features. The portable game console shown in Figure 23(A) has two display units 903 and a display unit. Although it has part 904, the number of display units that a portable game console has is not limited to this. . 【0285】 Figure 23(B) shows a portable data terminal, comprising a first housing 911, a second housing 912, and a first display unit 9 13. It has a second display unit 914, a connection unit 915, an operation key 916, etc. First display unit 913 The first housing 911 is provided, and the second display unit 914 is provided in the second housing 912. Furthermore, the first housing 911 and the second housing 912 are connected by a connecting part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connecting part 915. The video in the first display unit 913 is connected to the first housing 911 and the second housing 9 in the connection unit 915. The configuration may be such that it switches according to the angle between 12 and 12. Also, the first display unit 913 and A display device in which at least one of the second display units 914 is equipped with a function as a position input device. It may also be used. Furthermore, the function as a position input device is provided by a touch panel on the display device. It can be added by providing a loop. Alternatively, the function as a position input device can be provided by a photo It is also possible to add a photoelectric conversion element, also called a sensor, to the pixel portion of the display device. can. 【0286】 Figure 23(C) shows a notebook personal computer, comprising a casing 921, a display unit 922, and a keyboard. It includes a board 923, a pointing device 924, and the like. 【0287】 Figure 23(D) shows an electric refrigerator-freezer, consisting of a casing 931, a refrigerator door 932, and a freezer door 93 It has a third-class rating. 【0288】 Figure 23(E) shows a video camera, comprising a first housing 941, a second housing 942, a display unit 943, It has an operation key 944, a lens 945, a connecting part 946, etc. Operation key 944 and lens 9 45 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. Furthermore, the first housing 941 and the second housing 942 are connected by a connecting part 946. The angle between the first housing 941 and the second housing 942 can be changed by the connecting part 946. The video on the display unit 943 is connected to the first housing 941 and the second housing 942 in the connection unit 946. The configuration may also be configured to switch according to the angle between the two points. 【0289】 Figure 23(F) is an automobile, consisting of a body 951, wheels 952, dashboard 953, and lights. It has 954, etc. 【0290】 This embodiment can be appropriately combined with other embodiments described herein, at least in part. They can be implemented together. 【0291】 (Embodiment 10) In this embodiment, an example of the use of an RF tag according to one aspect of the present invention will be shown with reference to Figure 24. Let me explain. RF tags have a wide range of applications, such as banknotes, coins, securities, and bearer tags. Bonds, certificates (such as driver's licenses and residence certificates, see Figure 24(A)), recording media (DVDs and videotapes) Tapes, etc. (see Figure 24(B)), packaging containers (wrapping paper, bottles, etc., see Figure 24(C)) ), vehicles (bicycles, etc., see Figure 24(D)), personal belongings (bags, glasses, etc.), food products, plants Objects, animals, human bodies, clothing, household goods, medical products including drugs and pharmaceuticals, or electronic devices (liquids) Items such as crystal display devices, EL display devices, television equipment, or mobile phones, or each It can be used by attaching it to luggage tags (see Figures 24(E) and 24(F)) etc. Cut. 【0292】 An RF tag 4000 according to one aspect of the present invention can be attached to or embedded in the surface of an object. It is fixed to the product. For example, in the case of a book, it is embedded in the paper, and in the case of a package made of organic resin. The RF tag is embedded inside the organic resin and fixed to each article. The 4000 is designed to be small, thin, and lightweight, and even after being fixed to an object, it does not affect the design of the object itself. It does not impair the integrity of banknotes, coins, securities, bearer bonds, or certificates. By providing an RF tag 4000 according to one aspect of the present invention to the same type of object, an authentication function can be provided. This allows for counterfeiting to be prevented by utilizing this authentication function. Furthermore, packaging containers... The present invention applies to items such as recording media, personal belongings, food products, clothing, household goods, or electronic devices. By attaching RF tags related to the configuration, the efficiency of systems such as inspection systems can be improved. It is possible to attach an RF tag according to one aspect of the present invention to vehicles as well. This can enhance security against theft and other crimes. 【0293】 As described above, the RF tag according to one aspect of the present invention can be used for each of the applications listed in this embodiment. This reduces the operating power, including the power required for writing and reading information, thus extending the maximum communication distance. It becomes possible to store information for a long period of time. Furthermore, even when the power is cut off, information can be stored for an extremely long period of time. Because it can retain data for extended periods, it can be suitably used in applications where the frequency of writing and reading is low. Cut. 【0294】 This embodiment can be appropriately combined with other embodiments described herein, at least in part. They can be implemented together. [Examples] 【0295】 In this embodiment 1, the wiring layer of embodiment 1 is fabricated and scanned using a scanning transmission electron microscope (Scann ing Transmission Electron Microscope:STE Cross-sectional observation was performed using method M). 【0296】 A thermal oxide film with a thickness of 400 nm was formed on a silicon single crystal wafer. Next, silicon nitride was formed. The film was deposited to a thickness of 50 nm using plasma CVD. Next, the silicon oxidnitride film was deposited using plasma The film was deposited to a thickness of 150 nm using the Zuma CVD method. 【0297】 Next, to form grooves in the silicon oxidizride film, the resist pattern is formed by electron beam exposure. The resist pattern was then etched. Using this resist pattern as a mask, the dry etching method was used. Grooves were formed in the silicon oxidnitride film. 【0298】 After removing the resist, the conductive material was deposited using the metal CVD method. First, titanium nitride was used. A film was deposited to a thickness of nm, and then tungsten was deposited continuously to a thickness of 200 nm. 【0299】 Next, CMP is performed using a silica-containing slurry to create a tongue on the silicon oxide nitride film. Stainless steel and titanium nitride were removed. 【0300】 After CMP (Chemical Polishing), cleaning was performed to remove any slurry or particles remaining on the substrate. The cleaning process involves immersion in ozonated water, followed by brush cleaning, and then treatment with diluted hydrofluoric acid. The sample was washed, then rinsed with pure water and dried. The sample was prepared in this manner. 【0301】 This sample was observed in cross-section in two orthogonal directions using STEM. Figure 25(A) and Figure 25( Figures B) and 25(C) are cross-sectional STEM images taken in two orthogonal directions. 【0302】 Observation revealed that, as in Embodiment 1, the end of the titanium nitride, which is the first conductor, is the end of the groove. In this case, the height is the same as or lower than the height of the groove, and the upper surface of the second conductor W is the edge of titanium nitride. We confirmed that it was at the same height as or lower than the height of the tungsten. Also, the oxidation of tungsten and the associated We confirmed that problems such as periapical detachment were suppressed. [Examples] 【0303】 In this embodiment, the transient having the wiring layer of Embodiment 1 as the first gate electrode, as shown in Figure 3 A transistor was fabricated, and its characteristics were measured. 【0304】 The fabricated transistor had a channel length L = 59 nm and a channel width W = 67 nm. First, we measured the initial characteristics of the transistor. 【0305】 The initial characteristics were measured at room temperature, with the source grounded and the drain voltage (Vd) set to 0.1V. The second gate voltage (Vg) is fixed and varied from -3.0V to +3.0V in 0.1V increments. Next, the drain current (Id) was measured and its fluctuation curve was recorded. Then, the drain voltage was measured. The voltage was fixed at 1.8V, and the drain current fluctuation curve was recorded in the same manner. At this time, the back gate was One of the first gate electrodes was grounded. The result is shown in Figure 26(A), which shows superior on / off characteristics. The desired transistor characteristics were obtained. 【0306】 Next, using the same transistor as above, a voltage is applied to the first gate electrode, which is the back gate. The transistor characteristics were measured after applying the voltage. The first gate potential (Vb) was the back gate. g) is varied at 2V intervals from -4V, -2V, 0V, +2V, to +4V, and the initial characteristics described above are obtained. Under similar measurement conditions, the curve of change in drain current was recorded. Figure 26(B) shows the drain current The voltage is such that the first gate potential, which is the back gate when +0.1V, is -4V, -2V, 0V, + Figure 26(C) shows the curve of change in drain current when the voltage is changed to 2V and +4V. The first gate potential, which is the back gate when the voltage is +1.8V, is set to -4V, -2V, 0V. The curves showing the change in drain current when the voltage is changed to +2V and +4V are shown. 【0307】 When the first gate voltage, which is the back gate, is changed in the negative direction, the drain current As the change curve shifts in the positive direction, and the first gate voltage is changed in the positive direction, We confirmed that the curve of the current change shifted in the negative direction. As a result, the first gate We confirmed that the electrodes functioned as back gates and that threshold voltage control could be performed correctly. [Explanation of symbols] 【0308】 100 transistors 110 transistors 130 Capacitive elements 140 Capacitive elements 200 Imaging device 201 Switch 202 Switch 203 Switch 210 pixel section 211 pixels 212 subpixels 212B subpixels 212G sub-pixels 212R sub-pixels 220 Photoelectric conversion element 230-pixel circuit 231 Wiring 247 Wiring 248 Wiring 249 Wiring 250 Wiring 253 Wiring 254 filters 254B filter 254G filter 254R filter 255 lens 256 light 257 Wiring 260 Peripheral Circuits 270 Peripheral Circuits 280 Peripheral Circuits 290 Peripheral Circuits 291 Light source 300 circuit boards 301 Insulator 302 Insulator 303 Insulator 304 Insulator 305 Insulator 306 Insulator 307 Insulator 308 Insulator 310 Conductors 311 Conductors 312 Conductors 312a Source electrode or drain electrode 312b Source electrode or drain electrode 314 Conductors 315 Conductors 316 Conductors 320 Semiconductors 320a Semiconductor 320c semiconductor 330 Postal Codes 331 gate 341 Electrode 342 Electrode 350 circuit boards 351 STI 353 Diffusion layer 354 Insulator 355 Sidewall 360 Insulator 361 Insulator 362 Insulator 363 Insulator 364 Insulator 365 Insulator 370 plug 371 Plug 372 plug 373 Wiring layer 374 Wiring layer 375 Wiring layer 376 wiring layer 377 Wiring layer 378 Wiring layer 379 Wiring layer 380 wiring layer 381 Wiring layer 382 plug 383 plug 384 plug 385 wiring layer 386 wiring layer 387 Wiring layer 388 plug 389 plug 390 wiring layer 391 Plug 392 plug 393 Wiring layer 394 Wiring layer 500 silicon substrates 510 layers 520 layers 530 layers 540 layers 551 transistors 552 transistors 553 Transistors 560 Photodiodes 561 Anodes 563 Low resistance region 570 plug 571 Wiring 572 Wiring 573 Wiring 580 Insulator 700 circuit boards 704a Conductor 704b Conductor 706 Semiconductors 708 Insulator 712a Insulator 712b Insulator 714a Conductor 714b Conductor 716a Conductor 716b Conductor 718a Insulator 718b Insulator 718c insulator 719 Light-emitting element 720 Insulator 721 Insulator 731 terminal 732 FPC 733a Wiring 734 Sealant 735 Drive Circuit 736 Drive Circuit 737 pixels 741 transistors 742 Capacitive elements 743 Switching element 744 signal line 750 circuit boards 751 transistors 752 Capacitive element 753 Liquid crystal elements 754 scan lines 755 signal line 781 Conductors 782 Emitting layer 783 Conductors 784 Bulkhead 791 Conductors 792 Insulator 793 Liquid crystal layer 794 Insulator 795 Spacer 796 Conductors 797 circuit board 800 RF tags 801 Communication device 802 Antenna 803 Wireless signal 804 Antenna 805 Rectifier circuit 806 Constant Voltage Circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuits 810 Memory circuit 811 ROM 901 cabinet 902 cabinet 903 Display section 904 Display section 905 Microphone 906 Speakers 907 Operation Keys 908 Stylus 911 cabinet 912 cabinet 913 Display section 914 Display section 915 Connection part 916 Operation Keys 921 cabinet 922 Display section 923 Keyboard 924 Pointing Devices 931 cabinet 932 Refrigerator door 933 Freezer door 941 cabinet 942 cabinets 943 Display section 944 Operation Keys 945 lens 946 Connection part 951 Body 952 wheels 953 Dashboard 954 Light 1189 ROM Interface 1190 circuit board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 Memory circuit 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic Element 1207 Capacitive element 1208 Capacitive element 1209 Transistors 1210 Transistors 1213 Transistor 1214 Transistors 1220 Circuit 4000 RF tags 5100 pellets 5120 circuit board 5161 area

Claims

[Claim 1] A semiconductor device having a plurality of insulating films, a first conductor, a second conductor, a third conductor, a fourth conductor, and a fifth conductor, The plurality of insulating films have a first opening, The second conductor is provided below the plurality of insulating films, The first conductor has a region at the bottom of the first opening that is in contact with the second conductor. The third conductor is provided within the plurality of insulating films. The fourth conductor is provided above the plurality of insulating films, The first conductor has a region that is in contact with the side surface of the third conductor, The first conductor has a region in contact with the fourth conductor, The first conductor does not have a region in contact with the fifth conductor. The plurality of insulating films each comprises at least a first insulating film, a second insulating film, and a third insulating film. The first insulating film has a region in contact with the bottom surface of the fifth conductor and a region in contact with the side surface of the first conductor. The second insulating film has a region in contact with the upper surface of the first insulating film, a region in contact with the first side surface of the fifth conductor, and a region in contact with the side surface of the first conductor. The third insulating film has a region in contact with the upper surface of the second insulating film, a region in contact with the second side surface of the fifth conductor, a region in contact with the upper surface of the fifth conductor, and a region in contact with the side surface of the first conductor. The semiconductor device wherein the second conductor is tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum, or a tungsten alloy. [Claim 2] A semiconductor device comprising a silicon substrate, a plurality of insulating films, a first conductor, a second conductor, a third conductor, a fourth conductor, and a fifth conductor, The silicon substrate is provided with a channel formation region for transistors. The plurality of insulating films are provided above the silicon substrate, The plurality of insulating films have a first opening, The second conductor is provided above the silicon substrate and below the plurality of insulating films. The first conductor has a region at the bottom of the first opening that is in contact with the second conductor. The third conductor is provided within the plurality of insulating films. The fourth conductor is provided above the plurality of insulating films, The first conductor has a region that is in contact with the side surface of the third conductor, The first conductor has a region in contact with the fourth conductor, The first conductor does not have a region in contact with the fifth conductor. The plurality of insulating films each comprises at least a first insulating film, a second insulating film, and a third insulating film. The first insulating film has a region in contact with the bottom surface of the fifth conductor and a region in contact with the side surface of the first conductor. The second insulating film has a region in contact with the upper surface of the first insulating film, a region in contact with the first side surface of the fifth conductor, and a region in contact with the side surface of the first conductor. The third insulating film has a region in contact with the upper surface of the second insulating film, a region in contact with the second side surface of the fifth conductor, a region in contact with the upper surface of the fifth conductor, and a region in contact with the side surface of the first conductor. The semiconductor device wherein the second conductor is tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum, or a tungsten alloy. [Claim 3] An electronic device having a semiconductor device as described in claim 1 or claim 2.

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