Semiconductor equipment

Abstract

To improve the active clamp tolerance.SOLUTION: A semiconductor device 1 includes a semiconductor element 20 including a substrate including a transistor formation region 29 with a shape other than a tetragon, where a transistor is formed, and an electrode pad 21 on the transistor formation region 29, and a first bonding wire 41 connected to the electrode pad 21. The electrode pad 21 is provided to cover the center of gravity of the transistor formation region 29 in a plan view. In the plan view, the first bonding wire 41 overlaps the center of gravity of the transistor formation region 29 at a connection point with the electrode pad 21.SELECTED DRAWING: Figure 31A

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] As an example of a semiconductor device, a vertical MOSFET is known in which a drain electrode is formed on a surface on the side mounted on a lead frame, and source electrode pads and gate electrode pads are formed on a surface opposite to the surface on which the drain electrode is formed (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] By the way, a semiconductor device may be connected to an inductive load and may be required to have a function of absorbing energy released from this inductive load at turn-off. If the energy given to the semiconductor device from the inductive load exceeds a predetermined value, the semiconductor device may fail due to a temperature rise. An index indicating how much energy accumulated in the inductive load can be absorbed is shown by the active clamp tolerance. As the value of the active clamp tolerance increases, more energy accumulated in the inductive load can be absorbed. Therefore, it is preferable that the value of the active clamp tolerance is large.

[0005] A semiconductor device according to one aspect of the present disclosure includes a substrate including a transistor formation region having a shape other than a quadrilateral in which a transistor is formed, a semiconductor element having an electrode pad on the transistor formation region, and a first connection member connected to the electrode pad at one location. The electrode pad is provided so as to cover the center of gravity of the transistor formation region in a plan view, and in the plan view, a connection region where the first connection member is connected to the electrode pad includes the center of gravity position of the transistor formation region.

[0006] The inventors of this invention focused on the connection position of the electrode pads of a first connecting member connected to a semiconductor element with respect to the transistor formation region of the semiconductor element in order to improve the active clamp withstand capability of a semiconductor device. The inventors of this invention found that the active clamp withstand capability is improved when the first connecting member is connected to an electrode pad position corresponding to the centroid of the transistor formation region. In view of this, the present semiconductor device is configured such that the connection region to which the first connecting member is connected to the electrode pads includes the centroid of the transistor formation region. Therefore, the active clamp withstand capability can be improved.

[0007] A semiconductor device according to one aspect of the present disclosure includes a substrate including a transistor formation region having a shape other than a rectangle on which a transistor is formed, an electrode pad on the transistor formation region, and a first connecting member connected to the electrode pad at a plurality of locations, wherein the transistor formation region is divided into a plurality of divided regions of equal area according to the number of connection locations of the first connecting member, the electrode pad is provided so as to cover the centroid of each of the plurality of divided regions in a plan view, and in the plan view, the connection region to which the first connecting member is connected to the electrode pad includes the centroid position of each of the plurality of divided regions.

[0008] The inventors of this invention focused on the connection position of the electrode pads of a first connecting member connected to a semiconductor element with respect to the transistor formation region of the semiconductor element in order to improve the active clamp withstand capability of a semiconductor device. The inventors of this invention found that when the first connecting member is connected to the electrode pads at two locations, the active clamp withstand capability is improved when the first connecting member is connected to the electrode pads at positions corresponding to the centroids of two divided regions into equal areas of the transistor formation region. In view of this, the present semiconductor device is configured such that the connection region to which the first connecting member is connected to the electrode pads includes the centroids of each of the multiple divided regions into equal areas of the transistor formation region. Therefore, the active clamp withstand capability can be improved.

[0009] A semiconductor device according to one aspect of the present disclosure includes a substrate including a transistor formation region having a shape other than a rectangle on which a transistor is formed, an electrode pad on the transistor formation region, and a plurality of first connecting members connected to the electrode pad, wherein the transistor formation region is divided into a plurality of divided regions having equal areas according to the number of first connecting members, the electrode pad is provided so as to cover the centroid of each of the plurality of divided regions in a plan view, and the connection region to which each of the plurality of first connecting members is connected in a plan view includes the centroid position of each of the plurality of divided regions.

[0010] The inventors of this invention focused on the connection position of the electrode pads of the first connecting members connected to the semiconductor element with respect to the transistor formation region of the semiconductor element in order to improve the active clamp withstand capability of a semiconductor device. The inventors of this invention found that when multiple first connecting members are connected to electrode pads, the active clamp withstand capability is improved when the first connecting members are connected to electrode pads at positions corresponding to the centroid of each of the multiple divided regions, which are obtained by dividing the transistor formation region into equal areas according to the number of first connecting members. In view of this, the present semiconductor device is configured such that the connection region to which multiple first connecting members are connected to electrode pads includes the centroid of each of the multiple divided regions, which are obtained by dividing the region into equal areas according to the number of first connecting members. Therefore, the active clamp withstand capability can be improved.

[0011] A semiconductor device according to one aspect of the present disclosure includes a substrate including a transistor formation region having a shape other than a rectangle on which a transistor is formed, a semiconductor element having an electrode pad on the transistor formation region, and a first connecting member connected to the electrode pad at one point, wherein the electrode pad is provided so as to cover the center of gravity of the transistor formation region in a plan view, and in the plan view, the connecting region to which the first connecting member is connected to the electrode pad includes the position of the center of gravity of the transistor formation region, and the substrate includes a plurality of trenches and a plurality of functional element shapes including channel formation regions arranged along each of the plurality of trenches and forming current paths A plurality of functional element formation regions are formed, and the plurality of functional element formation regions include a first functional element formation region in which the area of ​​the channel formation region per unit area is relatively small, and a second functional element formation region in which the area of ​​the channel formation region per unit area is relatively large, the first functional element formation region is provided in a region of the plurality of functional element formation regions in which heat generation should be suppressed, a metal layer is formed between the functional element formation region and the electrode pad to electrically connect the functional element formation region and the electrode pad, and one or more slits are provided in at least the portion of the metal layer facing the electrode pad.

[0012] A semiconductor device according to one aspect of the present disclosure includes a substrate including a transistor formation region having a shape other than a rectangle on which a transistor is formed, a semiconductor element having an electrode pad on the transistor formation region, and a first connecting member connected to the electrode pad at one location, wherein the electrode pad is provided so as to cover the centroid of the transistor formation region in a plan view, and in the plan view, the connecting region to which the first connecting member is connected to the electrode pad includes the centroid of the transistor formation region, and the electrode pad has a first protective layer covering an interlayer insulating film, a first electrode layer covering the first protective layer, a second protective layer covering the first electrode layer, and a second electrode layer covering the second protective layer, wherein the Vickers hardness of the first protective layer and the second protective layer are greater than the Vickers hardness of the first electrode layer and the second electrode layer, respectively.

[0013] A semiconductor device according to one aspect of the present disclosure includes a substrate including a transistor formation region having a shape other than a rectangle on which a transistor is formed, an electrode pad on the transistor formation region, and a first connecting member connected to the electrode pad at one point, wherein the electrode pad is provided so as to cover the center of gravity of the transistor formation region in a plan view, and in the plan view, the connecting region to which the first connecting member is connected to the electrode pad includes the position of the center of gravity of the transistor formation region, and the first connecting member is an aluminum wire wedge-bonded to the electrode pad.

[0014] A semiconductor device according to one aspect of the present disclosure includes a substrate including a transistor formation region having a shape other than a rectangle on which a transistor is formed, an electrode pad on the transistor formation region, and a first connecting member connected to the electrode pad at one point, wherein the electrode pad is provided so as to cover the centroid of the transistor formation region in a plan view, and in the plan view, the connecting region to which the first connecting member is connected to the electrode pad includes the centroid of the transistor formation region, and the first connecting member is a copper wire wedge-bonded to the electrode pad.

[0015] A semiconductor device according to one aspect of the present disclosure includes a substrate including a transistor formation region having a shape other than a rectangle on which a transistor is formed and a control circuit region provided with a circuit for controlling the transistor; a semiconductor element having a temperature sensor provided in the control circuit region and an electrode pad on the transistor formation region; and a first connecting member connected to the electrode pad, wherein the transistor formation region has a first region and a second region having a larger area than the first region; the temperature sensor is positioned adjacent to the transistor formation region; the electrode pad is provided so as to cover the respective centers of gravity of the first region and the second region in a plan view; and in the plan view, the connecting region to which the first connecting member is connected to the electrode pad includes the center of gravity of the transistor formation region. A semiconductor device according to one aspect of the present disclosure includes a substrate including a transistor formation region having a shape other than a rectangle on which transistors are formed, and a semiconductor element having an electrode pad on the transistor formation region, and a first bonding wire connected to the electrode pad. The electrode pad is provided so as to cover the center of gravity of the transistor formation region in a plan view, and in the plan view, the first bonding wire overlaps with the center of gravity of the transistor formation region at a connection point with the electrode pad.

Brief Description of the Drawings

[0016] [Figure 1] A semiconductor device according to the first embodiment, where (a) is a plan view of the semiconductor device, (b) is a side view of the semiconductor device, and (c) is a bottom view of the semiconductor device. [Figure 2] A plan view showing the internal structure of the semiconductor device. [Figure 3] A cross-sectional view taken along line 3-3 of FIG. 1. [Figure 4] A cross-sectional view taken along line 4-4 of FIG. 1. [Figure 5] A plan view schematically showing the layout of a semiconductor element, which is the semiconductor element of the semiconductor device. [Figure 6] A circuit diagram showing the circuit configuration of the semiconductor device. [Figure 7] A plan view schematically showing the active region and source pad of the semiconductor element. [Figure 8] A plan view schematically showing the active region and source pad of the semiconductor element. [Figure 9] A cross-sectional view schematically showing the structure of a MISFET constituting a part of the semiconductor element. [Figure 10] An enlarged view of one trench gate structure in FIG. 9 and its periphery. [Figure 11] A plan view schematically showing the epitaxial layer of the MISFET. [Figure 12] A cross-sectional view schematically showing the structure of a low-voltage CMOSFET constituting a part of the semiconductor element. [Figure 13] A cross-sectional view schematically showing the structure of a MOS capacitor constituting a part of the semiconductor element. [Figure 14] Cross-sectional view schematically showing the structure of a polysilicon resistor forming part of a semiconductor device. [Figure 15] Cross-sectional view schematically showing the structure of a high-voltage N-channel MOSFET forming part of a semiconductor device. [Figure 16] Cross-sectional view schematically showing the structure of a high-voltage P-channel MOSFET forming part of a semiconductor device. [Figure 17] Cross-sectional view schematically showing the structure of an NPN transistor forming part of a semiconductor device. [Figure 18] Flowchart showing a method of manufacturing a semiconductor device. [Figure 19A] Diagram showing part of the manufacturing process of a semiconductor device. [Figure 19B] Diagram showing the step following that of Fig. 19A. [Figure 19C] Diagram showing the step following that of Fig. 19B. [Figure 19D] Diagram showing the step following that of Fig. 19C. [Figure 19E] Diagram showing the step following that of Fig. 19D. [Figure 19F] Diagram showing the step following that of Fig. 19E. [Figure 20] Plan view schematically showing the active region and source pad of a semiconductor device according to the second embodiment. [Figure 21] Plan view schematically showing the active region and source pad of the same semiconductor device. [Figure 22] Side view of the first wire connected to the source pad of Fig. 21. [Figure 23] Cross-sectional view schematically showing the structure of part of a MISFET of a semiconductor device according to the third embodiment. [Figure 24] Plan view schematically showing the active region and source pad of a semiconductor device according to the fourth embodiment. [Figure 25] Plan view schematically showing the active region and source pad of the same semiconductor device. [Figure 26A] Plan view schematically showing the epitaxial layer of the same semiconductor device. [Figure 26B] A schematic plan view showing the epitaxial layer of the semiconductor device. [Figure 26C] A schematic plan view showing the epitaxial layer of the semiconductor device. [Figure 27A] This diagram shows part of the manufacturing process for MISFETs, a type of semiconductor device. [Figure 27B] This diagram shows the next step after Figure 27A. [Figure 27C] This diagram shows the next step after Figure 27B. [Figure 27D] This figure shows the next step after Figure 27C. [Figure 27E] This figure shows the next step after Figure 27D. [Figure 27F] This diagram shows the next step in Figure 27E. [Figure 27G] This diagram shows the next step after Figure 27F. [Figure 27H] This figure shows the next step after Figure 27G. [Figure 27I] This figure shows the next step after Figure 27H. [Figure 27J] This figure shows the next step after Figure 27I. [Figure 27K] This figure shows the next step in Figure 27J. [Figure 28A] A schematic plan view showing the active region and source pad of a semiconductor element in a modified semiconductor device. [Figure 28B] A schematic plan view showing the active region and source pad of the semiconductor device. [Figure 29] Side views of the heat dissipation members provided on the semiconductor elements in Figures 28A and 28B. [Figure 30A] A schematic plan view showing the active region and source pad of a semiconductor element in a modified semiconductor device. [Figure 30B] A schematic plan view showing the active region and source pad of the semiconductor device. [Figure 31A] Figure 30A is a schematic plan view showing the internal structure of a semiconductor device having a semiconductor element. [Figure 31B] Figure 30B is a schematic plan view showing the internal structure of a semiconductor device having a semiconductor element. [Figure 31C] Figure 30B is a schematic plan view showing the internal structure of a semiconductor device having a semiconductor element. [Figure 32A] A schematic plan view showing the active region and source pad of a semiconductor element in a modified semiconductor device. [Figure 32B] A schematic plan view showing the active region and source pad of the semiconductor device. [Figure 33A] Figure 32A is a schematic plan view showing the internal structure of a semiconductor device having a semiconductor element. [Figure 33B] Figure 32B is a schematic plan view showing the internal structure of a semiconductor device having a semiconductor element. [Figure 34A] A schematic plan view showing the active region and source pad of a semiconductor element in a modified semiconductor device. [Figure 34B] A schematic plan view showing the active region and source pad of the semiconductor device. [Figure 35A] Figure 34A is a schematic plan view showing the internal structure of a semiconductor device having a semiconductor element. [Figure 35B] Figure 34B is a schematic plan view showing the internal structure of a semiconductor device having a semiconductor element. [Figure 36] A schematic plan view showing the internal structure of a modified semiconductor device. [Figure 37] Figure 36 is a schematic plan view showing the active region and source pad of the semiconductor element of the semiconductor device. [Figure 38] A schematic plan view showing the internal structure of a modified semiconductor device. [Figure 39] A schematic cross-sectional view showing part of the structure of a modified semiconductor device called a MISFET. [Figure 40] A graph showing the relationship between the pad thickness of the source pad and the maximum principal stress. [Figure 41] A graph showing the relationship between source pad thickness and TDDB failure time. [Figure 42] An explanatory diagram relating to the first application example of a semiconductor device. [Figure 43] An explanatory diagram relating to a second application example of a semiconductor device. [Figure 44]An explanatory diagram relating to the third application example of a semiconductor device. [Figure 45] An explanatory diagram relating to the fourth application example of the semiconductor device. [Figure 46] An explanatory diagram relating to the fifth application example of the semiconductor device.

[0017] [Detailed explanation] The embodiments of the semiconductor device will be described below with reference to the drawings. The embodiments shown below are illustrative of configurations and methods for realizing the technical concept, and are not limited to the materials, shapes, structures, arrangements, dimensions, etc., of each component. Various modifications can be made to the embodiments below.

[0018] In this specification, "member A connected to member B" includes cases where member A and member B are physically and directly connected, as well as cases where member A and member B are indirectly connected via other members that do not affect the electrical connection state.

[0019] Similarly, "the state in which member C is provided between member A and member B" includes cases where member A and member C, or member B and member C are directly connected, as well as cases where member A and member C, or member B and member C are indirectly connected via other members that do not affect the electrical connection state.

[0020] (First Embodiment) As shown in Figures 1(a) to 3, the semiconductor device 1 comprises a lead frame 10, a semiconductor element 20 mounted on the lead frame 10, and a sealing resin 30 that seals a part of the lead frame 10 and the semiconductor element 20. The semiconductor element 20 includes, for example, a transistor connected to an inductive load, and switches the transistor on and off. Preferably, the semiconductor device 1 has an on-resistance of 30 mΩ or less for the semiconductor element 20. An example of an on-resistance of the semiconductor element 20 is 28 mΩ. The semiconductor device 1 is used, for example, in a control circuit of an in-vehicle electrical component. Examples of in-vehicle electrical components include engines, air conditioning systems, steering systems, etc. The dimensions of the sealing resin 30 are approximately 6.6 mm in the horizontal direction X, approximately 6.1 mm in the vertical direction Y, and approximately 2.3 mm in the thickness direction Z. The semiconductor device 1 may also be used in a control device for equipment other than in-vehicle electrical components (for example, an outdoor unit of an air conditioner).

[0021] The sealing resin 30 has a first side surface 31 and a second side surface 32 which are the lateral X side surfaces, a third side surface 33 and a fourth side surface 34 which are the longitudinal Y side surfaces, and a fifth side surface 35 and a sixth side surface 36 which are the thickness Z side surfaces. The sealing resin 30 is formed from a thermosetting resin in which a filler is dispersed. An example of a thermosetting resin is an epoxy resin. An example of a filler is a silica filler. An example of a filler mixing ratio to epoxy resin is 85 to 90 volume%. It is preferable that the sealing resin 30 is made of a material with a linear expansion coefficient greater than 10 ppm / K and less than 15 ppm / K. The linear expansion coefficient of the sealing resin 30 can be changed, for example, by the filler mixing ratio. In this embodiment, the linear expansion coefficient of the sealing resin 30 is 12 ppm / K.

[0022] The lead frame 10 has a first lead frame 11, a second lead frame 12, and a third lead frame 13. Each lead frame 11, 12, and 13 is formed of, for example, copper (Cu). The outer surface of each lead frame 11, 12, and 13 is plated with nickel (Ni). Figures 3 and 4 show examples of the plating layers 14 of the first lead frame 11 and the second lead frame 12.

[0023] As shown in Figures 1(a) and 2, the first lead frame 11 is configured to include an output terminal OUT. It has a first island portion 11a and a first terminal portion 11b. The first island portion 11a and the first terminal portion 11b are formed integrally. However, the first island portion 11a and the first terminal portion 11b may be formed individually and then connected to each other.

[0024] The first island portion 11a is formed in a substantially rectangular shape in plan view. A portion of the first island portion 11a in the vertical direction Y protrudes in the vertical direction Y from the third side surface 33 of the sealing resin 30. As shown in Figures 1(b) and 1(c), the first island portion 11a is exposed from the sixth side surface 36 of the sealing resin 30. The first island portion 11a has a main body portion 11c located inside the sealing resin 30, a narrow portion 11d provided inside the sealing resin 30 near the third side surface 33, and a tip portion 11e extending in the vertical direction Y from the narrow portion 11d. A portion of the tip portion 11e protrudes from the third side surface 33 of the sealing resin 30. In this embodiment, the lateral dimension X of the tip portion 11e is smaller than the lateral dimension X of the main body portion 11c. A recess 11f is provided at the tip edge of the tip portion 11e in the vertical direction Y, which is recessed toward the third side surface 33. Since the narrow portion 11d of the first island portion 11a creates a recess in the lateral direction X, the adhesion with the sealing resin 30 is improved and the movement of the first island portion 11a in the vertical direction Y relative to the sealing resin 30 can be suppressed.

[0025] As shown in Figures 1(a) and 1(c), the area of ​​the portion of the main body 11c of the first island portion 11a that is exposed from the sixth side surface 36 of the sealing resin 30 is smaller than the area of ​​the main body 11c in a plan view. More specifically, in the thickness direction Z, the portion of the main body 11c on the fifth side surface 35 of the sealing resin 30 is longer in the lateral direction X than the portion of the main body 11c on the sixth side surface 36 of the sealing resin 30. As a result, the portion of the main body 11c on the fifth side surface 35 of the sealing resin 30 is sandwiched by the sealing resin 30 in the thickness direction Z, thereby suppressing movement of the first lead frame 11 in the thickness direction Z.

[0026] The shape of the first island portion 11a can be arbitrarily changed. For example, at least one of the narrow portion 11d and the recess 11f may be omitted. Also, the lateral dimension X of the tip portion 11e may be greater than or equal to the lateral dimension X of the main body portion 11c. Furthermore, the tip portion 11e may constitute an output terminal OUT. In addition, the area of ​​the portion of the first island portion 11a that is exposed from the sixth side surface 36 of the sealing resin 30 in the main body portion 11c may be equal to the area of ​​the main body portion 11c in plan view.

[0027] As shown in Figure 4, the first terminal portion 11b, which constitutes the output terminal OUT, protrudes in the vertical direction Y from the fourth side surface 34 of the sealing resin 30. The portion of the first terminal portion 11b that protrudes from the fourth side surface 34 of the sealing resin 30 is located on the fifth side surface 35 side of the sealing resin 30 in the thickness direction Z, compared to the first island portion 11a. The first terminal portion 11b has a first bent portion 11g that is bent toward the fifth side surface 35 of the sealing resin 30 from the portion connected to the first island portion 11a, an inclined portion 11h that slopes toward the fifth side surface 35 as it approaches the fourth side surface 34 of the sealing resin 30, a second bent portion 11i that is bent again near the fourth side surface 34 of the sealing resin 30, and a tip portion 11j that is perpendicular to the thickness direction Z and extends in the vertical direction Y. A part of the tip portion 11j protrudes from the fourth side surface 34 of the sealing resin 30. In this embodiment, the first bent portion 11g, the inclined portion 11h, the second bent portion 11i, and the tip portion 11j are integrally formed.

[0028] As shown in Figure 2, the second lead frame 12 constitutes the input terminal IN. The second lead frame 12 is positioned on the first side surface 31 and the fourth side surface 34 of the sealing resin 30. The second lead frame 12 has a second island portion 12a and a second terminal portion 12b. The second island portion 12a and the second terminal portion 12b are formed integrally. However, the second island portion 12a and the second terminal portion 12b may be formed individually and then connected to each other.

[0029] The second island portion 12a is formed in a rectangular shape in a plan view, with a length in the horizontal direction X being longer than the length in the vertical direction Y. In the vertical direction Y, the second island portion 12a is positioned closer to the fourth side surface 34 of the sealing resin 30 than the first island portion 11a. In the horizontal direction X, the second island portion 12a is positioned closer to the first side surface 31 of the sealing resin 30 than the first terminal portion 11b. In the thickness direction Z, the second island portion 12a is positioned closer to the fifth side surface 35 of the sealing resin 30 than the first island portion 11a.

[0030] The second terminal portion 12b extends in the vertical direction Y from the portion of the second island portion 12a closer to the first side surface 31 of the sealing resin 30. The second terminal portion 12b protrudes from the fourth side surface 34 of the sealing resin 30. The length in the vertical direction Y of the portion of the second terminal portion 12b protruding from the fourth side surface 34 of the sealing resin 30 is longer than the length in the vertical direction Y of the portion of the first terminal portion 11b protruding from the fourth side surface 34 of the sealing resin 30. The second terminal portion 12b is formed by bending its tip so that it is at the same position as the first island portion 11a in the thickness direction Z.

[0031] The third lead frame 13 constitutes the ground terminal GND. The third lead frame 13 has a third island portion 13a and a third terminal portion 13b. The third island portion 13a and the third terminal portion 13b are formed integrally. However, the third island portion 13a and the third terminal portion 13b may be formed individually and then connected to each other.

[0032] The third island portion 13a is formed in a rectangular shape in a plan view, with a length in the horizontal direction X being longer than the length in the vertical direction Y. In the vertical direction Y, the third island portion 13a is positioned closer to the fourth side surface 34 of the sealing resin 30 than the first island portion 11a. In the horizontal direction X, the third island portion 13a is positioned closer to the second side surface 32 of the sealing resin 30 than the first terminal portion 11b. In the thickness direction Z, the third island portion 13a is positioned closer to the fifth side surface 35 of the sealing resin 30 than the first island portion 11a (see Figure 3).

[0033] The third terminal portion 13b extends in the vertical direction Y from the portion of the sealing resin 30 near the second side surface 32 in the third island portion 13a. The third terminal portion 13b protrudes from the fourth side surface 34 of the sealing resin 30. The length in the vertical direction Y of the portion of the third terminal portion 13b that protrudes from the fourth side surface 34 of the sealing resin 30 is longer than the length in the vertical direction Y of the portion of the first terminal portion 11b that protrudes from the fourth side surface 34 of the sealing resin 30, and is equal to the length in the vertical direction Y of the portion of the second terminal portion 12b that protrudes from the fourth side surface 34 of the sealing resin 30. The third terminal portion 13b is formed by bending its tip so that it is at the same position as the first island portion 11a in the thickness direction Z (see Figure 3).

[0034] As shown in Figures 2 and 3, a semiconductor element 20 is mounted on the surface 11x of the main body portion 11c of the first lead frame 11. More specifically, solder SD is applied to the surface 11x of the main body portion 11c. The semiconductor element 20 is placed on the solder SD. As shown in Figure 2, the semiconductor element 20 is located in the portion of the main body portion 11c closer to the fourth side surface 34 of the sealing resin 30 (closer to the second island 12a and the third island 13a in the vertical direction Y) in the vertical direction Y. The semiconductor element 20 is located in the center of the main body portion 11c in the horizontal direction X.

[0035] The semiconductor element 20 in this embodiment is a power MOSFET or an IGBT. The semiconductor element 20 is formed in a rectangular shape in a plan view, with the horizontal direction X being the longitudinal direction relative to the vertical direction Y. The dimensions of the semiconductor element 20 in this embodiment are 2.25 mm in the vertical direction Y and 2.68 mm in the horizontal direction X. However, the shape or dimensions of the semiconductor element 20 in a plan view are not limited to these. For example, the semiconductor element 20 may be formed in the shape of a square with the dimensions in the vertical direction Y and the horizontal direction X being equal to each other.

[0036] The surface 20x of the semiconductor element 20 is provided with a source pad 21, which is an example of an electrode pad, and a gate pad 22, which is an example of a control electrode pad. The back surface 20y of the semiconductor element 20 (see Figure 3), that is, the surface of the semiconductor element 20 facing the first island portion 11a, is provided with a drain electrode. The drain electrode is electrically connected to the first island portion 11a (first lead frame 11) via solder SD.

[0037] One end of a first wire 41, which is an example of a connecting member, is connected to the source pad 21. The other end of the first wire 41 is connected to the third island portion 13a of the third lead frame 13. The first wire 41 is connected to the source pad 21 and the third island portion 13a, respectively, by wedge bonding, for example. In this embodiment, there is one first wire 41. The first wire 41 in this embodiment is an aluminum wire made of aluminum (Al). The wire diameter of the first wire 41 is preferably, for example, 100 μm or more. The wire diameter of the first wire 41 is more preferably, for example, 300 μm to 400 μm. In this embodiment, the wire diameter of the first wire 41 is about 300 μm. The first wire 41 may also be a copper wire made of copper (Cu).

[0038] As shown in Figure 2, one end of the second wire 42 is connected to the gate pad 22. The other end of the second wire 42 is connected to the second island portion 12a of the second lead frame 12. The second wire 42 is connected to the gate pad 22 and the second island portion 12a, respectively, by wedge bonding, for example. In this embodiment, there is one second wire 42. The material of the second wire 42 can be, for example, aluminum (Al) or copper (Cu). In this embodiment, aluminum is used for the second wire 42. The diameter of the second wire 42 is smaller than the diameter of the first wire 41. The diameter of the second wire 42 is, for example, 125 μm.

[0039] As shown in Figures 2 and 5, the semiconductor element 20 has a rectangular substrate 50 in plan view. The substrate 50 has a first side surface 51 and a second side surface 52 along the vertical direction Y, and a third side surface 53 and a fourth side surface 54 along the horizontal direction X. The first side surface 51 is the side of the substrate 50 that is on the side of the first side surface 31 of the sealing resin 30, the second side surface 52 is the side of the substrate 50 that is on the side of the second side surface 32 of the sealing resin 30, the third side surface 53 is the side of the substrate 50 that is on the side of the third side surface 33 of the sealing resin 30, and the fourth side surface 54 is the side of the substrate 50 that is on the side of the fourth side surface 34 of the sealing resin 30.

[0040] The semiconductor element 20 has a switching circuit 23 that includes multiple power MISFETs (Metal Insulator Semiconductor Field Effect Transistors), which are examples of functional elements fabricated on the surface layer of the substrate 50. The semiconductor element 20 further includes an overcurrent protection (OCD) circuit 24, an overheating protection (TSD) circuit 25, an undervoltage lockout (UVLO) circuit 26, a temperature sensor 27, and a current sensor 28, which are examples of control circuits that control the switching circuit 23. The overcurrent protection circuit 24, the overheating protection circuit 25, the undervoltage lockout circuit 26, the temperature sensor 27, and the current sensor 28 are all fabricated on the surface layer of the substrate 50. In other words, the semiconductor element 20 is an Intelligent Power Switch (IPS) in which a switching circuit 23 (power MISFET), an overcurrent protection circuit 24, an overheat protection circuit 25, an undervoltage malfunction prevention circuit 26, a temperature sensor 27, and a current sensor 28 are fabricated on the surface layer of a common substrate 50.

[0041] The switching circuit 23 is formed within an active region 29 set on the substrate 50. The active region 29 is formed in a roughly L-shape so as to avoid the gate pad 22 and the temperature sensor 27 in a plan view. More specifically, in a plan view, the active region 29 has a first side 29a closest to the first side surface 51 of the substrate 50, a second side 29b closest to the third side surface 53 of the substrate 50, a third side 29c closest to the second side surface 52 of the substrate 50, a fourth side 29d closest to the fourth side surface 54 of the substrate 50, and a fifth side 29e and a sixth side 29f that constitute a notch portion of the active region 29. The fifth side 29e is a side extending in the vertical direction Y, and the sixth side 29f is a side extending in the horizontal direction X. One end of the first side 29a is connected to the second side 29b, and the other end of the first side 29a is connected to the sixth side 29f. On the second side 29b, the end opposite to the first side 29a is connected to the third side 29c. On the third side 29c, the end opposite to the second side 29b is connected to the fourth side 29d. On the fourth side 29d, the end opposite to the third side 29c is connected to the fifth side 29e. On the fifth side 29e, the end opposite to the fourth side 29d is connected to the sixth side 29f. As can be seen from Figure 5, the length of the first side 29a is shorter than the length of the third side 29c, and the length of the second side 29b is longer than the length of the fourth side 29d. The active region 29 is covered by the source pad 21. The source pad 21 is formed in a roughly L-shape in plan view. More specifically, the source pad 21 is provided on the substrate 50 closer to the third side surface 53. The source pad 21 is formed in a substantially L-shape in plan view by cutting out the area of ​​the substrate 50 on the side where the gate pad 22 is located, that is, the area on the first side surface 51 and the second side surface 52 of the substrate 50. In this embodiment, the shape of the source pad 21 is similar to the shape of the active area 29. Note that the shape of the source pad 21 and the shape of the active area 29 can be arbitrarily changed. In one example, the shape of the source pad 21 may be different from the shape of the active area 29.

[0042] As shown in Figures 2 and 5, the semiconductor element 20 has a control circuit region 29LG formed to avoid the source pad 21 and gate pad 22. The control circuit region 29LG includes a first portion that is on the fourth side surface 54 side of the substrate 50, closer to the source pad 21 and gate pad 22, and a second portion that extends from the first portion toward the third side surface 53 side of the substrate 50. This second portion is formed between the gate pad 22 and the source pad 21 in the lateral direction X. An overcurrent protection circuit 24, an overheat protection circuit 25, an undervoltage malfunction prevention circuit 26, and a temperature sensor 27 are provided within the control circuit region 29LG. The overcurrent protection circuit 24, the overheat protection circuit 25, and the undervoltage malfunction prevention circuit 26 are provided in the region of the control circuit region 29LG that is on the fourth side surface 54 side of the substrate 50, closer to the active region 29. The overcurrent protection circuit 24, the overheat protection circuit 25, and the undervoltage malfunction prevention circuit 26 are arranged in a line in the lateral direction X. The undervoltage malfunction prevention circuit 26 is located on the first side surface 51 of the substrate 50, closer to the overcurrent protection circuit 24 and the overheat protection circuit 25 within the control circuit region 29LG. A portion of the undervoltage malfunction prevention circuit 26 is adjacent to the gate pad 22 in the vertical direction Y.

[0043] The temperature sensor 27 is located within the control circuit region 29LG. The position of the temperature sensor 27 is set to the location where the temperature is highest in the region outside the source pad 21 when the semiconductor device 1 is driven. The position of the temperature sensor 27 is set based on the temperature distribution of the substrate 50 when the semiconductor device 1 is driven, for example, by simulation. In this embodiment, the temperature sensor 27 is located near the intersection of the fifth side 29e and the sixth side 29f of the active region 29.

[0044] The current sensor 28 is located on the substrate 50 between the overcurrent protection circuit 24 and the source pad 21. The current sensor 28 is located within the active region 29. In the vertical direction Y, the current sensor 28 is positioned closer to the overcurrent protection circuit 24 than to the source pad 21.

[0045] Next, the electrical configuration of the semiconductor device 1 will be explained using Figure 6. Figure 6 shows an example of the circuit configuration of the semiconductor device 1. In Figure 6, a battery 2 and an inductive load 3 are externally connected to the output terminal OUT and the ground terminal GND. Also in Figure 6, an example is shown where the inductive load 3 is a relay containing a coil L.

[0046] The switching circuit 23 is connected between the output terminal OUT and the ground terminal GND. The switching circuit 23 includes the power MISFET (hereinafter referred to as "MISFET23a"), which is an example of a power transistor. The MISFET23a has a gate terminal G as a control terminal, a drain terminal D, and a source terminal S. The switching circuit 23 is configured such that the drain terminal D of the MISFET23a is connected to the output terminal OUT, and the source terminal S is connected to the ground terminal GND. Although the switching circuit 23 includes multiple power MISFETs, only one MISFET23a is shown in Figure 6 for the sake of explanation.

[0047] An input wire 43 is connected between the input terminal IN and the gate terminal G of MISFET 23a. A ground wire 44 is connected between the ground terminal GND and the source terminal S of MISFET 23a. Between the input wire 43 and the ground wire 44, the diode D1, the first resistor R1, the overcurrent protection circuit 24, the overheat protection circuit 25, the undervoltage malfunction prevention circuit 26, and the second resistor R2 are connected in parallel, in that order from the input terminal IN side. In the input wire 43, a third resistor R3 is connected in series between the first resistor R1 and the overcurrent protection circuit 24. In the input wire 43, a fourth resistor R4 is connected in series between the undervoltage malfunction prevention circuit 26 and the second resistor R2.

[0048] The current sensor 28 is electrically connected to the overcurrent protection circuit 24. The current sensor 28 detects the current flowing through, for example, the switching circuit 23. The current value detected by the current sensor 28 is supplied to the overcurrent protection circuit 24. The overcurrent protection circuit 24 is driven based on the current value supplied by the current sensor 28. In one example, if a current exceeding a predetermined value (overcurrent) flows through the switching circuit 23 due to a short circuit, the overcurrent protection circuit 24 limits the current and protects the circuit.

[0049] The temperature sensor 27 is electrically connected to the overheat protection circuit 25. The temperature sensor 27 detects the temperature of the substrate 50. The temperature of the substrate 50 detected by the temperature sensor 27 is provided to the overheat protection circuit 25. The overheat protection circuit 25 is driven based on the temperature of the substrate 50 provided by the temperature sensor 27. In one example, when the temperature of the substrate 50 exceeds a predetermined value, the overheat protection circuit 25 stops the switching circuit 23 via the overcurrent protection circuit 24, thereby protecting the circuit. As a result, the temperature rise of the substrate 50 is suppressed.

[0050] The low-voltage malfunction prevention circuit 26 is configured to prevent the switching circuit 23 from operating when the potential difference between the input wiring 43 and the ground wiring 44 is less than or equal to a predetermined value, and to allow the switching circuit 23 to operate when the potential difference is greater than or equal to a predetermined value.

[0051] A clamp diode D2 is electrically connected between the gate terminal G and drain terminal D of MISFET23a. The clamp diode D2 is formed by connecting two diodes in reverse bias. The two diodes may include a Zener diode. The number of diodes constituting the clamp diode D2 can be arbitrarily changed.

[0052] When the input terminal IN is at a high level, the MISFET 23a of semiconductor device 1 turns on, and current flows from battery 2 through coil L of inductive load 3 and MISFET 23a. Next, when the input terminal IN changes from a high level to a low level, the MISFET23a turns off. At this time, the voltage Vout at the output terminal OUT rises due to the current flowing through the inductive load 3. The voltage Vout at the output terminal OUT rises to the voltage determined by the clamp diode D2 from the battery 2 (for example, 48V). The rise in the output voltage Vout causes a current to flow through the resistor R2 via the clamp diode D2, which slightly raises the gate voltage of the MISFET23a. As a result, current flows through the MISFET23a. In this way, a gate voltage is generated and a small amount of current flows through the MISFET23a, i.e., an active clamp state is created. This active clamp state continues until the current from the battery 2 to the MISFET23a becomes 0A, and the output voltage Vout drops to the voltage of the battery 2.

[0053] [Connecting the first wire to the source pad] Figures 7 and 8 are enlarged plan views showing a portion of the substrate 50. In Figure 7, the active region 29 is shown with a solid line, and the source pad 21 is shown with a dashed line. In Figure 8, the active region 29 is shown with a dashed line, and the source pad 21 is shown with a solid line.

[0054] The inventors of the present invention focused on the connection position of the first wire 41 connected to the source pad 21 of the semiconductor element 20 in order to improve the active clamp withstand capability Eac of the semiconductor device 1. The inventors of the present invention found that the active clamp withstand capability Eac is improved when the first wire 41 is connected to a connection position that includes the centroid position GC of the active region 29 of the semiconductor element 20. In view of this, in this embodiment, the first wire 41 is connected to the source pad 21 so as to overlap with the centroid position GC of the active region 29.

[0055] Here, the centroid position GC of the active region 29 can be determined as follows. As shown in Figure 7, first, the active region 29 is divided into two regions, the first region RA1 and the second region RA2. Preferably, the first region RA1 and the second region RA2 are rectangular in shape. Next, the centroid position GA1 of the first region RA1 and the centroid position GA2 of the second region RA2 are determined. As shown in Figure 7, since the first region RA1 and the second region RA2 are rectangular, the centroid position GA1 of the first region RA1 is the intersection of the diagonals of the first region RA1, and the centroid position GA2 of the second region RA2 is the intersection of the diagonals of the second region RA2. Next, the area SA1 of the first region RA1 and the area SA2 of the second region RA2 are determined. Next, the centroid position GC of the active region 29 is determined based on the relationship between the distance DA1 between centroid position GA1 and centroid position GC of the active region 29, the distance DA2 between centroid position GA2 and centroid position GC of the active region 29, and the area SA1 of the first region RA1 and the area SA2 of the second region RA2, along the line segment LA connecting centroid position GA1 and centroid position GA2. More specifically, the ratio of distance DA2 to distance DA1 (DA2 / DA1) is equal to the inverse ratio of the ratio of the area SA2 of the second region RA2 to the area SA1 of the first region RA1 (SA1) (SA1 / SA2) (DA2 / DA1 = SA1 / SA2). Thus, by determining at least one of the distances DA1 and DA2, the centroid position GC of the active region 29 can be determined. Also, as shown in Figure 7, the source pad 21 is provided so as to cover the centroid position GC of the active region 29.

[0056] The dashed-dotted region RX shown in Figure 7 represents the tool head for ultrasonic bonding the first wire 41 to the source pad 21 in a wedge bonding apparatus (not shown) (hereinafter referred to as wedge RX). The wedge bonding apparatus moves wedge RX so that its center lies on the centroid position GC of the active region 29. The end of the first wire 41 passed through wedge RX is connected so as to overlap with the centroid position GC of the active region 29, as shown in Figure 8. That is, the contact region of the first wire 41 to the source pad 21 (wedge RX) includes the centroid position GC of the active region 29. In this embodiment, the center position of the connection region of the first wire 41 to the source pad 21 (wedge RX) coincides with the centroid position GC of the active region 29.

[0057] Furthermore, as shown in Figures 2 and 8, the connection portion 41a of the first wire 41 connected to the source pad 21 extends in directions different from the lateral X and vertical Y directions in a plan view of the semiconductor device 1. In this embodiment, the connection portion 41a extends from the semiconductor element 20 toward the third island portion 13a.

[0058] As shown in Figure 8, the dashed-dotted region RS surrounding the connection portion 41a of the first wire 41 is a margin that takes into account variations in the wire diameter of the first wire 41 and variations in the connection position of the first wire 41 to the source pad 21 by the wedge bonding apparatus. That is, the connection portion 41a of the first wire 41 is always located within region RS. For example, region RS may be set as an opening 89 (see Figure 9) created by opening the surface protective film 88 from the source pad 21. It is preferable that the opening 89 be set to be wider than region RS.

[0059] In other words, in the first embodiment, as shown in Figure 7, the active region 29 is approximately L-shaped, formed by combining a small rectangular first region RA1 and a larger rectangular second region RA2. The first wire 41 and the source pad 21, which serve as connecting members, are connected to each other at a position on the line segment LA that connects the centroid position GA1 of the first region RA1 and the centroid position GA2 of the second region RA2.

[0060] Furthermore, the semiconductor element 20 includes a transistor. The semiconductor device includes a second lead frame (external control terminal) 12 for controlling the on / off state of the transistor, and a third lead frame (external terminal) 13 connected to a first wire 41 as a connecting member. As shown in Figure 2, the second lead frame 12 is positioned on the side of the small rectangular first region RA1, and the third lead frame 13 is positioned on the side of the large rectangular second region RA2. In other words, the second lead frame 12 is positioned closer to the first region RA1 than to the second region RA2, and the third lead frame 13 is positioned closer to the second region RA2 than to the first region RA1.

[0061] Furthermore, as shown in Figures 2 and 5, the semiconductor element 20 is equipped with a gate pad (control metal pad) 22 connected to a second lead frame (external control terminal) 12. The gate pad 22 is located in the rectangular region where no transistor is situated, within the area enclosed by the extension of the side (first side 29a) of the small rectangular first region RA1 and the extension of the side (fourth side 29d) of the larger rectangular second region RA2.

[0062] Furthermore, as shown in Figure 5, the source pad 21 is also roughly L-shaped. The source pad 21 is formed across a small rectangular first region RA1 and a larger rectangular second region RA2, both included in the active region 29. The source pad 21 is configured such that its first side 29a, which is furthest from the second region RA2, coincides with the position where the gate pad 22 is provided in the lateral direction X. In detail, as shown in Figure 5, the gate pad 22 has a left side and a right side in the lateral direction X, and the left side of the gate pad 22 extends further from the second region RA2 than the right side of the gate pad 22. The first side 29a of the source pad 21 coincides with the position between the left and right sides of the gate pad 22 in the lateral direction X.

[0063] Furthermore, the temperature sensor 27 is positioned between the gate pad 22 and the source pad 21. [MISFET structure] The detailed structure of MISFET23a will be described with reference to Figures 9 to 11.

[0064] As shown in Figure 9, the substrate 50 on which the MISFET 23a is formed is, for example, a silicon substrate. The substrate 50 is n + A semiconductor substrate 61 of type n formed on the semiconductor substrate 61 - It includes an epitaxial layer 62 of a certain type. A drain region 63 is formed by the semiconductor substrate 61 and the epitaxial layer 62. The surface of the substrate 50 is formed by the epitaxial layer 62, and the back surface of the substrate 50 is formed by the semiconductor substrate 61. An example of the thickness of the epitaxial layer 62 is 9.5 μm.

[0065] A source pad 21 is formed on the surface side of the substrate 50, and a drain electrode 64 is formed on the back side of the substrate 50. Multiple trench gate structures 65 are provided on the surface side of the active region 29 of the substrate 50. The multiple trench gate structures 65 are fabricated in the surface layer of the epitaxial layer 62 and have trenches 66 formed by excavating the epitaxial layer 62, and gate electrodes 68 and embedded electrodes 69 embedded in the trenches 66 with a gate insulating film 67 in between.

[0066] As shown in Figure 10, the gate electrode 68 and the embedded electrode 69 are separated (insulated) by a gate insulating film 67 in the depth direction of the trench 66. The gate electrode 68 is located on the opening side of the trench 66, and the embedded electrode 69 is located on the bottom side of the trench 66, closer to the gate electrode 68. An example of the gate insulating film 67 is a silicon oxide film.

[0067] The gate insulating film 67 includes a thick film portion 67a in contact with the embedded electrode 69 and a thin film portion 67b in contact with the gate electrode 68. One surface (the surface on the drain region 63 side) and the opposite surface of the thick film portion 67a of the gate insulating film 67 are formed along the inner wall of the trench 66, and it has a laminated structure in which a silicon oxide film with a low density is laminated on a silicon oxide film with a high density. The thickness T1 of the thick film portion 67a of the gate insulating film 67 is thicker than the thickness T2 of the thin film portion 67b (T2 < T1). The thickness T1 of the thick film portion 67a is thicker than the thickness T3 of the separation portion 67c that separates the gate electrode 68 and the embedded electrode 69 in the gate insulating film 67 (T3 < T1). The thickness T3 of the separation portion 67c is thicker than the thickness T2 of the thin film portion 67b (T2 < T3 < T1). Note that the thickness T1 of the thick film portion 67a, the thickness T2 of the thin film portion 67b, and the thickness T3 of the separation portion 67c can each be arbitrarily changed. For example, the thickness T2 of the thin film portion 67b and the thickness T3 of the separation portion 67c may be equal to each other.

[0068] The gate electrode 68 is made of, for example, polysilicon. A concave portion 68a that opens toward the embedded electrode 69 is formed at the lower end portion of the gate electrode 68. The upper end portion 69a of the embedded electrode 69 is accommodated in the concave portion 68a. Thus, the upper end portion 69a of the embedded electrode 69 faces the gate electrode 68 through the thin film portion 67b of the gate insulating film 67. The embedded electrode 69 is made of, for example, polysilicon. In the present embodiment, the embedded electrode 69 is electrically floating from the outside by being covered with the thick film portion 67a and the separation portion 67c of the gate insulating film 67. Note that the embedded electrode 69 may have the same potential (ground potential) as the source pad 21. In a cross-sectional view of the embedded electrode 69, the width dimension D1 of the upper end portion 69a is smaller than the width dimension D2 of the portion below the upper end portion 69a (on the back surface side of the substrate 50) in the embedded electrode 69.

[0069] Figures 9 and 10 show an example in which the trench 66 is formed substantially perpendicular to the surface of the epitaxial layer 62. However, in the depth direction of the trench 66, a tapered trench 66 may be formed in cross-sectional view, where the opening width gradually narrows towards the bottom of the trench 66. Also, Figures 9 and 10 show an example in which the bottom of the trench 66 has a flat portion parallel to the surface of the epitaxial layer 62. However, the bottom of the trench 66 may be formed in a curved shape extending outward from the side of the trench 66.

[0070] On the sides (both sides) of the trench gate structure 65, from the surface side of the substrate 50 in the depth direction, n + Source area 70 of type, p - A body region 71 and a drain region 63 (epitaxial layer 62) are provided in order. The source region 70, body region 71, and drain region 63 are all formed to be in contact with the trench gate structure 65 and face the gate electrode 68 across the gate insulating film 67. Furthermore, the drain region 63 faces the embedded electrode 69 across the gate insulating film 67.

[0071] The body region 71 is shared between adjacent trench gate structures 65 by one trench gate structure 65 and the other trench gate structure 65. The source region 70 is provided so as to be exposed from the surface of the body region 71. The planar shape of the source region 70 corresponds to the planar shape of the channel forming region 72, which becomes the current path. Below the source region 70, the body region 71 that forms the side surface of the trench gate structure 65 is the channel forming region 72. The formation of the channel in the channel forming region 72 is controlled by the trench gate structure 65 (gate electrode 68).

[0072] Figure 11 shows an example of the planar structure of the epitaxial layer 62 of the MISFET 23a. As shown in Figure 11, in the body region 71 (see Figure 10) sandwiched between adjacent trench gate structures 65, multiple source regions 70 are alternately formed on one trench gate structure 65 side and the other trench gate structure 65 side. The area of ​​each source region 70 is the same. Thus, in the MISFET 23a of this embodiment, the ratio of the channel formation region 72 area to the area per unit area is about 50%.

[0073] Here, the case where channel-forming regions 72 exist throughout the entire region between each trench gate structure 65 is defined as the ratio of the area of ​​channel-forming regions 72 per unit area being 100%. Furthermore, the area of ​​the channel-forming region 72 is defined as the area of ​​the region that becomes the current path in a plan view. Specifically, the area of ​​the channel-forming region 72 is defined as the opposing area where the source region 70 faces the drain region 63 (epitaxial layer 62) across the body region 71 in a plan view. Furthermore, the ratio of the area of ​​channel-forming regions 72 per unit area is the ratio of the area of ​​channel-forming regions 72 within a predetermined region between the trench gate structures 65. Furthermore, the predetermined region is a region of a predetermined area obtained by multiplying the width between the trench gate structures 65 by an arbitrary length along the longitudinal direction of the trench gate structures 65.

[0074] Furthermore, between the multiple trench gate structures 65, p is provided so as to be exposed from the surface of the body region 71 other than the source region 70. + A body contact region 73 of the type is formed. The body contact region 73 is formed to be in contact with the side surface of the trench gate structure 65, and a portion of it faces the gate electrode 68 across the gate insulating film 67. In this embodiment, the depth of the body contact region 73 and the depth of the source region 70 are equal to each other.

[0075] The depths of the body contact region 73 and the source region 70 can be arbitrarily changed. For example, the depth of the body contact region 73 may be greater than the depth of the source region 70. Alternatively, the body contact region 73 may be omitted from the MISFET 23a. In this case, the body region 71 will be exposed from the surface of the epitaxial layer 62.

[0076] Furthermore, as shown in Figure 9, a DTI (Deep Trench Isolation) structure 90 is formed in the epitaxial layer 62 as an element isolation structure that demarcates the region where the MISFET 23a is formed from other regions. For example, the DTI structure 90 is formed in a substantially annular shape in a plan view (hereinafter simply referred to as "plan view") of the surface of the epitaxial layer 62 viewed from the normal direction. The DTI structure 90 has a trench 91 formed by excavating the epitaxial layer 62 and an insulator 92 embedded in the trench 91 with the gate insulating film 67 in between. An example of the insulator 92 is polysilicon. Note that silicon oxide may also be used as the insulator 92. In this embodiment, an example in which the DTI structure 90 is formed as an element isolation structure has been described, but the element isolation structure may also utilize a diffusion isolation method that includes an annular p-type diffusion region that demarcates the region where the MISFET 23a is formed, that is, a pn connection isolation method.

[0077] An interlayer insulating film 74 is formed on the surface of the epitaxial layer 62. The interlayer insulating film 74 includes at least one of a silicon oxide film and a silicon nitride film. The interlayer insulating film 74 has a laminated structure in which a first interlayer insulating film 75, a second interlayer insulating film 76, a third interlayer insulating film 77, and a fourth interlayer insulating film 78 are sequentially stacked from the surface side of the epitaxial layer 62. The first interlayer insulating film 75, the second interlayer insulating film 76, the third interlayer insulating film 77, and the fourth interlayer insulating film 78 are formed of an insulator such as silicon oxide or silicon nitride. For example, USG (HDP-USG: High Density Plasma-CVD-Undoped Silica Glass) produced by the high-density plasma CVD method may be used for the first interlayer insulating film 75, the second interlayer insulating film 76, the third interlayer insulating film 77, and the fourth interlayer insulating film 78. The first interlayer insulating film 75 covers the surface of the epitaxial layer 62. The first interlayer insulating film 75 is embedded in a recess 79 formed by the height difference between the upper surface of the gate electrode 68 and the surface of the epitaxial layer 62. The thickness TF1 of the first interlayer insulating film 75 is, for example, 13,500 Å, the thickness TF2 of the second interlayer insulating film 76 is, for example, 8,000 Å, the thickness TF3 of the third interlayer insulating film 77 is, for example, 13,500 Å, and the thickness TF4 of the fourth interlayer insulating film 78 is, for example, 10,000 Å.

[0078] A first source electrode 80 is formed on the first interlayer insulating film 75 as the first metal (first metal layer). The first source electrode 80 is an electrode film comprising one or more metal species selected from the group including, for example, aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), and tantalum (Ta). The thickness of the first source electrode 80 is, for example, 4000 Å. The first source electrode 80 is electrically connected to the source region 70 and the body contact region 73 via corresponding contacts 81. The first source electrode 80 is covered by a second interlayer insulating film 76.

[0079] Furthermore, a body contact region 73 is formed in the body region 71 between the trench gate structure 65 and the DTI structure 90, while a source region 70 is not formed. Therefore, the contact 81 on the body region 71 between the trench gate structure 65 and the DTI structure 90 is electrically connected to the body contact region 73. Wiring 93 is formed on the first interlayer insulating film 75 so as to be electrically connected to this contact 81. Wiring 93 extends to cover the DTI structure 90. A contact 94 is electrically connected to wiring 93. Contact 94 is connected to an insulator 92. Although not shown in Figure 9, wiring 93 is also connected to the first source electrode 80.

[0080] A second source electrode 82 is formed on the third interlayer insulating film 77 as a second metal (second metal layer). The second source electrode 82 is an electrode film containing one or more metal species selected from the group including, for example, aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), and tantalum (Ta). The thickness of the second source electrode 82 is, for example, 8000 Å. The second source electrode 82 is electrically connected to the first source electrode 80 via a corresponding contact 83. The outer periphery of the second source electrode 82 is covered by a fourth interlayer insulating film 78.

[0081] A passivation film 84 is formed on the surface of the fourth interlayer insulating film 78. The passivation film 84 includes, for example, at least one of silicon nitride and silicon oxide. The passivation film 84 may also be a laminated film including a silicon oxide film and a silicon nitride film formed on the silicon oxide film. In this embodiment, the passivation film 84 consists of a silicon nitride film. The thickness of the passivation film 84 is, for example, 11,000 Å.

[0082] The source pad 21 is provided in an opening 85 that penetrates the fourth interlayer insulating film 78 and the passivation film 84. The source pad 21 has an inner circumferential portion 86 that contacts the second source electrode 82 within the opening 85, and an outer circumferential portion 87 that extends beyond the opening 85 and covers the surface of the passivation film 84. The thickness of the inner circumferential portion 86 of the source pad 21 is, for example, 42,000 Å.

[0083] A surface protective film 88 is formed on the surface of the source pad 21. An example of the surface protective film 88 is a film containing polyimide. The surface protective film 88 covers a portion of the inner circumference 86 and a portion of the outer circumference 87 of the source pad 21. The surface protective film 88 is provided with an opening 89 for connecting the first wire 41 to the source pad 21.

[0084] [Structure of semiconductor elements constituting a control circuit] Referring to Figures 12 to 17, the structures of the control semiconductor elements constituting the overcurrent protection circuit 24, the overheat protection circuit 25, and the undervoltage malfunction prevention circuit 26, which are control circuits for controlling the MISFET 23a of the semiconductor device 1, will be described. Examples of control semiconductor elements include low-voltage CMOS (Complementary MOS) FETs, MOS capacitors, polysilicon resistors, high-voltage P-channel MOSFETs, high-voltage N-channel MOSFETs, and NPN transistors. These control semiconductor elements are provided on the substrate 50, similar to the MISFET 23a. In the following description, when referring to n-type impurities (n-type), it means that pentavalent elements (e.g., phosphorus (P), arsenic (As), etc.) are the main impurities, and when referring to p-type impurities (p-type), it means that trivalent elements (e.g., boron (B), indium (In), gallium (Ga), etc.) are the main impurities.

[0085] The low-voltage CMOSFET shown in Figure 12 has a CMOS region 100 on which a CMOS transistor is formed. A DTI structure 101 is formed in the epitaxial layer 62 of the substrate 50 as an element isolation structure that demarcates the CMOS region 100 from other regions. The DTI structure 101 is formed in a substantially ring shape in a plan view (hereinafter simply referred to as "plan view") taken from the direction normal to the surface of the epitaxial layer 62. The DTI structure 101 includes an insulator 101b embedded in a trench 101a formed in the epitaxial layer 62. An example of the insulator 101b is polysilicon. Silicon oxide may also be used as the insulator 101b. In this embodiment, an example in which the DTI structure 101 is formed as an element isolation structure has been described, but the element isolation structure may also utilize a diffusion isolation method that includes an annular p-type diffusion region that demarcates the CMOS region 100, that is, a pn connection isolation method.

[0086] In the CMOS region 100, a first P-well region 102, which is a p-type high-voltage well region, is formed at a distance from the DTI structure 101. To ensure the distance between the DTI structure 101 and the first P-well region 102, a second P-well region 103, which is a p-type low-voltage well region, is formed on the surface of the epitaxial layer 62. The second P-well region 103 is formed in a substantially ring shape adjacent to the DTI structure 101. If the DTI structure 101 is formed in a stripe shape instead of a substantially ring shape, the second P-well region 103 is formed in a stripe shape adjacent to each DTI structure 101. The impurity concentration in the second P-well region 103 is higher than the impurity concentration in the first P-well region 102.

[0087] Within the first P well region 102, two n-type well regions, the first N well region 104 and the second N well region 105, are formed on the surface of the epitaxial layer 62. The first N well region 104 is formed to surround the second N well region 105. The thickness of the first N well region 104 is thinner than the thickness of the first P well region 102. The thickness of the second N well region 105 is thinner than the thickness of the first N well region 104. The impurity concentration in the first N well region 104 is higher than the impurity concentration in the first P well region 102. The impurity concentration in the second N well region 105 is higher than the impurity concentration in the first N well region 104. In the following description, thickness refers to the length in the direction normal to the surface of the epitaxial layer 62.

[0088] Within the second N-well region 105, a p-type source region 106, a p-type drain region 107, and an n-type contact region 108 are formed on the surface of the epitaxial layer 62. The source region 106, drain region 107, and contact region 108 are formed with a gap between them. The source region 106 is formed between the contact region 108 and the drain region 107. The impurity concentrations in the source region 106, drain region 107, and contact region 108 are each higher than the impurity concentrations in the second N-well region 105.

[0089] Furthermore, within the CMOS region 100, a third P-well region 109, which is a p-type low-voltage well region, is formed on the surface of the epitaxial layer 62, spaced apart from the first N-well region 104. The third P-well region 109 is integrated with the second P-well region 103. An n-type source region 110, an n-type drain region 111, and a p-type contact region 112 are formed on the surface of the third P-well region 109. The source region 110, drain region 111, and contact region 112 are spaced apart from each other. The contact region 112 is formed in the third P-well region 109 closer to the DTI structure 101 adjacent to the third P-well region 109 (the second P-well region 103). In other words, the contact region 112 is formed in the region of the third P-well region 109 where the second P-well region 103 is integrated. In other words, the contact region 112 also serves as the contact region of the second P well region 103. The source region 110 is formed between the drain region 111 and the contact region 112.

[0090] An insulating film 113 is formed between the surface of the epitaxial layer 62 within the CMOS region 100 and between the trench 101a of the DTI structure 101 and the insulator 101b. An example of the insulating film 113 is a silicon oxide film. A first gate electrode 114 facing the second N well region 105 and a second gate electrode 115 facing the third P well region 109 are formed on the insulating film 113. Each gate electrode 114, 115 is, for example, polysilicon with impurities added. Both sides of each gate electrode 114, 115 are covered with sidewalls 116, 117 containing insulating material such as silicon oxide or silicon nitride.

[0091] Within the CMOS region 100, an interlayer insulating film 74 and a passivation film 84 are stacked in the same order on the epitaxial layer 62 as in the MISFET 23a. On the first interlayer insulating film 75, a first source electrode 118, a first drain electrode 119, a first gate electrode (not shown), a second source electrode 120, a second drain electrode 121, a second gate electrode (not shown), a back gate electrode 122, and a ground electrode 123 are formed as the first metal. These electrodes are electrode films containing one or more metal species selected from the group including, for example, aluminum, copper, titanium, tungsten, and tantalum.

[0092] The first source electrode 118 is electrically connected to the source region 106 of the second N-well region 105 via a contact, the first drain electrode 119 is electrically connected to the drain region 107 of the second N-well region 105 via a contact, and the back gate electrode 122 is electrically connected to the contact region 108 of the second N-well region 105 via a contact. In this way, a p-type MOSFET is formed.

[0093] The second source electrode 120 is electrically connected to the source region 110 of the third P well region 109 via a contact, and the second drain electrode 121 is electrically connected to the drain region 111 of the third P well region 109 via a contact. In this way, an n-type MOSFET is formed.

[0094] The ground electrode 123 is electrically connected to the contact region 112 of the second P-well region 103 via a contact. The ground electrode 123 is electrically connected to the insulator 101b of the DTI structure 101 via a contact. Furthermore, the ground electrode 123, which is electrically connected to the contact region 112 of the third P-well region 109, becomes the back gate of the n-type MOSFET formed in the third P-well region 109. In this way, the DTI structure 101, the third P-well region 109, and the first P-well region 102 are at ground potential.

[0095] On the third interlayer insulating film 77, a third source electrode, a third drain electrode, a third gate electrode, a fourth source electrode, and a fourth gate electrode are formed as a second metal (all not shown). The third source electrode is electrically connected to the first source electrode 118, the third drain electrode is electrically connected to the first drain electrode 119 and the second drain electrode 121, and the third gate electrode is electrically connected to the first gate electrode 114. The fourth source electrode is electrically connected to the second source electrode 120, and the fourth gate electrode is electrically connected to the second gate electrode. In this way, a CMOS transistor is formed by electrically connecting the first drain electrode 119 and the second drain electrode 121 via the third drain electrode.

[0096] The MOS capacitor shown in Figure 13 has a capacitor region 130 in which the capacitor is formed. A DTI structure 131 is formed in the epitaxial layer 62 of the substrate 50 as an element isolation structure that demarcates the capacitor region 130 from other regions. The DTI structure 131 has the same structure as the DTI structure 101 of the low-voltage CMOSFET (see Figure 12), and is a structure in which an insulator 131b is embedded in a trench 131a. An example of the insulator 131b is polysilicon. Note that the insulator 131b may also be silicon oxide. In this embodiment, an example in which a DTI structure 131 is formed as an element isolation structure has been described, but the element isolation structure may also utilize a pn connection isolation method that includes an annular p-type diffusion region that demarcates the capacitor region 130.

[0097] The capacitor region 130 has a first P-well region 132, which is a p-type high-voltage well region, and a second P-well region 133, which is a p-type low-voltage well region. The first P-well region 132 is formed at a distance from the DTI structure 131. The second P-well region 133 is formed adjacent to the DTI structure 131, straddling the first P-well region 132, in order to ensure a distance between the DTI structure 131 and the first P-well region 132. The thickness of the second P-well region 133 is thinner than the thickness of the first P-well region 132. The impurity concentration in the second P-well region 133 is higher than that of the first P-well region 132. A p-type contact region 134 is formed on the surface of the second P-well region 133.

[0098] Within the first P well region 132, the surface layer of the epitaxial layer 62 is formed with three n-type well regions: the first N well region 135, the second N well region 136, and the third N well region 137. The first N well region 135 is formed to surround the second N well region 136. The second N well region 136 is formed to surround the third N well region 137. The thickness of the first N well region 135 is thinner than the thickness of the first P well region 132. The thickness of the second N well region 136 is thinner than the thickness of the first N well region 135. The thickness of the third N well region 137 is thinner than the thickness of the second N well region 136. The impurity concentration in the first N well region 135 is higher than the impurity concentration in the first P well region 132. The impurity concentration in the second N well region 136 is higher than the impurity concentration in the first N well region 135. The impurity concentration in the third N well region 137 is higher than that in the second N well region 136. In the second N well region 136, an n-type contact region 138 is formed in the surface layer outside the third N well region 137. The impurity concentration in the contact region 138 is higher than that in the second N well region 136.

[0099] An insulating film 139 is formed between the surface of the epitaxial layer 62 within the capacitor region 130 and between the trench 131a of the DTI structure 131 and the insulator 131b. An example of the insulating film 139 is a silicon oxide film. A gate electrode 140 is formed on the insulating film 139. The gate electrode 140 is formed to cover the entire third N well region 137 and a portion of the second N well region 136. The gate electrode 140 is, for example, polysilicon with impurities added. Both end faces of the gate electrode 140 are covered with sidewalls 141 containing an insulating material such as silicon oxide or silicon nitride.

[0100] Within the capacitor region 130, an interlayer insulating film 74 and a passivation film 84 are stacked in the same order on the epitaxial layer 62 as in the MISFET 23a. On the first interlayer insulating film 75, a first electrode 142, a first gate electrode 143, and a ground electrode 144 are formed as the first metal. These electrodes are electrode films containing one or more metal species selected from the group including, for example, aluminum, copper, titanium, tungsten, and tantalum.

[0101] The first electrode 142 is electrically connected to the contact region 138 of the second N well region 136 via a contact, and the first gate electrode 143 is electrically connected to the gate electrode 140 via a contact. The ground electrode 144 is electrically connected to the contact region 134 of the second P well region 133 via a contact. The ground electrode 144 is electrically connected to the insulator 131b of the DTI structure 131 via a contact. In this way, the DTI structure 131 and the second P well region 133 are at ground potential.

[0102] A second electrode and a second gate electrode are formed on the third interlayer insulating film 77 as a second metal (neither is shown in the figure). The second electrode is electrically connected to the first electrode 142, and the second gate electrode is electrically connected to the first gate electrode 143.

[0103] The polysilicon resistor shown in Figure 14 has a resistive region 150 in which resistance is formed. A DTI structure 151 is formed in the epitaxial layer 62 of the substrate 50 as an element isolation structure that demarcates the resistive region 150 from other regions. The DTI structure 151 has the same structure as the DTI structure 101 of the low-voltage CMOSFET (see Figure 12), and is a structure in which an insulator 151b is embedded in a trench 151a. An example of the insulator 151b is polysilicon. Note that the insulator 151b may also be silicon oxide. In this embodiment, an example in which a DTI structure 151 is formed as an element isolation structure has been described, but the element isolation structure may also utilize a pn connection isolation method that includes an annular p-type diffusion region that demarcates the resistive region 150.

[0104] The resistive region 150 has a first P-well region 152, which is a p-type high-voltage well region, and a second P-well region 153, which is a p-type low-voltage well region. The first P-well region 152 is formed at a distance from the DTI structure 151. The second P-well region 153 is formed adjacent to the DTI structure 151, straddling the first P-well region 152, in order to ensure a distance between the DTI structure 151 and the first P-well region 152. The thickness of the second P-well region 153 is thinner than the thickness of the first P-well region 152. The impurity concentration in the second P-well region 153 is higher than that of the first P-well region 152. A p-type contact region 154 is formed on the surface of the second P-well region 153.

[0105] An insulating film 155 is formed between the surface of the epitaxial layer 62 within the resistive region 150 and between the trench 151a of the DTI structure 151 and the insulator 151b. An example of the insulating film 155 is a silicon oxide film. A first polysilicon resistor 156 and a second polysilicon resistor 157 are formed on the insulating film 155, spaced apart from each other. The first polysilicon resistor 156 and the second polysilicon resistor 157 face the first P well region 152. Both sides of the first polysilicon resistor 156 are covered with sidewalls 156a containing an insulating material such as silicon oxide or silicon nitride, and both sides of the second polysilicon resistor 157 are covered with sidewalls 157a, similar to the first polysilicon resistor 156. In this embodiment, the first polysilicon resistor 156 has a low concentration of impurities added to the polysilicon, i.e., high resistance, and the second polysilicon resistor 157 has a low concentration of impurities added to the polysilicon, i.e., low resistance. The number and type of polysilicon resistors formed in the resistive region 150 can be arbitrarily changed. For example, one of the first polysilicon resistor 156 and the second polysilicon resistor 157 may be omitted.

[0106] Within the resistive region 150, an interlayer insulating film 74 and a passivation film 84 are stacked in this order on the epitaxial layer 62, similar to the MISFET 23a. A ground electrode 158 is formed on the first interlayer insulating film 75 as the first metal. The ground electrode is an electrode film containing one or more metal species selected from the group including, for example, aluminum, copper, titanium, tungsten, and tantalum. The ground electrode 158 is electrically connected to the insulator 151b and contact region 154 of the DTI structure 151 via a plurality of contacts. In this way, the DTI structure 151, the second P-well region 153, and the first P-well region 152 are at ground potential.

[0107] The high-voltage N-channel MOSFET shown in Figure 15 has an NMOS region 160 on which the N-channel MOSFET is formed. A DTI structure 161 is formed in the epitaxial layer 62 of the substrate 50 as an element isolation structure that demarcates the NMOS region 160 from other regions. The DTI structure 161 has the same structure as the DTI structure 101 of the low-voltage CMOSFET (see Figure 12), and is a structure in which an insulator 161b is embedded in a trench 161a. An example of the insulator 161b is polysilicon. Note that the insulator 161b may also be silicon oxide. In this embodiment, an example in which a DTI structure 161 is formed as an element isolation structure has been described, but the element isolation structure may also utilize a pn connection isolation method that includes an annular p-type diffusion region that demarcates the NMOS region 160.

[0108] In the NMOS region 160, a first P-well region 162, which is a p-type low-voltage well region, is formed at a distance from the DTI structure 161. To ensure the distance between the DTI structure 161 and the first P-well region 162, a second P-well region 163, which is a p-type low-voltage well region, is formed on the surface of the epitaxial layer 62. The second P-well region 163 is formed in a substantially ring shape adjacent to the DTI structure 161. If the DTI structure 161 is formed in a stripe shape instead of a substantially ring shape, the second P-well region 163 is formed in a stripe shape adjacent to each DTI structure 161. The impurity concentration in the second P-well region 163 is higher than the impurity concentration in the first P-well region 162.

[0109] Within the NMOS region 160, an n-type well region, the N-well region 164, is formed on the surface of the epitaxial layer 62. The N-well region 164 is formed within the first P-well region 162. The thickness of the N-well region 164 is thinner than the thickness of the first P-well region 162. The impurity concentration in the N-well region 164 is higher than that of the first P-well region 162. An n-type drain region 165 is formed on the surface of the N-well region 164. The impurity concentration in the drain region 165 is higher than that of the N-well region 164.

[0110] Furthermore, within the NMOS region 160, a third P-well region 166, which is a p-type low-voltage well region, is formed on the surface of the epitaxial layer 62. The third P-well region 166 is formed with a gap between it and the N-well region 164. The third P-well region 166 is formed integrally with the second P-well region 163. The thickness of the third P-well region 166 is thinner than the thickness of the first P-well region 162 and the N-well region 164. An n-type source region 167 and a p-type contact region 168 are formed on the surface of the third P-well region 166. The source region 167 and the contact region 168 are formed with a gap between them. The contact region 168 is formed in the region of the third P-well region 166 that is integrated with the second P-well region 163. In other words, it also serves as the contact region of the second P-well region 163.

[0111] An insulating film 169 is formed between the surface of the epitaxial layer 62 within the NMOS region 160 and between the trench 161a of the DTI structure 161 and the insulator 161b. An example of the insulating film 169 is a silicon oxide film. On the insulating film 169, a gate electrode 170 is formed that faces each other across the third P well region 166, the first P well region 162, and the N well region 164. The gate electrode 170 is, for example, polysilicon with impurities added. Both sides of the gate electrode 170 are covered with sidewalls 171 containing an insulating material such as silicon oxide or silicon nitride.

[0112] Within the NMOS region 160, an interlayer insulating film 74 and a passivation film 84 are stacked in this order on the epitaxial layer 62, similar to the MISFET 23a. On the first interlayer insulating film 75, a first source electrode 172, a first drain electrode 173, a first gate electrode 174, and a ground electrode 175 are formed as the first metal. These electrodes are electrode films containing one or more metal species selected from the group including, for example, aluminum, copper, titanium, tungsten, and tantalum.

[0113] The first source electrode 172 is electrically connected to the source region 167, the first drain electrode 173 is electrically connected to the drain region 165, and the first gate electrode 174 is electrically connected to the gate electrode 170. The ground electrode 175 is electrically connected via multiple contacts to the contact region 168 of the second P well region 163 and the insulator 161b of the DTI structure 161. In this way, the DTI structure 161, the second P well region 163, and the first P well region 162 are at ground potential.

[0114] On the third interlayer insulating film 77, a second source electrode, a second drain electrode, and a second gate electrode are formed as a second metal (none of which are shown). The second source electrode is electrically connected to the first source electrode 172, the second drain electrode is electrically connected to the first drain electrode 173, and the second gate electrode is electrically connected to the first gate electrode 174. These electrodes are formed from the same material as, for example, the electrodes that form the first metal (first source electrode 172, etc.).

[0115] The high-voltage P-channel MOSFET shown in Figure 16 has a PMOS region 180 on which the P-channel MOSFET is formed. A DTI structure 181 is formed in the epitaxial layer 62 of the substrate 50 as an element isolation structure that demarcates the PMOS region 180 from other regions. The DTI structure 181 has the same structure as the DTI structure 101 of the low-voltage CMOSFET (see Figure 12), and is a structure in which an insulator 181b is embedded in a trench 181a. An example of the insulator 181b is polysilicon. Note that the insulator 181b may also be silicon oxide. In this embodiment, an example in which a DTI structure 181 is formed as an element isolation structure has been described, but the element isolation structure may also utilize a pn connection isolation method that includes an annular p-type diffusion region that demarcates the PMOS region 180.

[0116] Within the PMOS region 180, the surface layer of the epitaxial layer 62 has a p-type high-voltage well region, the P-well region 182, and an n-type well region, the N-well region 183. The P-well region 182 and the N-well region 183 are formed at a distance from the DTI structure 181. The thickness of the N-well region 183 is thinner than the thickness of the P-well region 182. A p-type drain region 184 is formed on the surface layer of the P-well region 182. A p-type source region 185 is formed on the surface layer of the N-well region 183.

[0117] Within the PMOS region 180, an n-type contact region 186 is formed on the surface of the epitaxial layer 62. The contact region 186 is formed in a substantially annular shape, spaced apart from the P-well region 182 and the DTI structure 181 between the P-well region 182 and the DTI structure 181, and spaced apart from the N-well region 183 and the DTI structure 181 between the N-well region 183 and the DTI structure 181.

[0118] An insulating film 187 is formed between the surface of the epitaxial layer 62 within the PMOS region 180 and between the trench 181a of the DTI structure 181 and the insulator 181b. An example of the insulating film 187 is a silicon oxide film. On the insulating film 187, a gate electrode 188 is formed that spans the N well region 183, the epitaxial layer 62, and the P well region 182. The gate electrode 188 is, for example, polysilicon with impurities added. Both sides of the gate electrode 188 are covered with sidewalls 189 containing an insulating material such as silicon oxide or silicon nitride.

[0119] Within the PMOS region 180, an interlayer insulating film 74 and a passivation film 84 are stacked in this order on the epitaxial layer 62, similar to the MISFET 23a. On the first interlayer insulating film 75, a first source electrode 190, a first drain electrode 191, and a first gate electrode 192 are formed as the first metal. These electrodes are electrode films containing one or more metal species selected from the group including, for example, aluminum, copper, titanium, tungsten, and tantalum.

[0120] The first source electrode 190 is electrically connected to the source region 185 via a contact, the first drain electrode 191 is electrically connected to the drain region 184 via a contact, and the first gate electrode 192 is electrically connected to the gate electrode 188 via a contact.

[0121] On the third interlayer insulating film 77, a second source electrode, a second drain electrode, and a second gate electrode are formed as a second metal (none of which are shown). The second source electrode is electrically connected to the first source electrode 190, the second drain electrode is electrically connected to the first drain electrode 191, and the second gate electrode is electrically connected to the first gate electrode 192. These electrodes are formed from the same material as, for example, the electrodes that form the first metal (first source electrode 190, etc.).

[0122] The NPN transistor shown in Figure 17 has a transistor region 200 that forms a bipolar transistor. A DTI structure 201 is formed in the epitaxial layer 62 of the substrate 50 as an element isolation structure that demarcates the transistor region 200 from other regions. The DTI structure 201 has the same structure as the DTI structure 101 of the low-voltage CMOSFET (see Figure 12), and is a structure in which an insulator 201b is embedded in a trench 201a. An example of the insulator 201b is polysilicon. Note that the insulator 201b may also be silicon oxide. In this embodiment, an example in which a DTI structure 201 is formed as an element isolation structure has been described, but the element isolation structure may also utilize a pn connection isolation method that includes an annular p-type diffusion region that demarcates the transistor region 200.

[0123] In the transistor region 200, a first P-well region 202, which is a p-type low-voltage well region, is formed at a distance from the DTI structure 201. To ensure the distance between the DTI structure 201 and the first P-well region 202, a second P-well region 203, which is a p-type low-voltage well region, is formed on the surface of the epitaxial layer 62. The second P-well region 203 is formed in a roughly ring shape adjacent to the DTI structure 201. If the DTI structure 201 is formed in a stripe shape instead of a roughly ring shape, the second P-well region 203 is formed in a stripe shape adjacent to each DTI structure 201. The impurity concentration in the second P-well region 203 is higher than that of the first P-well region 202. An annular p-type contact region 204 is formed on the surface of the second P-well region 203. The impurity concentration in the contact region 204 is higher than that of the second P-well region 203.

[0124] Within the transistor region 200, an n-type well region, the N-well region 205, is formed on the surface of the epitaxial layer 62. The N-well region 205 is formed within the first P-well region 202. The thickness of the N-well region 205 is thinner than the thickness of the first P-well region 202. The impurity concentration in the N-well region 205 is higher than the impurity concentration in the first P-well region 202.

[0125] Within the N-well region 205, a p-type base region 206 is formed on the surface of the epitaxial layer 62. The N-well region 205 is formed to surround the base region 206. The thickness of the base region 206 is thinner than the thickness of the N-well region 205. A p-type base contact region 207 and an n-type emitter region 208 are formed on the surface of the base region 206. The base contact region 207 and the emitter region 208 are formed with a gap between them. The impurity concentrations in the base contact region 207 and the emitter region 208 are higher than the impurity concentrations in the N-well region 205. In addition, an annular n-type collector region 209 is formed outside the base region 206 within the N-well region 205. The impurity concentration in the collector region 209 is higher than the impurity concentration in the N-well region 205.

[0126] An insulating film 210 is formed on the surface of the epitaxial layer 62 within the transistor region 200 and between the trench 201a of the DTI structure 201 and the insulator 201b. An example of the insulating film 210 is a silicon oxide film.

[0127] Within the transistor region 200, an interlayer insulating film 74 and a passivation film 84 are stacked in this order on the epitaxial layer 62, similar to the MISFET 23a. On the first interlayer insulating film 75, a first emitter electrode 211, a first collector electrode 212, a first base electrode 213, and a ground electrode 214 are formed as the first metal. These electrodes are electrode films containing one or more metal species selected from the group including, for example, aluminum, copper, titanium, tungsten, and tantalum.

[0128] The first emitter electrode 211 is electrically connected to the emitter region 208 via a contact, the first collector electrode 212 is electrically connected to the collector region 209 via a contact, and the first base electrode 213 is electrically connected to the base contact region 207 via a contact. The ground electrode 214 is electrically connected to the contact region 204 of the second P well region 203 via a contact. The ground electrode 214 is electrically connected to the insulator 201b of the DTI structure 201 via multiple contacts. In this way, the DTI structure 201, the second P well region 203, and the first P well region 202 are at ground potential.

[0129] On the third interlayer insulating film 77, a second emitter electrode, a second collector electrode, and a second base electrode are formed as a second metal (none of which are shown). The second emitter electrode is electrically connected to the first emitter electrode 211, the second collector electrode is electrically connected to the first collector electrode 212, and the second base electrode is electrically connected to the first base electrode 213. These electrodes are formed from the same material as, for example, the electrodes that form the first metal (first emitter electrode 211, etc.).

[0130] [Method of manufacturing semiconductor devices] The manufacturing method of the semiconductor device 1 will be described with reference to Figures 18 to 19F. As shown in Figure 18, the method for manufacturing the semiconductor device 1 includes an element mounting step (step S1), a first wire connection step (step S2), a second wire connection step (step S3), a molding step (step S4), a frame separation step (step S5), and a terminal bending step (step S6).

[0131] In the component mounting process shown in Figure 19A, a frame FL including a lead frame 10 is first prepared. Frame FL is composed of a first lead frame 11, a second lead frame 12, and a third lead frame 13, each connected to an outer frame FL1. The first terminal portion 11b of the first lead frame 11 is connected to the second terminal portion 12b of the second lead frame 12 and the third terminal portion 13b of the third lead frame 13 by a connecting portion FL2 (diver). In frame FL, the first terminal portion 11b already has a first bend portion 11g, an inclined portion 11h, a second bend portion 11i, and a tip portion 11j formed. Also in frame FL, the second terminal portion 12b and the third terminal portion 13b are positioned at the same location as the tip portion 11j of the first terminal portion 11b. Frame FL is also pre-plated with nickel.

[0132] Next, solder SD (not shown in Figure 19A, see Figure 3) is applied to each first island portion 11a of the frame FL. Then, semiconductor elements 20 are mounted on each solder SD. In one example, a die bonder (not shown) picks up the semiconductor elements 20 and fixes them to the solder SD of the first island portion 11a.

[0133] In the first wire connection process shown in Figure 19B, the first wire 41 is connected to the source pad 21 of the semiconductor element 20 and the third island portion 13a of the third lead frame 13 by wedge bonding. More specifically, the wedge bonding apparatus (not shown) that performs the wedge bonding first connects the first wire 41 to the source pad 21 (first bonding), and then connects it to the third island portion 13a (second bonding).

[0134] As explained using Figures 7 and 8, the connection portion 41a of the source pad 21 in the first wire 41 includes the centroid position GC of the active region 29 of the semiconductor element 20. At this time, the connection portion 41a is formed by a wedge bonding apparatus so as to extend toward the third island portion 13a of the third lead frame 13.

[0135] In the second wire connection process shown in Figure 19C, the second wire 42 is connected to the gate pad 22 of the semiconductor element 20 and the second island portion 12a of the second lead frame 12 by wedge bonding.

[0136] In the molding process shown in Figure 19D, the sealing resin 30 is molded, for example, by a molding apparatus. In one example, with the assembly manufactured in the second wire connection process placed inside the mold cavity of the molding apparatus, molten epoxy resin is poured into the mold cavity. This forms the sealing resin 30 that seals the semiconductor element 20, the first wire 41, and the second wire 42 (see Figure 19C).

[0137] In the frame separation process shown in Figure 19E, the lead frame 10 is separated from the frame FL (see Figure 19D) by, for example, a press forming apparatus. More specifically, the first lead frame 11, the second lead frame 12, and the third lead frame 13 are cut from the outer frame portion FL1 (see Figure 19D), and the connecting portion FL2 (see Figure 19D) that connects the first terminal portion 11b of the first lead frame 11, the second terminal portion 12b of the second lead frame 12, and the third terminal portion 13b of the third lead frame 13 is cut.

[0138] In the terminal bending process shown in Figure 19F, for example, the portions of the second terminal portion 12b of the second lead frame 12 and the third terminal portion 13b of the third lead frame 13 that protrude from the sealing resin 30 are bent by a press molding device. Through the above process, the semiconductor device 1 shown in Figure 1 can be obtained.

[0139] According to this embodiment, the following effects can be obtained. (1-1) The region in which the first wire 41 is connected to the source pad 21, i.e., the connection portion 41a of the first wire 41, includes the centroid position GC of the active region 29, which is the transistor formation region. With this configuration, the active clamp withstand capability Eac can be improved compared to the case in which the connection portion 41a of the first wire 41 is connected to a location in the source pad 21 that is different from the centroid position GC of the active region 29.

[0140] (1-2) The connection portion 41a of the first wire 41 extends toward the second island portion 12a of the second lead frame 12. Therefore, the middle portion of the first wire 41 connecting the semiconductor element 20 and the second island portion 12a is bent, but the degree of bending can be reduced. Thus, the reliability of the semiconductor device 1 can be improved.

[0141] (1-3) A plating layer 14 is formed on the surface of the first island portion 11a of the first lead frame 11. With this configuration, when solder SD is applied to the first island portion 11a, the wettability of the solder SD decreases, making it difficult for the solder SD to spread across the surface of the first island portion 11a. As a result, the thickness of the solder SD is prevented from becoming excessively thin, and the semiconductor element 20 and the first island portion 11a can be properly connected.

[0142] (1-4) The first wire 41 is made of aluminum, and the second lead frame 12 is made of copper. A plating layer 14 is formed on the surface of the second island portion 12a of the second lead frame 12 to which the first wire 41 is connected. This configuration makes it possible to suppress corrosion at the connection point between the first wire 41 and the second island portion 12a.

[0143] (1-5) The second wire 42 is made of aluminum, and the third lead frame 13 is made of copper. A plating layer 14 is formed on the surface of the third island portion 13a of the third lead frame 13 to which the second wire 42 is connected. This configuration makes it possible to suppress corrosion at the connection point between the second wire 42 and the third island portion 13a.

[0144] (1-6) The temperature sensor 27 is positioned in the area outside the source pad 21 in the active region 29 where heat is most concentrated when the semiconductor device 1 is driven. This allows for high-precision detection of the temperature of the semiconductor device 1.

[0145] (1-7) Generally, the coefficient of linear expansion of the sealing resin used to encapsulate LSIs that do not contain power transistors (hereinafter referred to as the comparative sealing resin) is 8 ppm / K to 10 ppm / K. The inventors of this invention then conducted a temperature cycle test on a semiconductor device using the comparative sealing resin. The temperature cycle test involved changing the temperature conditions from -65°C to 150°C for approximately 1000 cycles. As a result, it was found that pitting corrosion occurred on the first wire connected to the source pad of the semiconductor element and the third island portion of the third lead frame. The first wire used is the same as the first wire 41 of the semiconductor device 1.

[0146] From this, it can be concluded that although the surface of the first wire is protected by a native oxide film, the temperature cycling test applies a load to the first wire based on the difference between the linear expansion coefficient of the first wire and the linear expansion coefficient of the sealing resin. This causes the native oxide film to break down, and chloride ions from the sealing resin combine with the first wire, resulting in pitting corrosion on the first wire.

[0147] In this embodiment, a material with a coefficient of thermal expansion greater than 10 ppm / K was used as the sealing resin 30. More specifically, a sealing resin 30 with a coefficient of thermal expansion of 12 ppm / K was used. As a result, the difference between the coefficient of thermal expansion of the first wire 41 and the coefficient of thermal expansion of the sealing resin 30 is reduced, thereby reducing the load on the first wire 41 during temperature cycling tests. This suppresses the rupture of the native oxide film on the first wire 41, and thus suppresses the occurrence of pitting corrosion on the first wire 41.

[0148] On the other hand, in this embodiment, the filler content is increased to increase the coefficient of thermal expansion of the sealing resin 30. However, if the filler content is excessively high, the moldability of the sealing resin 30 will be excessively reduced. Specifically, if the coefficient of thermal expansion of the sealing resin 30 is 15 ppm / K or higher, the moldability of the sealing resin 30 will be excessively reduced.

[0149] In this respect, the sealing resin 30 in this embodiment uses a sealing resin 30 with a coefficient of linear expansion smaller than 15 ppm / K, so a decrease in the moldability of the sealing resin 30 can be suppressed. Thus, in this embodiment, the occurrence of pitting corrosion of the first wire 41 can be suppressed, as can a decrease in the moldability of the sealing resin 30.

[0150] (1-8) In the MISFET 23a, the ratio of the channel formation region 72 area to the unit area is less than 100%. In the MISFET 23a of this embodiment, the ratio of the channel formation region 72 area to the unit area is about 50%. Therefore, compared to the case where the above ratio is 100%, the generation of heat in the active region 29 can be suppressed. Consequently, the active clamping capacity Eac can be improved.

[0151] (1-9) The surface of the source pad 21 of the MISFET 23a is formed with an uneven shape. This configuration improves the adhesion between the source pad 21 and the sealing resin 30.

[0152] (Second Embodiment) The semiconductor device 1 of the second embodiment will be described with reference to Figures 20 to 22. The semiconductor device 1 of this embodiment differs from the semiconductor device 1 of the first embodiment in the connection structure of the first wire 41 to the source pad 21. In the following description, components common to the semiconductor device 1 of the first embodiment are denoted by the same reference numerals, and their descriptions are omitted. Figures 20 and 21 are enlarged plan views showing a part of the substrate 50. In Figure 20, the active region 29 is shown by a solid line, and the source pad 21 is shown by a dashed line. In Figure 21, the active region 29 is shown by a dashed line, and the source pad 21 is shown by a solid line.

[0153] The inventors of the present invention focused on the connection position of the source pad 21 of the first wire 41 connected to the semiconductor element 20 with respect to the active region 29 of the semiconductor element 20 in order to improve the active clamp withstand capability Eac of the semiconductor device 1. The inventors of the present invention found that when the first wire 41 is connected to the source pad 21 at two locations, the active clamp withstand capability Eac is improved when the first wire 41 is connected to the source pad 21 at positions corresponding to the centroids of two divided regions, which are obtained by dividing the active region 29 into two equal areas. In view of this, as shown in Figure 21, in this embodiment, the first wire 41 is connected to the source pad 21 at two connection points. These two connection points are the centroids GB1 and GB2 of the divided active region 29 when the area of ​​the active region 29 is divided into two equal parts.

[0154] Here, the centroid positions GB1 and GB2 of the active region 29 can be determined as follows. As shown in Figure 20, first, the source pad 21 is divided into two division regions (first region RB1 and second region RB2) with equal areas. As shown in Figure 20, at least one of the first region RB1 and the second region RB2 may be a region other than a rectangle. The first region RB1 shown in Figure 20 is a region with a rectangular protrusion. On the other hand, the second region RB2 is a rectangular region.

[0155] Next, we determine the centroid GB1 of the first region RB1 and the centroid GB2 of the second region RB2. As shown in Figure 20, the second region RB2 is rectangular, so the centroid GB2 of the second region RB2 is the intersection of its diagonals. On the other hand, the first region RB1 is not rectangular, so we further divide the first region RB1 into the first divided region RB11 and the second divided region RB12. More specifically, the rectangular convex portion of the first region RB1 is designated as the first divided region RB11, and the remaining region of the first region RB1 (the rectangular region) is designated as the second divided region RB12. Then we determine the centroid GB11 of the first divided region RB11 and the centroid GB12 of the second divided region RB12. The centroid GB11 of the first divided region RB11 is the intersection of its diagonals. The centroid GB12 of the second divided region RB12 is the intersection of the diagonals of the second divided region RB12. Next, the area SB1 of the first divided region RB11 and the area SB2 of the second divided region RB12 are determined. Then, on the line segment LB connecting the centroid GB11 and the centroid GB12, the centroid GB1 of the first region RB1 is determined based on the relationship between the distance DB1 between the centroid GB11 and the centroid GB1, the distance DB2 between the centroid GB12 and the centroid GB1, and the areas SB1 of the first divided region RB11 and the area SB2 of the second divided region RB12. More specifically, the ratio of distance DB2 to distance DB1 (DB2 / DB1) is equal to the inverse ratio of the ratio of the area SB2 of the second divided region RB12 to the area SB1 of the first divided region RB11 (SB1 / SB2) (DB2 / DB1 = SB1 / SB2). This allows us to determine the centroid position GB1 of the first region RB1 by finding at least one of the distances DB1 and DB2. Furthermore, as shown in Figure 20, the source pad 21 is positioned to cover the respective centroid positions GB1 and GB2 of the divided active regions 29 (the centroid position GB1 of the first region RB1 and the centroid position GB2 of the second region RB2).

[0156] The two dashed-dotted regions RY shown in Figure 20 represent the tool head (hereinafter referred to as wedge RY) for ultrasonic bonding the first wire 41 to the source pad 21 in a wedge bonding apparatus (not shown). The wedge bonding apparatus moves the wedge RY so that it is positioned on the centroid GB1 of the first region RB1 of the active region 29, and connects the end of the first wire 41 to the source pad 21. As a result, the end of the first wire 41 passed through the wedge RY is connected so as to overlap the centroid GB1 of the first region RB1, as shown in Figure 21. That is, the first connection portion 41b (connection region) of the first wire 41 to the source pad 21 includes the centroid GB1 of the first region RB1. In this embodiment, the center position of the first connection portion 41b and the centroid GB1 of the first region RB1 coincide. Next, the wedge bonding apparatus moves the wedge RY away from the source pad 21, causing the first wire 41 to move away from the source pad 21 (see Figure 22). The wedge bonding apparatus then moves the wedge RY so that it is positioned on the centroid GB2 of the second region RB2 of the active region 29, thereby connecting the first wire 41 to the source pad 21 (see Figure 22). As a result, the first wire 41 passed through the wedge RY is connected so as to overlap the centroid GB2 of the second region RB2, as shown in Figure 21. That is, the second connection portion 41c (connection region) of the first wire 41 to the source pad 21 includes the centroid GB2 of the second region RB2. In this embodiment, the center position of the second connection portion 41c coincides with the centroid GB2 of the second region RB2. Also, as shown in Figure 22, the portion of the first wire 41 between the first connection portion 41b and the second connection portion 41c is spaced upward from the source pad 21.

[0157] Furthermore, as shown in Figure 21, the first connection portion 41b and the second connection portion 41c connected to the source pad 21 on the first wire 41 extend in directions different from the horizontal X and vertical Y directions in a plan view of the semiconductor device 1. More specifically, the first connection portion 41b and the second connection portion 41c extend from the semiconductor element 20 toward the second island portion 12a (see Figure 2). Note that the direction in which the first connection portion 41b extends and the direction in which the second connection portion 41c extends can be arbitrarily changed. For example, the direction in which the first connection portion 41b extends and the direction in which the second connection portion 41c extends may be different from each other.

[0158] As shown in Figure 21, the dashed-dotted region RS surrounding the first connection portion 41b and the second connection portion 41c of the first wire 41 is a margin that takes into account variations in the wire diameter of the first wire 41 and variations in the connection position of the first wire 41 to the source pad 21 by the wedge bonding apparatus. That is, the first connection portion 41b and the second connection portion 41c of the first wire 41 are always located within region RS. In this embodiment, region RS includes the vicinity of the intersection of the fifth side 29e and the sixth side 29f of the active region 29. In this embodiment, the temperature sensor 27 is provided adjacent to region RS in a plan view of the semiconductor device 1.

[0159] According to this embodiment, in addition to the effects of the first embodiment, the following effects can be obtained. (2-1) The first wire 41 is connected to the centroid positions GB1 and GB2 of the first region RB1 and the second region RB2, which are two divided regions that divide the active region 29 into equal areas. This reduces the concentration of heat in the active region 29 when the semiconductor device 1 is driven, thereby improving the active clamp withstand capacity Eac.

[0160] (Third embodiment) Referring to Figure 23, the semiconductor device 1 of the third embodiment will be described. The semiconductor device 1 of this embodiment differs from the semiconductor device 1 of the first embodiment in some aspects of the structure of the MISFET 23a. In the following description, components common to the semiconductor device 1 of the first embodiment are denoted by the same reference numerals, and their descriptions are omitted. The differences from the MISFET 23a of the first embodiment will be described in detail below.

[0161] As shown in Figure 23, one or more first slits 220 are provided in the first source electrode 80, which serves as the first metal layer, in the portion facing the source pad 21. The first slits 220 penetrate the first source electrode 80 and extend in the direction in which the trench gate structure 65 extends (the depth direction of the paper). In this embodiment, the first slits 220 face the trench gate structure 65.

[0162] In the second source electrode 82, which serves as the second metal layer, one or more second slits 221 are provided in the portion facing the source pad 21. The second slits 221 penetrate the second source electrode 82 and extend in the direction in which the trench gate structure 65 extends.

[0163] The second slit 221 is provided so that at least a portion of it faces the first slit 220. The width dimension DS2 of the second slit 221 and the width dimension DS1 of the first slit 220 can be arbitrarily changed. In this embodiment, the width dimension DS2 of the second slit 221 and the width dimension DS1 of the first slit 220 are equal to each other. Also in this embodiment, the entire second slit 221 faces the first slit 220.

[0164] The first slit 220 is embedded with the second interlayer insulating film 76. The second slit 221 is embedded with the fourth interlayer insulating film 78. The fourth interlayer insulating film 78 extends over the second slit 221 and covers the periphery of the second slit 221 of the second source electrode 82. In this way, a support column 222 made of the first interlayer insulating films 75 to the fourth interlayer insulating films 78 is provided in the portion of the semiconductor element 20 where the first slit 220 and the second slit 221 are provided. The support column 222 is constructed by sequentially stacking the first interlayer insulating film 75, the second interlayer insulating film 76, the third interlayer insulating film 77, and the fourth interlayer insulating film 78. The upper end of the support column 222 is covered by the source pad 21. Thus, the support column 222 supports the source pad 21.

[0165] Such configurations including the first slit 220 and the second slit 221 are preferably provided at least on the periphery of the source pad 21. In this embodiment, the configurations including the first slit 220 and the second slit 221 are provided all over the source pad 21. More specifically, the MISFET 23a is formed by combining a large number of configurations including the first slit 220 and the second slit 221. An example of a configuration including the first slit 220 and the second slit 221 is a configuration in which the first slit 220 and the second slit 221 are provided at positions corresponding to three trench gate structures 65 and one of the three trench gate structures 65. The MISFET 23a is formed by combining a plurality of configurations including the first slit 220 and the second slit 221.

[0166] The source pad 21 in this embodiment is made of copper (Cu). The thickness of the source pad 21 is preferably about 4 μm or more. Furthermore, the thickness of the source pad 21 is preferably about 20 μm or less. In this embodiment, the thickness of the source pad 21 is about 8 μm. The source pad 21 can be formed by copper plating growth. A connecting layer 21a containing nickel (Ni) plating is formed on the surface of the copper constituting the source pad 21. In this embodiment, the connecting layer 21a is formed by nickel-palladium (NiPd) plating. Note that the source pad 21 may also be made of an aluminum alloy (e.g., AlCu).

[0167] (action) The operation of this embodiment will now be described. For example, when a semiconductor device is connected to an inductive load and is required to absorb the energy released from the inductive load when the switching element (MISFET) of the semiconductor device turns off, the active clamp withstand capability Eac is known as an indicator of how much energy stored in the inductive load can be absorbed.

[0168] Incidentally, if the energy supplied to a semiconductor device exceeds a predetermined value, the device may fail due to a temperature rise. Thus, the active clamp withstand capability Eac is primarily determined by the failure of the semiconductor device due to heat. For this reason, for example, when energy is supplied to the semiconductor device, transient and localized high temperatures may occur in the substrate, resulting in a higher likelihood of failure in those areas, where energy absorption may be impaired. This makes it difficult to improve the active clamp withstand capability Eac.

[0169] To address these problems, one possible solution is to replace the power electrode pads (source pads) of the semiconductor device with copper, which has excellent heat dissipation properties, and to increase the thickness of the source pads in order to absorb the transient energy of the semiconductor device. This can improve the active clamp withstand capability Eac.

[0170] However, when heat is applied to the source pad during the manufacturing of semiconductor devices, a copper source pad is more prone to stretching than an aluminum source pad. This causes the outer edge of the source pad to press against the interlayer insulating film formed within the source pad toward the epitaxial layer. As a result, passivation cracks may occur in the external region of the source pad, for example, where the first metal protrudes from the passivation film.

[0171] In light of these circumstances, in this embodiment, a first slit 220 is formed in the first source electrode 80 and a second slit 221 is formed in the second source electrode 82. As a result, even if the first source electrode 80 deforms, the deformation is interrupted at the first slit 220, and even if the second source electrode 82 deforms, the deformation is interrupted at the second slit 221, thereby reducing the amount of deformation of the first source electrode 80 and the second source electrode 82, respectively.

[0172] In addition, since a support column 222 is formed to support the source pad 21 so as to connect the first slit 220 and the second slit 221, the support column 222 supports the source pad 21 against thermal deformation, thereby suppressing deformation of the first source electrode 80 and the second source electrode 82. Therefore, the occurrence of passivation cracks can be suppressed.

[0173] According to this embodiment, in addition to the above-mentioned actions and effects, the following effects can be obtained. (3-1) For example, if the source pad 21 is made of aluminum, it is difficult to make the source pad 21 sufficiently thick because it is formed by sputtering. Therefore, it is difficult to increase the heat capacity of the source pad 21, and there is a risk that it may not be able to dissipate heat sufficiently when heat is instantaneously applied to the semiconductor device. For this reason, there is room for improvement in sufficiently improving the active clamp withstand capacity Eac.

[0174] In this embodiment, the source pad 21 is made of plated copper. This allows the thickness of the source pad 21 to be greater than that of a source pad 21 made of aluminum. Therefore, the heat capacity of the source pad 21 can be increased, and thus the active clamping capacity Eac can be improved. In addition, by making the source pad 21 thicker, it is possible to suppress the transmission of the impact when the first wire 41 is connected to the source pad 21 to the interlayer insulating film 74.

[0175] (3-2) Nickel plating is formed on the copper surface of the source pad 21. The first wire 41 is made of aluminum. This makes it possible to suppress corrosion at the connection point between the source pad 21 and the first wire 41.

[0176] (Fourth Embodiment) Referring to Figures 24 to 27K, the semiconductor device 1 of the fourth embodiment will be described. The semiconductor device 1 of this embodiment differs from the semiconductor device 1 of the first embodiment in the structure of the MISFET 23a. In the following description, components common to the semiconductor device 1 of the first embodiment are denoted by the same reference numerals, and their descriptions are omitted. In this embodiment, the channel formation region 72 is different in the MISFET 23a, so for the sake of explanation, the interlayer insulating film 74, the first source electrode 80, the second source electrode 82, and the source pad 21 are shown in a simplified manner in Figures 27J and 27K. In this embodiment, the configuration including the first source electrode 80, the second source electrode 82, and the source pad 21 is defined as the source metal 230.

[0177] The MISFET 23a of this embodiment has a plurality of functional element formation regions 231 with different ratios of channel formation region 72 area per unit area. In this embodiment, the active region 29 of the MISFET 23a is composed of a plurality of functional element formation regions 231. The plurality of functional element formation regions 231 include a first functional element formation region 232 in which the ratio of channel formation region 72 area per unit area is relatively small, and a second functional element formation region 233 in which the ratio of channel formation region 72 area per unit area is relatively high. Furthermore, the plurality of functional element formation regions 231 of this embodiment also include a third functional element formation region 234 in which the ratio of channel formation region 72 area per unit area is larger than that of the first functional element formation region 232 and smaller than that of the second functional element formation region 233.

[0178] The first functional element formation region 232 generates relatively little heat because the ratio of the channel formation region 72 area per unit area is smaller than that of the second functional element formation region 233 and the third functional element formation region 234. On the other hand, the on-resistance of the first functional element formation region 232 is higher than that of the second functional element formation region 233 and the third functional element formation region 234 due to the relatively small channel formation region 72.

[0179] Conversely, the second functional element formation region 233 and the third functional element formation region 234 have a larger proportion of channel formation region 72 area per unit area than the first functional element formation region 232, and therefore generate relatively more heat. On the other hand, the on-resistance of the second functional element formation region 233 and the third functional element formation region 234 is lower than that of the first functional element formation region 232 due to the relatively large area of ​​channel formation region 72.

[0180] The relative magnitudes of the heat generation in the first to third functional element formation regions 232 to 234 are as follows: heat generation in the first functional element formation region 232 < heat generation in the third functional element formation region 234 < heat generation in the second functional element formation region 233. The relative magnitudes of the on-resistances in the first to third functional element formation regions 232 to 234 are as follows: on-resistance in the second functional element formation region 233 < on-resistance in the third functional element formation region 234 < on-resistance in the first functional element formation region 232. Furthermore, the relative magnitudes of the active clamp withstand voltage Eac in the first to third functional element formation regions 232 to 234 are as follows: active clamp withstand voltage Eac in the second functional element formation region 233 < active clamp withstand voltage Eac in the third functional element formation region 234 < active clamp withstand voltage Eac in the first functional element formation region 232.

[0181] In this embodiment, the semiconductor device 1 (MISFET 23a) aims to provide a semiconductor device 1 that can achieve both excellent active clamp withstand capability Eac and on-resistance while suppressing the temperature rise throughout the semiconductor device 1 (semiconductor element 20) by devising the arrangement pattern of the first functional element formation region 232, the second functional element formation region 233, and the third functional element formation region 234. In particular, the semiconductor device 1 aims to achieve the above objective by arranging the first functional element formation region 232 in the part of the source pad 21 that is prone to temperature rise, and arranging the second functional element formation region 233 and the third functional element formation region 234 in the other parts.

[0182] For example, areas in the source pad 21 where the temperature is likely to rise and where temperature rise should be suppressed include the inner region separated by a predetermined distance from the periphery of the source pad 21, the region surrounded by multiple channel formation regions 72 (multiple functional element formation regions 231), the region where the first wire 41 is not connected in a plan view, and regions where these regions are selectively combined. In these regions, heat is difficult to dissipate and tends to accumulate. In particular, the inner region of the source pad 21 is prone to temperature rise and tends to become relatively hotter than other parts.

[0183] Therefore, in this embodiment, the first functional element formation region 232 is arranged in the inner region of the active region 29, and the second functional element formation region 233 and the third functional element formation region 234 are arranged in the outer region of the active region 29. As a result, the ratio of the area of ​​the channel formation region 72 per unit area gradually increases from the inside to the outside of the active region 29.

[0184] Furthermore, in the active region 29, the temperature of the active region 29 tends to decrease at the point where the first wire 41 is connected to the source pad 21, as heat is dissipated to the first wire 41 through the source pad 21. Considering this point, the second functional element formation region 233, which generates the most heat, is located at the point where the first wire 41 is connected to the source pad 21.

[0185] The arrangement of the multiple functional element formation regions 231 will be described in detail below. Figures 24 and 25 show an example of the arrangement of the multiple functional element formation regions 231, and the size and number of regions that divide the active region 29 can be arbitrarily changed.

[0186] As shown in Figures 24 and 25, the multiple functional element formation regions 231 include a first functional element formation region unit U1 containing multiple (four in this embodiment) first functional element formation regions 232, a second functional element formation region unit U2 containing multiple (four in this embodiment) second functional element formation regions 233, and a third functional element formation region unit U3 containing multiple (four in this embodiment) third functional element formation regions 234.

[0187] In this embodiment, the first to third functional element formation area units U1 to U3 are roughly the same size and have a rectangular shape in plan view, and are arranged in a predetermined layout to tile the active area 29 in a matrix (regular grid in the vertical and horizontal directions). In other words, the first to third functional element formation area units U1 to U3 are arranged in a predetermined layout within a plurality of rectangular areas that divide the active area 29 in a matrix.

[0188] More specifically, the first to third functional element formation region units U1 to U3 are arranged according to the amount of heat generated in each region of the active region 29 when the semiconductor device 1 is driven, for example by simulation. For example, the second functional element formation region unit U2 is placed in regions where the amount of heat generated is below the first threshold, the first functional element formation region unit U1 is placed in regions where the amount of heat generated is greater than the first threshold but above the second threshold, and the third functional element formation region unit U3 is placed in regions where the amount of heat generated is greater than the first threshold but less than the second threshold.

[0189] Figure 24 shows the arrangement of the first to third functional element formation area units U1 to U3 in the active area 29 when the first wire 41 is connected to the source pad 21 at one point.

[0190] As shown in Figure 24, the first functional element formation region unit U1 is located in a region where heat generation should be suppressed. The first functional element formation region unit U1 is located in the inner region of the active region 29. The third functional element formation region unit U3 is located in a region adjacent to the first functional element formation region unit U1. The second functional element formation region unit U2 is located in a region adjacent to the third functional element formation region unit U3, on the opposite side from the first functional element formation region unit U1.

[0191] Furthermore, in the active region 29, a second functional element formation region unit U2 is provided in the region where the first wire 41 is connected to the source pad 21 (the region indicated by the dashed line). A first functional element formation region unit U1 is provided in the region surrounding this second functional element formation region unit U2. A third functional element formation region unit U3 is provided in the region surrounding this first functional element formation region unit U1.

[0192] Figure 25 shows the arrangement of the first to third functional element formation area units U1 to U3 in the active area 29 when the first wire 41 is connected to the source pad 21 at two locations.

[0193] As shown in Figure 25, the first functional element formation region unit U1 is located in a region where heat generation should be suppressed. The first functional element formation region unit U1 is located in the inner region of the active region 29. In one example, the first functional element formation region unit U1 is located in the inner region between two regions (regions indicated by dashed lines) in the active region 29 where the first wire 41 is connected to the source pad 21. The third functional element formation region unit U3 is located in a region adjacent to the first functional element formation region unit U1.

[0194] Furthermore, in the active region 29, a second functional element formation region unit U2 is provided in the region that includes two areas where the first wire 41 is connected to the source pad 21 (the region where the wedge RY is located). A first functional element formation region unit U1 is provided in the region surrounding these second functional element formation region units U2. A third functional element formation region unit U3 is provided in the region surrounding these first functional element formation region units U1.

[0195] Furthermore, the outer region of the active region 29 is not limited to the arrangement of the second functional element formation region unit U2 and the third functional element formation region unit U3 shown in Figures 24 and 25; it is sufficient if either the second functional element formation region unit U2 or the third functional element formation region unit U3 is present.

[0196] Next, the planar structures of the first to third functional element formation region units U1 to U3 will be described with reference to Figures 26A to 26C. As shown in Figures 26A to 26C, the layout of the first to third functional element formation regions 232 to 234 has been changed in the first to third functional element formation region units U1 to U3 by adjusting the ratio of the channel formation region 72 area per unit area.

[0197] The first functional element formation region unit U1 shown in Figure 26A includes multiple functional element formation regions 231 in which the area of ​​the channel formation region 72 accounts for approximately 25% of the unit area. The second functional element formation region unit U2 shown in Figure 26B includes multiple functional element formation regions 231 in which the area of ​​the channel formation region 72 accounts for approximately 75% of the unit area. The third functional element formation region unit U3 shown in Figure 26C includes multiple functional element formation regions 231 in which the area of ​​the channel formation region 72 accounts for approximately 50% of the unit area.

[0198] As shown in Figures 26A to 26C, in this embodiment, multiple channel formation regions 72 are formed in the first to third functional element formation regions 232 to 234 in a layout based on a staggered or zigzag pattern.

[0199] As shown in Figure 26A, in each first functional element formation region 232 of the first functional element formation region unit U1, the multiple channel formation regions 72 are arranged in a staggered pattern along the length of the trench gate structure 65. In each trench gate structure 65, the multiple channel formation regions 72 are arranged alternately with spacing between them on one side and the other side of each trench gate structure 65 along the length of the trench gate structure 65. The multiple channel formation regions 72 are located only on one side or the other side in the lateral direction intersecting the trench gate structure 65. With this configuration, the ratio of the area of ​​the channel formation regions 72 to the area per unit area in the first functional element formation region unit U1 is approximately 25%. In the first functional element formation region unit U1, since the channel formation regions 72 are arranged with spacing between them on one side or the other side of the trench gate structure 65, the heat source can be effectively dispersed.

[0200] Furthermore, the channel formation region 72 located on one side does not face the channel formation region 72 located on the other side, across the trench gate structure 65. Therefore, in the lateral direction intersecting the trench gate structure 65, multiple heat sources do not face each other across the trench gate structure 65. This suppresses the transfer of heat generated in one channel formation region 72 to other channel formation regions 72, thereby effectively suppressing the occurrence of thermal interference. In this way, the first functional element formation region unit U1 is configured to effectively suppress temperature rise.

[0201] As shown in Figure 26B, each second functional element formation region 233 of the second functional element formation region unit U2 has a configuration in which the source region 70 and the body contact region 73 are swapped compared to the configuration shown in Figure 26A. More specifically, the channel formation region 72 extends along the length direction of the trench gate structure 65. In the lateral direction intersecting with the trench gate structure 65, the channel formation region 72 formed on one side of the trench gate structure 65 and the channel formation region 72 formed on the other side of the trench gate structure 65 are integrally formed. As a result, a cross-shaped channel formation region 72 is formed within each second functional element formation region 233. With this configuration, the ratio of the area of ​​the channel formation region 72 to the area per unit area in the second functional element formation region unit U2 is approximately 75%.

[0202] As shown in Figure 26C, each third functional element formation region 234 of the third functional element formation region unit U3 is configured such that, in the configuration shown in Figure 26A, the length of the channel formation region 72 in the longitudinal direction of the trench gate structure 65 is extended by approximately twice the length. With this configuration, in the third functional element formation region unit U3, the ratio of the area of ​​the channel formation region 72 to the area per unit area is approximately 50%. The cross-sectional structure of the first to third functional element formation region units U3 in this embodiment is generally the same as the cross-sectional structure of the MISFET 23a shown in Figure 9.

[0203] (Method of manufacturing MISFETs) An example of a manufacturing method for MISFET 23a will be described with reference to Figures 27A to 27K. Figures 27A to 27K are longitudinal cross-sectional views of the portion corresponding to line 27-27 in Figure 26A.

[0204] First, as shown in Figure 27A, a wafer-shaped substrate 50 is prepared, which includes a semiconductor substrate 61 and an epitaxial layer 62 formed on the semiconductor substrate 61. Next, as shown in Figure 27B, a hard mask 240 having selective openings 241 in the region where trenches 66 are to be formed is formed on the epitaxial layer 62. Then, the surface layer of the epitaxial layer 62 is selectively removed by etching through the hard mask 240. This forms multiple trenches 66. After the trenches 66 are formed, the hard mask 240 is removed.

[0205] Next, as shown in Figure 27C, a thermal oxide film 242 made of silicon oxide is formed on the inner wall surface of the trench 66, for example, by a thermal oxidation method. Next, as shown in Figure 27D, a polysilicon film 244 is deposited on the epitaxial layer 62 as a conductor. The polysilicon film 244 fills the trenches 66 and covers the surface of the epitaxial layer 62. After this, n-type impurities are injected into the polysilicon film 244 and diffused by heat treatment (drive-in). Examples of n-type impurities include phosphorus (P) and arsenic (As).

[0206] Next, as shown in Figure 27E, the polysilicon film 244 is etched. The etching of the polysilicon film 244 continues until the etched surface reaches the middle of each depth direction of the trench 66. This forms an embedded electrode 69 in the trench 66, consisting of the remaining polysilicon film 244.

[0207] Next, as shown in Figure 27F, the thick gate insulating film 67 located between the opening of the trench 66 and the upper end portion 69a of the embedded electrode 69 is etched. The thick gate insulating film 67 is removed so that a portion remains on each inner wall surface of the trench 66. At this time, a portion of the upper end portion 69a of the embedded electrode 69 is exposed from the thick gate insulating film 67. In this case, the etching performed may be wet etching.

[0208] Next, as shown in Figure 27G, the substrate 50 is subjected to thermal oxidation treatment, forming a thermal oxide film 242 on the exposed side surface of the trench 66 and the surface of the substrate 50. At this time, a portion of the exposed upper end 69a of the embedded electrode 69 is also oxidized, forming a thermal oxide film 242. At the upper end 69a of the embedded electrode 69, oxidation progresses more rapidly than on the exposed side of the trench 66 due to the polysilicon into which impurities have been introduced, resulting in the formation of a relatively thick thermal oxide film 242. In this process, a recess 245 is formed between the upper end 69a of the embedded electrode 69 and the side surface of the trench 66 by the thick film portion 67a and thin film portion 67b of the gate insulating film 67.

[0209] Next, as shown in Figure 27H, a polysilicon film 246 as a conductor is deposited on the substrate 50. The polysilicon film 246 fills the trenches 66 and covers the surface of the substrate 50. The polysilicon film 246 enters the recesses 245 in the trenches 66 and forms a projection that extends downward between it and the upper end 69a of the embedded electrodes 69 in the trenches 66, thereby forming a recess 68a that opens toward the embedded electrodes 69. After this, impurities are injected into the polysilicon film 246 and diffused by heat treatment (drive-in). Next, the polysilicon film 246 is etched.

[0210] Etching of the polysilicon film 246 is continued until the etched surface is slightly inside the trench 66 relative to the surface of the substrate 50. As a result, gate electrodes 68 made of the remaining polysilicon film 246 are formed in each of the trenches 66. Recesses 247 are also formed on top of the gate electrodes 68.

[0211] Next, as shown in Figure 27I, an ion implantation mask (not shown) that selectively opens into the region where the body region 71 is to be formed is formed on the substrate 50. Then, p-type impurities are implanted into the surface layer of the epitaxial layer 62 via the ion implantation mask. This forms the body region 71 on the surface layer of the epitaxial layer 62. After the body region 71 is formed, the ion implantation mask is removed. Next, n-type impurities and p-type impurities are implanted into the substrate 50 in sequence. After that, the implanted impurity ions are diffused by heat treatment (drive-in). This forms the n + Source area 70 and p + A body contact region 73 of the mold is formed. Next, as shown in Figure 27J, a silicon nitride film and a silicon oxide film are deposited sequentially, for example by CVD. This forms an interlayer insulating film 74.

[0212] Here, the source region 70 is formed by implanting n-type impurities through an ion implantation mask that selectively has openings in the region where the source region 70 is to be formed. As a result, in a plan view, source regions 70 with a relatively small area ratio per unit area and source regions 70 with a relatively large area ratio per unit area are selectively formed. In other words, a first functional element formation region 232 (first functional element formation region unit U1), a second functional element formation region 233 (second functional element formation region unit U2), and a third functional element formation region 234 (third functional element formation region unit U3) are formed.

[0213] Furthermore, the body contact region 73 is formed by implanting p-type impurities through an ion implantation mask that selectively has openings in the region where the body contact region 73 is to be formed. Next, the interlayer insulating film 74 is selectively etched by reactive ion etching (RIE) to form contact holes 248. Then, as shown in Figure 27K, after contacts 81 and 83 (not shown in Figure 27K) are embedded in the contact holes 248, an electrode film (not shown) is formed to cover the area on the substrate 50. By patterning this electrode film, a source pad 21 (source metal 230) and a gate pad 22 (see Figure 5) are formed. An electrode film (not shown) is also formed to cover the semiconductor substrate 61 of the substrate 50. By patterning this electrode film, a drain electrode 64 is formed. Through these steps, a semiconductor device 1 (MISFET 23a) is obtained.

[0214] According to this embodiment, the following effects can be obtained. (4-1) In the active region 29, a first functional element formation region unit U1 is placed in the region where heat generation should be suppressed, and which has a low heat generation capacity and a large active clamp withstand capacity Eac. This makes it possible to suppress the temperature rise of the active region 29 and to prevent the region in the active region 29 where heat generation should be suppressed from becoming transiently and locally hot. Furthermore, because the first functional element formation region unit U1 is placed in the active region 29, it is easier to improve the active clamp withstand capacity Eac compared to, for example, a configuration in which the active region 29 consists of a second functional element formation region unit U2 and a third functional element formation region unit U3.

[0215] (4-2) In the active region 29, a second functional element formation region unit U2 or a third functional element formation region unit U3 is arranged in a region other than the region where heat generation should be suppressed, for example, in the outer region of the active region 29, such that the ratio of the area of ​​the channel formation region 72 per unit area is larger than that of the first functional element formation region unit U1. As a result, the area of ​​the channel formation region 72 is larger than that of the first functional element formation region unit U1, and a larger current path can be secured. Therefore, even when the first functional element formation region unit U1 is used in conjunction with the channel formation region U3, a reduction in the current path relative to the entire active region 29 can be suppressed. This makes it possible to suppress the increase in the on-resistance of the semiconductor element 20 by utilizing the region other than the region where heat generation should be suppressed in the active region 29.

[0216] (4-3) In the active region 29, a second functional element formation region unit U2 is placed in the region corresponding to the point where the first wire 41 is connected to the source pad 21, and has a configuration that generates a large amount of heat and has a small active clamp withstand capability Eac. With this configuration, the heat from the active region 29 is transferred to the first wire 41 through the source pad 21, so the temperature does not rise easily in the region of the active region 29 corresponding to the point where the first wire 41 is connected to the source pad 21. For this reason, by using the second functional element formation region unit U2 which generates a large amount of heat, it is possible to suppress the increase in the on-resistance of the semiconductor element 20.

[0217] (4-4) The active region 29 is composed of a first functional element formation region unit U1, a second functional element formation region unit U2, and a third functional element formation region unit U3. This makes it easier to adjust the on-resistance and active clamp withstand voltage Eac of the semiconductor element 20 compared to the case where the active region 29 is composed of, for example, two types of functional element formation region units.

[0218] Furthermore, in a portion of the active region 29, a third functional element formation region unit U3 is positioned between the first functional element formation region unit U1 and the second functional element formation region unit U2. This suppresses rapid changes in on-resistance and active clamp withstand voltage Eac.

[0219] (modified version) The above descriptions of the embodiments are illustrative of possible forms of the semiconductor devices of the Disclosure and are not intended to limit their forms. The semiconductor devices of the Disclosure may take the form of, for example, variations of the embodiments shown below, and combinations of at least two non-inconsistent variations.

[0220] [Combination of embodiments] The second embodiment and the third embodiment may be combined. That is, the structures of the interlayer insulating film 74, the first source electrode 80, and the second source electrode 82 directly beneath the source pad 21 of the semiconductor device 1 in the second embodiment may be replaced with the structures of the interlayer insulating film 74, the first source electrode 80, and the second source electrode 82 in the third embodiment.

[0221] The third embodiment and the fourth embodiment may be combined. That is, the active region 29 of the semiconductor device 1 in the third embodiment may be replaced with a structure having multiple functional element formation regions 231 with different ratios of channel formation region area 72 area per unit area, as in the fourth embodiment.

[0222] [Addition of heat dissipation components] To improve the active clamping capacity Eac, it is necessary to improve the heat dissipation of the semiconductor device 1. Therefore, in each of the above embodiments, the heat dissipation of the semiconductor device 1 can be improved by connecting a heat dissipation member 250 to the source pad 21. As an example, as shown in Figures 28A and 28B, a plurality of heat dissipation members 250 are connected to the source pad 21. Figure 28A shows the arrangement of the heat dissipation member 250 when there is one connection point for the first wire 41 to the source pad 21, and Figure 28B shows the arrangement of the heat dissipation member 250 when there are two connection points for the first wire 41 to the source pad 21.

[0223] As shown in Figures 28A and 28B, the multiple heat dissipation members 250 are connected to the regions of the source pad 21 corresponding to the areas in the active region 29 where heat generation should be suppressed. More specifically, in Figure 28A, the multiple heat dissipation members 250 are connected to the regions of the source pad 21 corresponding to the inner region of the active region 29. Specifically, the multiple heat dissipation members 250 are arranged to surround a portion of the connection portion 41a (dotted line) of the first wire 41. Note that, in order to avoid interference with the first wire 41, the heat dissipation members 250 are not positioned in the direction in which the first wire 41 extends.

[0224] In Figure 28B, the heat dissipation members 250 are arranged to surround a portion of the first connection portion 41b and the second connection portion 41c (both indicated by dashed lines), which are the ends of the first wire 41. To avoid interference with the first wire 41, the heat dissipation members 250 are not positioned in the direction in which the first wire 41 extends. The multiple heat dissipation members 250 are connected to the inner region of the active region 29, that is, the region between the first connection portion 41b and the second connection portion 41c of the first wire 41 in the active region 29, and to the region of the source pad 21 that is adjacent to the first wire 41 in the vertical direction Y.

[0225] Such a heat dissipation member 250 is formed by connecting wires to the source pad 21 by wedge bonding or ball bonding. That is, the shape of the heat dissipation member 250 is the same as the shape of the connection portion when the wires are connected. The heat dissipation member 250 is made of, for example, copper or aluminum. Alternatively, for example, the heat dissipation member 250 may be formed by connecting a first wire 41 to the source pad 21.

[0226] Figure 29 shows an example of a heat dissipation member 250. The heat dissipation member 250 shown in Figure 29 is the case when the wire is connected to the source pad 21 by ball bonding. Furthermore, the arrangement of the multiple heat dissipation members 250 shown in Figures 28A and 28B is just one example, and the arrangement can be changed at will. For example, the multiple heat dissipation members 250 may be connected to at least one region of the source pad 21 corresponding to the region in the active region 29 shown in Figures 28A and 28B where the multiple third functional element formation region units U3 are arranged.

[0227] In the first to third embodiments described above, one or more heat dissipation members 250 may be connected to the source pad 21. With this configuration, the heat dissipation of the semiconductor device 1 is improved via the source pad 21, thereby improving the active clamping capacity Eac.

[0228] [Connection position of connecting members] In the first embodiment described above, as shown in Figure 7, the first wire 41 and the source pad 21, which serve as connecting members, are connected to each other at a position on the line segment LA that connects the centroid position GA1 of the first region RA1 and the centroid position GA2 of the second region RA2. The first wire 41 and the source pad 21 may also be connected to each other at two locations: the centroid position GA1 of the first region RA1 and the centroid position GA2 of the second region RA2.

[0229] [Shape of the active region and center of gravity] In each of the above embodiments, the shape of the active region 29 can be arbitrarily changed. The active region 29 can be changed as shown in (A) to (C) below. The centroid positions of these active regions 29 (A) to (C) will also be explained.

[0230] (A) As shown in Figures 30A and 30B, the shape of the active region 29 is concave. Figure 30A shows the case where the first wire 41 is connected to the source pad 21 at one point. As shown in Figure 30A, the active region 29 is divided into a rectangular first region RD1 that fills the recess 29x and a second region RD2 that corresponds to the rectangular recess 29x. Next, the centroid position GD1 of the first region RD1 and the centroid position GD2 of the second region RD2 are determined. As shown in Figure 30A, since the first region RD1 and the second region RD2 are both rectangular, the centroid position GD1 of the first region RD1 is the intersection of the diagonals of the first region RD1, and the centroid position GD2 of the second region RD2 is the intersection of the diagonals of the second region RD2. Next, the area SD1 of the first region RD1 and the area SD2 of the second region RD2 are determined. Next, the centroid position GD of the active region 29 is determined based on the relationship between the distance DD1 between centroid position GD1 and centroid position GD of the active region 29, the distance DD2 between centroid position GD2 and centroid position GD of the active region 29, and the area SD1 of the first region RD1 and the area SD2 of the second region RD2, along the line segment LD connecting centroid position GD1 and centroid position GD2. More specifically, the ratio of distance DD2 to distance DD1 (DD2 / DD1) is equal to the inverse ratio of the ratio of area SD2 of the second region RD2 to area SD1 of the first region RD1 (SD1 / SD2) (DD2 / DD1 = SD1 / SD2). Thus, by determining at least one of the distances DD1 and DD2, the centroid position GD of the active region 29 can be determined. Also, as shown in Figure 30A, the source pad 21 is provided so as to cover the centroid position GD of the active region 29.

[0231] The dashed-dotted region RX shown in Figure 30A represents the tool head (hereinafter referred to as wedge RX) for ultrasonic bonding the first wire 41 to the source pad 21 in a wedge bonding apparatus (not shown). The wedge bonding apparatus moves the wedge RX so that it is positioned on the centroid GD of the active region 29. The end of the first wire 41 passed through the wedge RX is connected so as to overlap with the centroid GD of the active region 29. That is, the contact region of the first wire 41 with the source pad 21 includes the centroid GD of the active region 29. In Figure 30A, the center of the contact region of the first wire 41 with the source pad 21 (wedge RX) coincides with the centroid GD of the active region 29. In this modified example, the contact area (wedge RX) of the first wire 41 with the source pad 21 only needs to include the center of gravity GD of the active area 29, and the center position of the contact area (wedge RX) of the first wire 41 with the source pad 21 may be different from the center of gravity GD of the active area 29.

[0232] Figure 31A shows an example of a semiconductor device 1 using the active region 29 and the contact region (wedge RX) of the first wire 41 to the source pad 21 as shown in Figure 30A. As shown in Figure 31A, compared to the active region 29 in Figure 30A, a part of the active region 29 is cut out to form the gate pad 22, but the center position of the contact region (wedge RX) of the first wire 41 to the source pad 21 remains the same as the centroid position GD of the active region 29. Also, as shown in Figure 31A, the recess 29x of the active region 29 is formed to be recessed in the lateral direction X. The control circuit region 29LG is formed across the cutout 29w and the recess 29x of the active region 29 where the gate pad 22 is formed. The temperature sensor 27 is provided at the center of the recess 29x in the vertical direction Y and adjacent to the bottom surface 29xa of the recess 29x in the lateral direction X. As shown in Figure 31A, the temperature sensor 27 is positioned in a location that does not overlap with the first wire 41 in a plan view, that is, in a location closer to the gate pad 22 in the lateral direction X than the first wire 41.

[0233] Figure 30B shows the case where the first wire 41 is connected to the source pad 21 at two points. As shown in Figure 30B, the active region 29 is divided into two regions (first region RE1 and second region RE2) of equal area. As shown in Figure 30B, the first region RE1 and the second region RE2 are formed in an approximately L-shape. Next, the centroid position GE1 of the first region RE1 and the centroid position GE2 of the second region RE2 are determined. The first region RE1 is divided into two rectangular regions, the first divided region RE11 and the second divided region RE12. Then, the centroid position GE11 of the first divided region RE11 and the centroid position GE12 of the second divided region RE12 are determined. Since the first divided region RE11 is rectangular, the intersection of the diagonals of the first divided region RE11 is the centroid position GE11 of the first divided region RE11. Since the second divided region RE12 is rectangular, the intersection of the diagonals of the second divided region RE12 is the second centroid position GE12 of the divided region RE12. Next, the area SE1 of the first divided region RE11 and the area SE2 of the second divided region RE12 are determined. Then, in the line segment LE1 connecting the centroid positions GE11 and GE12, the centroid position GE1 of the first region RE1 is determined based on the relationship between the distance DE1 between centroid positions GE11 and GE1, the distance DE2 between centroid positions GE12 and GE1, and the areas SE1 of the first divided region RE11 and SE2 of the second divided region RE12. More specifically, the ratio of distance DE2 to distance DE1 (DE2 / DE1) is equal to the inverse ratio of the ratio of the area SE2 of the second divided region RE12 to the area SE1 of the first divided region RE11 (SE1) (SE1 / SE2) (DE2 / DE1 = SE1 / SE2). This allows us to determine the centroid position GE1 of the first region RE1 by finding at least one of the distances DE1 and DE2. Similarly, for the second region RE2, we determine the centroid position GE2 based on the area SE21 of the first region RE21 and the area SE22 of the second region RE22, using the line segment LE2 connecting the centroid position GE21 of the first divided region RE21 and the centroid position GE22 of the second divided region RE22.Furthermore, as shown in Figure 30B, the source pad 21 is provided so as to cover the respective centroid positions GE1 and GE2 of the divided active regions 29 (the centroid position GE1 of the first region RE1 and the centroid position GE2 of the second region RE2).

[0234] The two dashed-dotted regions RY shown in Figure 30B represent the tool head (hereinafter referred to as wedge RY) for ultrasonic bonding the first wire 41 to the source pad 21 in a wedge bonding apparatus (not shown). The wedge bonding apparatus moves the wedge RY so that it is positioned on the centroid position GE1 of the first region RE1 of the active region 29, thereby connecting the end of the first wire 41 to the source pad 21. As a result, the end of the first wire 41 passed through the wedge RY is connected so as to coincide with the centroid position GB1 of the first region RB1. That is, the first connection portion 41b of the first wire 41 to the source pad 21 includes the centroid position GE1 of the first region RE1. In Figure 30B, the center position of the first connection portion 41b coincides with the centroid position GE1 of the first region RE1. Next, the wedge bonding apparatus moves the wedge RY away from the source pad 21, causing the first wire 41 to move away from the source pad 21. The wedge bonding apparatus then moves the wedge RY so that it is positioned on the centroid GB2 of the second region RB2 of the active region 29, and connects the first wire 41 to the source pad 21. As a result, the first wire 41 passed through the wedge RY is connected so that it overlaps with the centroid GE2 of the second region RE2. That is, the second connection portion 41c of the first wire 41 to the source pad 21 includes the centroid GE2 of the second region RE2. In Figure 30B, the center position of the second connection portion 41c coincides with the centroid GE2 of the second region RE2. In this modified example, the first connection portion 41b only needs to include the centroid GE1 of the first region RE1, and the center position of the first connection portion 41b may be at a different position from the centroid GE1 of the first region RE1. Furthermore, the second connecting portion 41c only needs to include the centroid position GE2 of the second region RE2, and the center position of the second connecting portion 41c may be different from the centroid position GE2 of the second region RE2.

[0235] FIG. 31B shows an example of the semiconductor device 1 using the contact region (wedge RX) to the active region 29 and the source pad 21 of the first wire 41 in FIG. 30B. The shape of the active region 29, the shape of the control circuit region 29LG, and the position of the temperature sensor 27 are the same as those in FIG. 31A. As shown in FIG. 31B, the temperature sensor 27 is provided at a position that does not overlap the first wire 41 in a plan view, that is, at a position on the gate pad 22 side in the lateral direction X with respect to the first wire 41.

[0236] Also, the position of the temperature sensor 27 is not limited to the positions shown in FIGS. 31A and 31B and can be arbitrarily changed. In one example, as shown in FIG. 31C, the temperature sensor 27 may be provided so as to approach the region where the temperature is the highest in the active region 29 during the driving of the semiconductor element 20. More specifically, the active region 29 shown in FIG. 31C has a second recess 29v that is recessed in the lateral direction X from the central portion in the longitudinal direction Y of the bottom surface 29xa of the recess 29x. The control circuit region 29LG has a convex portion 29u that enters the second recess 29v. The temperature sensor 27 is provided at the tip of the convex portion 29u. As shown in FIG. 31C, the temperature sensor 27 is provided at a position that does not overlap the first wire 41 in a plan view, that is, at a position on the gate pad 22 side in the lateral direction X with respect to the first wire 41.

[0237] (B) As shown in FIGS. 32A and 32B, the shape of the active region 29 is convex. In FIG. 32A, a case where the first wire 41 is connected to the source pad 21 at one location is shown. As shown in FIG. 32A, the active region 29 is divided into a rectangular first region RF1 excluding the convex portion 29y and a second region RF2 corresponding to the rectangular convex portion 29y. Next, the centroid position GF1 of the first region RF1 and the centroid position GF2 of the second region RF2 are obtained. As shown in FIG. 32A, since the first region RF1 and the second region RF2 are each rectangular, the centroid position GF1 of the first region RF1 is the intersection of the diagonals of the first region RF1, and the centroid position GF2 of the second region RF2 is the intersection of the diagonals of the second region RF2. Next, the area SF1 of the first region RF1 and the area SF2 of the second region RF2 are obtained respectively. Next, on the line segment LF connecting the centroid position GF1 and the centroid position GF2, based on the relationship between the distance DF1 between the centroid position GF1 and the centroid position GF of the active region 29, the distance DF2 between the centroid position GF2 and the centroid position GF of the active region 29, the area SF1 of the first region RF1, and the area SF2 of the second region RF2, the centroid position GF of the active region 29 is obtained. More specifically, the ratio of the distance DF2 to the distance DF1 (DF2 / DF1) is equal to the inverse ratio of the ratio of the area SF2 of the second region RF2 to the area SF1 of the first region RF1 (SF1 / SF2) (DF2 / DF1 = SF1 / SF2). Thereby, by obtaining at least one of the distances DF1 and DF2, the centroid position GF of the active region 29 is obtained. Also, as shown in FIG. 32A, the source pad 21 is provided so as to cover the centroid position GF of the active region 29.

[0238] The region RX shown by the dashed line in Figure 32A represents the tool head (hereinafter referred to as wedge RX) for ultrasonic bonding the first wire 41 to the source pad 21 in a wedge bonding apparatus (not shown). The wedge bonding apparatus moves the wedge RX so that it is positioned on the centroid position GF of the active region 29. The end of the first wire 41 passed through the wedge RX is connected so as to overlap with the centroid position GF of the active region 29. That is, the contact area of ​​the first wire 41 with the source pad 21 includes the centroid position GF of the active region 29. In Figure 32A, the center position of the contact area of ​​the first wire 41 with the source pad 21 (wedge RX) coincides with the centroid position GF of the active region 29. In this modified example, the contact area (wedge RX) of the first wire 41 with the source pad 21 only needs to include the center of gravity GF of the active area 29, and the center position of the contact area (wedge RX) of the first wire 41 with the source pad 21 may be different from the center of gravity GF of the active area 29.

[0239] Figure 33A shows an example of a semiconductor device 1 using the active region 29 and the contact region (wedge RX) of the first wire 41 to the source pad 21 as shown in Figure 32A. In Figure 33A, the semiconductor element 20 is provided such that the protrusion 29y of the active region 29 faces the second lead frame 12 and the third lead frame 13 in the vertical direction Y. As shown in Figure 33A, compared to the active region 29 in Figure 32A, a part of the active region 29 is cut out to accommodate the temperature sensor 27, but the center position of the contact region (wedge RX) of the first wire 41 to the source pad 21 remains the same as the centroid position GD of the active region 29. Also, as shown in Figure 33A, the region adjacent to the protrusion 29y in the active region 29 on the opposite side from the gate pad 22 has a recess 29t formed to be recessed in the vertical direction Y. The control circuit region 29LG is aligned with the active region 29 in the vertical direction Y and is formed to surround the protrusion 29y of the active region 29 from the horizontal direction X and the vertical direction Y. The control circuit region 29LG has a protrusion 29s that fits into the recess 29t of the active region 29. The temperature sensor 27 is provided at the tip of the protrusion 29s. As shown in Figure 33A, the temperature sensor 27 is positioned so as not to overlap with the first wire 41 in a plan view, that is, on the opposite side of the gate pad 22 in the lateral direction X from the first wire 41.

[0240] Figure 32B shows the case where the first wire 41 is connected to the source pad 21 at two points. As shown in Figure 32B, the active region 29 is divided into two regions (first region RG1 and second region RG2) of equal area. As shown in Figure 32B, the first region RG1 and the second region RG2 are formed in an approximately L shape. Next, the centroid position GG1 of the first region RG1 and the centroid position GG2 of the second region RG2 are determined. The first region RG1 is divided into two rectangular regions, the first divided region RG11 and the second divided region RG12. Then, the centroid position GG11 of the first divided region RG11 and the centroid position GG12 of the second divided region RG12 are determined. Since the first divided region RG11 is rectangular, the intersection of the diagonals of the first divided region RG11 is the centroid position GG11 of the first divided region RG11. Since the second divided region RG12 is rectangular, the intersection of the diagonals of the second divided region RG12 is the second centroid position GG12 of the divided region RG12. Next, the area SG1 of the first divided region RG11 and the area SG2 of the second divided region RG12 are determined. Then, in the line segment LG1 connecting the centroid positions GG11 and GG12, the centroid position GG1 of the first region RG1 is determined based on the relationship between the distance DG1 between the centroid positions GG11 and GG1, the distance DG2 between the centroid positions GG12 and GG1, and the areas SG1 of the first divided region RG11 and SG2 of the second divided region RG12. More specifically, the ratio of distance DG2 to distance DG1 (DG2 / DG1) is equal to the inverse ratio of the ratio of the area SG2 of the second divided region RG12 to the area SG1 of the first divided region RG11 (SG1 / SG2) (DG2 / DG1 = SG1 / SG2). By determining at least one of the distances DG1 and DG2, the centroid position GG1 of the first divided region RG1 can be determined. Similarly, for the second divided region RG2, the centroid position GG2 is determined based on the area SG21 of the first divided region RG21 and the area SG22 of the second divided region RG22, using the line segment LG2 connecting the centroid position GG21 of the first divided region RG21 and the centroid position GG22 of the second divided region RG22.Furthermore, as shown in Figure 32B, the source pad 21 is provided so as to cover the respective centroid positions GG1 and GG2 of the divided active region 29 (the centroid position GG1 of the first region RG1 and the centroid position GG2 of the second region RG2).

[0241] The two dashed-line regions RY shown in Figure 32B represent the tool head (hereinafter referred to as wedge RY) for ultrasonically connecting the first wire 41 to the source pad 21 in a wedge bonding apparatus (not shown). The wedge bonding apparatus connects the end of the first wire 41 to the source pad 21 by moving the wedge RY so that it is positioned on the centroid position GG1 of the first region RG1 of the active region 29. As a result, the end of the first wire 41 passed through the wedge RY is connected so that it overlaps with the centroid position GG1 of the first region RG1. That is, the first connection portion 41b of the first wire 41 to the source pad 21 includes the centroid position GG1 of the first region RG1. In Figure 32B, the center position of the first connection portion 41b coincides with the centroid position GG1 of the first region RG1. Next, the wedge bonding apparatus moves the wedge RY away from the source pad 21 so that the first wire 41 moves away from the source pad 21. The wedge bonding apparatus then moves the wedge RY so that it is positioned on the centroid GG2 of the second region RG2 of the active region 29, and connects the first wire 41 to the source pad 21. As a result, the first wire 41 passed through the wedge RY is connected so that it overlaps with the centroid GG2 of the second region RG2. That is, the second connection portion 41c of the first wire 41 to the source pad 21 includes the centroid GG2 of the second region RG2. In Figure 32B, the center position of the second connection portion 41c coincides with the centroid GG2 of the second region RG2. In this modified example, the first connection portion 41b only needs to include the centroid GG1 of the first region RG1, and the center position of the first connection portion 41b may be at a different position from the centroid GG1 of the first region RG1. Furthermore, the second connecting portion 41c only needs to include the centroid position GG2 of the second region RG2, and the center position of the second connecting portion 41c may be different from the centroid position GG2 of the second region RG2.

[0242] Figure 33B shows an example of a semiconductor device 1 using the active region 29 and the contact region (wedge RX) of the first wire 41 to the source pad 21 as shown in Figure 32B. In Figure 33B, the convex portion 29y of the active region 29 extends in the lateral direction X, and the semiconductor element 20 is provided such that the convex portion 29y faces the second lead frame 12 side in the lateral direction X. As shown in Figure 33B, compared to the active region 29 in Figure 32B, a part of the active region 29 is cut out to accommodate the temperature sensor 27, but the center position of the contact region (wedge RX) of the first wire 41 to the source pad 21 remains the same as the centroid position GD of the active region 29. Also, as shown in Figure 33B, the region adjacent to the convex portion 29y on the opposite side from the gate pad 22 has a recess 29r formed to be recessed in the vertical direction Y. The recess 29r is formed to be recessed diagonally toward the third lead frame 13. The control circuit region 29LG is aligned with the active region 29 in the lateral direction X, and is formed to surround the protrusion 29y of the active region 29 from both the lateral direction X and the vertical direction Y. The gate pad 22 is located on the second lead frame 12 side of the protrusion 29y of the active region 29 in the vertical direction Y, and is formed between the control circuit region 29LG and the active region 29 in the lateral direction X. The control circuit region 29LG has a protrusion 29q that fits into the recess 29r of the active region 29. The temperature sensor 27 is provided at the tip of the protrusion 29q. As shown in Figure 33B, the temperature sensor 27 is located in a position that does not overlap with the first wire 41 in a plan view, that is, in the lateral direction X, between the first wire 41 and the gate pad 22.

[0243] (C) As shown in Figures 34A and 34B, the shape of the active region 29 is a combination of multiple rectangular shapes. Figure 34A shows the case where the first wire 41 is connected to the source pad 21 at one point. As shown in Figure 34A, the active region 29 is divided into a rectangular first region RH1 and a convex second region RH2. Next, the centroid position GH1 of the first region RH1 and the centroid position GH2 of the second region RH2 are determined. As shown in Figure 34A, since the first region RH1 is rectangular, the centroid position GH1 of the first region RH1 is the intersection of the diagonals of the first region RH1. Since the second region RH2 is convex, similar to the active region 29 in Figure 33A, the second region RH2 is divided into two rectangular regions, the first divided region RH21 and the second divided region RH22. Then, the centroid position GH21 of the first divided region RH21 and the centroid position GH22 of the second divided region RH22 are determined. Since the first divided region RH21 is rectangular, the intersection of its diagonals is the centroid GH21 of the first divided region RH21. Since the second divided region RH22 is rectangular, the intersection of its diagonals is the second centroid GH22 of the second divided region RH22. Next, the area SH21 of the first divided region RH21 and the area SH22 of the second divided region RH22 are determined. Then, using the line segment LH1 connecting the centroid GH21 and centroid GH2, the centroid GH2 of the second region RH2 is determined based on the relationship between the distance DH21 between centroid GH21 and centroid GH2, the distance DH22 between centroid GH22 and centroid GH2, and the area SH21 of the first divided region RH21 and the area SH22 of the second divided region RH22. More specifically, the ratio of distance DH22 to distance DH21 (DH22 / DH21) is equal to the inverse ratio of the ratio of the area SH22 of the second divided region RH22 to the area SH21 of the first divided region RH21 (SH21 / SH22) (DH22 / DH21 = SH21 / SH22). By determining at least one of the distances DH21 and DH22, the centroid position GH2 of the second divided region RH2 can be determined.

[0244] Next, the centroid GH of the active region 29 is determined based on the relationship between the distance DH1 between the centroid GH1 of the first region RH1 and the centroid GH of the second region RH2, the distance DH2 between the centroid GH1 and the centroid GH of the active region 29, and the area SH1 of the first region RH1 and the area SH2 of the second region RH2, along with the area SH2 of the second region RH2. More specifically, the ratio of distance DH2 to distance DH1 (DH1 / DH2) is equal to the inverse ratio of the ratio of the area SH2 of the second region RH2 to the area SH1 of the first region RH1 (SH1 / SH2) (DH2 / DH1 = SH1 / SH2). Thus, by determining at least one of the distances DH1 and DH2, the centroid GH of the active region 29 is determined.

[0245] The region RX shown by the dashed line in Figure 34A represents the tool head (hereinafter referred to as wedge RX) for ultrasonic bonding the first wire 41 to the source pad 21 in a wedge bonding apparatus (not shown). The wedge bonding apparatus moves the wedge RX so that it is positioned on the centroid GD of the active region 29. The end of the first wire 41 passed through the wedge RX is connected so as to overlap with the centroid GH of the active region 29. That is, the contact region of the first wire 41 with the source pad 21 includes the centroid GH of the active region 29. In Figure 34A, the center of the contact region of the first wire 41 with the source pad 21 (wedge RX) coincides with the centroid GH of the active region 29. In this modified example, the contact area (wedge RX) of the first wire 41 with the source pad 21 only needs to include the center of gravity GH of the active area 29, and the center position of the contact area (wedge RX) of the first wire 41 with the source pad 21 may be different from the center of gravity GH of the active area 29.

[0246] Figure 35A shows an example of a semiconductor device 1 using the active region 29 and the contact region (wedge RX) of the first wire 41 to the source pad 21 as shown in Figure 34A. In Figure 35A, the first region RH1 and the second region RH2 in the active region 29 are arranged in the lateral direction X, and the semiconductor element 20 is provided such that the second divided region RH22 of the second region RH2 is on the second lead frame 12 side. As shown in Figure 35A, the gate pad 22 is formed adjacent to the second divided region RH22 on the opposite side from the first region RH1 with respect to the second divided region RH22. The control circuit region 29LG is arranged in the vertical direction Y, alongside the active region 29, and has a protrusion 29p that fits between the second divided region RH22 and the first region RH1 of the active region 29 in the lateral direction X. The temperature sensor 27 is provided at the tip of the protrusion 29p. As shown in Figure 35A, the temperature sensor 27 is positioned in a location that does not overlap with the first wire 41 in a plan view, that is, in a location that is closer to the second lead frame 12 in the vertical Y direction than the first wire 41.

[0247] Figure 34B shows the case where the first wire 41 is connected to the source pad 21 at two points. As shown in Figure 34B, the active region 29 is divided into two regions (first region RJ1 and second region RJ2) of equal area. As shown in Figure 34B, the first region RJ1 is formed in an approximately L-shape, and the second region RJ2 is formed in a convex shape. Next, the centroid position GJ1 of the first region RJ1 and the centroid position GJ2 of the second region RJ2 are determined. The first region RJ1 is divided into two rectangular regions, the first divided region RJ11 and the second divided region RJ12. Then, the centroid position GJ11 of the first divided region RJ11 and the centroid position GJ12 of the second divided region RJ12 are determined. Since the first divided region RJ11 is rectangular, the intersection of the diagonals of the first divided region RJ11 is the centroid position GJ11 of the first divided region RJ11. Since the second divided region RJ12 is rectangular, the intersection of the diagonals of the second divided region RJ12 is the centroid GJ12 of the divided region RJ12. Next, the area SJ11 of the first divided region RJ11 and the area SJ12 of the second divided region RJ12 are calculated. Then, in the line segment LJ1 connecting the centroid GJ11 and the centroid GJ12, ​​the centroid GJ1 of the first region RJ1 is determined based on the relationship between the distance DJ11 between the centroid GJ11 and the centroid GJ1, the distance DJ12 between the centroid GJ12 and the centroid GJ1, and the areas SJ11 of the first divided region RJ11 and the area SJ12 of the second divided region RJ12. More specifically, the ratio of distance DJ12 to distance DJ11 (DJ12 / DJ11) is equal to the inverse ratio of the ratio of the area SJ12 of the second divided region RJ12 to the area SJ11 of the first divided region RJ11 (SJ11 / SJ12) (DJ12 / DJ11 = SJ11 / SJ12). By determining at least one of the distances DJ11 and DJ12, the centroid position GJ1 of the first region RJ1 can be found.

[0248] Next, the second region RJ2 is divided into two rectangular regions: the first divided region RJ21 and the second divided region RJ22. Then, the centroid position GJ21 of the first divided region RJ21 and the centroid position GJ22 of the second divided region RJ22 are determined. Since the first divided region RJ21 is rectangular, the intersection of its diagonals is the centroid position GJ21. Since the second divided region RJ22 is rectangular, the intersection of its diagonals is the second centroid position GJ22. Next, the area SJ21 of the first divided region RJ21 and the area SJ22 of the second divided region RJ22 are determined. Next, in the line segment LJ2 connecting centroid positions GJ21 and GJ22, the centroid position GJ2 of the second region RJ2 is determined based on the relationship between the distance DJ21 between centroid positions GJ21 and GJ2, the distance DJ22 between centroid positions GJ22 and GJ2, and the area SJ21 of the first divided region RJ21 and the area SJ22 of the second divided region RJ22. More specifically, the ratio of distance DJ22 to distance DJ21 (DJ22 / DJ21) is equal to the inverse ratio of the ratio of the area SJ22 of the second divided region RJ22 to the area SJ21 of the first divided region RJ21 (SJ21 / SJ22) (DJ22 / DJ21 = SJ21 / SJ22). This allows us to determine the centroid position GJ2 of the second region RJ2 by ​​finding at least one of the distances DJ21 and DJ22.

[0249] The two dashed-dotted regions RY shown in Figure 34B represent the tool head (hereinafter referred to as wedge RY) for ultrasonically connecting the first wire 41 to the source pad 21 in a wedge bonding apparatus (not shown). The wedge bonding apparatus moves the wedge RY so that it is positioned on the centroid GJ1 of the first region RJ1 of the active region 29, thereby connecting the end of the first wire 41 to the source pad 21. As a result, the end of the first wire 41 passed through the wedge RY is connected so as to coincide with the centroid GJ1 of the first region RJ1. That is, the first connection portion 41b of the first wire 41 to the source pad 21 includes the centroid GJ1 of the first region RJ1. In Figure 34B, the center position of the first connection portion 41b coincides with the centroid GJ1 of the first region RJ1. Next, the wedge bonding apparatus moves the wedge RY away from the source pad 21, causing the first wire 41 to move away from the source pad 21. The wedge bonding apparatus then moves the wedge RY so that it is positioned on the centroid GJ2 of the second region RJ2 in the active region 29, and connects the first wire 41 to the source pad 21. As a result, the first wire 41 passed through the wedge RY is connected so that it overlaps with the centroid GJ2 of the second region RJ2. That is, the second connection portion 41c of the first wire 41 to the source pad 21 includes the centroid GJ2 of the second region RJ2. In Figure 34B, the center position of the second connection portion 41c coincides with the centroid GJ2 of the second region RJ2. In this modified example, the first connection portion 41b only needs to include the centroid GJ1 of the first region RJ1, and the center position of the first connection portion 41b may be at a different position from the centroid GJ1 of the first region RJ1. Furthermore, the second connecting portion 41c only needs to include the centroid position GJ2 of the second region RJ2, and the center position of the second connecting portion 41c may be different from the centroid position GJ2 of the second region RJ2.

[0250] Figure 35B shows an example of a semiconductor device 1 using the active region 29 and the contact region (wedge RX) of the first wire 41 with the source pad 21 as shown in Figure 34B. The shapes of the active region 29 and the control circuit region 29LG, as well as the position of the temperature sensor 27 in Figure 35B, are the same as in Figure 35A. As shown in Figure 35B, the temperature sensor 27 is positioned so as not to overlap with the first wire 41 in a plan view, that is, it is positioned on the second lead frame 12 side in the vertical Y direction relative to the first wire 41.

[0251] [Multiple first wires] In the second embodiment described above, there was one first wire 41, but the number of first wires 41 is not limited to this. For example, as shown in Figure 36, the semiconductor element 20 and the third lead frame 13 may be connected by two first wires 41A and 41B. In this case, as shown in Figure 37, when the active region 29 is divided into a first region RB1 and a second region RB2 of equal area, similar to the second embodiment, the first region RB1 and the second region RB2 are arranged in the vertical direction Y, and the semiconductor element 20 is provided such that the second region RB2 is on the third lead frame 13 side. The gate pad 22 is formed so as to be adjacent in the horizontal direction X to the end of the second region RB2 on the third lead frame 13 side in the vertical direction Y. The gate pad 22 is formed on the second lead frame 12 side of the second region RB2. The position of the temperature sensor 27 relative to the active region 29 is the same as in the second embodiment.

[0252] Furthermore, in Figure 37, the active region 29 is divided into a first region RB1 and a second region RB2 of equal area, similar to the second embodiment described above, and the centroid position GB1 of the first region RB1 and the centroid position GB2 of the second region RB2 are determined. As shown in Figure 37, the first wire 41A is connected to the region of the source pad 21 corresponding to the centroid position GB1 of the first region RB1, and the first wire 41B is connected to the region of the source pad 21 corresponding to the centroid position GB2 of the second region RB2. As shown in Figure 36, the temperature sensor 27 is positioned so as not to overlap with the two first wires 41A and 41B in a plan view. That is, the temperature sensor 27 is located on the second lead frame 12 side in the lateral direction X than the first wire 41A, and on the opposite side of the gate pad 22 side in the vertical direction Y than the first wire 41B.

[0253] [Example of the first connecting member] In each of the above embodiments, a first wire 41 is used as the first connecting member, but the invention is not limited to this. Instead of the first wire 41, a connecting plate (hereinafter referred to as "clip 45") as shown in Figure 38 may be used as the first connecting member. The clip 45 has an element connection portion 46 that is connected to the semiconductor element 20, a lead connection portion 47 that is connected to the third island portion 13a of the third lead frame 13, and a connecting portion 48 that connects the element connection portion 46 and the lead connection portion 47.

[0254] The element connection portion 46 is connected to the source pad 21 of the semiconductor element 20, for example, by solder. The element connection portion 46 is formed in a strip shape in a plan view. A first projection 46a and a second projection 46b are formed on the element connection portion 46. The first projection 46a and the second projection 46b are positioned closer to the source pad 21 than other parts of the element connection portion 46. The first projection 46a is positioned within a wedge RY that includes the centroid position GB1 of the first region RB1, and the second projection 46b is positioned within a wedge RY that includes the centroid position GB2 of the second region RB2.

[0255] The lead connection portion 47 is formed in a rectangular flat plate shape. The lead connection portion 47 is connected to the third island portion 13a of the third lead frame 13 by solder. The connecting portion 48 extends along the vertical direction Y. In FIG. 38, the size of the connecting portion 48 in the lateral direction X is formed to increase as it goes from the lead connection portion 47 toward the element connection portion 46 in the vertical direction Y. The connecting portion 48 is bent from each of the element connection portion 46 and the lead connection portion 47, and is disposed at a position spaced apart from the semiconductor element 20 more than the element connection portion 46 and the lead connection portion 47 in the thickness direction Z.

[0256] As the material of the clip 45, for example, copper (Cu), aluminum (Al), copper alloy, aluminum alloy, etc. can be used. Substantially the entire surface of the clip 45 is covered by a plating layer. As the material of the plating layer, for example, silver (Ag), nickel (Ni), tin (Sn), alloys containing them, etc. can be used. Note that a plurality of plating layers can also be used. Also, the shape of the clip 45 is not limited to the shape of the clip 45 shown in FIG. 38, and can be arbitrarily changed.

[0257] 〔Structure of MISFET〕 ·In each of the above embodiments, the structure of the MISFET 23a can be arbitrarily changed. In one example, the structure of the MISFET 23a shown in FIG. 39 may be used. The MISFET 23a in FIG. 39 has different gate electrode structures and source pad 21 structures compared to the MISFET 23a in each of the above embodiments.

[0258] As shown in Figure 39, only the gate electrode 260 is embedded in the trench 66. That is, the MISFET 23a in Figure 39 has a structure in which the embedded electrode 69 is omitted from the MISFET 23a of each of the above embodiments. Accordingly, the recess 68a is not formed in the gate electrode 260. The depth of the trench 66 can also be arbitrarily changed. For example, the trench 66 of the MISFET 23a shown in Figure 39 may be formed to be shallower than the trench 66 of the MISFET 23a of each of the above embodiments. Also, as shown in Figure 39, the thickness of the body contact region 73 may be thicker than the thickness of the source region 70.

[0259] As shown in Figure 39, the source pad 270 consists of multiple layered structures. More specifically, the source pad 270 is composed of a first protective layer 271 covering the epitaxial layer 62 and the interlayer insulating film 74, a first electrode layer 272 covering the first protective layer 271, a second protective layer 273 covering the first electrode layer 272, and a second electrode layer 274 covering the second protective layer 273. A connecting layer 275 for connecting the first wire 41 is formed on the second electrode layer 274. The connecting layer 275 is formed by nickel-palladium (NiPd) alloy plating.

[0260] The first protective layer 271 and the second protective layer 273 are made of, for example, titanium nitride (TiN). The thickness of the first protective layer 271 and the second protective layer 273 is thinner than the thickness of the first electrode layer 272 and the second electrode layer 274. The first electrode layer 272 and the second electrode layer 274 are made of, for example, aluminum or an aluminum alloy. In one example, the first electrode layer 272 is made of AlSiCu, and the second electrode layer 274 is made of AlCu. The first electrode layer 272 and the second electrode layer 274 may also be made of copper. Furthermore, the Vickers hardness of the first protective layer 271 and the second protective layer 273 is greater than the Vickers hardness of the first electrode layer 272 and the second electrode layer 274. As a result, the first protective layer 271 and the second protective layer 273 are less prone to deformation than the first electrode layer 272 and the second electrode layer 274.

[0261] With this configuration of the source pad 270, the stress on the gate insulating film 67 due to the force and vibration applied to the source pad 270 when the first wire 41 is connected to the source pad 270 by wedge bonding, for example, can be reduced. Therefore, the occurrence of cracks in the gate insulating film 67 can be suppressed.

[0262] Furthermore, the thickness Tsp of the source pad 270 is 16,000 Å or more, and preferably 20,000 Å or more. Figure 40 is a graph showing the relationship between the thickness Tsp of the source pad 270 and the stress (maximum principal stress) on the gate insulating film 67 when the first wire 41 is connected to the source pad 270. As can be seen from the graph in Figure 40, the stress on the gate insulating film 67 decreases as the thickness Tsp of the source pad 270 increases. In particular, when the thickness Tsp is less than 20,000 Å, the degree of increase in the stress on the gate insulating film 67 is large as the thickness Tsp decreases. On the other hand, when the thickness Tsp is greater than 20,000 Å, the degree of increase in the stress on the gate insulating film 67 is small even when the thickness Tsp decreases.

[0263] Figure 41 is a graph showing the relationship between the thickness Tsp of the source pad 270 and the TDDB failure time. Here, the TDDB failure time is the time it takes for the cumulative failure rate to reach 0.1% by a TDDB (Time Dependent Dielectric Breakdown) test.

[0264] As can be seen from Figure 41, when the thickness Tsp of the source pad 270 is 8000 Å or more and less than 16000 Å, the stress on the gate insulating film 67 increases when the first wire 41 is connected to the source pad 270, causing damage to the gate insulating film 67 and resulting in the failure of the semiconductor element 20 in a short time. On the other hand, when the thickness Tsp of the source pad 21 is 16000 Å or more, particularly in the range of thickness Tsp between 16000 Å and 20000 Å, the TDDB failure time increases sharply as the thickness Tsp increases. In other words, as the thickness Tsp increases in the range of 16000 Å or more and 20000 Å or less, the semiconductor element 20 becomes less prone to failure. Thus, by having a source pad 270 thickness Tsp of 16000 Å or more, and especially 20000 Å or more, the semiconductor element 20 becomes less prone to failure.

[0265] [Sealing resin] In each of the above embodiments, an ion trap material containing aluminum (Al) and magnesium (Mg) may be added to the sealing resin 30. With this configuration, chloride ions (Cl) in the sealing resin 30 - By trapping chloride ions with the first wire 41, the ion trap material can capture these ions, thereby suppressing the binding of chloride ions to the first wire 41 and causing pitting corrosion.

[0266] [Lead frame] In each of the above embodiments, the locations on the lead frame 10 where the plating layer 14 is formed can be arbitrarily changed. For example, the plating layer 14 may be formed partially on the lead frame 10. In one example, the plating layer 14 is formed on the first island portion 11a of the first lead frame 11, the second island portion 12a of the second lead frame 12, and the third island portion 13a of the third lead frame 13. The plating layer 14 is not formed on at least one of the first terminal portion 11b of the first lead frame 11, the second terminal portion 12b of the second lead frame 12, and the third terminal portion 13b of the third lead frame 13.

[0267] [Functional element formation region] In the first to third embodiments described above, the ratio of the channel-forming region 72 area per unit area is not limited to 50% but can be changed as desired. For example, the ratio of the channel-forming region 72 area per unit area may be 25% or 75%. The ratio of the channel-forming region 72 area per unit area is set based on the balance between the active clamp withstand capacity Eac and the on-resistance. Preferably, the ratio of the channel-forming region 72 area per unit area is, for example, 20% or more and 80% or less.

[0268] In the fourth embodiment described above, a second functional element formation region unit U2 that generates a large amount of heat may be placed in the region adjacent to the temperature sensor 27 in the active region 29. This allows the temperature to be adjusted so that the area near the temperature sensor 27 is the highest in the active region 29.

[0269] In the fourth embodiment described above, the plurality of functional element formation regions 231 are composed of first to third functional element formation regions 232 to 234, but the types of the plurality of functional element formation regions 231 are not limited thereto. The number of types of functional element formation regions 231 can be arbitrarily changed. For example, the types of functional element formation regions 231 may consist of two types of functional element formation regions, or four or more types of functional element formation regions. Also, in the fourth embodiment described above, the ratio of the area of ​​the channel formation region 72 per unit area was 25%, 50%, and 75%, but it is not limited to these, and may be other values ​​(for example, 30%, 60%, 80%, etc.).

[0270] [Examples of applications for semiconductor device 1] Refer to Figures 42 to 46 to illustrate and explain the circuit to which the semiconductor device 1 is applied. (First application example) As shown in Figure 42, the semiconductor device 1 can be configured as an asynchronous rectifier type switching power supply circuit 280. The switching power supply circuit 280 includes one semiconductor device 1, an inductor 281, and a smoothing capacitor 282. The switching power supply circuit 280 drives the semiconductor device 1 to generate a desired output voltage Vout from an input voltage Vin.

[0271] (Second application example) As shown in Figure 43, the semiconductor device 1 can be configured as a synchronous rectification type switching power supply circuit 290. The switching power supply circuit 290 has an inverter unit 291, an inductor 292, and a smoothing capacitor 293. The inverter unit 291 has an upper switching element 294U and a lower switching element 294L. The source terminal of the upper switching element 294U and the drain terminal of the lower switching element 294L are electrically connected. The gate terminal of the upper switching element 294U and the gate terminal of the lower switching element 294L are connected to a gate drive circuit 295. The switching power supply circuit 290 drives the upper switching element 294U and the lower switching element 294L complementaryly (exclusively) to generate a desired output voltage Vout from the input voltage Vin. The semiconductor device 1 can be applied to at least one of the upper switching element 294U and the lower switching element 294L. For example, when semiconductor device 1 is applied to the lower switching element 294L, the lower switching element 294L in the inverter unit 291 and the gate drive circuit that drives the lower switching element 294L in the gate drive circuit 295 are replaced by semiconductor device 1.

[0272] (Third application example) The semiconductor device 1 can be applied to an H-bridge type converter. Figure 44 shows the circuit configuration of an H-bridge type buck-boost converter circuit (hereinafter simply referred to as "converter circuit 300"), which is an example of an H-bridge type converter.

[0273] The converter circuit 300 comprises a first inverter section 301, a second inverter section 302, an input capacitor 303, an output capacitor 304, an inductor 305, and a gate drive circuit 306, and steps up or down the input voltage Vi to the output voltage Vo.

[0274] The first inverter section 301 includes an upper switching element 301U and a lower switching element 301L. The source terminal of the upper switching element 301U and the drain terminal of the lower switching element 301L are electrically connected. The first inverter section 301 is connected in parallel with the input capacitor 303. More specifically, the drain terminal of the upper switching element 301U is electrically connected to the first terminal of the input capacitor 303, and the source terminal of the lower switching element 301L is electrically connected to the second terminal of the input capacitor 303.

[0275] The second inverter section 302 includes an upper switching element 302U and a lower switching element 302L. The source terminal of the upper switching element 302U and the drain terminal of the lower switching element 302L are electrically connected. The second inverter section 302 is connected in parallel with the output capacitor 304. More specifically, the drain terminal of the upper switching element 302U is electrically connected to the first terminal of the output capacitor 304, and the source terminal of the lower switching element 302L is electrically connected to the second terminal of the output capacitor 304.

[0276] The inductor 305 is connected to the first inverter section 301 and the second inverter section 302. More specifically, the first terminal of the inductor 305 is connected to the connection point between the source terminal of the upper switching element 301U and the drain terminal of the lower switching element 301L in the first inverter section 301. The second terminal of the inductor 305 is connected to the connection point between the source terminal of the upper switching element 302U and the drain terminal of the lower switching element 302L in the second inverter section 302.

[0277] The gate drive circuit 306 is electrically connected to the gate terminals of each switching element 301U, 301L, 302U, and 302L. The gate drive circuit 306 controls the on / off state of each switching element 301U, 301L, 302U, and 302L.

[0278] The semiconductor device 1 can be applied to at least one of the switching elements 301U, 301L, 302U, and 302L. For example, when the semiconductor device 1 is applied to the lower switching element 301L of the first inverter unit 301, the lower switching element 301L of the first inverter unit 301 and the gate drive circuit that drives the lower switching element 301L of the gate drive circuit 306 are replaced by the semiconductor device 1.

[0279] (Fourth application example) The semiconductor device 1 can be applied to the full-bridge inverter circuit shown in Figure 45 (hereinafter simply referred to as "inverter circuit 310"). The inverter circuit 310 comprises a first inverter section 311, a second inverter section 312, an input capacitor 313, and a gate drive circuit 314, and converts the input voltage Vi into the output voltage Vo between the first inverter section 311 and the second inverter section 312.

[0280] The first inverter section 311 includes an upper switching element 311U and a lower switching element 311L. The source terminal of the upper switching element 311U and the drain terminal of the lower switching element 311L are electrically connected. The first inverter section 311 is connected in parallel with the input capacitor 313. More specifically, the drain terminal of the upper switching element 311U is electrically connected to the first terminal of the input capacitor 313, and the source terminal of the lower switching element 311L is electrically connected to the second terminal of the input capacitor 313.

[0281] The second inverter section 312 has an upper switching element 312U and a lower switching element 312L. The source terminal of the upper switching element 312U and the drain terminal of the lower switching element 312L are electrically connected. The second inverter section 312 is connected in parallel with the first inverter section 311. More specifically, the drain terminal of the upper switching element 312U is electrically connected to the drain terminal of the upper switching element 311U, and the source terminal of the lower switching element 312L is electrically connected to the source terminal of the lower switching element 311L. The output voltage Vo is defined by the voltage obtained between the connection point between the source terminal of the upper switching element 311U and the drain terminal of the lower switching element 311L, and the connection point between the source terminal of the upper switching element 312U and the drain terminal of the lower switching element 312L.

[0282] The gate drive circuit 314 is electrically connected to the gate terminals of each switching element 311U, 311L, 312U, and 312L. The gate drive circuit 314 controls the on / off state of each switching element 311U, 311L, 312U, and 312L.

[0283] The semiconductor device 1 can be applied to at least one of the switching elements 311U, 311L, 312U, and 312L. For example, when the semiconductor device 1 is applied to the lower switching element 311L of the first inverter unit 311, the lower switching element 311L of the first inverter unit 311 and the gate drive circuit that drives the lower switching element 311L of the gate drive circuit 314 are replaced by the semiconductor device 1.

[0284] (Fifth application example) The semiconductor device 1 can be applied to the three-phase AC inverter circuit shown in Figure 46 (hereinafter simply referred to as "three-phase inverter circuit 320").

[0285] The three-phase inverter circuit 320 includes a power drive unit 321 electrically connected to the U-phase, V-phase, and W-phase coils of a three-phase AC motor (hereinafter simply referred to as "motor 327"), a gate drive circuit 325 that controls the power drive unit 321, and a converter unit 326 connected to the power supply ES. The converter unit 326 has a positive power terminal EP and a negative power terminal EN.

[0286] The power drive unit 321 controls the power supplied to the U-phase, V-phase, and W-phase coils of the motor 327. The power drive unit 321 includes a U-phase inverter unit 322, a V-phase inverter unit 323, and a W-phase inverter unit 324. The U-phase inverter unit 322, the V-phase inverter unit 323, and the W-phase inverter unit 324 are connected in parallel to each other between the positive power terminal EP and the negative power terminal EN.

[0287] The U-phase inverter section 322 includes an upper switching element 322U and a lower switching element 322L. The drain terminal of the upper switching element 322U is electrically connected to the positive power terminal EP. The source terminal of the upper switching element 322U and the drain terminal of the lower switching element 322L are electrically connected. The source terminal of the lower switching element 322L is connected to the negative power terminal EN. A snubber diode 322A is connected in antiparallel to the upper switching element 322U, and a snubber diode 322B is connected in antiparallel to the lower switching element 322L. More specifically, the anode of the snubber diode 322A is electrically connected to the source terminal of the upper switching element 322U, and the cathode of the snubber diode 322A is electrically connected to the drain terminal of the upper switching element 322U. The anode of the snubber diode 322B is electrically connected to the source terminal of the lower switching element 322L, and the cathode of the snubber diode 322B is electrically connected to the drain terminal of the lower switching element 322L.

[0288] The V-phase inverter section 323 includes an upper switching element 323U and a lower switching element 323L. The drain terminal of the upper switching element 323U is electrically connected to the positive power terminal EP. The source terminal of the upper switching element 323U and the drain terminal of the lower switching element 323L are electrically connected. The source terminal of the lower switching element 323L is connected to the negative power terminal EN. A snubber diode 323A is connected in antiparallel to the upper switching element 323U, and a snubber diode 323B is connected in antiparallel to the lower switching element 323L. More specifically, the anode of the snubber diode 323A is electrically connected to the source terminal of the upper switching element 323U, and the cathode of the snubber diode 323A is electrically connected to the drain terminal of the upper switching element 323U. The anode of the snubber diode 323B is electrically connected to the source terminal of the lower switching element 323L, and the cathode of the snubber diode 323B is electrically connected to the drain terminal of the lower switching element 323L.

[0289] The W-phase inverter section 324 has an upper switching element 324U and a lower switching element 324L. The drain terminal of the upper switching element 324U is electrically connected to the positive power terminal EP. The source terminal of the upper switching element 324U and the drain terminal of the lower switching element 324L are electrically connected. The source terminal of the lower switching element 324L is connected to the negative power terminal EN. A snubber diode 324A is connected in antiparallel to the upper switching element 324U, and a snubber diode 324B is connected in antiparallel to the lower switching element 324L. More specifically, the anode of the snubber diode 324A is electrically connected to the source terminal of the upper switching element 324U, and the cathode of the snubber diode 324A is electrically connected to the drain terminal of the upper switching element 324U. The anode of the snubber diode 324B is electrically connected to the source terminal of the lower switching element 324L, and the cathode of the snubber diode 324B is electrically connected to the drain terminal of the lower switching element 324L.

[0290] The gate drive circuit 325 is electrically connected to the gate terminals of each switching element 322U, 322L, 323U, 323L, 324U, and 324L. The gate drive circuit 325 controls the on / off state of each switching element 322U, 322L, 323U, 323L, 324U, and 324L.

[0291] The semiconductor device 1 can be applied to at least one of the switching elements 322U, 322L, 323U, 323L, 324U, and 324L. For example, when the semiconductor device 1 is applied to the lower switching element 322L of the U-phase inverter unit 322, the lower switching element 322L of the U-phase inverter unit 322 and the gate drive circuit that drives the lower switching element 322L of the gate drive circuit 325 are replaced by the semiconductor device 1.

[0292] [Note] The technical ideas that can be understood from the above embodiments and modifications are described below. (Note 1-1) The active region is approximately L-shaped, formed by combining a small rectangular first region and a large rectangular second region, and the first wire and source pad, which serve as connecting members, are connected to each other at a position on the line segment connecting the centroid of the first region and the centroid of the second region, in a semiconductor device.

[0293] (Appendix 1-2) The semiconductor device according to Appendix 1-1, wherein the semiconductor element includes a transistor, and the semiconductor device comprises a second lead frame for controlling the on / off state of the transistor and a third lead frame connected to the first wire, the second lead frame being located on the first region side and the third lead frame being located on the second region side.

[0294] (Appendix 1-3) The semiconductor device according to Appendix 1-2, wherein the semiconductor element is provided with a gate pad connected to the second lead frame, and the gate pad is located in a rectangular region where the transistor is not located, within the region enclosed by the extension of the first edge of the first region RA1 and the extension of the fourth edge of the second region.

[0295] (Appendix 1-4) The semiconductor device according to Appendix 1-3, wherein the source pad is also substantially L-shaped, and the source pad is formed across the first region and the second region included in the active region, and the source pad is configured such that the first side of the source pad that is furthest from the second region coincides in the lateral direction with the position where the gate pad is provided.

[0296] (Appendix 1-5) The semiconductor device described in Appendix 1-3, wherein the temperature sensor is positioned between the gate pad and the source pad.

[0297] (Appendix 1-6) The semiconductor device according to Appendix 1-1, wherein the first wire and the source pad are connected to each other at two locations: the centroid position of the first region and the centroid position of the second region.

[0298] (Note 2-1) A semiconductor device comprising: a substrate including a transistor formation region on which a transistor is formed; an electrode pad on the transistor formation region; and a first connecting member connected to the electrode pad at one point, wherein the transistor formation region is formed in a concave shape having one recess in the vertical center of a rectangle or one recess in the horizontal center in a plan view, the electrode pad is provided so as to cover the center of gravity of the transistor formation region in a plan view, and the connecting region to which the first connecting member is connected to the electrode pad in a plan view includes the position of the center of gravity of the transistor formation region.

[0299] (Note 2-2) The semiconductor device described in Appendix 2-1, wherein the center position of the connection region coincides with the centroid position of the transistor formation region.

[0300] (Appendix 2-3) A semiconductor device comprising: a substrate including a transistor-forming region on which a transistor is formed; an electrode pad on the transistor-forming region; and a first connecting member connected to the electrode pad at multiple locations, wherein the transistor-forming region is formed in a concave shape having one recess in the vertical center of a rectangle or one recess in the horizontal center in a plan view, and is divided into a plurality of divided regions of equal area according to the number of connection locations of the first connecting member; the electrode pad is provided so as to cover the centroid of each of the plurality of divided regions in a plan view, and the connection region to which the first connecting member is connected to the electrode pad in a plan view includes the centroid position of each of the plurality of divided regions.

[0301] (Appendix 2-4) A semiconductor device comprising a substrate including a transistor-forming region on which a transistor is formed, an electrode pad on the transistor-forming region, and a plurality of first connecting members connected to the electrode pad, wherein the transistor-forming region is formed in a concave shape having one recess in the vertical center of a rectangle or one recess in the horizontal center in a plan view, and is divided into a plurality of divided regions of equal area according to the number of first connecting members, the electrode pad is provided so as to cover the centroid of each of the plurality of divided regions in a plan view, and the connection region to which each of the plurality of first connecting members is connected in a plan view includes the centroid position of each of the plurality of divided regions.

[0302] (Appendix 2-5) The semiconductor device according to Appendix 4, wherein the number of the first connecting members is two, and the transistor formation region is divided into two divided regions by a virtual line extending in the horizontal direction at the vertical center when the recess is located in the vertical center, and divided into two divided regions by a virtual line extending in the vertical direction at the horizontal center when the recess is located in the horizontal center.

[0303] (Appendix 2-6) A semiconductor device according to any one of the appendices 2-1 to 2-5, further comprising a control circuit region formed in a region of the semiconductor element different from the transistor formation region, which controls the current flowing through the semiconductor device.

[0304] (Appendix 2-7) The semiconductor device according to Appendix 2-6, wherein at least a portion of the control circuit region is located within the recess of the transistor formation region.

[0305] (Appendix 2-8) The semiconductor device according to Appendix 2-6 or 2-7, wherein a temperature sensor is provided in the control circuit region.

[0306] (Appendix 2-9) The semiconductor device according to Appendix 2-8, wherein the temperature sensor is located in a portion of the control circuit region that does not overlap with the first connecting member in the plan view.

[0307] (Appendix 2-10) The semiconductor device according to Appendix 2-8 or 2-9, wherein the temperature sensor is provided in a location adjacent to the bottom surface of the recess within the control circuit region located within the recess.

[0308] (Appendix 2-11) The semiconductor device according to Appendix 2-8 or 2-9, wherein the transistor formation region has a first recess and a second recess as recesses, the second recess is recessed from the bottom surface of the first recess, at least a part of the control circuit region is located within the second recess, and the temperature sensor is provided in a location within the control circuit region that is located within the second recess.

[0309] (Appendix 2-12) The semiconductor device according to any one of the appendices 2-1 to 2-11, wherein the semiconductor element comprises a power transistor and a control electrode pad connected to the control terminal of the power transistor, and the control electrode pad is arranged in a region cut out at a location different from the recess in the transistor formation region.

[0310] (Note 3-1) A semiconductor element having a substrate including a transistor formation region having a shape other than a rectangle on which transistors are formed, and electrode pads on the transistor formation region, A first connecting member connected to the electrode pad at one point, It has, The electrode pad is provided so as to cover the center of gravity of the transistor formation region in a plan view thereof. In the plan view, the connection region in which the first connecting member is connected to the electrode pad includes the centroid of the transistor formation region. Semiconductor equipment.

[0311] (Appendix 3-2) The center position of the connection region coincides with the centroid position of the transistor formation region. Semiconductor equipment as described in Appendix 3-1. (Note 4-1) A semiconductor element comprising a substrate including a transistor formation region having a shape other than a rectangle on which transistors are formed and a control circuit region having a circuit for controlling the transistors, a temperature sensor provided in the control circuit region, and electrode pads on the transistor formation region, A first connecting member connected to the electrode pad, It has, The transistor formation region is The first area and, A second region having a larger area than the first region, It has, The temperature sensor is positioned adjacent to the transistor formation region. The electrode pad is provided such that, in a plan view, it covers the respective centers of gravity of the first region and the second region. In the plan view, the connection region in which the first connecting member is connected to the electrode pad includes the centroid of the transistor formation region. Semiconductor equipment. (Appendix 4-2) The temperature sensor is positioned in the area outside the electrode pad within the control circuit region where heat is most concentrated when the semiconductor device is operating. Semiconductor device as described in Appendix 4-1. (Appendix 4-3) The temperature sensor is provided so as to be adjacent to the connection area in the plan view. Semiconductor device as described in Appendix 4-1 or 4-2. (Appendix 4-4) The transistor has a current sensor that detects the current flowing through it, The current sensor is positioned between the electrode pad and the control circuit region. A semiconductor device as described in any one of the appendices 4-1 to 4-3. (Appendix 4-5) The current sensor is provided within the transistor formation region. Semiconductor equipment as described in Appendix 4-4. (Appendix 4-6) The center position of the connection region coincides with the centroid position of the transistor formation region. A semiconductor device as described in any one of the appendices 4-1 to 4-5. (Appendix 4-7) The semiconductor element comprises a power transistor and a control electrode pad connected to the control terminal of the power transistor. A first lead frame on which the aforementioned semiconductor element is mounted, A second lead frame to which the other end of a second connecting member, one end of which is connected to the control electrode pad, is connected, A third lead frame to which the other end of the first connecting member, one end of which is connected to the semiconductor element, is connected, has A semiconductor device as described in any one of the appendices 4-1 to 4-6. (Appendix 4-8) The first lead frame and the third lead frame are made of copper, The first connecting member is made up of aluminum, At least one surface of the first lead frame and the third lead frame has a plating layer. Semiconductor devices as described in Appendix 4-7. (Appendix 4-9) The first lead frame has a first island portion on which the semiconductor element is mounted, The surface of the first island portion on which the semiconductor element is mounted has a plating layer. Semiconductor devices as described in Appendix 4-8. (Appendix 4-10) The third lead frame has a third island portion to which the first connecting member is connected, The surface of the third island portion to which the first connecting member is connected has a plating layer. Semiconductor devices as described in Appendix 4-8 or 4-9. (Appendix 4-11) The second lead frame, which is made of copper, has a second island portion to which the second connecting member is connected. The second connecting member is made up of aluminum, The surface of the second island portion to which the second connecting member is connected has a plating layer. A semiconductor device as described in any one of the appendices 4-7 to 4-10. (Appendix 4-12) The first connecting member is connected to the electrode pad by wedge bonding and has a connecting portion connected to the electrode pad. In a plan view, the connecting portion extends from the semiconductor element toward the third island portion. Semiconductor devices as described in Appendix 4-10. (Appendix 4-13) The substrate has a plurality of trenches and a plurality of functional element formation regions arranged along each of the plurality of trenches, including channel formation regions that serve as current paths. The plurality of functional element formation regions include a first functional element formation region in which the area of ​​the channel formation region per unit area is relatively small, and a second functional element formation region in which the area of ​​the channel formation region per unit area is relatively large. The first functional element formation region is provided in a region among the plurality of functional element formation regions where heat generation should be suppressed. A semiconductor device as described in any one of the appendices 4-1 to 4-12. (Appendix 4-14) The first connecting member is electrically connected to the plurality of functional element formation regions, The second functional element formation region is provided in the region among the plurality of functional element formation regions in which the first connecting member is electrically connected. Semiconductor equipment as described in Appendix 4-13. (Appendix 4-15) The first connecting member is connected to the electrode pad at multiple points, The first functional element formation region is provided in the region between adjacent second functional element formation regions, of which the first connecting member is connected to the plurality of functional element formation regions. Semiconductor equipment as described in Appendix 4-14. (Appendix 4-16) A metal layer is formed between the functional element formation region and the electrode pad to electrically connect the functional element formation region and the electrode pad. One or more slits are provided in at least the portion of the metal layer facing the electrode pad. A semiconductor device as described in any one of the appendices 4-13 to 4-15. (Appendix 4-17) The metal layer comprises a first metal layer and a second metal layer provided to be laminated with the first metal layer through contacts electrically connected to the first metal layer. In the first metal layer and the second metal layer, at least the portion facing the electrode pad is provided with one or more slits. The slits in the first metal layer and the slits in the second metal layer face each other in the stacking direction of the first and second metal layers. Semiconductor device as described in Appendix 4-16. (Appendix 4-18) Formed on the functional element formation region, and having an interlayer insulating film covering the first metal layer and the second metal layer, The interlayer insulating film is embedded in the slit of the first metal layer and the slit of the second metal layer. Semiconductor device as described in Appendix 4-17. (Appendix 4-19) The electrode pad is composed of copper. A semiconductor device as described in any one of the appendices 4-1 to 4-18. (Appendix 4-20) A connecting layer for connecting the first connecting member is provided on the surface of the electrode pad. A semiconductor device as described in any one of the appendices 4-1 to 4-19. (Appendix 4-21) The thickness of the electrode pad is 16,000 Å or more. A semiconductor device as described in any one of the appendices 4-1 to 4-20. (Appendix 4-22) The thickness of the electrode pad is 20,000 Å or more. Semiconductor device as described in Appendix 4-21. (Appendix 4-23) The first connecting member is made of aluminum. It has at least the semiconductor element and the first connecting member, and a sealing resin that seals them. The coefficient of linear expansion of the sealing resin is greater than 10 ppm / K and less than 15 ppm / K. A semiconductor device as described in any one of the appendices 4-1 to 4-22. (Appendix 4-24) The coefficient of linear expansion of the sealing resin is 12 ppm / K. Semiconductor equipment as described in Appendix 4-23. (Appendix 4-25) The sealing resin is provided with an ion trap material containing aluminum and magnesium. Semiconductor devices as described in Appendix 4-23 or 4-24. (Appendix 4-26) The electrode pad is A first protective layer covering the interlayer insulating film, A first electrode layer covering the first protective layer, A second protective layer covering the first electrode layer, A second electrode layer covering the second protective layer, It has, The Vickers hardness of the first protective layer and the second protective layer is greater than the Vickers hardness of the first electrode layer and the second electrode layer. A semiconductor device as described in any one of the appendices 4-1 to 4-25. (Appendix 4-27) The first electrode layer and the second electrode layer are made of aluminum or an aluminum alloy. The first protective layer and the second protective layer are made of titanium nitride. Semiconductor device as described in Appendix 4-26. (Appendix 4-28) The first connecting member is an aluminum wire that is wedge-bonded to the electrode pad. A semiconductor device as described in any one of the appendices 4-1 to 4-27. (Appendix 4-29) The diameter of the aluminum wire is 300 μm or more and 400 μm or less. Semiconductor equipment as described in Appendix 4-28. (Appendix 4-30) The first connecting member is a copper wire that is wedge-bonded to the electrode pad. A semiconductor device as described in any one of the appendices 4-1 to 4-29. (Appendix 4-31) The on-resistance of the semiconductor device is 30 mΩ or less. A semiconductor device as described in any one of the appendices 4-1 to 4-30. (Note 5-1) A semiconductor element having a substrate including a transistor formation region having a shape other than a rectangle on which transistors are formed, and electrode pads on the transistor formation region, A first bonding wire connected to the electrode pad, It has, The electrode pad is provided so as to cover the center of gravity of the transistor formation region in a plan view thereof. In the plan view, the first bonding wire coincides with the centroid of the transistor formation region at the connection point with the electrode pad. Semiconductor equipment. (Note 5-2) The semiconductor element includes a DTI structure that demarcates the transistor formation region. The transistor is surrounded by the DTI structure in the plan view. Semiconductor device as described in Appendix 5-1. (Appendix 5-3) The DTI structure, in the plan view, includes a portion that overlaps with the electrode pad. Semiconductor equipment as described in Appendix 5-2. (Appendix 5-4) The DTI structure includes an insulator provided inside the DTI structure. A wiring layer connecting the insulator and the electrode pad is arranged in the transistor formation region. Semiconductor equipment as described in Appendix 5-3. (Appendix 5-5) The wiring layer includes a portion located near the electrode pad in the transistor formation region. Semiconductor device as described in Appendix 5-4. (Appendix 5-6) The semiconductor device includes a first lead frame on which the semiconductor element is mounted, and a third lead frame to which the first bonding wire is connected. The first terminal portion of the first lead frame that constitutes the output terminal and the third terminal portion of the third lead frame that constitutes the ground terminal are arranged on the same side of the semiconductor device in the plan view. Semiconductor device as described in Appendix 5-1. (Appendix 5-7) The semiconductor element includes a gate pad to which a signal for controlling the transistor is input. The gate pad is positioned towards the corner of the semiconductor element in the plan view. Semiconductor device as described in Appendix 5-1. (Appendix 5-8) The substrate includes a plurality of sides facing in a direction perpendicular to the thickness direction of the semiconductor element and a control circuit region provided with a circuit for controlling the transistor. The plurality of sides include, in the plan view, a first side positioned closer to the control circuit region and a second side positioned on the opposite side from the first side. The semiconductor element includes a temperature sensor located in the control circuit region. The temperature sensor is positioned in the plan view toward the first side surface of the substrate, Semiconductor device as described in Appendix 5-1. (Appendix 5-9) The temperature sensor is positioned at a distance from the electrode pad. Semiconductor devices as described in Appendix 5-8. (Appendix 5-10) The semiconductor element includes a surface protective film on the surface of the electrode pad. At least a portion of the electrode pad is covered by the surface protective film. Semiconductor device as described in Appendix 5-1. (Appendix 5-11) The surface protective film has an opening in the electrode pad. Semiconductor devices as described in Appendix 5-10. [Explanation of Symbols]

[0312] 1… Semiconductor equipment 11…First lead frame 11a...Island 1 12…Second lead frame 12a...Second Island Section 13…Third lead frame 13a…Third Island Section 14…Plating layer 20... Semiconductor elements 21… Source pad (electrode pad) 21a…Connecting layer 22... Gate pad (control electrode pad) 23a…MISFET (Power Transistor) 27…Temperature sensor 29…Active region (transistor formation region) 30…Sealing resin 41…First wire (first connecting member) 41a...Connection part 41b...First connection section 41c...Second connection section 42...Second wire (second connecting member) 50... Circuit board 66... ​​Trench 72... Channel formation region 74…Interlayer insulating film 80...First source electrode (first metal layer, metal layer) 81... Contact 82...Second source electrode (second metal layer, metal layer) 83... Contact 220...First Slit 221...Second Slit 231…Functional element formation region 232...First functional element formation region 233...Second functional element formation region 270... Source pad (electrode pad) 271...1st protective layer 272...First electrode layer 273…Second protective layer 274…Second electrode layer 275…Connection layer GC,GD,GF,GH…Center of gravity position GB1, GE1, GG1, GJ1... Centroid positions of regions divided into equal areas within the transistor formation region. GB2, GE2, GG2, GJ2... Centroid position of regions divided into equal areas within the transistor formation region. RX, RY… Wedge (connection area)

Claims

1. A semiconductor element comprising a substrate including a transistor formation region having a shape other than a rectangle on which transistors are formed, electrode pads on the transistor formation region, and a DTI structure that demarcates the transistor formation region, A first bonding wire connected to the electrode pad, It has, The electrode pad is provided so as to cover the center of gravity of the transistor formation region in a plan view thereof. In the plan view, the first bonding wire coincides with the centroid of the transistor formation region at the connection point with the electrode pad. The transistor is surrounded by the DTI structure in the plan view, The DTI structure includes an insulator provided inside the DTI structure, and a portion that overlaps with the electrode pad in the plan view. A wiring layer connecting the insulator and the electrode pad is arranged in the transistor formation region. The wiring layer includes a portion located near the electrode pad in the transistor formation region. Semiconductor equipment.

2. The semiconductor device includes a first lead frame on which the semiconductor element is mounted, and a third lead frame to which the first bonding wire is connected. The first terminal portion of the first lead frame that constitutes the output terminal and the third terminal portion of the third lead frame that constitutes the ground terminal are arranged on the same side of the semiconductor device in the plan view. The semiconductor device according to claim 1.

3. The semiconductor element includes a gate pad to which a signal for controlling the transistor is input. The gate pad is positioned towards the corner of the semiconductor element in the plan view. The semiconductor device according to claim 1.

4. The substrate includes a plurality of sides facing in a direction perpendicular to the thickness direction of the semiconductor element and a control circuit region provided with a circuit for controlling the transistor. The plurality of sides include, in the plan view, a first side positioned closer to the control circuit region and a second side positioned on the opposite side from the first side. The semiconductor element includes a temperature sensor located in the control circuit region. The temperature sensor is positioned in the plan view toward the first side surface of the substrate, The semiconductor device according to claim 1.

5. The temperature sensor is positioned at a distance from the electrode pad. The semiconductor device according to claim 4.

6. The semiconductor element includes a surface protective film on the surface of the electrode pad. At least a portion of the electrode pad is covered by the surface protective film. The semiconductor device according to claim 1.

7. The surface protective film has an opening in the electrode pad. The semiconductor device according to claim 6.

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