Semiconductor equipment
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- KK TOSHIBA
- Filing Date
- 2022-09-15
- Publication Date
- 2026-06-17
Smart Images

Figure 0007875082000001 
Figure 0007875082000002 
Figure 0007875082000003
Abstract
Claims
1. First electrode and, The second electrode and A third electrode is positioned between the first electrode and the second electrode, extending in a first direction and having first and second portions arranged alternately along the first direction, Connected to the first electrode, facing the first portion via an insulating layer, and comprising a first semiconductor layer of first conductivity type containing silicon and carbon, Connected to the aforementioned second electrode, a second semiconductor layer comprising silicon and carbon and having a first conductivity type, At least a portion of the third semiconductor layer is disposed between the first semiconductor layer and the second semiconductor layer, is in contact with the first semiconductor layer and the second semiconductor layer, faces the third electrode via the insulating layer, contains silicon and carbon, and is of the second conductivity type. At least a portion of a fourth semiconductor layer is disposed between the first semiconductor layer and the second portion, facing the second portion via the insulating layer, in contact with the third semiconductor layer, and containing silicon and carbon, with a carrier concentration higher than that of the third semiconductor layer, Equipped with, The third semiconductor layer and the fourth semiconductor layer are in contact with the insulating layer. The first contact surface between the insulating layer and the third semiconductor layer is in contact with the second contact surface between the insulating layer and the fourth semiconductor layer. Multiple third electrodes are provided along a second direction intersecting the first direction, The fourth semiconductor layer is provided in multiple layers along the first direction and is arranged in a matrix along the first and second directions. A semiconductor device in which a portion of the plurality of fourth semiconductor layers provided along the first direction is arranged over a region directly beneath the second portion of the plurality of third electrodes arranged along the second direction.
2. The semiconductor device according to claim 1, wherein the surface of the fourth semiconductor layer on the second electrode side is in contact with the third semiconductor layer and the insulating layer.
3. The semiconductor device according to claim 1, wherein the surface of the first semiconductor layer facing the first portion is in contact with the insulating layer.
4. The semiconductor device according to claim 1, wherein the length of the first portion in the first direction is less than or equal to the length of the second portion in the first direction.
5. The semiconductor device according to claim 1, wherein the first part and the second part are arranged periodically.
6. The semiconductor device according to claim 1, wherein the second semiconductor layer extends in the first direction and faces the third electrode via the insulating layer.
7. The semiconductor device according to claim 1, wherein the plurality of fourth semiconductor layers extend in the second direction and are arranged in the region directly below the plurality of third electrodes.
8. First electrode and, The second electrode and A third electrode is positioned between the first electrode and the second electrode, extending in a first direction, and having a first portion and a second portion. Connected to the first electrode, facing the first portion via an insulating layer, and comprising a first semiconductor layer of first conductivity type containing silicon and carbon, Connected to the aforementioned second electrode, a second semiconductor layer comprising silicon and carbon and having a first conductivity type, At least a portion of the third semiconductor layer is disposed between the first semiconductor layer and the second semiconductor layer, is in contact with the first semiconductor layer and the second semiconductor layer, faces the third electrode via the insulating layer, contains silicon and carbon, and is of the second conductivity type. At least a portion of a fourth semiconductor layer is disposed between the first semiconductor layer and the second portion, facing the second portion via the insulating layer, in contact with the third semiconductor layer, and containing silicon and carbon, with a carrier concentration higher than that of the third semiconductor layer, Equipped with, Multiple third electrodes are provided along a second direction intersecting the first direction, The aforementioned fourth semiconductor layer is provided in multiple locations along the aforementioned first direction, The fourth semiconductor layer is arranged in a matrix along the first and second directions, A semiconductor device in which the carrier concentration in the portion of the first semiconductor layer located between adjacent fourth semiconductor layers in the second direction is higher than the carrier concentration in the portion of the first semiconductor layer located between adjacent fourth semiconductor layers in the first direction.