Semiconductor device and method for manufacturing a semiconductor device

Abstract

This semiconductor device 1 includes a semiconductor layer 2, and a Schottky electrode 15 that is formed on a first surface 3 of the semiconductor layer 2 and that forms a Schottky barrier Sj between the Schottky electrode 15 and the semiconductor layer 2. The Schottky electrode 15 is selectively formed in the vicinity of the first surface 3 of the semiconductor layer 2 in a thickness direction of the Schottky electrode 15 and has a first portion 151 constituted by Ti containing oxygen. The Schottky electrode 15 may have a second portion 152 that is formed on the first portion 151 and that is constituted by Ti and N.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device comprising a Schottky barrier diode and a method for manufacturing the same. [Background technology]

[0002] Patent Document 1 describes n made of silicon carbide. + A molded substrate and a silicon carbide dopant formed on the main surface of the substrate, having a lower dopant concentration than the substrate. - Type drift layer and these n + Type substrate and n - SBD formed in the cell portion of the drift layer, and n + Type substrate and n - The present invention discloses a SiC semiconductor device comprising a termination structure formed in the outer peripheral region of a drift layer. The SBD includes a Schottky electrode. The Schottky electrode has an oxide layer made of molybdenum oxide in the portion that is in direct contact with the SiC, a metal layer made of molybdenum formed on the oxide layer, and a bonding electrode layer for making an electrical connection by wire bonding or the like. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2010-225877 [Overview of the project] [Problems that the invention aims to solve]

[0004] With the need for power savings in semiconductor devices, there is a demand for reducing the forward voltage of Schottky barrier diodes.

[0005] One embodiment of the present disclosure provides a semiconductor device that can reduce the forward voltage in a configuration having a Schottky junction. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor layer and a Schottky electrode formed on a first surface of the semiconductor layer and forming a Schottky junction with the semiconductor layer, wherein the Schottky electrode has a first portion which is selectively formed in the vicinity of the first surface of the semiconductor layer in the thickness direction of the Schottky electrode and is made of oxygen-containing Ti. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is a schematic plan view of a Schottky barrier diode according to the first embodiment of this disclosure. [Figure 2] Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. [Figure 3] Figure 3 is a plan view showing the Schottky barrier diode with the structure above the first main surface of the semiconductor layer removed. [Figure 4] Figure 4 is an enlarged view of the area enclosed by the dashed line IV in Figure 2. [Figure 5] Figure 5 is an enlarged view of the area enclosed by the dashed line V in Figure 2. [Figure 6] Figure 6 shows the results of the analysis of the constituent elements of the Schottky electrode and anode electrode of the Schottky barrier diode. [Figure 7] Figure 7 is a flowchart of the manufacturing process for the Schottky barrier diode. [Figure 8] Figures 8A and 8B show a part of the manufacturing process for the Schottky barrier diode. [Figure 9] Figures 9A and 9B show the next steps following Figures 8A and 8B, respectively. [Figure 10] Figures 10A and 10B show the next steps following Figures 9A and 9B, respectively. [Figure 11] Figures 11A and 11B show the next steps following Figures 10A and 10B, respectively. [Figure 12]FIG. 12A and FIG. 12B are diagrams showing the subsequent processes of FIGS. 11A and 11B, respectively. [Figure 13] FIG. 13A and FIG. 13B are diagrams showing the subsequent processes of FIGS. 12A and 12B, respectively. [Figure 14] FIG. 14A and FIG. 14B are diagrams showing the subsequent processes of FIGS. 13A and 13B, respectively. [Figure 15] FIG. 15A and FIG. 15B are diagrams showing the subsequent processes of FIGS. 14A and 14B, respectively. [Figure 16] FIG. 16 is a diagram showing the analysis results of the constituent elements of the Schottky electrode and the anode electrode of the Schottky barrier diode according to Sample 2. [Figure 17] FIG. 17A and FIG. 17B are I-V curves of the Schottky barrier diodes according to Samples 1 to 3. [Figure 18] FIG. 18A and FIG. 18B are I-V curves of the Schottky barrier diodes according to Samples 4 and 5. [Figure 19] FIG. 19 is a schematic cross-sectional view of the Schottky barrier diode according to the second embodiment of the present disclosure. [Figure 20] FIG. 20 is a plan view showing a state in which the structure above the first main surface of the semiconductor layer of the Schottky barrier diode in FIG. 19 is removed. [Figure 21] FIG. 21 is an enlarged view of the portion surrounded by the two-dot chain line XXI in FIG. 19. [Figure 22A] FIG. 22A is a circuit diagram for explaining the voltage drop around the inner impurity region included in the Schottky barrier diode in FIG. 19. [Figure 22B] FIG. 22B is a cross-sectional view for explaining the voltage drop around the inner impurity region.

Embodiments for Carrying Out the Invention

[0008] <Embodiments of the Present Disclosure> First, the embodiments of the present disclosure will be listed and described.

[0009] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor layer and a Schottky electrode formed on a first surface of the semiconductor layer and forming a Schottky junction with the semiconductor layer, wherein the Schottky electrode has a first portion which is selectively formed in the vicinity of the first surface of the semiconductor layer in the thickness direction of the Schottky electrode and is made of oxygen-containing Ti.

[0010] In this configuration, the Schottky electrode has a first portion selectively formed near the first surface of the semiconductor layer in the thickness direction of the Schottky electrode. This first portion is made of oxygen-containing Ti. This makes it possible to reduce the forward voltage of the Schottky electrode.

[0011] In a semiconductor device according to one embodiment of the present disclosure, the Schottky electrode may have a second portion formed on the first portion and composed of Ti and N.

[0012] In a semiconductor device according to one embodiment of the present disclosure, the oxygen concentration near the Schottky junction may be higher than both the oxygen concentration near the interface between the first and second portions and the average oxygen concentration of the semiconductor layer.

[0013] In a semiconductor device according to one embodiment of the present disclosure, when analyzed in a first direction from the Schottky electrode toward the semiconductor layer using a predetermined quantitative analysis method, the oxygen concentration profile corresponding to the first portion may have a peak closer to the boundary between the first portion and the semiconductor layer than to the central position of the first portion in the first direction.

[0014] With this configuration, the oxygen concentration near the boundary between the first portion of the Schottky electrode and the semiconductor layer is increased, which allows for a further reduction in the forward voltage.

[0015] In a semiconductor device according to one embodiment of the present disclosure, the concentration at the peak of the oxygen concentration profile may be 2.0 atm% or more and 10.0 atm% or less.

[0016] A semiconductor device according to one embodiment of the present disclosure includes an insulating layer formed on the first surface of the semiconductor layer and having an opening that partially exposes the first surface, the Schottky electrode includes a first covering portion that covers the first surface of the semiconductor layer within the opening of the insulating layer, and a second covering portion formed outside the opening of the insulating layer and covering the insulating layer, the first portion selectively containing oxygen in the first covering portion of the Schottky electrode, and the second covering portion not containing oxygen.

[0017] In a semiconductor device according to one embodiment of the present disclosure, the semiconductor layer does not need to contain oxygen near the first surface at the Schottky junction.

[0018] This configuration suppresses the increase in resistance of the semiconductor layer in contact with the first portion of the Schottky electrode, allowing for efficient forward current flow.

[0019] A semiconductor device according to one embodiment of the present disclosure may include a surface electrode formed on the Schottky electrode and composed of an Al alloy or Al.

[0020] In a semiconductor device according to one embodiment of the present disclosure, the Al alloy may include at least one of AlCu alloy, AlSi alloy, and AlSiCu alloy.

[0021] In a semiconductor device according to one embodiment of the present disclosure, the semiconductor layer includes a semiconductor layer of a first conductivity type and may further include an impurity region of a second conductivity type selectively formed on the first surface of the semiconductor layer so as to be in contact with the Schottky electrode, and forming a pn junction between itself and the semiconductor layer.

[0022] With this configuration, the depletion layer extending from the pn junction between the semiconductor layer and the impurity region can reduce reverse leakage current.

[0023] A semiconductor device according to one embodiment of the present disclosure further includes a lattice defect region selectively formed on the first surface of the semiconductor layer so as to be in contact with the Schottky electrode, and having more lattice defects than the semiconductor layer, wherein the impurity region may include a first region formed inside the lattice defect region so as to be in contact with the lattice defect region.

[0024] This configuration selectively forms lattice-fault regions with more lattice defects than the semiconductor layer. This makes it possible to reduce the current flowing through the lattice-fault regions to less than the current flowing through the Schottky junction.

[0025] Furthermore, a first impurity region is formed inside the lattice defect region. The voltage drop near the lattice defect region in the semiconductor layer is smaller than the voltage drop near the Schottky junction in the semiconductor layer. Because the first region is formed inside the lattice defect region, the voltage drop due to the semiconductor layer is also reduced around the inner impurity region. Therefore, a sufficient potential difference can be secured at the pn boundary of the pn junction between the first region and the semiconductor layer. As a result, surge resistance can be improved.

[0026] In a semiconductor device according to one embodiment of the present disclosure, the first conductivity type may be n-type and the second conductivity type may be p-type.

[0027] In a semiconductor device according to one embodiment of the present disclosure, the semiconductor layer may include a SiC semiconductor layer.

[0028] A method for manufacturing a semiconductor device according to one embodiment of the present disclosure includes the steps of: introducing oxygen to the first surface of a semiconductor layer having a first surface; forming a Schottky electrode having a first portion made of Ti in contact with the first surface of the semiconductor layer by depositing Ti on the first surface of the semiconductor layer; and diffusing the oxygen introduced into the semiconductor layer to the first portion of the Schottky electrode by annealing.

[0029] According to this method, oxygen is incorporated into the first portion of the Schottky electrode through oxygen diffusion. This makes it possible to provide a semiconductor device that can reduce the forward voltage of the Schottky electrode.

[0030] A method for manufacturing a semiconductor device according to one embodiment of the present disclosure includes a step of cleaning the first surface of the semiconductor layer with a chemical solution, and the oxygen introduction step may include a step of introducing oxygen into the semiconductor layer by irradiating the first surface of the semiconductor layer cleaned with the chemical solution with oxygen plasma.

[0031] In this method, the oxygen plasma irradiation process is performed after the cleaning process of the first surface of the semiconductor layer. Therefore, it is possible to prevent the oxygen introduced into the semiconductor layer by irradiation from being removed during the cleaning process.

[0032] In one embodiment of the present disclosure, the method for manufacturing a semiconductor device may include a step of forming a Schottky electrode, in which, after the formation of the first portion, Ti is further deposited in an N2 atmosphere to form a second portion composed of Ti and N on the first portion. <Detailed Description of Embodiments in This Disclosure> [First Embodiment] Figure 1 is a schematic plan view of a Schottky barrier diode 1 according to the first embodiment of the present disclosure. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Figure 3 is a plan view of the Schottky barrier diode 1 with the structure above the first main surface 3 of the semiconductor layer 2 removed. Figure 4 is an enlarged view of the area enclosed by the dashed line IV in Figure 2. Figure 5 is an enlarged view of the area enclosed by the dashed line V in Figure 2.

[0033] Referring to Figure 1, the Schottky barrier diode 1 is a Schottky barrier diode employing 4H-SiC (for example, a wide-bandgap semiconductor with a dielectric breakdown field of approximately 2.8 MV / cm and a bandgap width of approximately 3.26 eV). The Schottky barrier diode 1 is, for example, a chip with a square shape in plan view. The length of each side of the chip-shaped Schottky barrier diode 1 may be, for example, between 0.5 mm and 20 mm. That is, the chip size of the Schottky barrier diode 1 may be, for example, between 0.5 mm / □ and 20 mm / □.

[0034] The Schottky barrier diode 1 includes a semiconductor layer 2 formed in the shape of a rectangular parallelepiped chip. The semiconductor layer 2 may include, for example, a SiC semiconductor layer. The off-angle of the semiconductor layer 2 is preferably, for example, 4° or less. The semiconductor layer 2 has a first main surface 3 and a second main surface 4 on the opposite side (see Figure 2) in the thickness direction. The semiconductor layer 2 has sides 5a, 5b, 5c, and 5d that connect the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrilateral shape (square in this embodiment) in a plan view (hereinafter simply referred to as "plan view") as seen from their normal direction (third direction Z).

[0035] In this embodiment, sides 5a and 5c extend along the first direction X and face each other in the second direction Y which intersects the first direction X. Sides 5b and 5d extend along the second direction Y and face each other in the first direction X. More specifically, the second direction Y may be perpendicular to the first direction X.

[0036] Referring to Figure 2, in this embodiment, the semiconductor layer 2 has a laminated structure including an n-type (first conductivity type) semiconductor substrate 6 and an n-type epitaxial layer 7. The semiconductor substrate 6 and the epitaxial layer 7 may be a SiC semiconductor substrate and a SiC epitaxial layer, respectively. The semiconductor substrate 6 forms the second main surface 4 of the semiconductor layer 2, and the epitaxial layer 7 forms the first main surface 3 of the semiconductor layer 2.

[0037] The first main surface 3 of the semiconductor layer 2 may also be the surface 7a of the epitaxial layer 7 opposite to the semiconductor substrate 6, and the second main surface 4 of the semiconductor layer 2 may be the surface 6a of the semiconductor substrate 6 opposite to the epitaxial layer 7. Examples of n-type impurities contained in the semiconductor substrate 6 and the epitaxial layer 7 may be N (nitrogen), P (phosphorus), As (arsenic), etc.

[0038] The Schottky barrier diode 1 includes a cathode electrode 8 formed on the second main surface 4 of the semiconductor layer 2 (the surface 6a of the semiconductor substrate 6). The cathode electrode 8 is an ohmic electrode that covers the entire area of ​​the second main surface 4 of the semiconductor layer 2 (the surface 6a of the semiconductor substrate 6). The cathode electrode 8 contains a metal that makes ohmic contact with n-type SiC. Examples of such metals include Ti / Ni / Ag and Ti / Ni / Au / Ag.

[0039] The thickness TS of the semiconductor substrate 6 may be, for example, 40 μm or more and 150 μm or less. The thickness TS may be, for example, 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, 90 μm or more and 100 μm or less, 100 μm or more and 110 μm or less, 110 μm or more and 120 μm or less, 120 μm or more and 130 μm or less, 130 μm or more and 140 μm or less, or 140 μm or more and 150 μm or less. The thickness TS is preferably 40 μm or more and 130 μm or less.

[0040] The thickness TE of the epitaxial layer 7 may be, for example, 1 μm or more and 50 μm or less. The thickness TE may be, for example, 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or less, 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or less, or 45 μm or more and 50 μm or less. The thickness TE is preferably 5 μm or more and 15 μm or less.

[0041] The n-type impurity concentration of the epitaxial layer 7 may be equal to or less than the n-type impurity concentration of the semiconductor substrate 6, and is preferably less than the n-type impurity concentration of the semiconductor substrate 6. The n-type impurity concentration of the semiconductor substrate 6 is, for example, 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less. The n-type impurity concentration of the epitaxial layer 7 is, for example, 1.0×10 15 cm -3 or more and 1.0×10 18 cm -3 or less.

[0042] An active region 9 and an inactive region 10 are set on the first main surface 3 of the semiconductor layer 2 (the surface 7a of the epitaxial layer 7). The active region 9 is set at the central portion of the first main surface 3 of the semiconductor layer 2 with a space from the side surfaces 5a to 5d of the semiconductor layer 2 inward in a plan view. The active region 9 is set in a rectangular shape having four sides parallel to the side surfaces 5a to 5d of the semiconductor layer 2 in a plan view.

[0043] The inactive region 10 is set between the side surfaces 5a to 5d of the semiconductor layer 2 and the active region 9. The inactive region 10 is set in an endless shape (a square ring shape in this embodiment) surrounding the active region 9 in a plan view.

[0044] The Schottky barrier diode 1 further includes a p-type (second conductivity type) guard region 30 formed in the surface layer portion of the first main surface 3 of the semiconductor layer 2 (the surface layer portion of the surface 7a of the epitaxial layer 7) in the inactive region 10.

[0045] Referring to FIG. 3, the guard region 30 is formed in an endless shape (for example, a square ring shape, a square ring shape with chamfered corners or a circular ring shape) surrounding the active region 9 in a plan view. Thereby, the guard region 30 is formed as a guard ring region. The active region 9 may be a region partitioned by the guard region 30 in this embodiment.

[0046] The guard region 30 includes a first guard region 31 and a plurality of (five in the example of Figure 3) second guard regions 32 that surround the first guard region 31 and have a narrower width than the first guard region 31. The plurality of second guard regions 32 are provided at equal intervals. Unlike the example of Figure 3, the guard region 30 may consist of a single endless region (for example, a square ring, a square ring with chamfered corners, or a circular ring).

[0047] Referring to Figure 2, the Schottky barrier diode 1 includes an annular field insulating film 13 formed on the first main surface 3 of the semiconductor layer 2. The field insulating film 13, as an example of an insulating layer, covers a portion of the first main surface 3 of the semiconductor layer 2 in the inactive region 10. The field insulating film 13 has an opening 12 that exposes a portion of the first main surface 3 of the semiconductor layer 2.

[0048] The size of the active area 9 is, for example, 0.1 mm. 2 400mm or more 2 The following may also apply: The field insulating film 13 may have a single-layer structure consisting of, for example, a silicon oxide (SiO2) layer or a silicon nitride (SiN) layer. The thickness of the field insulating film 13 may be, for example, 0.5 μm or more and 3 μm or less.

[0049] The field insulating film 13 has a first surface 13a that is in contact with the first main surface 3, a second surface 13b opposite to the first surface 13a, and an inner surface 13c and an outer surface 13d that connect the first surface 13a and the second surface 13b. The inner surface 13c is an inclined surface that slopes to form an acute angle into the field insulating film 13 between the inner surface 13c and the first main surface 3. The outer surface 13d is an inclined surface that slopes to form an acute angle into the field insulating film 13 between the outer surface 13d and the first main surface 3.

[0050] The Schottky barrier diode 1 further includes a Schottky electrode 15 and an anode electrode 14 as an example of a surface electrode formed on the Schottky electrode 15.

[0051] The Schottky electrode 15 is formed on the first main surface 3 of the semiconductor layer 2 and forms a Schottky junction SJ with the semiconductor layer 2 (epitaxial layer 7). The Schottky junction SJ is formed near the contact interface between the first portion 151 and the epitaxial layer 7. The thickness of the Schottky electrode 15 may be, for example, 50 nm or more and 500 nm or less.

[0052] The Schottky electrode 15 includes a first covering portion 18 that covers the first main surface 3 of the semiconductor layer 2 in the active region 9, and a second covering portion 19 that covers the field insulating film 13. The second covering portion 19 covers the entire inner surface 13c and a part of the second surface 13b of the field insulating film 13. Therefore, the field insulating film 13 is positioned between the first main surface 3 of the semiconductor layer 2 and the Schottky electrode 15.

[0053] Referring to Figures 4 and 5, the Schottky electrode 15 includes a first portion 151 in contact with the first main surface 3 of the semiconductor layer 2, and a second portion 152 formed on the first portion 151. A boundary portion 153, shown by a dashed line in Figures 4 and 5, may be formed between the first portion 151 and the second portion 152. If the first portion 151 and the second portion 152 can be confirmed to be formed in layers using an electron microscope such as an SEM or TEM, they may be referred to as the first layer 151 and the second layer 152, respectively. Also, since the positional relationship between the first portion 151 and the second portion 152 in Figures 4 and 5 is upper and lower, they may be referred to as the lower layer 151 and the upper layer 152, respectively. Furthermore, since both the first portion 151 and the second portion 152 are made of metal, they may be referred to as the first metal portion 151 (first metal layer 151) and the second metal portion 152 (second metal layer 152), respectively. Although not shown in the diagram, a third portion containing a different material from the first portion 151 and the second portion 152 may be interposed between the first portion 151 and the second portion 152 as an intermediate portion (intermediate layer).

[0054] The boundary portion 153 between the first portion 151 and the second portion 152 is formed along the first main surface 3 of the semiconductor layer 2 in a transverse direction, extending across the entire Schottky electrode 15. As a result, as shown in Figure 5, the Schottky electrode 15 is divided vertically into the first portion 151 and the second portion 152, with the boundary portion 153 exposed at its end face 154. Therefore, a laminated structure including the first portion 151 and the second portion 152 is formed in the first coating portion 18 of the Schottky electrode 15, and a laminated structure including the first portion 151 and the second portion 152 is also formed in the second coating portion 19.

[0055] The thickness of the first part 151 may be less than the thickness of the second part 152. For example, the thickness of the first part 151 may be, for example, 5 nm or more and 300 nm or less, and the thickness of the second part 152 may be, for example, 50 nm or more and 500 nm or less. Also, the thickness of the first part 151 may be less than half the total thickness of the Schottky electrode 15. On the other hand, the thickness of the second part 152 may be half or more the total thickness of the Schottky electrode 15.

[0056] The first portion 151 is a portion of the Schottky electrode 15 that forms a Schottky junction SJ with the semiconductor layer 2 (epitaxial layer 7), and is composed of Ti. Here, "a portion composed of Ti" may mean a portion of the Schottky electrode 15 that contains only Ti as its main component. For example, the first portion 151 may be a portion in which an amount of Ti exceeding 50.0 atm% is detected when elemental analysis is performed in the direction from the Schottky electrode 15 toward the semiconductor layer 2 (in this embodiment, the third direction Z) using a predetermined quantitative analysis method (e.g., energy-dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), Auger electron spectroscopy (AES), etc.).

[0057] The second portion 152 is a portion that is not in contact with the semiconductor layer 2 (epitaxial layer 7) at least via the first portion 151, and is composed of Ti and N. Here, "a portion composed of Ti and N" may mean a portion of the Schottky electrode 15 that contains both Ti and N as its main components. For example, the second portion 152 may be a portion in which, when elemental analysis is performed in the direction from the Schottky electrode 15 toward the semiconductor layer 2 (in this embodiment, the third direction Z) using a predetermined quantitative analysis method (as described above), an amount of Ti of 30.0 atm% or more and an amount of N of 30.0 atm% or more are detected.

[0058] The first guard region 31 is in contact with the Schottky electrode 15 and the field insulating film 13, and the multiple second guard regions 32 are in contact with the field insulating film 13 (see Figure 5).

[0059] The anode electrode 14 is formed to cover the entire surface of the Schottky electrode 15. Therefore, the anode electrode 14 straddles the first coating portion 18 and the second coating portion 19 of the Schottky electrode 15. The anode electrode 14 is made of, for example, an Al alloy or Al. The Al alloy may include, for example, at least one of AlCu alloy, AlSi alloy, and AlSiCu alloy. Here, "Al alloy or Al" may be a metal in which an amount of Al greater than 70.0 atm% is detected when elemental analysis is performed in the direction from the anode electrode 14 toward the semiconductor layer 2 (in this embodiment, the third direction Z) using a predetermined quantitative analysis method (e.g., energy-dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), Auger electron spectroscopy (AES), etc.). Referring to Figures 2 and 4, the anode electrode 14 includes a connecting portion 16 having a surface 16a to which a connecting member 22 such as a bonding wire is connected.

[0060] The Schottky barrier diode 1 further comprises a passivation layer 20 as an example of a second insulating layer formed on the connection portion 16 of the anode electrode 14. The passivation layer 20 may have a single-layer structure consisting of a silicon oxide layer or a silicon nitride layer, or it may have a multilayer structure consisting of a silicon oxide layer and a silicon nitride layer. If the passivation layer 20 has a multilayer structure, the silicon oxide layer may be formed on the silicon nitride layer, or the silicon nitride layer may be formed on the silicon oxide layer. In this embodiment, the passivation layer 20 has a single-layer structure consisting of a silicon nitride layer.

[0061] The passivation layer 20 is formed inward from the sides 5a to 5d of the semiconductor layer 2 in a plan view, with a gap between them. The passivation layer 20 has a pad opening 21 that exposes a portion of the surface 16a of the connection portion 16 of the anode electrode 14 as a connection area 23 with the connecting member 22.

[0062] The Schottky barrier diode 1 further includes a p-type (second conductivity type) impurity region 40 formed in the active region 9 on the surface of the first main surface 3 (surface 7a of the epitaxial layer 7) of the semiconductor layer 2 so as to be in contact with the Schottky electrode 15. The impurity region 40 forms a pn junction PJ between the semiconductor layer 2 and the epitaxial layer 7. The pn junction PJ is formed near the contact interface between the impurity region 40 and the epitaxial layer 7.

[0063] Referring to Figure 3, the impurity region 40 includes a plurality of linear impurity regions 41 arranged in a stripe pattern. The p-type impurity concentration in the impurity region 40 is, for example, 10 × 10 16 cm -3 The above 10 x 10 21 cm -3 The following is also acceptable.

[0064] Multiple linear impurity regions 41 are arranged at equal intervals in the second direction Y, and each linear impurity region 41 extends in the first direction X. The multiple linear impurity regions 41 form an integral part with the first guard region 31. Specifically, both ends of the linear impurity regions 41 in the first direction X are connected to the inner ends of the first guard region 31.

[0065] Referring to Figure 4, the bottom of each linear impurity region 41 (the bottom 40a of the impurity region 40) is in contact with the epitaxial layer 7. The bottom of each linear impurity region 41 may include a pair of curved portions toward the second main surface 4 of the semiconductor layer 2 and a flat portion connecting the curved portions.

[0066] The width W of the linear impurity region 41 in the second direction Y may be, for example, 0.5 μm or more and 10 μm or less. The depth D of the linear impurity region 41 may be, for example, 0.3 μm or more and 1.5 μm or less. The pitch P of the multiple linear impurity regions 41 in the second direction Y may be, for example, 1.0 μm or more and 5 μm or less.

[0067] Next, with reference to Figure 6, a more detailed explanation will be given regarding the constituent elements of the Schottky electrode 15 and the anode electrode 14.

[0068] Figure 6 shows the results of the analysis of the constituent elements of the Schottky electrode 15 and the anode electrode 14. More specifically, it shows the results of energy-dispersive X-ray spectroscopy analysis of the constituent elements of the Schottky electrode 15 and the anode electrode 14 at the position of the first coating portion 18 of the Schottky electrode 15 in the first direction X and the second direction Y. In this embodiment, the elements carbon (C), nitrogen (N), oxygen (O), aluminum (Al), silicon (Si), and titanium (Ti) are detected. The acceleration voltage conditions for energy-dispersive X-ray spectroscopy when detecting these elements may be, for example, 150kV to 250kV.

[0069] In Figure 6, the horizontal axis represents the depth in the direction from the surface 16a of the anode electrode 14 toward the semiconductor layer 2, with the position of the surface 16a representing depth 0 (zero). Multiple dashed lines crossing the horizontal axis represent the boundary 155 between the anode electrode 14 and the Schottky electrode 15 (second part 152), the boundary 153 between the second part 152 and the first part 151 of the Schottky electrode 15, and the boundary 156 between the Schottky electrode 15 (first part 151) and the semiconductor layer 2 (epitaxial layer 7), respectively. The vertical axis in Figure 6 represents the concentration (atm%) of each constituent element.

[0070] Figure 6 shows the individual concentration profiles 171-176 for the detected constituent elements: carbon (C), nitrogen (N), oxygen (O), aluminum (Al), silicon (Si), and titanium (Ti). The concentration profiles 171-176 for each element are continuous across the boundaries 155, 153, and 156. Of the concentration profiles 171-176 for each element, the portion within the area between the horizontal axis 0 and boundary 155 represents the atomic proportion of the constituent elements of the anode electrode 14. Furthermore, of the concentration profiles 171-176 for each element, the portions within the area between boundary 155 and boundary 153, and the portions within the area between boundary 153 and boundary 156, represent the atomic proportions of the constituent elements of the second part 152 and the first part 151 of the Schottky electrode 15, respectively.

[0071] Referring to Figure 6, the anode electrode 14 (AlCu) primarily contains aluminum (Al) at a concentration of 75.0 atm% to 85.0 atm%. The anode electrode 14 also contains carbon (C) at a concentration of 10.0 atm% to 20.0 atm% and oxygen (O) at a concentration of 2.0 atm% to 5.0 atm% as minor components. Furthermore, since nitrogen (N), silicon (Si), and titanium (Ti) are hardly detectable in the anode electrode 14, it is determined that it is substantially free of nitrogen (N), silicon (Si), and titanium (Ti). Here, "substantially free" may refer to a concentration of at least less than 2.0 atm% in the measurement method (energy-dispersive X-ray spectroscopy) shown in Figure 6. Conversely, "substantially present" may refer to a concentration of at least 2.0 atm% or higher.

[0072] Next, the second portion 152 (TiN) of the Schottky electrode 15 contains titanium (Ti) as the main component at a concentration of 40.0 atm% to 50.0 atm%, and nitrogen (N) as the main component at a concentration of 35.0 atm% to 45.0 atm%. In addition, the second portion 152 of the Schottky electrode 15 contains carbon (C) as a minor component at a concentration of 5.0 atm% to 15.0 atm%. Furthermore, since oxygen (O), aluminum (Al), and silicon (Si) are hardly detectable in the second portion 152 of the Schottky electrode 15, it is substantially free of oxygen (O), aluminum (Al), and silicon (Si). Note that in Figure 6, although oxygen (O) is substantially absent, it is concentrated near the boundary 155. This is thought to be because, after the formation of the Schottky electrode 15, when the semiconductor wafer 75 (described later) is transferred to the anode electrode 14 forming apparatus 84 (for example, a sputtering apparatus), the surface of the Schottky electrode 15 comes into contact with air and oxidizes.

[0073] Next, the first portion 151 (oxygen-containing Ti) of the Schottky electrode 15 contains titanium (Ti) as its main component at a concentration of 50.0 atm% to 70.0 atm%. Furthermore, the first portion 151 of the Schottky electrode 15 contains carbon (C) at a concentration of 5.0 atm% to 15.0 atm%, nitrogen (N) at a concentration of 5.0 atm% to 15.0 atm%, and oxygen (O) at a concentration of 2.0 atm% to 10.0 atm% as minor components. Additionally, since aluminum (Al) and silicon (Si) are hardly detectable in the first portion 151 of the Schottky electrode 15, it is determined that it substantially does not contain aluminum (Al) and silicon (Si).

[0074] Here, the oxygen (O) contained in the first portion 151 of the Schottky electrode 15 is selectively concentrated near the boundary 156. In other words, it is concentrated closer to the boundary 156 than to the center in the depth direction (to the right on the horizontal axis) of the first portion 151 in Figure 6. More specifically, in the first portion 151, the oxygen (O) concentration profile 173 has a peak 177 closer to the boundary 156 than to the center in the depth direction of the first portion 151.

[0075] Next, semiconductor layer 2 (SiC) contains silicon (Si) at a concentration of 50.0 atm% to 60.0 atm% and carbon (C) as the main component at a concentration of 35.0 atm% to 45.0 atm%. Furthermore, since nitrogen (N), oxygen (O), aluminum (Al), and titanium (Ti) are hardly detectable in semiconductor layer 2, it is substantially free of nitrogen (N), oxygen (O), aluminum (Al), and titanium (Ti).

[0076] Figure 6 shows the analysis results of the constituent elements of the Schottky electrode 15 and the anode electrode 14 at the location of the first coating portion 18 of the Schottky electrode 15. The analysis results at the location of the first coating portion 18 may differ from the analysis results at the location of the second coating portion 19. For example, the first portion 151 of the Schottky electrode 15 does not have to substantially contain oxygen (O) in the second coating portion 19 (the portion in which the first portion 151 is in contact with the field insulating film 13). In other words, oxygen (O) may be selectively contained in the first coating portion 18 of the first portion 151. Also, as shown in Figure 5, the semiconductor layer 2 may contain oxygen 83 near the first main surface 3 directly below the second coating portion 19 (the portion in which the semiconductor layer 2 is in contact with the field insulating film 13). In other words, the semiconductor layer 2 may contain oxygen 83 near the first main surface 3 in the inactive region 10. In other words, it is preferable that the semiconductor layer 2 does not contain oxygen 83 in the portion that contacts the first portion 151 of the Schottky electrode 15. This suppresses an increase in the resistance of the active region 9 of the semiconductor layer 2, allowing the forward current to flow efficiently.

[0077] Figure 7 is a flowchart of the manufacturing process for Schottky barrier diode 1. Figures 8A, 8B to 15A, 15B are diagrams showing parts of the manufacturing process for Schottky barrier diode 1 in order. Of Figures 8A, 8B to 15A, 15B, the figures with "A" appended to the figure number are cross-sectional views corresponding to Figure 4, and the figures with "B" appended to the figure number are cross-sectional views corresponding to Figure 5.

[0078] First, a semiconductor wafer 75 is prepared (step S1) with reference to Figures 8A and 8B. The semiconductor wafer 75 serves as the base for the semiconductor layer 2. The semiconductor wafer 75 has a first wafer main surface 76 on one side and a second wafer main surface on the other side. The first wafer main surface 76 and the second wafer main surface correspond to the first main surface 3 and the second main surface 4 of the semiconductor layer 2, respectively.

[0079] Next, referring to Figures 9A and 9B, a mask 78 is formed on the first wafer main surface 76 of the semiconductor wafer 75. The mask 78 may be a hard mask such as silicon oxide or a photoresist. The mask 78 has openings 79 in the areas where the guard region 30 and the impurity region 40 are to be formed. Next, p-type impurities are injected into the first wafer main surface 76 of the semiconductor wafer 75 through the mask 78. This forms the guard region 30 and the impurity region 40 (step S2). After this, the mask 78 is removed.

[0080] Next, referring to Figures 10A and 10B, a cleaning process is performed on the first wafer main surface 76 of the semiconductor wafer 75 (step S3). In this process, for example, residue (particles) remaining after the removal of the mask 78, and resist residue used in dry etching, if necessary, are removed by the chemical solution 82. In this embodiment, a hydrofluoric acid (HF)-based cleaning solution is used as the chemical solution 82.

[0081] Next, referring to Figures 11A and 11B, oxygen 83 is introduced to the first wafer main surface 76 of the semiconductor wafer 75 (step S4). In this embodiment, oxygen 83 is introduced to the entire first wafer main surface 76, including the guard region 30 and the impurity region 40, by the oxygen plasma ashing process. In other words, oxygen 83 is introduced not only to the epitaxial layer 7, but also to the guard region 30 and the impurity region 40.

[0082] It is preferable that oxygen 83 is selectively introduced to the surface layer of the first wafer main surface 76 of the semiconductor wafer 75. This prevents oxygen 83 from remaining in the active region 9 after the annealing process described later (see Figures 15A and 15B). The ashing conditions for the oxygen plasma may be, for example, a chamber pressure of 10 Pa or more and 1000 Pa or less, an output of 0.1 kW or more and 5 kW or less, and an oxygen gas flow rate of 100 sccm or more and 1000 sccm or less.

[0083] Thus, the oxygen plasma irradiation process is performed after the cleaning process of the first main surface 3 of the semiconductor layer 2 (see Figures 10A and 10B). Therefore, it is possible to prevent the oxygen 83 introduced into the semiconductor layer 2 by irradiation from being removed in the cleaning process.

[0084] Next, referring to Figures 12A and 12B, a field insulating film 13 is formed on the first wafer main surface 76 of the semiconductor wafer 75 (step S5). The field insulating film 13 may be formed, for example, by CVD (Chemical Vapor Deposition).

[0085] Next, referring to Figures 13A and 13B, the first portion 151 of the Schottky electrode 15 is formed on the first wafer main surface 76 of the semiconductor wafer 75 (step S6). For example, the semiconductor wafer 75 is brought into an apparatus 84 for forming the electrode. In this embodiment, the apparatus 84 is a sputtering apparatus, but it may be a deposition apparatus. Then, argon (Ar) gas is introduced into the chamber of the apparatus 84, and sputtering targeting Ti is performed without introducing nitrogen (N2) gas. As a result, the first portion 151, mainly composed of Ti, is deposited on the semiconductor wafer 75.

[0086] Next, referring to Figures 14A and 14B, a second portion 152 is formed on the first portion 151 of the Schottky electrode 15 (step S7). More specifically, following the deposition of the first portion 151 (without removing the semiconductor wafer 75 from the apparatus 84), Ti is further deposited on the first wafer main surface 76 of the semiconductor wafer 75 while introducing nitrogen (N2) gas into the chamber of the apparatus 84. As a result, a second portion 152, mainly composed of Ti and N, is deposited on the semiconductor wafer 75, forming a Schottky electrode 15 including the first portion 151 and the second portion 152.

[0087] Next, referring to Figures 15A and 15B, an anode electrode 14 is formed on the Schottky electrode 15 (step S8). For example, the semiconductor wafer 75 may be removed from the apparatus 84, the targets in the chamber of the apparatus 84 may be changed to Al and Cu, and then the sputtering method may be performed again in the apparatus 84. This deposits an anode electrode 14 mainly composed of Al and Cu. During this temporary removal, the surface of the second portion 152 of the Schottky electrode 15 may be oxidized in the air.

[0088] Next, unwanted portions of the anode electrode 14 and Schottky electrode 15 are removed by patterning. After that, an annealing process is performed (step S9). During this annealing process, the oxygen 83 introduced into the surface layer of the first wafer main surface 76 of the semiconductor wafer 75 diffuses into the first portion 151 of the Schottky electrode 15, and the first portion 151 becomes infused with oxygen 83. At this time, the oxygen 83 introduced into the first wafer main surface 76 in contact with the field insulating film 13 may remain in the semiconductor wafer 75 even after the annealing process.

[0089] Next, for example, a passivation layer 20 is formed on the anode electrode 14 by CVD (step S10). Next, for example, a cathode electrode 8 is formed on the second wafer main surface 77 of the semiconductor wafer 75 by sputtering (step S11). After that, the semiconductor wafer 75 is cut, and a plurality of Schottky barrier diodes 1 are cut out. The aforementioned Schottky barrier diode 1 is obtained through the above process.

[0090] As described above, the Schottky barrier diode 1 has a first portion 151 that is selectively formed near the first main surface 3 of the semiconductor layer 2 in the thickness direction of the Schottky electrode 15. This first portion 151 is made of Ti containing oxygen (O). This makes it possible to reduce the forward voltage of the Schottky electrode 15. This effect can be explained, for example, by referring to Figures 6 and 16 to 18A, 18B.

[0091] Figure 16 shows the results of the analysis of the constituent elements of the Schottky electrode and anode electrode of the Schottky barrier diode for sample 2. Figures 17A and 17B are the IV curves of the Schottky barrier diodes for samples 1 to 3. Figures 18A and 18B are the IV curves of the Schottky barrier diodes for samples 4 and 5.

[0092] Here, the forward voltage reduction effect of the Schottky barrier diode 1 of this disclosure is explained by comparing the forward voltages of five samples 1 to 5.

[0093] Sample 1 is the aforementioned Schottky barrier diode 1 manufactured according to the flow chart in Figure 7. Therefore, the constituent elements of the Schottky electrode 15 and anode electrode 14 of Sample 1 are as shown in Figure 6.

[0094] Sample 2 is a Schottky barrier diode manufactured without performing the "ashing process" in step S4 in the flow chart of Figure 7. If the anode electrode, the second part of the Schottky electrode, the first part of the Schottky electrode, and the semiconductor layer of Sample 2 are denoted as anode electrode 161, second part of Schottky electrode 162, first part of Schottky electrode 163, and semiconductor layer 164, respectively, then their constituent elements are as shown in Figure 16. In Figure 16, reference numerals 165, 166, and 167 indicate the boundary between the anode electrode 161 and the second part of the Schottky electrode 162, the boundary between the second part of the Schottky electrode 162 and the first part 163, and the boundary between the Schottky electrode (first part 163) and the semiconductor layer 164, respectively. Concentration profiles 181-186 in Figure 16 represent the concentration profiles of carbon (C), nitrogen (N), oxygen (O), aluminum (Al), silicon (Si), and titanium (Ti), respectively.

[0095] Referring to Figures 6 and 16, the main difference between the Schottky barrier diode of Sample 2 and the Schottky barrier diode 1 of Sample 1 is that the first portion 163 of the Schottky electrode of Sample 2 substantially contains no oxygen (O). In other words, in Figure 6, the oxygen (O) concentration profile 173 contains oxygen (O) at a concentration of 2.0 atm% to 10.0 atm% near the boundary 156, whereas in the oxygen (O) concentration profile 183 of Figure 16, almost no oxygen (O) is detected near the boundary 167.

[0096] Next, Sample 3 is a Schottky barrier diode manufactured by reversing the order of the "cleaning process" in step S3 and the "ashing process" in step S4 in the flow chart of Figure 7. In other words, in the manufacturing process of Sample 3, oxygen 83 is introduced to the first main surface 76 of the semiconductor wafer 75, and then the chemical solution 82 is supplied to the first main surface 76 to perform the cleaning process.

[0097] Sample 4 is a Schottky barrier diode in which the Schottky electrode (mainly composed of Ti) of the Schottky barrier diode of Sample 2 is replaced with a Schottky electrode whose main component is molybdenum (Mo). In other words, in the manufacturing process of Sample 4, the "ashing process" in step S4 is not performed in the flow chart of Figure 7, and the Schottky electrode is then formed by sputtering targeting molybdenum (Mo).

[0098] Sample 5 is a Schottky barrier diode in which the Schottky electrode (mainly composed of Ti) of the Schottky barrier diode 1 of Sample 1 is replaced with a Schottky electrode mainly composed of molybdenum (Mo). In other words, in the manufacturing process of Sample 5, in the flow chart of Figure 7, the "cleaning process" in step S3 and the "ashing process" in step S4 are performed in that order, and then the Schottky electrode is formed by sputtering targeting molybdenum (Mo). In other words, the difference from Sample 4 is that the cleaning process and ashing process were performed.

[0099] Referring to Figures 17A, 17B and 18A, 18B, the horizontal axis of each figure shows the magnitude of the forward voltage applied to each sample 1-5. The vertical axis of each figure shows the magnitude of the forward current flowing through each sample 1-5. Figures 17B and 18B are logarithmic scale versions of the vertical axes of the graphs in Figures 17A and 18B, respectively. In Figures 17A and 17B, the solid line shows the IV curve of sample 1, the dashed line shows the IV curve of sample 2, and the dashed line shows the IV curve of sample 3. In Figures 18A and 18B, the solid line shows the IV curve of sample 4, and the dashed line shows the IV curve of sample 5.

[0100] Comparing the forward voltages of samples 1 to 5, it can be seen that Schottky barrier diode 1 of sample 1 rises at a lower voltage than the other Schottky barrier diodes of samples 2 to 5. In other words, it is thought that the forward voltage was reduced because the first portion 151 of the Schottky electrode 15 is made of Ti and this first portion 151 contains oxygen.

[0101] Referring to Figures 17A and 17B, Sample 2 has a first portion 163 made of Ti, but does not contain oxygen (O), so it is thought that the forward voltage was higher than that of Sample 1. Also, in Sample 3, oxygen 83 was introduced to the first wafer main surface 76 of the semiconductor wafer 75 by ashing, but it is thought that the oxygen 83 introduced to the first wafer main surface 76 was removed by the chemical solution 82 after the cleaning process was performed. As a result, it is thought that there was no diffusion of oxygen 83 from the semiconductor wafer 75 to the first portion 151 even after annealing (step S9 in Figure 7).

[0102] On the other hand, referring to Figures 18A and 18B, in Sample 5, similar to Sample 1, the "cleaning process" in step S3 and the "ashing process" in step S4 are performed in this order in the flow chart of Figure 7. However, unlike the comparison between Sample 1 and Sample 2, because the first part 151 is composed of molybdenum (Mo), the forward voltage increased compared to Sample 4, in which the ashing process was not performed. [Second Embodiment] Figure 19 is a schematic cross-sectional view of a Schottky barrier diode 1R according to a second embodiment of the present disclosure. Figure 20 is a plan view of the Schottky barrier diode 1R of Figure 19 with the structure above the first main surface 3 of the semiconductor layer 2 removed. Figure 21 is an enlarged view of the portion enclosed by the dashed line XXI in Figure 19. Figure 22A is a circuit diagram illustrating the voltage drop around the inner impurity region 45 contained in the Schottky barrier diode 1R of Figure 19. Figure 22B is a cross-sectional view illustrating the voltage drop around the inner impurity region 45. The main difference between the Schottky barrier diode 1R according to the second embodiment and the Schottky barrier diode 1 according to the first embodiment (see Figure 2) is that the lattice defect region 60 is formed on the surface layer of the surface 7a of the epitaxial layer 7.

[0103] Referring to Figures 19 to 21, the lattice defect region 60 is a region where the number of lattice defects is greater than that of the epitaxial layer 7. The lattice defect region 60 is formed by the injection of noble gas atoms such as argon (Ar) into the epitaxial layer 7. Therefore, the lattice defect region 60 may also be called a noble gas-containing region. The impurity concentration in the lattice defect region 60 is, for example, 10 × 10 19 cm -3 The above 10 x 10 21 cm -3 The following is also acceptable.

[0104] The lattice defect region 60 is in contact with the Schottky electrode 15. When noble gas atoms are injected into the epitaxial layer 7, the crystal lattice of the SiC constituting the epitaxial layer 7 is destroyed, and lattice defects are generated. Therefore, even though the lattice defect region 60 is in contact with the Schottky electrode 15, it does not form a Schottky junction with the Schottky electrode 15, and thus inhibits the flow of current from the Schottky electrode 15 to the epitaxial layer 7. In other words, because the lattice defect region 60 has more lattice defects than the epitaxial layer 7, it may be a high-resistance layer with higher resistance than the epitaxial layer 7.

[0105] The lattice defect region 60 is located around one of the multiple linear impurity regions 41.

[0106] More specifically, the impurity region 40 includes an inner impurity region 45 located inside the lattice defect region 60 so as to be in contact with the lattice defect region 60, and an outer impurity region 46 located outside the lattice defect region 60. Of the multiple linear impurity regions 41, the linear impurity region 41 located inside the lattice defect region 60 functions as the inner impurity region 45, and of the multiple linear impurity regions 41, the linear impurity region 41 located outside the lattice defect region 60 functions as the outer impurity region 46. The inner impurity region 45 is sandwiched between the lattice defect region 60 from both sides in the second direction Y.

[0107] The outer impurity region 46 includes a pair of outer contact impurity regions 47 that are in contact with the lattice defect region 60 and are located on the opposite side of the lattice defect region 60 from the inner impurity region 45, and a plurality of outer separated impurity regions 48 that are located away from the lattice defect region 60 and are located on the opposite side of the lattice defect region 60 from the inner impurity region 45.

[0108] The lattice defect region 60 is in contact with the inner impurity region 45 from both sides in the second direction Y. In the example of Figure 20, both ends of the lattice defect region 60 in the first direction X are in contact with the first guard region 31 at their inner ends. Unlike the example of Figure 20, both ends of the lattice defect region 60 in the first direction X are not in contact with the first guard region 31 at their inner ends, but may be facing the first guard region 31 via the epitaxial layer 7.

[0109] The lattice defect region 60 includes a first lattice defect region 61 that extends linearly in the first direction X and is in contact with the inner impurity region 45 from one side in the second direction Y, and a second lattice defect region 62 that extends linearly in the first direction X and is in contact with the inner impurity region 45 from the other side in the second direction Y.

[0110] In a plan view, the outer contact impurity region 47 on one side in the second direction Y is sandwiched between the first lattice defect region 61 and the epitaxial layer 7. In a plan view, the outer contact impurity region 47 on the other side in the second direction Y is sandwiched between the second lattice defect region 62 and the epitaxial layer 7.

[0111] The bottom portion 60a of the lattice defect region 60 includes a pair of curved portions toward the semiconductor substrate 6 and a flat portion connecting the curved portions. The flat portion of the bottom portion 60a of the lattice defect region 60 is formed flush with the flat portion of the bottom portion 45a of the inner impurity region 45 and the flat portion of the bottom portion 47a of the outer contact impurity region 47.

[0112] Unlike the example shown in Figure 21, the flat portion of the bottom 60a of the lattice defect region 60 may be located closer to the first main surface 3 than the flat portion of the bottom 45a of the inner impurity region 45 and the flat portion of the bottom 47a of the outer contact impurity region 47. Conversely, the flat portion of the bottom 60a of the lattice defect region 60 may be located closer to the second main surface 4 than the flat portion of the bottom 45a of the inner impurity region 45 and the flat portion of the bottom 47a of the outer contact impurity region 47. The Schottky barrier diode 1R of the second embodiment provides the same effects as the Schottky barrier diode 1 of the first embodiment. On the other hand, in a configuration in which a lattice defect region 60 is not provided, as in the Schottky barrier diode 1 of the first embodiment, if the thickness TE of the epitaxial layer 7 is large, the voltage drop due to the epitaxial layer 7 becomes large, and the voltage applied to the pn junction PJ may become small.

[0113] Therefore, as in the second embodiment, by providing a lattice defect region 60, the current I1 flowing through the lattice defect region 60 can be suppressed, making the current I1 smaller than the current I2 flowing through the Schottky junction SJ. As a result, as shown in Figure 22A, the voltage drop V1 due to the first neighboring portion 70 located near the lattice defect region 60 in the epitaxial layer 7 is reduced and becomes smaller than the voltage drop V2 due to the second neighboring portion 71 located near the Schottky junction SJ in the epitaxial layer 7.

[0114] Therefore, the voltage drop in the epitaxial layer 7 near the inner impurity region 45 is small, similar to the voltage drop V1 due to the first nearby region 70. As a result, the potential difference VP across the pn junction PJ1 formed between the inner impurity region 45 and the epitaxial layer 7 can be made larger than the potential difference VS across the Schottky junction SJ. Consequently, a sufficient potential difference VP across the pn junction PJ1 formed between the inner impurity region 45 and the epitaxial layer 7 can be ensured. Therefore, surge resistance can be improved.

[0115] As shown in Figure 21B, if the distance L between the Schottky junction SJ and the inner impurity region 45 is greater than the thickness TE of the epitaxial layer 7, the flow of current in the portion of the epitaxial layer 7 located between the inner impurity region 55 and the semiconductor substrate 6 can be further suppressed. The distance L between the Schottky junction SJ and the inner impurity region 45 corresponds to the sum of the width W1 of the outer contact impurity region 47 and the width W2 of the first lattice defect region 61 (width of the second lattice defect region 62).

[0116] The area inside the boundary 73 between the Schottky junction SJ and the pn junction PJ2 formed between the outer contact impurity region 47 and the epitaxial layer 7, by a width equal to the thickness TE of the epitaxial layer 7 toward the inner impurity region 45, is called the inner region IR, and the area outside the inner region IR is called the outer region OR. In the inner region IR, the current flowing through the epitaxial layer 7 is effectively suppressed by the lattice defect region 60. If the distance L between the Schottky junction SJ and the inner impurity region 45 is greater than the thickness TE of the epitaxial layer 7, then the inner region IR is established in the epitaxial layer 7. In other words, if the distance L between the Schottky junction SJ and the inner impurity region 45 is greater than the thickness TE of the epitaxial layer 7, then the first neighborhood portion 70 is located within the inner region IR.

[0117] While embodiments of this disclosure have been described above, this disclosure can also be implemented in other forms.

[0118] For example, a configuration in which the conductivity types of each semiconductor portion of the Schottky barrier diode 1,1R are inverted may be adopted. For instance, in the Schottky barrier diode 1,1R, the p-type portion may be n-type, and the n-type portion may be p-type.

[0119] Furthermore, the structure of the oxygen-containing Schottky electrode 15(Ti) described above is not limited to discrete products such as Schottky barrier diodes 1,1R, but can also be applied to Schottky junctions formed on composite elements that combine transistors such as MOSFETs and IGBTs with Schottky barrier diodes, or on LSIs that have many circuit elements including Schottky barrier diodes mounted on them.

[0120] This application corresponds to Japanese Patent Application No. 2021-064154, filed with the Japan Patent Office on April 5, 2021, and the full disclosure of this application is incorporated herein by reference. [Explanation of Symbols]

[0121] 1: Schottky barrier diode 1R: Schottky barrier diode 2: Semiconductor layer 3: First main surface 4: Second main surface 5a: Side 5b: Side 5c: Side 5d: side 6: Semiconductor substrates 6a: Surface 7: Epitaxial layer 7a: Surface 8: Cathode electrode 9: Active area 10: Inactive area 12:Aperture 13: Field insulating film 13a: 1st page 13b: 2nd side 13c: Inside surface 13d: Outer surface 14: Anode electrode 15: Schottky electrode 16: Connection part 16a: Surface 18: First covering section 19: Second covering section 20: Passivation layer 21: Pad opening 22: Connecting member 23: Connection area 30: Guard Area 31: First Guard Area 32: Second Guard Area 40: Impurity region 40a: Bottom 41: Linear impurity region 45: Inner impurity region 45a: Bottom 46:Outer impurity region 47:Outer contact impurity area 47a: Bottom 48:Outer spaced impurity region 55: Inner impurity region 60: Lattice defect region 60a: Bottom 61: First lattice defect region 62: Second lattice defect region 70: First Neighborhood 71: Second Neighborhood 73: Boundary 75: Semiconductor wafers 76: Main surface of the first wafer 77: Main surface of the second wafer 78: Mask 79 :Aperture 82: Chemical solution 83: Oxygen 84: Equipment 151 :1st part 152 :Second part 153: Boundary 154: End face 155: Boundary 156: Boundary 161: Anode electrode 162 :Second part 163 :1st part 164: Semiconductor layer 165: Boundary 166: Boundary 167: Boundary 171: Carbon (C) concentration profile 172: Nitrogen (N) Concentration Profile 173: Oxygen (O) concentration profile 174: Aluminum (Al) Concentration Profile 175: Silicon (Si) concentration profile 176: Titanium (Ti) Concentration Profile 177: Peak 181: Carbon (C) concentration profile 182: Nitrogen (N) Concentration Profile 183: Oxygen (O) concentration profile 184: Aluminum (Al) Concentration Profile 185: Silicon (Si) concentration profile 186: Titanium (Ti) Concentration Profile PJ: pn junction PJ1: pn junction PJ2 :pn junction SJ: Schottky junction

Claims

1. Semiconductor layer, The semiconductor layer includes a Schottky electrode formed on the first surface of the semiconductor layer, which forms a Schottky junction between itself and the semiconductor layer. The Schottky electrode has a first portion which is selectively formed in the vicinity of the first surface of the semiconductor layer in the thickness direction of the Schottky electrode and is composed of oxygen-containing Ti. When analyzed in a first direction from the Schottky electrode toward the semiconductor layer using a predetermined quantitative analysis method, the oxygen concentration profile corresponding to the first portion has a peak closer to the boundary between the first portion and the semiconductor layer than to the central position of the first portion in the first direction. A semiconductor device wherein the concentration at the peak of the oxygen concentration profile is 2.0 atm% or more and 10.0 atm% or less.

2. A semiconductor layer, The semiconductor layer includes a Schottky electrode formed on the first surface of the semiconductor layer, which forms a Schottky junction between itself and the semiconductor layer. The Schottky electrode has a first portion which is selectively formed in the vicinity of the first surface of the semiconductor layer in the thickness direction of the Schottky electrode and is composed of oxygen-containing Ti. The semiconductor layer includes a first conductivity type semiconductor layer, The material further includes an impurity region of a second conductivity type that is selectively formed on the first surface of the semiconductor layer so as to be in contact with the Schottky electrode, and that forms a pn junction with the semiconductor layer. A lattice defect region is selectively formed on the first surface of the semiconductor layer so as to be in contact with the Schottky electrode, and further includes a lattice defect region having more lattice defects than the semiconductor layer. The semiconductor device wherein the impurity region includes a first region formed inside the lattice defect region so as to be in contact with the lattice defect region.

3. The semiconductor device according to claim 1, wherein the Schottky electrode is formed on the first portion and has a second portion composed of Ti and N.

4. The semiconductor device according to claim 3, wherein the oxygen concentration near the Schottky junction is higher than both the oxygen concentration near the interface between the first and second portions and the average oxygen concentration of the semiconductor layer.

5. The semiconductor device according to claim 2, wherein the Schottky electrode is formed on the first portion and has a second portion composed of Ti and N.

6. The semiconductor device according to claim 5, wherein the oxygen concentration near the Schottky junction is higher than both the oxygen concentration near the interface between the first and second portions and the average oxygen concentration of the semiconductor layer.

7. The semiconductor device according to claim 2, 5, or 6, wherein, when analyzed in a first direction from the Schottky electrode toward the semiconductor layer using a predetermined quantitative analysis method, the oxygen concentration profile corresponding to the first portion has a peak closer to the boundary between the first portion and the semiconductor layer than to the central position of the first portion in the first direction.

8. The semiconductor device according to claim 7, wherein the concentration at the peak of the oxygen concentration profile is 2.0 atm% or more and 10.0 atm% or less.

9. The semiconductor layer includes an insulating layer formed on the first surface of the semiconductor layer and having an opening that partially exposes the first surface. The Schottky electrode includes a first covering portion that covers the first surface of the semiconductor layer within the opening of the insulating layer, and a second covering portion formed outside the opening of the insulating layer and covering the insulating layer. The semiconductor device according to any one of claims 1 to 8, wherein the first portion selectively contains oxygen in the first coating portion of the Schottky electrode and does not contain oxygen in the second coating portion.

10. The semiconductor device according to any one of claims 1 to 9, wherein the semiconductor layer does not contain oxygen in the vicinity of the first surface at the Schottky junction.

11. The semiconductor device according to any one of claims 1 to 10, comprising a surface electrode formed on the Schottky electrode and composed of an Al alloy or Al.

12. The semiconductor device according to claim 11, wherein the Al alloy includes at least one of AlCu alloy, AlSi alloy, and AlSiCu alloy.

13. The semiconductor layer includes a first conductivity type semiconductor layer, The semiconductor device according to claim 1, 3, or 4, further comprising an impurity region of a second conductivity type selectively formed on the first surface of the semiconductor layer so as to be in contact with the Schottky electrode, and which forms a pn junction with the semiconductor layer.

14. The semiconductor device according to claim 2 or 13, wherein the first conductivity type is n-type and the second conductivity type is p-type.

15. The semiconductor device according to any one of claims 1 to 13, wherein the semiconductor layer includes a SiC semiconductor layer.

16. A step of introducing oxygen to the first surface of a semiconductor layer having a first surface, A step of forming a Schottky electrode having a first portion made of Ti in contact with the first surface of the semiconductor layer by depositing Ti on the first surface of the semiconductor layer, The process includes diffusing the oxygen introduced into the semiconductor layer to the first portion of the Schottky electrode by annealing, A method for manufacturing a semiconductor device, wherein the Schottky electrode formation step includes a step of forming a second portion composed of Ti and N on the first portion by further depositing Ti in an N2 atmosphere after the formation of the first portion.

17. The process includes cleaning the first surface of the semiconductor layer with a chemical solution. The method for manufacturing a semiconductor device according to claim 16, wherein the oxygen introduction step includes a step of introducing oxygen into the semiconductor layer by irradiating the first surface of the semiconductor layer, which has been cleaned with the chemical solution, with oxygen plasma.

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