Semiconductor equipment

Abstract

To reduce turn-on loss of a semiconductor device.SOLUTION: There is provided a semiconductor device in which one mesa part among two mesa parts contacting a gate trench part is an active mesa part where an emitter part of a first conductivity type having higher doping concentration than a drift part is arranged while contacting to the gate trench part, and the other mesa part among the two mesa parts contacting the gate trench part is a dummy mesa part not having an emitter part. A dummy contact resistance being a resistance between the dummy mesa part and an emitter electrode is 1000 times or more of an active contact resistance being a resistance between the active mesa part and the emitter electrode.SELECTED DRAWING: Figure 2

Description

[Technical Field] 【0001】 This invention relates to a semiconductor device. [Background technology] 【0002】 Conventionally, semiconductor devices such as IGBTs are known (see, for example, Patent Document 1). Patent document 1 WO2017 / 033315 [Overview of the Initiative] [Problems that the invention aims to solve] 【0003】 In semiconductor devices, it is preferable to reduce switching losses. [Means for solving the problem] 【0004】 To solve the above problems, a first embodiment of the present invention provides a semiconductor device. The semiconductor device may include a semiconductor substrate having an upper surface and a lower surface, and having a drift region of a first conductivity type. The semiconductor device may include an emitter electrode provided above the upper surface of the semiconductor substrate. The semiconductor device may include a plurality of trench portions provided on the upper surface of the semiconductor substrate and arranged with spacing between them in the arrangement direction. The semiconductor device may include a plurality of mesa portions sandwiched between each of the trench portions inside the semiconductor substrate. The plurality of trench portions may include a gate trench portion to which a gate voltage is applied. One of the two mesa portions in contact with the gate trench portion may be an active mesa portion in which an emitter region of a first conductivity type with a doping concentration higher than that of the drift region is arranged in contact with the gate trench portion. The other of the two mesa portions in contact with the gate trench portion may be a dummy mesa portion that does not have the emitter region. The dummy contact resistance, which is the resistance between the dummy mesa portion and the emitter electrode, may be 1000 times or more the active contact resistance, which is the resistance between the active mesa portion and the emitter electrode. 【0005】 The dummy contact resistance may be 5000 times or more the active contact resistance. 【0006】 The dummy contact resistance may be 30,000 times or more the active contact resistance. 【0007】 The dummy contact resistance may be 50,000 times or more the active contact resistance. 【0008】 The dummy contact resistance may be 100,000 times or less the active contact resistance. 【0009】 The semiconductor device may include a resistive film provided between the dummy mesa portion and the emitter electrode, which is made of a material with a higher volume resistivity than the emitter electrode. 【0010】 The dummy mesa portion may have a region of a second conductivity type exposed on the upper surface of the semiconductor substrate. The active mesa portion may have a contact region of a second conductivity type with a higher doping concentration than the region of the second conductivity type in the dummy mesa portion. 【0011】 The active mesa portion may have a base region of a second conductivity type provided between the drift region and the emitter region. The doping concentration of the second conductivity type region of the dummy mesa portion may be less than or equal to that of the base region. 【0012】 The semiconductor device may include an interlayer insulating film provided between the upper surface of the semiconductor substrate and the emitter electrode. The interlayer insulating film may be provided with a first contact hole connecting the emitter electrode and the active mesa portion, and a second contact hole connecting the emitter electrode and the dummy mesa portion. In a top view, the total area of ​​the second contact holes for one dummy mesa portion may be smaller than the total area of ​​the first contact holes for one active mesa portion. 【0013】 The active mesa portion may be provided inside the semiconductor substrate from the upper surface of the semiconductor substrate and may have a trench contact connected to the emitter electrode. The trench contact may not be provided in the dummy mesa portion. 【0014】 The active mesa portion may have a base region of a second conductivity type provided between the drift region and the emitter region. The dummy mesa portion may have the base region between the drift region and the upper surface of the semiconductor substrate. The active mesa portion and the dummy mesa portion may have an accumulation region of a first conductivity type having a higher doping concentration than the drift region between the base region and the drift region. The integrated concentration obtained by integrating the doping concentration of the accumulation region of the dummy mesa portion in the depth direction may be larger than the integrated concentration obtained by integrating the doping concentration of the accumulation region of the active mesa portion in the depth direction. 【0015】 The gate trench portion may include a gate conductive portion and a gate insulating film provided between the gate conductive portion and the semiconductor substrate. The gate insulating film in contact with the dummy mesa portion may be thinner than the gate insulating film in contact with the active mesa portion. 【0016】 The plurality of trench portions may be arranged adjacent to the gate trench portion with the dummy mesa portion sandwiched therebetween in the arrangement direction, and may include a dummy trench portion to which a voltage different from the gate voltage is applied. Among the mesa portions in contact with the dummy trench portion, the mesa portion on the gate trench portion side may be a first dummy mesa portion having no emitter region, and the mesa portion on the side opposite to the gate trench portion may be a second dummy mesa portion having no emitter region. The dummy contact resistance of the first dummy mesa portion may be lower than the dummy contact resistance of the second dummy mesa portion. 【0017】 The plurality of mesa portions may include a third dummy mesa portion that does not have the emitter region, and a fourth dummy mesa portion that is disposed closer to an end portion of the semiconductor substrate than the third dummy mesa portion in the array direction and that does not have the emitter region. The dummy contact resistance of the fourth dummy mesa portion may be lower than the dummy contact resistance of the third dummy mesa portion. 【0018】 The semiconductor device may include a wiring connected to a connection region on an upper surface of the emitter electrode. The plurality of mesa portions may include a fifth dummy mesa portion that overlaps the connection region in a top view and that does not have the emitter region, and a sixth dummy mesa portion that does not overlap the connection region in a top view and that does not have the emitter region. The dummy contact resistance of the fifth dummy mesa portion may be lower than the dummy contact resistance of the sixth dummy mesa portion. 【0019】 The current-voltage change rate characteristic indicating the relationship between the collector current flowing through the semiconductor device and the voltage change rate between the collector and the emitter when the semiconductor device is turned on may include a peak portion where the voltage change rate shows a maximum value, and a maintenance increase region where the voltage change rate is maintained or increased in a direction of increasing the collector current from the peak portion. 【0020】 The current-voltage change rate characteristic may be such that the voltage change rate when the collector current is equal to the rated current of the semiconductor device is greater than the voltage change rate when the collector current is 5% of the rated current of the semiconductor device. 【0021】 The current-voltage change rate characteristic may include a valley portion where the voltage change rate shows a minimum value in a region where the collector current ranges from 5% to 100% of the rated current of the semiconductor device. 【0022】 A second embodiment of the present invention provides a semiconductor device. The semiconductor device may include a semiconductor substrate having an upper surface and a lower surface, and having a drift region of a first conductivity type. The semiconductor device may include an emitter electrode provided above the upper surface of the semiconductor substrate. The semiconductor device may include a plurality of trench portions provided on the upper surface of the semiconductor substrate and arranged with spacing between them in the arrangement direction. The semiconductor device may include a plurality of mesa portions within the semiconductor substrate, sandwiched between each of the trench portions. The plurality of trench portions may include a gate trench portion to which a gate voltage is applied. One of the two mesa portions in contact with the gate trench portion may be an active mesa portion in which an emitter region of a first conductivity type with a doping concentration higher than that of the drift region is provided in contact with the gate trench portion. The other of the two mesa portions in contact with the gate trench portion may be a dummy mesa portion that does not have the emitter region. The current-voltage change rate characteristic, which shows the relationship between the collector current flowing through the semiconductor device and the rate of change of the collector-emitter voltage when the semiconductor device is turned on, may have a peak portion in which the rate of change of the voltage shows a maximum value, and a sustained-increase region in which the rate of change of the voltage is maintained or increases in the direction of increasing the collector current from the peak portion. 【0023】 The current-voltage change rate characteristic may be such that the voltage change rate when the collector current is the rated current is greater than the voltage change rate when the collector current is 10% of the rated current of the semiconductor device. 【0024】 The current-voltage change rate characteristic may have a valley in which the voltage change rate shows a minimum value in the region where the collector current is between 10% and 100% of the rated current of the semiconductor device. 【0025】 It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. Subcombinations of these features may also constitute an invention. [Brief explanation of the drawing] 【0026】 [Figure 1] This is an example of a top view of a semiconductor device 100. [Figure 2] Figure 1 shows an example of a cross-section AA. [Figure 3] This figure shows an example of the arrangement of the resistive film 210 in a top view. [Figure 4] This figure shows another example of a cross-section of the transistor section 70. [Figure 5] This figure shows an example of the arrangement of the trench contacts 220 in a top view. [Figure 6] This figure shows another example of a cross-section of the transistor section 70. [Figure 7] This figure shows an example of the arrangement of the P-shaped region of the dummy mesa portion 61 in a top view. [Figure 8] This figure shows another example of a cross-section of the transistor section 70. [Figure 9] This figure shows an example of the arrangement of the contact holes 54 in the dummy mesa portion 61 in a top view. [Figure 10] This figure shows an example of the time waveforms of the collector-emitter voltage Vce and gate voltage Vge of the semiconductor device 100 during turn-on. [Figure 11] Figure 10 is a magnified view of the gate voltage waveform in region 300. [Figure 12] This figure shows the relationship between the contact resistance ratio R2 / R1 and the amount of rise in gate voltage Vge. [Figure 13] This figure shows the relationship between the contact resistance ratio R2 / R1 and the turn-on loss. [Figure 14] This figure shows an example of the current (Ic)-voltage change rate (dv / dt) characteristics during turn-on. [Figure 15] This figure shows an example of the current (Ic)-voltage change rate (dv / dt) characteristics during turn-on. [Figure 16] This figure shows another example of a cross-section of the semiconductor device 100. [Figure 17] This figure shows another example of a cross-section of the semiconductor device 100. [Figure 18] This figure shows another example of the gate trench section 40. [Figure 19] This figure shows a top view of the semiconductor device 100, illustrating a portion of the dummy mesa portion 61. [Figure 20] This figure shows a top view of the semiconductor device 100, illustrating a portion of the dummy mesa portion 61. [Modes for carrying out the invention] 【0027】 The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the invention as defined in the claims. Not all combinations of features described in the embodiments are necessarily essential to the solution of the invention. 【0028】 In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "top," and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the top surface, and the other surface as the bottom surface. The directions of "top" and "bottom" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted. 【0029】 In this specification, technical matters may be described using the Cartesian coordinate axes, the X, Y, and Z axes. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z and -Z axes. 【0030】 In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction. In this specification, when the term "top side of the semiconductor substrate" is used, it refers to the region from the center to the top surface in the depth direction of the semiconductor substrate. When the term "bottom side of the semiconductor substrate" is used, it refers to the region from the center to the bottom surface in the depth direction of the semiconductor substrate. 【0031】 In this specification, the terms "identical" or "equal" may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 10%. 【0032】 In this specification, the conductivity type of a doped region containing impurities is described as P-type or N-type. N-type and P-type are examples of first and second conductivity types. N-type may be the first conductivity type and P-type the second conductivity type, or P-type may be the first conductivity type and N-type the second conductivity type. In this specification, impurities may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as dopants. In this specification, doping means introducing a donor or acceptor into a semiconductor substrate to make it a semiconductor exhibiting an N-type conductivity type or a P-type conductivity type. 【0033】 In this specification, doping concentration means the concentration of the donor or acceptor at thermal equilibrium. In this specification, net doping concentration means the net concentration obtained by adding up the charge polarity, with the donor concentration being the concentration of positive ions and the acceptor concentration being the concentration of negative ions. As an example, the donor concentration is N D , the acceptor concentration is N A Therefore, the net doping concentration at any given position is |N D -N A | 【0034】 Donors have the function of supplying electrons to a semiconductor. Acceptors have the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, VOH defects, which are composed of vacancies (V), oxygen (O), and hydrogen (H) present in a semiconductor, function as electron donors. 【0035】 In this specification, when P+ or N+ is mentioned, it means a higher doping concentration than P or N, and when P- or N- is mentioned, it means a lower doping concentration than P or N. Furthermore, when P++ or N++ is mentioned in this specification, it means a higher doping concentration than P+ or N+. 【0036】 In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electrical activation state. Chemical concentration (atomic density) can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by voltage-capacitance (CV) spectroscopy. The carrier density measured by spheroidal resistance (SR) spectroscopy may be used as the net doping concentration. The carrier density measured by CV or SR spectroscopy may be the value at thermal equilibrium. In the N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier density in that region may be used as the donor concentration. Similarly, in the P-type region, the carrier density in that region may be used as the acceptor concentration. 【0037】 If the concentration distribution of donor, acceptor, or net doping has a peak, that peak value may be used as the concentration of donor, acceptor, or net doping in that region. If the concentrations of donor, acceptor, or net doping are nearly uniform, the average value of the concentrations of donor, acceptor, or net doping in that region may be used as the concentration of donor, acceptor, or net doping. 【0038】 The carrier density measured by the SR method may be lower than the donor or acceptor concentration. When measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value for the crystalline state in the range where current flows. The decrease in carrier mobility occurs because carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc. 【0039】 The donor or acceptor concentrations calculated from carrier densities measured by the CV or SR method may be lower than the chemical concentrations of the elements exhibiting donor or acceptor properties. For example, in silicon semiconductors, the donor concentrations of phosphorus or arsenic, or the acceptor concentration of boron, are approximately 99% of their respective chemical concentrations. On the other hand, the donor concentration of hydrogen in silicon semiconductors is approximately 0.1% to 10% of the hydrogen chemical concentration. 【0040】 In this specification, the transistor section is described as an IGBT (Insulated Gate Bipolar Transistor), but the transistor section may also be a MOSFET. When the transistor section is a MOSFET, "emitter" in this specification refers to the source of the MOSFET, and "collector" refers to the drain of the MOSFET. When the transistor section is a MOSFET, an N-type drain region may be provided instead of a P-type collector region. 【0041】 Figure 1 is an example of a top view of a semiconductor device 100. In Figure 1, the positions of each component projected onto the top surface of the semiconductor substrate 10 are shown. In Figure 1, only some of the components of the semiconductor device 100 are shown, and some components are omitted. 【0042】 The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. In the semiconductor substrate 10 of this example, N-type bulk donors are distributed throughout. The bulk donors are donors by dopants contained substantially uniformly in an ingot when the ingot serving as the source of the semiconductor substrate 10 is manufactured. The bulk donors in this example are elements other than hydrogen. The dopants of the bulk donors are, for example, elements of Group V or Group VI, such as phosphorus, antimony, arsenic, selenium, or sulfur, but are not limited thereto. The bulk donor in this example is phosphorus. The bulk donors are also included in the P-type regions. The semiconductor substrate 10 may be a wafer cut out from a semiconductor ingot, or may be a chip obtained by singulating the wafer. The semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), the magnetic field applied Czochralski method (MCZ method), or the float zone method (FZ method). 【0043】 The oxygen chemical concentration contained in a substrate manufactured by the MCZ method is, for example, 1×10 17 ~7×10 17 atoms / cm 3 . The oxygen chemical concentration contained in a substrate manufactured by the FZ method is, for example, 1×10 15 ~5×10 16 atoms / cm 3 . The bulk donor concentration may be the chemical concentration of the bulk donors distributed throughout the semiconductor substrate 10, and may be a value between 90% and 100% of the chemical concentration. In a semiconductor substrate doped with dopants of Group V or Group VI such as phosphorus, the bulk donor concentration may be 1×10 11 / cm 3 or more and 3×10 13 / cm 3 or less. The bulk donor concentration of a semiconductor substrate doped with dopants of Group V or Group VI is preferably 1×10 12 / cm 3 or more and 1×10 13 / cm 3The following applies: The semiconductor substrate 10 may be a non-doped substrate that substantially does not contain bulk dopants such as phosphorus. In that case, the bulk donor concentration of the non-doped substrate may be, for example, 1 × 10⁻⁶. 10 / cm 3 The above 5 x 10 12 / cm 3 The following applies: The bulk donor concentration of the non-doped substrate is preferably 1 × 10⁻⁶. 11 / cm 3 That concludes the explanation. The bulk donor concentration of the non-doped substrate is preferably 5 × 10⁻⁶. 12 / cm 3 The following applies: 【0044】 The semiconductor substrate 10 may have P-type bulk acceptors distributed throughout. The bulk acceptors may be acceptors formed by dopants that are substantially uniformly contained within the ingot during the manufacturing of the ingot that forms the basis of the semiconductor substrate 10, or they may be acceptors injected throughout the wafer or chip-shaped semiconductor substrate 10. The bulk acceptors may be boron. The bulk acceptor concentration may be lower than the bulk donor concentration. In other words, the bulk of the ingot or semiconductor substrate 10 is N-type. As an example, the bulk acceptor concentration is 5 × 10⁻⁶. 11 ( / cm 3 )~8×10 14 ( / cm 3 ) and the bulk donor concentration is 5 × 10 12 ( / cm 3 )~1×10 15 ( / cm 3 The bulk acceptor concentration may be 1% or more, 10% or more, or 50% or more of the bulk donor concentration. The bulk acceptor concentration may be 99% or less, 95% or less, or 90% or less of the bulk donor concentration. The bulk acceptor concentration and bulk donor concentration may be the chemical concentration of impurities such as boron or phosphorus distributed throughout the semiconductor substrate 10. The bulk acceptor concentration and bulk donor concentration may be the value at the center in the depth direction of the semiconductor substrate 10 of the chemical concentration of impurities such as boron or phosphorus distributed throughout the semiconductor substrate 10. 【0045】 The semiconductor substrate 10 has a top surface and a bottom surface. The top surface and the bottom surface are the two main surfaces of the semiconductor substrate 10. The semiconductor substrate 10 has edges 102 when viewed from above. When referred to simply as "top view" in this specification, it means viewing from the top side of the semiconductor substrate 10. In this example, the semiconductor substrate 10 has two pairs of edges 102 that face each other when viewed from above. In Figure 1, the X and Y axes are parallel to either edge 102. The Z axis is perpendicular to the top surface of the semiconductor substrate 10. 【0046】 The semiconductor substrate 10 is provided with an active section 160. The active section 160 is a region in which the main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 100 when the semiconductor device 100 is operating. An emitter electrode is provided above the active section 160, but it is omitted in Figure 1. 【0047】 The active section 160 is provided with a transistor section 70, which includes a transistor element such as an IGBT. The active section 160 may or may not be provided with a diode section 80, which includes a diode element such as a freewheeling diode (FWD). In the example shown in Figure 1, the transistor section 70 and the diode section 80 are arranged alternately along a predetermined arrangement direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10. 【0048】 In Figure 1, the region where the transistor section 70 is located is denoted by the symbol "I," and the region where the diode section 80 is located is denoted by the symbol "F." In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (Y-axis direction in Figure 1). The transistor section 70 and the diode section 80 may each have their longitudinal length in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section described later. 【0049】 The diode section 80 has an N+ type cathode region in the area in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is the region that overlaps with the cathode region when viewed from above. A P+ type collector region may be provided on the lower surface of the semiconductor substrate 10 in areas other than the cathode region. In this specification, an extension region 81, which is an extension of the diode section 80 in the Y-axis direction to the gate wiring described later, may also be included in the diode section 80. A collector region is provided on the lower surface of the extension region 81. 【0050】 The transistor section 70 has a P+ type collector region in the area in contact with the lower surface of the semiconductor substrate 10. The transistor section 70 has a gate structure periodically arranged on the upper surface side of the semiconductor substrate 10, which includes an N+ type emitter region, a P- type base region, a gate conductive portion, and a gate insulating film. 【0051】 The semiconductor device 100 may have one or more pads on the semiconductor substrate 10. In this example, the semiconductor device 100 has a gate pad 112. The semiconductor device 100 may have an anode pad and a cathode pad connected to a diode for temperature detection, and may also have a pad for current detection. Each pad is located near the edge 102. The vicinity of the edge 102 refers to the region between the edge 102 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as wires. 【0052】 A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to the conductive portion of the gate trench of the active portion 160. The semiconductor device 100 is provided with gate wiring that connects the gate pad 112 to the gate trench. In Figure 1, the gate wiring is hatched with diagonal lines. 【0053】 The gate wiring in this example has an outer perimeter gate wiring 130 and an active-side gate wiring 131. The outer perimeter gate wiring 130 is positioned between the active portion 160 and the edge 102 of the semiconductor substrate 10 in a top view. In this example, the outer perimeter gate wiring 130 surrounds the active portion 160 in a top view. The area surrounded by the outer perimeter gate wiring 130 in a top view may be considered the active portion 160. The outer perimeter gate wiring 130 is connected to the gate pad 112. The outer perimeter gate wiring 130 is positioned above the semiconductor substrate 10. The gate wiring may be a metal wiring containing aluminum or the like, a wiring formed from polysilicon, or a laminated wiring in which these wirings are stacked. 【0054】 The active gate wiring 131 is provided in the active section 160. By providing the active gate wiring 131 in the active section 160, variations in the wiring length from the gate pad 112 can be reduced for each region of the semiconductor substrate 10. 【0055】 The active gate wiring 131 is connected to the gate trench portion of the active section 160. The active gate wiring 131 is positioned above the semiconductor substrate 10. The active gate wiring 131 may be wiring formed of a semiconductor such as polysilicon doped with impurities. 【0056】 The active gate wiring 131 may be connected to the outer gate wiring 130. In this example, the active gate wiring 131 extends in the X-axis direction, crossing the active section 160 from one outer gate wiring 130 to the other outer gate wiring 130 approximately in the center in the Y-axis direction. When the active section 160 is divided by the active gate wiring 131, the transistor section 70 and the diode section 80 may be arranged alternately in the X-axis direction in each divided region. 【0057】 The semiconductor device 100 may include a temperature sensing unit (not shown) which is a PN junction diode made of polysilicon or the like, and a current detection unit (not shown) which simulates the operation of a transistor unit provided in the active unit 160. 【0058】 The semiconductor device 100 in this example includes an edge termination structure 90 between the active portion 160 and the edge 102. The edge termination structure 90 is located on the semiconductor substrate 10, outside of the active portion 160. On the semiconductor substrate 10, "outside" refers to the side closer to the edge 102. In this example, the edge termination structure 90 is located between the outer peripheral gate wiring 130 and the edge 102. The edge termination structure 90 mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 has a plurality of guard rings 92. The guard rings 92 are P-shaped regions in contact with the upper surface of the semiconductor substrate 10. The guard rings 92 may surround the active portion 160 when viewed from above. The plurality of guard rings 92 are arranged at predetermined intervals between the outer peripheral gate wiring 130 and the edge 102. The outer guard rings 92 may surround the guard ring 92 located one position inward. The outer side refers to the side closer to the edge 102, and the inner side refers to the side closer to the center when viewed from above the semiconductor substrate 10. By providing multiple guard rings 92, the depletion layer on the upper side of the active portion 160 can be extended outwards, thereby improving the breakdown voltage of the semiconductor device 100. The edge termination structure 90 may further include at least one of a field plate and a resurf, which are provided in an annular shape surrounding the active portion 160. 【0059】 Figure 2 shows an example of the AA cross-section in Figure 1. The AA cross-section is the XZ plane passing through a part of the transistor section 70. Each component shown in Figure 2 is provided extending in the Y-axis direction. The semiconductor device 100 in this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the said cross-section. The interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is a film that includes at least one layer of insulating film such as silicate glass with impurities such as boron or phosphorus added, a thermal oxide film, a nitride film, and other insulating films. The interlayer insulating film 38 is provided with a contact hole 54 that connects the emitter electrode 52 and the semiconductor substrate 10. 【0060】 The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 is in contact with the upper surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. The emitter electrode 52 may be in contact with the emitter region 12, contact region 15, and base region 14, which will be described later. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metallic material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (Z-axis direction) is referred to as the depth direction. 【0061】 The semiconductor substrate 10 has an N-type drift region 18. The doping concentration of the drift region 18 may be equal to the bulk donor concentration, or it may be equal to the bulk net doping concentration, which is the difference between the bulk donor concentration and the bulk acceptor concentration. In other examples, the doping concentration of the drift region 18 may be higher than the bulk donor concentration or the bulk net doping concentration. The drift region 18 is provided in both the transistor section 70 and the diode section 80. 【0062】 In both the transistor section 70 and the diode section 80, an N+ type buffer section 20 may be provided on the lower surface 23 side of the drift section 18. The doping concentration of the buffer section 20 is higher than that of the drift section 18. The buffer section 20 has one or more donor concentration peaks with higher donor concentrations than the drift section 18. The buffer section 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base section 14 from reaching the P+ type collector section 22 and the N+ type cathode section. 【0063】 In the transistor section 70, a P+ type collector section 22 is provided below the buffer section 20. The acceptor concentration of the collector section 22 is higher than that of the base section 14. The collector section 22 may contain the same acceptor as the base section 14, or it may contain different acceptors. The acceptor of the collector section 22 is, for example, boron. In the diode section 80, an N+ type cathode section is provided below the buffer section 20. The donor concentration of the cathode section is higher than that of the drift section 18. The donor of the cathode section is, for example, hydrogen or phosphorus. In this example, the boundary in the X-axis direction between the diode section 80 and the transistor section 70 is the boundary between the cathode section and the collector section 22. 【0064】 The elements that act as donors and acceptors in each region are not limited to the examples described above. The collector region 22 and the cathode region are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed from a metallic material such as aluminum. 【0065】 One or more gate trenches 40 and one or more dummy trenches 30 are provided on the upper surface of the semiconductor substrate 10. In Figure 2, the gate trenches 40 are denoted by the symbol G, and the dummy trenches 30 are denoted by the symbol E. The gate trenches 40 function as gate electrodes when a gate voltage is applied, while the dummy trenches 30 do not function as gate electrodes when a voltage different from the gate voltage is applied. In this example, the voltage of the emitter electrode 52 is applied to the dummy trenches 30. In this specification, the gate trenches 40 and dummy trenches 30 may be referred to as trenches. The trenches are provided in the depth direction from the upper surface 21 of the semiconductor substrate 10 to the drift region 18. The trenches extend in the stretching direction (Y-axis direction) on the upper surface 21 of the semiconductor substrate 10. The trenches are arranged with spacing between them in the arrangement direction. 【0066】 The gate trench portion 40 has a groove-shaped gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate trench portion 40 is an example of a gate structure. The gate insulating film 42 is provided covering the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench, on the inside of the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. 【0067】 The gate conductive portion 44 may be longer than the base region 14 in the depth direction. The gate trench portion 40 in this cross-section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface of the base region 14 that is in contact with the gate trench portion 40. 【0068】 The dummy trench portion 30 may have the same structure as the gate trench portion 40 in its cross-section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 may be connected to an electrode different from the gate pad. For example, the dummy conductive portion 34 may be connected to a dummy pad (not shown) that is connected to an external circuit different from the gate pad, and different control may be performed from that of the gate conductive portion 44. The dummy conductive portion 34 may be electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided covering the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed from the same material as the gate conductive portion 44. For example, the dummy conductive part 34 is formed of a conductive material such as polysilicon. The dummy conductive part 34 may have the same length as the gate conductive part 44 in the depth direction. 【0069】 The gate trench portion 40 and the dummy trench portion 30 in the cross-section are covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. As described above, the gate trench portion 40 is connected to the gate wiring at some point, and the dummy trench portion 30 may be connected to wiring other than the gate wiring at some point, or it may be connected to the emitter electrode 52. That is, the dummy trench portion 30 may be controlled to have a different potential than the gate trench portion 40, or it may be controlled to have the same potential as the emitter electrode 52. 【0070】 The transistor section 70 has multiple trench sections arranged in the direction of arrangement. In this example, the transistor section 70 has one or more gate trench sections 40 and one or more dummy trench sections 30 alternately arranged along the direction of arrangement. In the example in Figure 2, two gate trench sections 40 and two dummy trench sections 30 are alternately arranged in the direction of arrangement, but the arrangement of the trench sections is not limited to this. One gate trench section 40 and one dummy trench section 30 may be alternately arranged in the direction of arrangement, or two gate trench sections 40 and three or more dummy trench sections 30 may be alternately arranged in the direction of arrangement. Note that the diode section 80 shown in Figure 1 may have multiple dummy trench sections 30 arranged along the direction of arrangement. The diode section 80 does not need to have gate trench sections 40. 【0071】 A mesa portion is provided between each trench portion in the arrangement direction. A mesa portion refers to the region within the semiconductor substrate 10 that is sandwiched between two adjacent trench portions in the arrangement direction. For example, the upper end of a mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of a mesa portion is the same as the depth position of the lower end of a trench portion. In this example, the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending along the trench in the extension direction (Y-axis direction). In this example, the transistor portion 70 is provided with one or more active mesa portions 60 and one or more dummy mesa portions 61. The diode portion 80 may be provided with one or more dummy mesa portions 61. In this specification, when simply referred to as a mesa portion, it refers to the active mesa portion 60 and the dummy mesa portion 61, respectively. 【0072】 The active mesa portion 60 is a mesa portion in which, when the transistor portion 70 is turned on, a channel region is formed on the surface of the base region 14, which is the interface with the gate trench portion 40, and current flows between the emitter region 12 and the drift region 18. The active mesa portion 60 is in contact with at least one gate trench portion 40. In Figure 2, the active mesa portion 60 is sandwiched between two gate trench portions 40, but in other examples, it may be sandwiched between a gate trench portion 40 and a dummy trench portion 30. The active mesa portion 60 has an N+ type emitter region 12 and a P- type base region 14, which are provided in order from the upper surface 21 side of the semiconductor substrate 10. An N- type drift region 18 is provided below the base region 14. 【0073】 The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the active mesa portion 60. The doping concentration of the emitter region 12 is higher than that of the drift region 18. 【0074】 The base region 14 is located below the emitter region 12. In this example, the base region 14 is located in contact with the emitter region 12. The base region 14 may be in contact with the trenches on both sides of the active mesa 60. When a predetermined gate voltage is applied to the gate trench 40, a channel formed by an electron inversion layer is created on the surface of the interface of the base region 14 that is in contact with the gate trench 40. 【0075】 The dummy mesa portion 61 does not have an emitter region 12 that is in contact with the gate trench portion 40. In this example, the dummy mesa portion 61 does not have an emitter region 12 at a position away from the gate trench portion 40. In the dummy mesa portion 61, even when a predetermined ON voltage is applied to the gate trench portion 40, no current flows between the emitter region 12 and the drift region 18. The dummy mesa portion 61 has a P-type region in contact with the upper surface 21 of the semiconductor substrate 10. The P-type region may be the base region 14, or it may be a region with a different doping concentration from the base region 14. In the example of Figure 2, a P+-type contact region 15 with a higher doping concentration than the base region 14 is provided in contact with the upper surface 21. Below the base region 14, a drift region 18 is provided. In this example, the dummy mesa portion 61 is sandwiched between the gate trench portion 40 and the dummy trench portion 30. The mesa portion sandwiched between the two dummy trench portions 30 may also be a dummy mesa portion 61. 【0076】 The active mesa portion 60 may be provided with a contact region 15 exposed on the upper surface 21 of the semiconductor substrate 10. For example, in the active mesa portion 60, the contact region 15 and the emitter region 12 may be arranged alternately along the Y-axis. 【0077】 Of the two mesa portions that are in contact with at least one gate trench portion 40, one mesa portion is an active mesa portion 60 and the other mesa portion is a dummy mesa portion 61. In Figure 2, each of the multiple gate trench portions 40 is in contact with both an active mesa portion 60 and a dummy mesa portion 61. All of the gate trench portions 40 provided in the transistor portion 70 may be in contact with both an active mesa portion 60 and a dummy mesa portion 61. 【0078】 Let R1 be the active contact resistance between one active mesa portion 60 and the emitter electrode 52. R1 may be the contact resistance between the emitter electrode 52 and a p-type region provided in the active mesa portion 60. In this example, the p-type region is the contact region 15. Alternatively, R1 may be the contact resistance between the emitter electrode 52 and an emitter region 12 provided in the active mesa portion 60. In this example, R1 is the contact resistance between the emitter electrode 52 and the contact region 15 provided in the active mesa portion 60. Let R2 be the dummy contact resistance between one dummy mesa portion 61 and the emitter electrode 52. R2 may be the contact resistance between the emitter electrode 52 and a p-type region provided in the dummy mesa portion 61. In this example, the p-type region is the contact region 15. In this example, the dummy contact resistor R2 is more than 1000 times greater than the active contact resistor R1. 【0079】 In this example, the dummy contact resistance R2 is increased by providing a resistive film 210 between each dummy mesa portion 61 and the emitter electrode 52. The resistive film 210 is in contact with at least a portion of the upper surface of the dummy mesa portion 61 in the contact hole 54. The resistive film 210 is made of a material with a higher volume resistivity than the emitter electrode 52. The resistive film 210 is made of a material with a lower volume resistivity than the interlayer insulating film 38. For example, the emitter electrode 52 is a metal electrode containing aluminum, and the resistive film 210 is a polysilicon film doped with impurities. The resistive film 210 may be entirely placed inside the contact hole 54 as shown in Figure 2. A portion of the resistive film 210 may be placed above the upper end of the contact hole 54. The resistive film 210 may cover a portion of the interlayer insulating film 38. By using the resistive film 210, the dummy contact resistance R2 of the dummy mesa portion 61 can be easily increased. 【0080】 When the transistor section 70 is turned on, turn-on losses occur. In particular, large turn-on losses occur when a large collector current flows through the transistor section 70. Turn-on losses can be reduced by increasing the turn-on speed. For example, reducing the gate resistance to the gate conductive section 44 can increase the turn-on speed and reduce turn-on losses. However, reducing the gate resistance also increases the turn-on speed at low currents, leading to the generation of radiated noise and other issues. 【0081】 In this example, increasing the dummy contact resistance R2 reduces the turn-on loss when a large collector current is flowing. Normally, the Hall current that flows into the dummy mesa section 61 during turn-on passes through the dummy mesa section 61 and exits to the emitter electrode 52. By increasing the dummy contact resistance R2, the Hall current to the emitter electrode 52 is inhibited, and a portion of the Hall current that flows into the dummy mesa section 61 flows into the active mesa section 60 along the side walls and bottom surface of the gate trench section 40. This flow of Hall current generates a displacement current in the gate conductive section 44. The displacement current generated in the gate conductive section 44 raises the potential of the gate conductive section 44, promoting the formation of the channel region and speeding up the turn-on of the active mesa section 60. The larger the collector current, the more holes flow into the active mesa section 60, and the more pronounced the speed increase in turn-on becomes. Therefore, at low currents, the generation of radiated noise and other issues can be suppressed without increasing the turn-on speed, while at high currents, the turn-on speed can be increased to reduce turn-on losses. 【0082】 The dummy contact resistor R2 may be 5,000 times or more, 10,000 times or more, 30,000 times or more, or 50,000 times or more than the active contact resistor R1. However, if the dummy contact resistor R2 is too large, the extraction of the hole current from the dummy mesa portion 61 to the emitter electrode 52 will be suppressed too much, for example, causing the turn-off to be delayed. The dummy contact resistor R2 may be 100,000 times or less of the active contact resistor R1. The dummy contact resistor R2 may be 90,000 times or less of the active contact resistor R1, or 80,000 times or less. 【0083】 Figure 3 shows an example of the arrangement of the resistive film 210 in a top view. Figure 3 shows top views of the active mesa portion 60, dummy mesa portion 61, gate trench portion 40, and dummy trench portion 30 shown in Figure 2. Figure 3 shows a portion of these configurations in the Y-axis direction. Figure 2 shows a cross-section along line AA in Figure 3. In Figure 3, the hatching of the gate conductive portion 44 and dummy conductive portion 34 is omitted, and hatching of the resistive film 210 is applied. 【0084】 The emitter region 12 is exposed on the upper surface of the active mesa portion 60. A P+ type contact region 15 may also be exposed on the upper surface of the active mesa portion 60. The emitter region 12 and the contact region 15 may be arranged alternately along the extension direction (Y-axis direction) of the active mesa portion 60 and the gate trench portion 40. In another example, the emitter region 12 may extend along the gate trench portion 40 in the Y-axis direction. The contact region 15 may be located in the center of the active mesa portion 60 in the X-axis direction and extend in the Y-axis direction. In other words, the emitter region 12 and the contact region 15 may be arranged in a stripe pattern with the Y-axis direction being the longitudinal direction. 【0085】 The upper surface of the active mesa portion 60 is connected to the emitter electrode 52 via a contact hole 54. The contact hole 54 may expose the center of the active mesa portion 60 in the X-axis direction. The contact hole 54 may extend along the Y-axis direction. The contact hole 54 may be provided continuously from one emitter region 12 located at one end of the multiple emitter regions 12 in the Y-axis direction to the other emitter region 12 located at the other end. 【0086】 A P-shaped region is exposed on the upper surface of the dummy mesa portion 61. In this example, the P-shaped region is the contact region 15. The doping concentration of the contact region 15 of the dummy mesa portion 61 may be the same as or different from the doping concentration of the contact region 15 of the active mesa portion 60. The contact region 15 of the dummy mesa portion 61 may be continuously provided from a position facing one of the emitter regions 12 located at one end in the Y-axis direction to a position facing the emitter region 12 located at the other end of the multiple emitter regions 12 of the active mesa portion 60. 【0087】 The contact holes 54 of the dummy mesa portion 61 in this example may have the same width in the X-axis direction and length in the Y-axis direction as the contact holes 54 of the active mesa portion 60. The contact holes 54 of the dummy mesa portion 61 may be provided in a range that overlaps with the contact area 15. 【0088】 The resistive film 210 is provided inside the contact hole 54 of the dummy mesa portion 61. The resistive film 210 may be provided in the dummy mesa portion 61 adjacent to the active mesa portion 60. The resistive film 210 may also be provided in the dummy mesa portion 61 that is not adjacent to the active mesa portion 60. The width in the X-axis direction and the length in the Y-axis direction of the resistive film 210 may be the same as that of the contact hole 54. In other words, the resistive film 210 may be provided over the entire bottom surface of the contact hole 54 of the dummy mesa portion 61. In another example, the resistive film 210 may be provided over only a portion of the bottom surface of the contact hole 54 of the dummy mesa portion 61. 【0089】 The active contact resistor R1 of the active mesa section 60 and the dummy contact resistor R2 of the dummy mesa section 61 may use the resistance value of the mesa section in the same length range W in the Y-axis direction. The length range W includes at least one emitter region 12 of the active mesa section 60. The length range W also includes the region where the resistive film 210 is provided. The length range W may include one or more emitter regions 12 and one or more contact regions 15 of the active mesa section 60. The length range W may be a continuous region from an emitter region 12 located at one end of the Y-axis direction to an emitter region 12 located at the other end of the multiple emitter regions 12 of the active mesa section 60. In other words, the length range W may be a range that includes all emitter regions 12 in the Y-axis direction. The length range W may be the unit length of one emitter region 12 among the multiple emitter regions 12 of the active mesa section 60. The unit length is 1 μm as an example, but is not limited to this. 【0090】 The contact resistance may be the resistance value per unit area on the upper surface of the mesa portion. In this case as well, the active contact resistance R1 of the active mesa portion 60 and the dummy contact resistance R2 of the dummy mesa portion 61 may be the resistance values ​​per unit area in the same length range W in the Y-axis direction. 【0091】 The contact resistance R(Ω) may be given by the following formula. R = R0 × L / S However, R0 is the resistivity of the resistive part (Ω·cm), L is the length of the resistive part in the direction of current flow (cm), and S is the cross-sectional area of ​​the resistive part in the direction perpendicular to the direction of current flow (cm²). 2 ) In this example, the dummy contact resistor R2 is the resistivity R0 of the resistive film 210, in the Z-axis direction. length The active contact resistance R1 may be calculated from L and the area S in the XY plane. The active contact resistance R1 may be calculated from the resistivity R0 of the emitter electrode 52, which is the same size as the resistive film 210, the length L in the Z-axis direction, and the area S in the XY plane. 【0092】 Figure 4 shows another example of a cross-section of the transistor section 70. The transistor section 70 in this example differs from the transistor section 70 shown in Figures 2 and 3 in that it further includes trench contacts 220. The other structures are the same as those of any of the embodiments described in Figures 2 and 3. The transistor section 70 in this example does not have a resistive film 210, but the transistor section 70 may have a resistive film 210. 【0093】 The trench contact 220 is provided in the active mesa portion 60. The dummy mesa portion 61 does not have a trench contact 220. That is, the upper surface 21 of the semiconductor substrate 10 in the dummy mesa portion 61 may be flat. The trench contact 220 is a conductive member connected to the emitter electrode 52. The trench contact 220 may be made of the same material as the emitter electrode 52, or it may be made of a different material. The trench contact 220 may have a tungsten plug, and may contain a titanium or titanium nitride barrier metal. A P-type plug contact region 201 may be formed so as to be in contact with the bottom surface of the trench contact 220. The doping concentration of the plug contact region 201 may be higher than that of the base region 14, and may be higher than that of the contact region 15. The plug contact region 201 may or may not be connected to the base region 14. 【0094】 The trench contact 220 is provided inside the semiconductor substrate 10 from the upper surface 21. The trench contact 220 may be entirely located inside the emitter region 12, or it may penetrate the emitter region 12 and reach the base region 14. Providing the trench contact 220 increases the contact area between the active mesa portion 60 and the electrode. The trench contact 220 may also be formed by filling it with a material whose contact resistance with the semiconductor substrate 10 is lower than that of the emitter electrode 52. By providing the trench contact 220, the active contact resistance R1 can be reduced and the dummy contact resistance R2 can be relatively increased. Even if the active contact resistance R1 is further reduced by providing the plug contact region 201, the dummy contact resistance R2 can be relatively increased. With such a configuration, switching losses at high currents can be reduced while radiated noise at low currents can be suppressed. 【0095】 Figure 5 shows an example of the arrangement of the trench contact 220 in a top view. Figure 5 shows top views of the active mesa section 60, dummy mesa section 61, gate trench section 40, and dummy trench section 30 shown in Figure 4. Figure 5 shows a portion of these configurations in the Y-axis direction. Figure 4 shows a cross-section along line BB in Figure 5. In Figure 5, the hatching of the gate conductive section 44 and dummy conductive section 34 is omitted, and the trench contact 220 is hatched with hatching. 【0096】 The configuration other than the trench contact 220 is the same as in the example shown in Figure 3. As described above, the dummy mesa portion 61 may or may not be provided with a resistive film 210. The trench contact 220 is connected to the contact hole 54 of the active mesa portion 60. The width in the X-axis direction and the length in the Y-axis direction of the trench contact 220 may be the same as that of the contact hole 54. In other words, the trench contact 220 may be provided on the entire bottom surface of the contact hole 54 of the active mesa portion 60. In other examples, the trench contact 220 may be provided only on a part of the bottom surface of the contact hole 54 of the active mesa portion 60. The width in the X-axis direction of the trench contact 220 may be smaller or larger than that of the contact hole 54. 【0097】 The active contact resistance R1 may be calculated from the material of the semiconductor substrate 10, the doping concentration on the upper surface of the active mesa portion 60, the material of the trench contact 220, the contact area with the semiconductor substrate 10, etc. The dummy contact resistance R2 may be calculated from the material of the semiconductor substrate 10, the doping concentration on the upper surface of the dummy mesa portion 61, the material of the emitter electrode 52, the contact area with the semiconductor substrate 10, etc. 【0098】 Figure 6 shows another example of a cross-section of the transistor section 70. The transistor section 70 in this example differs from the transistor section 70 shown in Figures 2 to 5 in the area exposed on the upper surface of the dummy mesa section 61. The other structures are the same as those of any of the embodiments described in Figures 2 to 5. The transistor section 70 in this example does not have a resistive film 210 and trench contacts 220, but the transistor section 70 may have at least one of the resistive film 210 and trench contacts 220. 【0099】 As described above, a P-shaped region is exposed on the upper surface of the dummy mesa portion 61. On the upper surface of the active mesa portion 60, a contact region 15 (see Figures 3 and 5) with a higher doping concentration than the P-shaped region of the dummy mesa portion 61 is exposed. In this example, the base region 14 is exposed on the upper surface of the dummy mesa portion 61. In other examples, the upper surface of the dummy mesa portion 61 may have a region with a higher doping concentration than the base region 14, or a region with a lower doping concentration than the base region 14. 【0100】 By lowering the doping concentration of the P-type region on the upper surface of the dummy mesa portion 61 than that of the contact region 15, the contact resistance between the dummy mesa portion 61 and the emitter electrode 52 can be increased. By making the doping concentration of the base region 14 of the dummy mesa portion 61 lower than that of the base region 14 of the active mesa portion 60, the doping concentration of the P-type region on the upper surface of the dummy mesa portion 61 may be 1 / 1000 or less, or even 1 / 10000 or less, of the doping concentration of the contact region 15 on the upper surface of the active mesa portion 60. Even with such a configuration, switching losses at high currents can be reduced while radiated noise at low currents can be suppressed. 【0101】 Figure 7 shows an example of the arrangement of the P-type region of the dummy mesa section 61 in a top view. Figure 7 shows a top view of the active mesa section 60, dummy mesa section 61, gate trench section 40, and dummy trench section 30 shown in Figure 6. Figure 7 shows a portion of these configurations in the Y-axis direction. Figure 6 shows a cross-section along the CC line in Figure 7. In Figure 7, the hatching of the gate conductive section 44 and dummy conductive section 34 is omitted. 【0102】 The configuration of the dummy mesa portion 61, other than the upper surface, is the same as in the example shown in Figure 3 or Figure 5. As described above, the dummy mesa portion 61 may or may not be provided with a resistive film 210. The active mesa portion 60 may or may not be provided with trench contacts 220. 【0103】 In this example, a base region 14 is exposed on the upper surface of the dummy mesa portion 61. The base region 14 is connected to the contact hole 54 of the dummy mesa portion 61. The base region 14 may be provided in the same or a wider area than the contact hole 54 in the Y-axis direction. In other examples, the base region 14 may be provided in a narrower area than the contact hole 54 in the Y-axis direction. The base region 14 of the dummy mesa portion 61 may be provided continuously from a position facing a contact region 15 located at one end of the multiple contact regions 15 of the active mesa portion 60 in the Y-axis direction to a position facing a contact region 15 located at the other end. Contact regions 15 may be provided in areas on the upper surface of the dummy mesa portion 61 where the base region 14 is not provided. As described above, instead of the base region 14, a P-type region with a lower doping concentration than the base region 14 may be exposed on the upper surface of the dummy mesa portion 61, or a P-type region with a higher doping concentration than the base region 14 may be exposed. 【0104】 The active contact resistance R1 may be calculated from the material of the semiconductor substrate 10, the doping concentration on the upper surface of the active mesa portion 60, the material of the trench contact 220, the contact area with the semiconductor substrate 10, etc. The dummy contact resistance R2 may be calculated from the material of the semiconductor substrate 10, the doping concentration on the upper surface of the dummy mesa portion 61, the material of the emitter electrode 52, the contact area with the semiconductor substrate 10, etc. 【0105】 Figure 8 shows another example of a cross-section of the transistor section 70. The transistor section 70 in this example differs from the transistor section 70 shown in Figures 2 to 7 in the arrangement of the contact holes 54 of the dummy mesa section 61. The other structures are the same as any of the embodiments described in Figures 2 to 7. The transistor section 70 in this example does not have a resistive film 210 and trench contacts 220, but the transistor section 70 may have at least one of the resistive film 210 and trench contacts 220. The upper surface of the dummy mesa section 61 in this example may have an exposed contact region 15, and as in the examples of Figures 6 and 7, an area with a doping concentration lower than the contact region 15 may be exposed. 【0106】 In this example, the total area of ​​the contact holes 54 in a top view for one dummy mesa portion 61 is smaller than the total area of ​​the contact holes 54 in a top view for one active mesa portion 60. In the cross-section of Figure 8, a contact hole 54 is provided for the active mesa portion 60, but no contact hole 54 is provided for the dummy mesa portion 61 adjacent to the active mesa portion 60. 【0107】 This configuration also allows for a large dummy contact resistance R2 in the dummy mesa section 61. The ratio of the area of ​​the contact holes 54 in the dummy mesa section 61 to the area of ​​the contact holes 54 in the active mesa section 60 may be used as the resistance ratio between the dummy contact resistance R2 and the active contact resistance R1. 【0108】 Figure 9 shows an example of the arrangement of contact holes 54 in the dummy mesa portion 61 in a top view. Figure 9 shows top views of the active mesa portion 60, dummy mesa portion 61, gate trench portion 40, and dummy trench portion 30 shown in Figure 8. Figure 9 shows a portion of these configurations in the Y-axis direction. Figure 8 shows a cross-section along the DD line in Figure 9. In Figure 9, the hatching of the gate conductive portion 44 and dummy conductive portion 34 is omitted. 【0109】 The configuration of the dummy mesa portion 61, other than the upper surface, is the same as in the example shown in Figures 3, 5, or 7. As described above, the dummy mesa portion 61 may or may not be provided with a resistive film 210. The active mesa portion 60 may or may not be provided with trench contacts 220. The upper surface of the dummy mesa portion 61 may have a contact region 15 exposed, or a P-type region with a lower doping concentration than the contact region 15 may be exposed. 【0110】 The area of ​​the contact holes 54 (second contact holes) in a dummy mesa portion 61-1 adjacent to an active mesa portion 60 in the X-axis direction is smaller than the area of ​​the contact holes 54 (first contact holes) in the active mesa portion 60. In the dummy mesa portion 61-1, the contact holes 54 may be discretely arranged in the Y-axis direction. The total area of ​​the contact holes 54 in one dummy mesa portion 61-1 may be 1 / 1000 or less, 1 / 5000 or less, 1 / 30000 or less, or 1 / 50000 or less of the total area of ​​the contact holes 54 in one active mesa portion 60. The total area of ​​the contact holes 54 in one dummy mesa portion 61-1 may be 1 / 100000 or more, 1 / 90000 or more, or 1 / 80000 or more of the total area of ​​the contact holes 54 in one active mesa portion 60. 【0111】 Dummy mesa portions 61-2 that are not adjacent to the active mesa portion 60 in the X-axis direction may have the same configuration as dummy mesa portion 61-1, or they may have a different configuration. In this example, the area of ​​the contact hole 54 in dummy mesa portion 61-2 is larger than the area of ​​the contact hole in dummy mesa portion 61-1. The area of ​​the contact hole 54 in dummy mesa portion 61-2 may be the same as or smaller than the area of ​​the contact hole 54 in active mesa portion 60. The area of ​​the contact hole in dummy mesa portion 61 may increase as it moves away from the active mesa portion 60. 【0112】 Figure 10 shows an example of the time waveforms of the collector-emitter voltage Vce and gate voltage Vge of the semiconductor device 100 during turn-on. Figure 10 shows the waveforms for each contact resistance ratio R2 / R1 of the dummy mesa section 61 and the active mesa section 60. 【0113】 When the semiconductor device 100 is turned on, the collector-emitter voltage Vce drops to a predetermined on-voltage Von. In the collector-emitter voltage Vce, waveform 301 is an example where the contact resistance ratio is 1 (i.e., R1 = R2), waveform 302 is an example where the contact resistance ratio is 30000 (i.e., R2 is 30000 times R1), waveform 303 is an example where the contact resistance ratio is 50000, and waveform 304 is an example where the contact resistance ratio is infinite (i.e., the dummy mesa portion 61 is floating relative to the emitter electrode 52). 【0114】 Figure 11 is an enlarged view of the gate voltage waveform in region 300 shown in Figure 10. At a gate voltage Vge, waveform 311 is an example where the contact resistance ratio is 1, waveform 312 is an example where the contact resistance ratio is 30000, waveform 313 is an example where the contact resistance ratio is 50000, and waveform 314 is an example where the contact resistance ratio is infinite. Note that in Figures 10 and 11, the collector current is the rated current (210A in this example), and a large current is flowing through the semiconductor device 100. 【0115】 As shown in Figure 11, the larger the contact resistance ratio, the larger the peak gate voltage values ​​Vge1, 2, 3, and 4 become. As explained in Figure 2, it is thought that increasing the dummy contact resistance R2 causes displacement current to flow into the gate trench 40, raising the peak gate voltage value Vge. In this specification, the differences between the peak values ​​Vge1, 2, 3, and 4 (Vge4-Vge0, Vge3-Vge0, Vge2-Vge0, Vge1-Vge0) relative to the steady-state gate voltage Vge0 after turn-on are sometimes referred to as the amount of rise in gate voltage Vge. 【0116】 As the peak value of the gate voltage Vge rises, the time it takes for the collector-emitter voltage Vce to converge to the on-voltage Von is shortened, as shown in Figure 10. This reduces switching losses during turn-on. On the other hand, when the collector current is small (for example, less than 10% of the rated current), the displacement current is small, so the rise in gate voltage Vge is very small. Therefore, the switching time during low-current drive is not shortened, and radiated noise can be suppressed. 【0117】 Figure 12 shows the relationship between the contact resistance ratio R2 / R1 and the amount of gate voltage Vge rise. As mentioned above, increasing the contact resistance ratio R2 / R1 can increase the amount of gate voltage Vge rise. When the contact resistance ratio R2 / R1 is 1, the active contact resistor R1 and the dummy contact resistor R2 but These are equivalent comparative examples. When the contact resistance ratio R2 / R1 is less than 1000, the rise in gate voltage Vge is approximately 0.8V, which is no different compared to the case where the contact resistance ratio R2 / R1 is 1. However, when the contact resistance ratio R2 / R1 is 1000 or more, the rise in gate voltage Vge increases compared to the case where the contact resistance ratio R2 / R1 is 1. In other words, it is preferable for the contact resistance ratio R2 / R1 to be 1000 or more. 【0118】 When the contact resistance ratio R2 / R1 is 5000, the increase in the gate voltage Vge rise becomes significant. The contact resistance ratio R2 / R1 may be 5000 or higher. When the contact resistance ratio R2 / R1 is 10000, the rise in the gate voltage Vge becomes even more pronounced. The contact resistance ratio R2 / R1 may be 10000 or higher. The contact resistance ratio R2 / R1 may be 30000 or higher, and may also be 50000 or higher. 【0119】 Figure 13 shows the relationship between the contact resistance ratio R2 / R1 and the turn-on loss. When the contact resistance ratio R2 / R1 is 1, the active contact resistance R1 and the dummy contact resistance R2 butThese are equivalent comparative examples. When the contact resistance ratio R2 / R1 is less than 1000, the turn-on loss is 25 (mJ), which is unchanged compared to when the contact resistance ratio R2 / R1 is 1. However, when the contact resistance ratio R2 / R1 is 1000 or more, the turn-on loss decreases compared to when the contact resistance ratio R2 / R1 is 1. In other words, it is preferable for the contact resistance ratio R2 / R1 to be 1000 or more. When the contact resistance ratio R2 / R1 is 5000, the decrease in turn-on loss becomes larger. When the contact resistance ratio R2 / R1 is 10000, the decrease in turn-on loss becomes even more pronounced. 【0120】 Figure 14 shows an example of the current (Ic)-voltage change rate (dv / dt) characteristics during turn-on. Current Ic is the collector current of semiconductor device 100. Voltage change rate is the voltage change per unit time, obtained by differentiating the waveform of the collector-emitter voltage Vce with respect to time. Alternatively, voltage change rate may be the value at which the absolute value of voltage change rate is maximum while the collector-emitter voltage Vce decreases to the on-voltage Von, or it may be the slope of the waveform between two points where the collector-emitter voltage Vce is from 90% to 10% of its maximum value. Waveform 321 is an example with a contact resistance ratio of 1, waveform 322 is an example with a contact resistance ratio of 30000, waveform 323 is an example with a contact resistance ratio of 50000, and waveform 325 is an example with a contact resistance ratio of 80000. In this example, the rated current of semiconductor device 100 is shown as Ir. The rated current Ir in Figure 14 is 210A, but is not limited to this. 【0121】 As shown in each waveform, the current-voltage change rate characteristic has a peak portion 330 where the voltage change rate dv / dt shows a maximum value in the low current region (for example, the region where the collector current Ic is less than Ir × 5%). As shown in waveform 321, when the contact resistance ratio R2 / R1 is 1, increasing the collector current Ic beyond the peak portion 330 causes the voltage change rate dv / dt to decrease monotonically. Therefore, in the high current region (for example, the region where the collector current Ic is between Ir × 5%) and Ir, the turn-on time becomes longer and the turn-on loss increases. 【0122】 In contrast, as shown in waveforms 322, 323, and 325, increasing the contact resistance ratio R2 / R1 maintains or increases the voltage change rate dv / dt in some current regions when increasing the collector current Ic from the peak portion 330. Waveform 322 has a maintenance-increase region 352 where the voltage change rate dv / dt is maintained or slightly increases. Waveform 323 has a maintenance-increase region 353 where the voltage change rate dv / dt increases significantly, and waveform 325 has a maintenance-increase region 355 where the voltage change rate dv / dt increases significantly. Because the current-voltage change rate characteristic has a maintenance-increase region on the high current side of the peak portion 330, the turn-on speed becomes significantly shorter and the turn-on loss is significantly reduced. 【0123】 Figure 15 shows an example of the current (Ic)-voltage change rate (dv / dt) characteristics during turn-on. Each waveform in Figure 15 is the same as the waveforms shown in Figure 14. The current-voltage change rate characteristic can be greater when the collector current is the rated current Ir than when the collector current is 5% of the rated current Ir. In the example in Figure 15, in waveforms 323 and 325, the dv / dt when Ic = Ir is greater than the dv / dt when Ic = Ir × 5%. This further shortens the turn-on speed and significantly reduces turn-on losses. The dv / dt when Ic = Ir may be 1.1 times or more, 1.2 times or more, or 1.5 times or more than the dv / dt when Ic = Ir × 5%. 【0124】 The current-voltage change rate characteristics preferably show a maximum value for the voltage change rate dv / dt in the high current region (for example, the region where the collector current Ic is 5% or more of Ir and less than or equal to Ir). The waveform 325 has a peak portion 345 that shows a maximum value in the high current region, and the waveform 323The voltage curve has a peak portion 343 in the high-current region. Preferably, the voltage change rate dv / dt at the peak portions 345 and 343 in the high-current region is greater than the voltage change rate dv / dt at the peak portion 330 in the low-current region. The voltage change rate dv / dt at the peak portions 345 and 343 may be 1.1 times or more, 1.2 times or more, or 1.5 times or more than the voltage change rate dv / dt at the peak portion 330 in the low-current region. 【0125】 In the current-voltage change rate characteristics, the voltage change rate dv / dt may show a minimum value in the high current region. Waveform 325 has a trough 335 that shows a minimum value, waveform 323 has a trough 333, and waveform 322 has a trough 332. 【0126】 Figure 16 shows another example of a cross-section of the semiconductor device 100. The semiconductor device 100 in this example has a storage region 16. The other structures are the same as any of the embodiments described in Figures 1 to 15. Figure 16 shows a structure in which a storage region 16 is added to the AA cross-section structure shown in Figure 2, but the structures other than the storage region 16 are not limited to the AA cross-section structure. 【0127】 The accumulation region 16 is located below the base region 14 in each mesa. The accumulation region 16 is an N+ type region with a higher doping concentration than the drift region 18. By providing a high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect) can be enhanced, and the on-voltage can be reduced. 【0128】 The active mesa section 60 and the dummy mesa section 61 may be provided with accumulation regions 16 having the same doping concentration. In another example, the integrated concentration obtained by integrating the doping concentration in the accumulation region 16 of the dummy mesa section 61 in the depth direction may be greater than the integrated concentration obtained by integrating the doping concentration in the accumulation region 16 of the active mesa section 60 in the depth direction. For example, the accumulation region 16 of the dummy mesa section 61 may have a larger peak value of doping concentration than the accumulation region 16 of the active mesa section 60. Also, the accumulation region 16 of the dummy mesa section 61 may have more doping concentration peaks in the depth direction than the accumulation region 16 of the active mesa section 60. By increasing the integrated concentration of the accumulation region 16 of the dummy mesa section 61, holes are more likely to accumulate below the dummy mesa section 61, and displacement current is more likely to flow in the gate trench section 40. As a result, the turn-on time can be further shortened. The integrated concentration of the storage region 16 of the dummy mesa section 61 may be twice or more, five times or more, or ten times or more, the integrated concentration of the storage region 16 of the active mesa section 60. 【0129】 Figure 17 shows another example of a cross-section of the semiconductor device 100. The semiconductor device 100 in this example has a first dummy mesa portion 61-1 and a second dummy mesa portion 61-2, each having different contact resistances R2. The structure of the dummy mesa portion 61, other than the contact resistance R2, is the same as in any of the embodiments described in Figures 1 to 16. 【0130】 The first dummy mesa portion 61-1 and the second dummy mesa portion 61-2 are both in contact with the dummy trench portion 30. The first dummy mesa portion 61-1 is the dummy mesa portion 61 on the gate trench portion 40 side of the dummy mesa portion 61 that is in contact with the dummy trench portion 30. The second dummy mesa portion 61-2 is the dummy mesa portion 61 on the opposite side from the gate trench portion 40 (or the first dummy mesa portion 61-1). 【0131】 In this example, the dummy contact resistance of the first dummy mesa portion 61-1 is lower than that of the second dummy mesa portion 61-2. In the example shown in Figure 17, the first dummy mesa portion 61-1 is provided with a first resistive film 210-1, and the second dummy mesa portion 61-2 is provided with a second resistive film 210-2. The thickness of the second resistive film 210-2 may be greater than that of the first resistive film 210-1. In other examples, the dummy contact resistances of the first dummy mesa portion 61-1 and the second dummy mesa portion 61-2 may be adjusted by differentiating the doping concentration on the upper surface of the dummy mesa portion 61, or the area of ​​the contact hole 54 that exposes the upper surface of the dummy mesa portion 61. 【0132】 In the active mesa section 60, the holes below the emitter region 12 flow to the contact region 15, bypassing the emitter region 12. As a result, the distance the holes travel in the active mesa section 60 becomes large, which can cause latch-up. By making the dummy contact resistance of the first dummy mesa section 61-1, which is close to the active mesa section 60, relatively small, the holes below the active mesa section 60 can flow more easily to the first dummy mesa section 61-1. As a result, the hole current flowing through the active mesa section 60 can be reduced, and latch-up can be suppressed. The dummy contact resistance of the first dummy mesa section 61-1 may be half or less of the dummy contact resistance of the second dummy mesa section 61-2, or 25% or less, or 10% or less. However, the dummy contact resistors of both the first dummy mesa section 61-1 and the second dummy mesa section 61-2 satisfy the conditions for the dummy contact resistors of the dummy mesa section 61 as described in Figures 1 to 16. 【0133】 Figure 18 shows another example of the gate trench section 40 structure. The structure other than the gate trench section 40 is the same as in any of the embodiments described in Figures 1 to 17. In Figure 18, the vicinity of the gate trench section 40 is magnified. Also, the hatching of the gate conductive section 44 and dummy conductive section 34 has been omitted. 【0134】 In the gate trench portion 40 of this example, the thickness T2 of the gate insulating film 42 in contact with the dummy mesa portion 61 is smaller than the thickness T1 of the gate insulating film 42 in contact with the active mesa portion 60. The thickness of the gate insulating film 42 may be the thickness in the X-axis direction. The thickness of the gate insulating film 42 may be the average film thickness of the portion in contact with the base region 14. By making the gate insulating film 42 on the dummy mesa portion 61 side thinner, displacement current flows more easily from the dummy mesa portion 61 to the gate conductive portion 44. This shortens the turn-on time and further reduces turn-on loss. According to the configuration of this example, turn-on loss can be reduced even if the contact resistance ratio R2 / R1 is relatively small. The thickness T2 may be 75% or less of the thickness T1, or 50% or less. For example, after oxidizing the entire inner wall of the gate trench to form an insulating film, the insulating film on the dummy mesa portion 61 side can be selectively removed, and then the entire inner wall of the gate trench can be oxidized again to form a gate insulating film 42 with partially different thicknesses. 【0135】 Furthermore, the thickness of the dummy insulating film 32 in the dummy trench portion 30 is denoted as T3. Thickness T2 may be the same as thickness T3. Thickness T2 may be smaller than thickness T3. Also, the thicknesses T2 and T1 of the gate insulating film 42 may be the same, and the thickness T3 of the dummy insulating film 32 may be smaller than thickness T2. 【0136】 Figure 19 is a top view of the semiconductor device 100, showing some of the dummy mesa portions 61. In Figure 19, the third dummy mesa portion 61-3 and the fourth dummy mesa portion 61-4 are shown among the multiple dummy mesa portions 61. The other dummy mesa portions 61 are omitted in Figure 19. The structure of the third dummy mesa portion 61-3 and the fourth dummy mesa portion 61-4 is the same as that of the dummy mesa portions 61 described in Figures 1 to 18. 【0137】 The fourth dummy mesa portion 61-4 is located closer to the edge of the semiconductor substrate 10 (edge ​​102 in this example) than the third dummy mesa portion 61-3. For example, the third dummy mesa portion 61-3 is the central dummy mesa portion 61 in the X-axis direction among the multiple dummy mesa portions 61. For example, the fourth dummy mesa portion 61-4 is the outermost dummy mesa portion 61 in the X-axis direction among the multiple dummy mesa portions 61. 【0138】 The dummy contact resistance of the fourth dummy mesa portion 61-4 may be the same as, or lower than, the dummy contact resistance of the third dummy mesa portion 61-3. Near the edge of the semiconductor substrate 10, holes from the edge termination structure 90 tend to flow into the active mesa portion 60, making latch-up more likely. By making the dummy contact resistance of the fourth dummy mesa portion 61-4 relatively low, holes from the edge termination structure 90 can be more easily extracted by the fourth dummy mesa portion 61-4, thereby suppressing latch-up in the active mesa portion 60. The dummy contact resistance of the third dummy mesa portion 61-3 may be 1.2 times or more, 1.5 times or more, or 2 times or more than the dummy contact resistance of the fourth dummy mesa portion 61-4. The closer the dummy mesa portion 61 is to the edge of the semiconductor substrate 10 in the X-axis direction, the smaller the dummy contact resistance may be. Furthermore, the dummy contact resistance of the dummy mesa portion 61 closest to the edge of the semiconductor substrate 10 may be the minimum value among all the dummy contact resistances of the dummy mesa portions 61. 【0139】 Figure 20 is a top view of the semiconductor device 100, showing a portion of the dummy mesa portion 61. In Figure 20, the transistor portion 70 and the diode portion 80 of the active portion 160 are omitted. The semiconductor device 100 in this example has wiring 372 connected to the connection region 370 on the upper surface of the emitter electrode 52. The wiring 372 may be a linear wire, a plate-shaped lead frame, or a rod-shaped pin. If the wiring 372 is fixed with a conductive material such as solder, the conductive material is also included in the wiring 372. The connection region 370 is the region where the upper surface of the emitter electrode 52 and the wiring 372 are in contact. 【0140】 Figure 20 shows the fifth dummy mesa section 61-5 and the sixth dummy mesa section 61-6 among the multiple dummy mesa sections 61. The other dummy mesa sections 61 are omitted in Figure 20. The structure of the fifth dummy mesa section 61-5 and the sixth dummy mesa section 61-6 is the same as that of the dummy mesa section 61 described in Figures 1 to 18. 【0141】 The fifth dummy mesa portion 61-5 overlaps with any of the connection regions 370 in a top view. Part of the fifth dummy mesa portion 61-5 may overlap with the connection region 370, or the entire portion may overlap with the connection region 370. The sixth dummy mesa portion 61-6 does not overlap with any of the connection regions 370 in a top view. 【0142】 The dummy contact resistance of the fifth dummy mesa section 61-5 may be the same as, or lower than, the dummy contact resistance of the sixth dummy mesa section 61-6. In the region overlapping with the connection region 370, a large collector current may flow, making latch-up more likely. By making the dummy contact resistance of the fifth dummy mesa section 61-5 relatively low, it becomes easier to pull out the hole in the fifth dummy mesa section 61-5, thereby suppressing latch-up in the active mesa section 60. The dummy contact resistance of the sixth dummy mesa section 61-6 may be 1.2 times or more, 1.5 times or more, or 2 times or more than the dummy contact resistance of the fifth dummy mesa section 61-5. The closer the dummy mesa section 61 is to the connection region 370 in the X-axis direction, the smaller the dummy contact resistance may be. Furthermore, the dummy contact resistance of the fifth dummy mesa section 61-5 may be the minimum value among the dummy contact resistances of all dummy mesa sections 61. 【0143】 Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention. 【0144】 It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of symbols] 【0145】 10...Semiconductor substrate, 12...Emitter region, 14...Base region, 15...Contact region, 16...Storage region, 18...Drift region, 20...Buffer region, 21...Top surface, 22...Collector region, 23...Bottom surface, 24...Collector electrode, 30...Dummy trench section, 32...Dummy insulating film, 34...Dummy conductive section, 38...Interlayer insulating film, 40...Gate trench section, 42...Gate insulating film, 44...Gate conductive section, 52...Emitter electrode, 54...Contact hole, 60...Active mesa section, 61...Dummy mesa section, 70...Transistor section, 80...Diode D section, 81...extension area, 90...edge termination structure section, 92...guard ring, 100...semiconductor device, 102...edge, 112...gate pad, 130...outer periphery gate wiring, 131...active side gate wiring, 160...active section, 210...resistive film, 220...trench contact, 300...area, 301, 302, 303, 304, 311, 312, 313, 314, 321, 322, 323, 325...waveform, 330...peak section, 332, 333, 335...trough section, 343, 345...peak section, 352, 353, 355...maintenance increase area, 370...connection area, 372...wiring

Claims

[Claim 1] A semiconductor substrate having an upper surface and a lower surface, and provided with a first conductivity type drift region, An emitter electrode provided above the upper surface of the semiconductor substrate, A plurality of trench portions are provided on the upper surface of the semiconductor substrate and are arranged with intervals between them in the arrangement direction, Within the semiconductor substrate, there are multiple mesa portions sandwiched between each trench portion, Equipped with, The plurality of trenches include gate trenches to which a gate voltage is applied. One of the two mesa portions in contact with the gate trench portion is an active mesa portion in which a first conductivity type emitter region with a higher doping concentration than the drift region is positioned in contact with the gate trench portion. The other of the two mesa portions that are in contact with the gate trench portion is a dummy mesa portion that does not have the emitter region. The dummy contact resistance, which is the resistance between the dummy mesa portion and the emitter electrode, is 5000 times or more the active contact resistance, which is the resistance between the active mesa portion and the emitter electrode. Semiconductor equipment. [Claim 2] The dummy contact resistance is 30,000 times or more the active contact resistance. The semiconductor device according to claim 1. [Claim 3] The dummy contact resistance is 50,000 times or more the active contact resistance. The semiconductor device according to claim 1. [Claim 4] A semiconductor substrate having an upper surface and a lower surface, and provided with a first conductivity type drift region, An emitter electrode provided above the upper surface of the semiconductor substrate, A plurality of trench portions are provided on the upper surface of the semiconductor substrate and are arranged with intervals between them in the arrangement direction, Within the semiconductor substrate, there are multiple mesa portions sandwiched between each trench portion, Equipped with, The plurality of trenches include gate trenches to which a gate voltage is applied. One of the two mesa portions in contact with the gate trench portion is an active mesa portion in which a first conductivity type emitter region with a higher doping concentration than the drift region is positioned in contact with the gate trench portion. The other of the two mesa portions that are in contact with the gate trench portion is a dummy mesa portion that does not have the emitter region. The dummy contact resistance, which is the resistance between the dummy mesa portion and the emitter electrode, is 1000 times or more the active contact resistance, which is the resistance between the active mesa portion and the emitter electrode. The active mesa portion has a second conductivity type base region provided between the drift region and the emitter region. The dummy mesa portion has the base region between the drift region and the upper surface of the semiconductor substrate. The active mesa portion and the dummy mesa portion have a first conductivity type accumulation region between the base region and the drift region, with a doping concentration higher than that of the drift region. The integrated concentration obtained by integrating the doping concentration in the accumulation region of the dummy mesa in the depth direction is greater than the integrated concentration obtained by integrating the doping concentration in the accumulation region of the active mesa in the depth direction. Semiconductor equipment. [Claim 5] A semiconductor substrate having an upper surface and a lower surface, and provided with a first conductivity type drift region, An emitter electrode provided above the upper surface of the semiconductor substrate, A plurality of trench portions are provided on the upper surface of the semiconductor substrate and are arranged with intervals between them in the arrangement direction, Within the semiconductor substrate, there are multiple mesa portions sandwiched between each trench portion, Equipped with, The plurality of trenches include gate trenches to which a gate voltage is applied. One of the two mesa portions in contact with the gate trench portion is an active mesa portion in which a first conductivity type emitter region with a higher doping concentration than the drift region is positioned in contact with the gate trench portion. The other of the two mesa portions that are in contact with the gate trench portion is a dummy mesa portion that does not have the emitter region. The dummy contact resistance, which is the resistance between the dummy mesa portion and the emitter electrode, is 1000 times or more the active contact resistance, which is the resistance between the active mesa portion and the emitter electrode. The gate trench portion includes a gate conductive portion and a gate insulating film provided between the gate conductive portion and the semiconductor substrate. The gate insulating film in contact with the dummy mesa portion is thinner than the gate insulating film in contact with the active mesa portion. Semiconductor equipment. [Claim 6] A semiconductor substrate having an upper surface and a lower surface, and provided with a first conductivity type drift region, An emitter electrode provided above the upper surface of the semiconductor substrate, A plurality of trench portions are provided on the upper surface of the semiconductor substrate and are arranged with intervals between them in the arrangement direction, Within the semiconductor substrate, there are multiple mesa portions sandwiched between each trench portion, Equipped with, The plurality of trenches include gate trenches to which a gate voltage is applied. One of the two mesa portions in contact with the gate trench portion is an active mesa portion in which a first conductivity type emitter region with a higher doping concentration than the drift region is positioned in contact with the gate trench portion. The other of the two mesa portions that are in contact with the gate trench portion is a dummy mesa portion that does not have the emitter region. The dummy contact resistance, which is the resistance between the dummy mesa portion and the emitter electrode, is 1000 times or more the active contact resistance, which is the resistance between the active mesa portion and the emitter electrode. The plurality of trenches are arranged adjacent to the gate trenches with the dummy mesa in the arrangement direction, and include dummy trenches to which a voltage different from the gate voltage is applied. Of the mesa portions in contact with the dummy trench portion, the mesa portion on the gate trench portion side is a first dummy mesa portion that does not have an emitter region, and the mesa portion on the opposite side from the gate trench portion is a second dummy mesa portion that does not have an emitter region. The dummy contact resistance of the first dummy mesa is lower than the dummy contact resistance of the second dummy mesa. Semiconductor equipment. [Claim 7] A semiconductor substrate having an upper surface and a lower surface, and provided with a first conductivity type drift region, An emitter electrode provided above the upper surface of the semiconductor substrate, A plurality of trench portions are provided on the upper surface of the semiconductor substrate and are arranged with intervals between them in the arrangement direction, Within the semiconductor substrate, there are multiple mesa portions sandwiched between each trench portion, Equipped with, The plurality of trenches include gate trenches to which a gate voltage is applied. One of the two mesa portions in contact with the gate trench portion is an active mesa portion in which a first conductivity type emitter region with a higher doping concentration than the drift region is positioned in contact with the gate trench portion. The other of the two mesa portions that are in contact with the gate trench portion is a dummy mesa portion that does not have the emitter region. The dummy contact resistance, which is the resistance between the dummy mesa portion and the emitter electrode, is 1000 times or more the active contact resistance, which is the resistance between the active mesa portion and the emitter electrode. The plurality of mesa portions include a third dummy mesa portion that does not have an emitter region, and a fourth dummy mesa portion that is positioned closer to the edge of the semiconductor substrate than the third dummy mesa portion in the arrangement direction, and does not have an emitter region. The dummy contact resistance of the fourth dummy mesa is lower than the dummy contact resistance of the third dummy mesa. Semiconductor equipment. [Claim 8] A semiconductor substrate having an upper surface and a lower surface, and provided with a first conductivity type drift region, An emitter electrode provided above the upper surface of the semiconductor substrate, Wiring connected to the connection area on the upper surface of the emitter electrode, A plurality of trench portions are provided on the upper surface of the semiconductor substrate and are arranged with intervals between them in the arrangement direction, Within the semiconductor substrate, there are multiple mesa portions sandwiched between each trench portion, Equipped with, The plurality of trenches include gate trenches to which a gate voltage is applied. One of the two mesa portions in contact with the gate trench portion is an active mesa portion in which a first conductivity type emitter region with a higher doping concentration than the drift region is positioned in contact with the gate trench portion. The other of the two mesa portions that are in contact with the gate trench portion is a dummy mesa portion that does not have the emitter region. The dummy contact resistance, which is the resistance between the dummy mesa portion and the emitter electrode, is 1000 times or more the active contact resistance, which is the resistance between the active mesa portion and the emitter electrode. The plurality of mesa portions include a fifth dummy mesa portion that overlaps with the connection region in a top view and does not have the emitter region, and a sixth dummy mesa portion that does not overlap with the connection region in a top view and does not have the emitter region. The dummy contact resistance of the fifth dummy mesa is lower than the dummy contact resistance of the sixth dummy mesa. Semiconductor equipment. [Claim 9] A semiconductor substrate having an upper surface and a lower surface, and provided with a first conductivity type drift region, An emitter electrode provided above the upper surface of the semiconductor substrate, A plurality of trench portions are provided on the upper surface of the semiconductor substrate and are arranged with intervals between them in the arrangement direction, Within the semiconductor substrate, there are multiple mesa portions sandwiched between each trench portion, Equipped with, The plurality of trenches include gate trenches to which a gate voltage is applied. One of the two mesa portions in contact with the gate trench portion is an active mesa portion in which a first conductivity type emitter region with a higher doping concentration than the drift region is positioned in contact with the gate trench portion. The other of the two mesa portions that are in contact with the gate trench portion is a dummy mesa portion that does not have the emitter region. The dummy contact resistance, which is the resistance between the dummy mesa portion and the emitter electrode, is 1000 times or more the active contact resistance, which is the resistance between the active mesa portion and the emitter electrode. The current-voltage change rate characteristic, which shows the relationship between the collector current flowing through the semiconductor device and the rate of change of the collector-emitter voltage when the semiconductor device is turned on, is: The aforementioned voltage change rate shows a peak portion where it is at its maximum value, In the direction of increasing the collector current from the peak portion, there is a maintenance-increase region in which the voltage change rate is maintained or increases. Semiconductor device. [Claim 10] The current-voltage change rate characteristic is such that the voltage change rate when the collector current is the rated current is greater than the voltage change rate when the collector current is 5% of the rated current of the semiconductor device. The semiconductor device according to claim 9. [Claim 11] The current-voltage change rate characteristic has a valley where the voltage change rate is at its minimum in the region where the collector current is between 5% and 100% of the rated current of the semiconductor device. The semiconductor device according to claim 9 or 10. [Claim 12] A semiconductor substrate having an upper surface and a lower surface, and provided with a first conductivity type drift region, An emitter electrode provided above the upper surface of the semiconductor substrate, A plurality of trench portions are provided on the upper surface of the semiconductor substrate and are arranged with intervals between them in the arrangement direction, Within the semiconductor substrate, there are multiple mesa portions sandwiched between each trench portion, Equipped with, The plurality of trenches include gate trenches to which a gate voltage is applied. One of the two mesa portions in contact with the gate trench portion is an active mesa portion in which a first conductivity type emitter region with a higher doping concentration than the drift region is positioned in contact with the gate trench portion. The other of the two mesa portions that are in contact with the gate trench portion is a dummy mesa portion that does not have the emitter region. The active mesa portion is connected to the emitter electrode with a predetermined active contact resistor. The dummy mesa portion is connected to the emitter electrode with a predetermined dummy contact resistor. The dummy contact resistance is 5000 times or more than the active contact resistance. In a top view of the semiconductor substrate, a second conductivity type collector region is provided on the lower surface of the semiconductor substrate at a position overlapping with the active mesa portion, and also on the lower surface of the semiconductor substrate at a position overlapping with the dummy mesa portion in the top view. Semiconductor equipment. [Claim 13] The dummy contact resistance is 100,000 times or less the active contact resistance. The semiconductor device according to any one of claims 1 to 12. [Claim 14] The dummy mesa portion and the emitter electrode are further provided with a resistive film made of a material with a higher volume resistivity than the emitter electrode. The semiconductor device according to any one of claims 1 to 13. [Claim 15] The dummy mesa portion has a second conductivity type region exposed on the upper surface of the semiconductor substrate, The active mesa portion has a contact region of the second conductivity type with a higher doping concentration than the second conductivity type region of the dummy mesa portion. The semiconductor device according to any one of claims 1 to 14. [Claim 16] The active mesa portion has a second conductivity type base region provided between the drift region and the emitter region. The doping concentration in the second conductivity type region of the dummy mesa is less than or equal to that in the base region. The semiconductor device according to claim 15. [Claim 17] The semiconductor substrate further comprises an interlayer insulating film provided between the upper surface and the emitter electrode, The interlayer insulating film is provided with a first contact hole connecting the emitter electrode and the active mesa portion, and a second contact hole connecting the emitter electrode and the dummy mesa portion. In a top view, the total area of ​​the second contact holes for one dummy mesa portion is smaller than the total area of ​​the first contact holes for one active mesa portion. The semiconductor device according to any one of claims 1 to 16. [Claim 18] The active mesa portion is provided from the upper surface of the semiconductor substrate into the interior of the semiconductor substrate and has a trench contact that connects to the emitter electrode. The trench contact is not provided in the dummy mesa portion. The semiconductor device according to any one of claims 1 to 17. [Claim 19] A semiconductor substrate having an upper surface and a lower surface, and provided with a first conductivity type drift region, An emitter electrode provided above the upper surface of the semiconductor substrate, A plurality of trench portions are provided on the upper surface of the semiconductor substrate and are arranged with intervals between them in the arrangement direction, Within the semiconductor substrate, there are multiple mesa portions sandwiched between each trench portion, Equipped with, The plurality of trenches include gate trenches to which a gate voltage is applied. One of the two mesa portions in contact with the gate trench portion is an active mesa portion in which a first conductivity type emitter region with a higher doping concentration than the drift region is positioned in contact with the gate trench portion. The other of the two mesa portions that are in contact with the gate trench portion is a dummy mesa portion that does not have the emitter region. The current-voltage change rate characteristic, which shows the relationship between the collector current flowing through the semiconductor device and the rate of change of the collector-emitter voltage when the semiconductor device is turned on, is: The aforementioned voltage change rate shows a peak portion where it is at its maximum value, In the direction of increasing the collector current from the peak portion, there is a maintenance-increase region in which the voltage change rate is maintained or increases. Semiconductor device. [Claim 20] The current-voltage change rate characteristic is such that the voltage change rate when the collector current is the rated current is greater than the voltage change rate when the collector current is 5% of the rated current of the semiconductor device. The semiconductor device according to claim 19. [Claim 21] The current-voltage change rate characteristic has a valley where the voltage change rate is at its minimum in the region where the collector current is between 5% and 100% of the rated current of the semiconductor device. The semiconductor device according to claim 19 or 20. [Claim 22] The active mesa portion has a second conductivity type base region provided between the drift region and the emitter region. The dummy mesa portion has the base region between the drift region and the upper surface of the semiconductor substrate. The active mesa portion and the dummy mesa portion have a first conductivity type accumulation region between the base region and the drift region, with a doping concentration higher than that of the drift region. The integrated concentration obtained by integrating the doping concentration in the accumulation region of the dummy mesa in the depth direction is greater than the integrated concentration obtained by integrating the doping concentration in the accumulation region of the active mesa in the depth direction. The semiconductor device according to any one of claims 5 to 9. [Claim 23] The gate trench portion includes a gate conductive portion and a gate insulating film provided between the gate conductive portion and the semiconductor substrate. The gate insulating film in contact with the dummy mesa portion is thinner than the gate insulating film in contact with the active mesa portion. A semiconductor device according to any one of claims 4, 6, 7, 8, or 9. [Claim 24] The plurality of trenches are arranged adjacent to the gate trenches with the dummy mesa in the arrangement direction, and include dummy trenches to which a voltage different from the gate voltage is applied. Of the mesa portions in contact with the dummy trench portion, the mesa portion on the gate trench portion side is a first dummy mesa portion that does not have an emitter region, and the mesa portion on the opposite side from the gate trench portion is a second dummy mesa portion that does not have an emitter region. The dummy contact resistance of the first dummy mesa is lower than the dummy contact resistance of the second dummy mesa. A semiconductor device according to any one of claims 4, 5, 7, 8, or 9. [Claim 25] The plurality of mesa portions include a third dummy mesa portion that does not have an emitter region, and a fourth dummy mesa portion that is positioned closer to the edge of the semiconductor substrate than the third dummy mesa portion in the arrangement direction, and does not have an emitter region. The dummy contact resistance of the fourth dummy mesa is lower than the dummy contact resistance of the third dummy mesa. The semiconductor device according to any one of claims 4, 5, 6, 8, or 9. [Claim 26] The wiring further comprises connections to a connection region on the upper surface of the emitter electrode, The plurality of mesa portions include a fifth dummy mesa portion that overlaps with the connection region in a top view and does not have the emitter region, and a sixth dummy mesa portion that does not overlap with the connection region in a top view and does not have the emitter region. The dummy contact resistance of the fifth dummy mesa is lower than the dummy contact resistance of the sixth dummy mesa. A semiconductor device according to any one of claims 4, 5, 6, 7, or 9. [Claim 27] The current-voltage change rate characteristic, which shows the relationship between the collector current flowing through the semiconductor device and the rate of change of the collector-emitter voltage when the semiconductor device is turned on, is: The aforementioned voltage change rate shows a peak portion where it is at its maximum value, In the direction of increasing the collector current from the peak portion, there is a maintenance-increase region in which the voltage change rate is maintained or increases. has The semiconductor device according to any one of claims 4 to 8.

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