Semiconductor equipment

Abstract

To suppress a serge voltage of a semiconductor device.SOLUTION: A semiconductor device includes: a semiconductor substrate having an upper surface and a lower surface and provided with a first conductivity type drift region; and a buffer region provided between the drift region and the lower surface and having a higher doping concentration than that of the drift region. The buffer region has M doping concentration peaks provided at different positions in a depth direction of the semiconductor substrate, and a charge carrier coefficient α shown by an equation (1) is 2000 or more and 50000 or less for at least one integer i (i is an integer greater than or equal to 1 and less than or equal to M-1).SELECTED DRAWING: Figure 5

Description

[Technical Field] 【0001】 This invention relates to a semiconductor device. [Background technology] 【0002】 Conventionally, in semiconductor devices such as IGBTs, a configuration is known in which a buffer region such as a field stop layer is provided (see, for example, Patent Documents 1 and 2). Patent Document 1 WO2014-65080 Patent Document 2: Japanese Unexamined Patent Publication No. 2021-93541 [Overview of the Initiative] [Problems that the invention aims to solve] 【0003】 In semiconductor devices, it is preferable to suppress surge voltages during turn-off and other similar events. [Means for solving the problem] 【0004】 To solve the above problems, a first embodiment of the present invention provides a semiconductor device. The semiconductor device may include a semiconductor substrate having an upper surface and a lower surface, and a drift region of a first conductivity type provided therein. The semiconductor device may include a buffer region provided between the drift region and the lower surface, the buffer region having a higher doping concentration than the drift region. The buffer region may have M doping concentration peaks provided at different positions in the depth direction of the semiconductor substrate. The charge carrier coefficient α shown by equation (1) may be between 2000 and 50000 for any one integer i (where i is an integer between 1 and M-1). 【number】 however, v sat This is the saturation velocity (cm / s) of holes, which are charge carriers. J rate The rated current density (A / cm²) of the semiconductor device is the rated current density (A / cm²) of the semiconductor device. 2 ), VB is the avalanche breakdown voltage (V) of the semiconductor substrate, x i is the depth position (cm) from the upper surface of the i-th doping concentration peak among the plurality of doping concentration peaks in the buffer region, counted from the lower surface, x i+1 is the depth position (cm) from the upper surface of the (i + 1)-th doping concentration peak among the plurality of doping concentration peaks in the buffer region, counted from the lower surface, x j is the depth position (cm) from the upper surface of the PN junction that is disposed on the upper surface side of the buffer region and is closest to the buffer region in the depth direction, N DR is the doping concentration ( / cm 3 ) of the drift region, ε0 is the permittivity of vacuum, 8.85418×10 -14 (F / cm), ε r is the relative permittivity of the semiconductor substrate, q is the elementary charge, 1.60218×10 -19 (C). 【0005】 For at least one integer i, the charge carrier coefficient α may be 5000 or more. 【0006】 For at least one integer i, the charge carrier coefficient α may be 20000 or less. 【0007】 The buffer region may have three or more of the doping concentration peaks. The peak-to-peak distance between the i-th doping concentration peak and the (i + 1)-th doping concentration peak counted from the lower surface may be greater than the peak-to-peak distance between the (i + 1)-th doping concentration peak and the (i + 2)-th doping concentration peak. 【0008】 The distance between the i-th doping concentration peak and the (i+1)th doping concentration peak, counting from the lower surface, may be twice or more the distance between the (i+1)th doping concentration peak and the (i+2)th doping concentration peak. 【0009】 The distance between the i-th doping concentration peak and the (i+1)th doping concentration peak, counting from the bottom surface, may be greater than the distance between any of the other doping concentration peaks. 【0010】 The distance between the i-th doping concentration peak and the (i+1)th doping concentration peak, counting from the lower surface, may be 8 μm or more. 【0011】 The minimum doping concentration between the i-th doping concentration peak and the (i+1)th doping concentration peak, counting from the lower surface, may be 10 times or less the doping concentration in the drift region. 【0012】 The buffer region may have three or more doping concentration peaks. In equation (1), i may be 2. 【0013】 Each of the aforementioned multiple doping concentration peaks may have a peak at which the doping concentration shows a maximum value. When the semiconductor device is turned off with a power supply voltage of 0.7 times the rated voltage applied and a collector-emitter current of twice the rated current flowing, the position of the lower end of the space charge region at the point when the collector-emitter voltage matches the power supply voltage may be located between the peak of the i-th doping concentration peak and the peak of the (i+1)-th doping concentration peak, counting from the lower surface. 【0014】 Each of the plurality of doping concentration peaks may have a lower tail in which the doping concentration monotonically decreases from the apex toward the lower surface, and an upper tail in which the doping concentration monotonically decreases from the apex toward the upper surface. The position of the lower end of the space charge region may be located in a region that does not overlap with the upper tail of the i-th doping concentration peak. 【0015】 The doping concentration may exhibit a minimum value between the i-th doping concentration peak and the (i+1)-th doping concentration peak. The buffer region may have a flat portion between the i-th doping concentration peak and the (i+1)-th doping concentration peak where the doping concentration is 2 times or less the minimum value. The position of the lower end of the space charge region may be located in the flat portion. 【0016】 It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. Furthermore, subcombinations of these features may also constitute an invention. [Brief explanation of the drawing] 【0017】 [Figure 1] This is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention. [Figure 2] This is a magnified view of region D in Figure 1. [Figure 3] Figure 2 shows an example of an ee cross-section. [Figure 4] Figure 3 shows an example of the doping concentration distribution of 300 along the ff line. [Figure 5] This is an enlarged view of the doping concentration distribution 300 in buffer region 20. [Figure 6] This is an example of a circuit 400 in which the semiconductor device 100 is used. [Figure 7] This figure schematically shows one arm of the semiconductor device 100 in Figure 6. [Figure 8]This figure shows an overview of the time waveforms of the collector-emitter current Ice, collector-emitter voltage Vce, and power (W) when the semiconductor device 100 shown in Figure 6 is turned off. [Figure 9] This figure shows an example of the distribution of electric field strength E from the vicinity of depth position xj to depth position xE. [Figure 10] The doping concentration distribution of the buffer region 20 in one embodiment is shown. [Figure 11] This figure shows the relationship between the charge carrier coefficient α and the peak voltage ratio (Vp / Vcc) in the first embodiment (rated voltage 600V). [Figure 12] This figure shows doping concentration peaks 210-i and 210-i+1, positioned on either side of the lower end position xE of the space charge region. [Modes for carrying out the invention] 【0018】 The present invention will be described below through embodiments of the invention, but these embodiments are not intended to limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention. 【0019】 In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "top," and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the top surface, and the other surface as the bottom surface. The directions of "top" and "bottom" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted. 【0020】 In this specification, technical matters may be described using the Cartesian coordinate axes, the X, Y, and Z axes. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z and -Z axes. 【0021】 In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction. 【0022】 Furthermore, the region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate is sometimes referred to as the top surface. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate is sometimes referred to as the bottom surface. 【0023】 In this specification, the terms "identical" or "equal" may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 10%. 【0024】 In this specification, the conductivity type of a doped region containing impurities is described as either P-type or N-type. In this specification, impurities may specifically refer to either N-type donors or P-type acceptors, and may be referred to as dopants. In this specification, doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor exhibiting either an N-type conductivity or a P-type conductivity. 【0025】 In this specification, doping concentration means the concentration of the donor or acceptor at thermal equilibrium. In this specification, net doping concentration means the net concentration obtained by adding up the charge polarity, with the donor concentration being the concentration of positive ions and the acceptor concentration being the concentration of negative ions. As an example, the donor concentration is N D , the acceptor concentration is N A Therefore, the net doping concentration at any given position is N D -N A In this specification, net doping concentration may be simply referred to as doping concentration. 【0026】 A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, a VOH defect in a semiconductor, which is a combination of a vacancy (V), oxygen (O), and hydrogen (H), functions as an electron-supplying donor. In this specification, a VOH defect may be referred to as a hydrogen donor. A hydrogen donor may be a donor that is a combination of at least a vacancy (V) and hydrogen (H). 【0027】 In this specification, the semiconductor substrate has N-type bulk donors distributed throughout. Bulk donors are donors from dopants that are substantially uniformly contained within the ingot during the manufacturing of the semiconductor substrate ingot. In this example, the bulk donor is an element other than hydrogen. The bulk donor dopants are, for example, phosphorus, antimony, arsenic, selenium, or sulfur, but are not limited to these. In this example, the bulk donor is phosphorus. Bulk donors are also contained in the P-type region. The semiconductor substrate may be a wafer cut from a semiconductor ingot, or it may be a chip made by cutting a wafer into individual pieces. The semiconductor ingot may be manufactured by one of the following methods: the Czochralski method (CZ method), the magnetic field-applied Czochralski method (MCZ method), or the float-zone method (FZ method). In this example, the ingot is manufactured by the MCZ method. The oxygen concentration in the substrate manufactured by the MCZ method is 1 × 10⁻¹⁶ 17 ~7×10 17 / cm 3 The oxygen concentration in a substrate manufactured by the FZ method is 1 × 10⁻⁶. 15 ~5×10 16 / cm 3 The oxygen concentration tends to generate hydrogen donors more easily. The bulk donor concentration may be the chemical concentration of bulk donors distributed throughout the semiconductor substrate, and may be a value between 90% and 100% of that chemical concentration. Alternatively, a non-doped substrate that does not contain dopants such as phosphorus may be used as the semiconductor substrate. In that case, the bulk donor concentration (D0) of the non-doped substrate may be, for example, 1 × 10⁻⁶. 10 / cm 3The above 5 x 10 12 / cm 3 The following applies: The bulk donor concentration (D0) of the non-doped substrate is preferably 1 × 10⁻⁶. 11 / cm 3 That concludes the explanation. The bulk donor concentration (D0) of the non-doped substrate is preferably 5 × 10⁻⁶. 12 / cm 3 The following applies. Note that the concentrations in this invention may be values ​​at room temperature. For example, the values ​​at room temperature may be those at 300 K (Kelvin) (approximately 26.9°C). 【0028】 In this specification, when P+ type or N+ type is mentioned, it means a higher doping concentration than P type or N type, and when P- type or N- type is mentioned, it means a lower doping concentration than P type or N type. Furthermore, when P++ type or N++ type is mentioned in this specification, it means a higher doping concentration than P+ type or N+ type. Unless otherwise specified, the units used in this specification are SI units. Although units of length may be expressed in cm, calculations may be performed after converting to meters (m). 【0029】 In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electrical activation state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by voltage-capacitance (CV) spectroscopy. Alternatively, the carrier concentration measured by broadened resistance (SR) spectroscopy may be used as the net doping concentration. The carrier concentration measured by CV or SR spectroscopy may be the value at thermal equilibrium. Furthermore, in the N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in that region may be used as the acceptor concentration. In this specification, the doping concentration in the N-type region may be referred to as the donor concentration, and the doping concentration in the P-type region may be referred to as the acceptor concentration. 【0030】 Furthermore, if the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be used as the concentration of the donor, acceptor, or net doping in that region. In cases where the concentrations of the donor, acceptor, or net doping are nearly uniform, the average value of the concentrations of the donor, acceptor, or net doping in that region may be used as the concentration of the donor, acceptor, or net doping. In this specification, concentrations per unit volume are expressed as atoms / cm³. 3 , or / cm 3 This unit is used for donor or acceptor concentrations in semiconductor substrates, or for chemical concentrations. The atom notation may be omitted. 【0031】 The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. When measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value for the crystalline state in the range where current flows. The decrease in carrier mobility occurs because carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc. 【0032】 The donor or acceptor concentrations calculated from carrier concentrations measured by the CV method or SR method may be lower than the chemical concentrations of the elements that act as donors or acceptors. For example, in silicon semiconductors, the donor concentrations of phosphorus or arsenic, or the acceptor concentration of boron, are approximately 99% of their respective chemical concentrations. On the other hand, the donor concentration of hydrogen, which also acts as a donor in silicon semiconductors, is approximately 0.1% to 10% of the hydrogen chemical concentration. 【0033】 Figure 1 is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention. In Figure 1, the positions of each component projected onto the upper surface of the semiconductor substrate 10 are shown. In Figure 1, only some components of the semiconductor device 100 are shown, and some components are omitted. 【0034】 The semiconductor device 100 comprises a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has edges 162 when viewed from above. In this specification, when simply referred to as "top view," it means viewing from the top side of the semiconductor substrate 10. In this example, the semiconductor substrate 10 has two pairs of edges 162 that face each other when viewed from above. In Figure 1, the X and Y axes are parallel to either edge 162. The Z axis is perpendicular to the top surface of the semiconductor substrate 10. 【0035】 The semiconductor substrate 10 is provided with an active area 160. The active area 160 is a region in which the main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 100 when the semiconductor device 100 is operating. An emitter electrode is provided above the active area 160, but it is omitted in Figure 1. The active area 160 may refer to the region that overlaps with the emitter electrode when viewed from above. Also, the region sandwiched between the active areas 160 when viewed from above may be included in the active area 160. 【0036】 The active section 160 is provided with at least one of a transistor section 70 including a transistor element such as an IGBT (Insulated Gate Bipolar Transistor), and a diode section 80 including a diode element such as a freewheeling diode (FWD). In the example shown in Figure 1, the transistor section 70 and the diode section 80 are arranged alternately along a predetermined arrangement direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 in this example is a reverse-conducting IGBT (RC-IGBT). 【0037】 In Figure 1, the region where the transistor section 70 is located is denoted by the symbol "I," and the region where the diode section 80 is located is denoted by the symbol "F." In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (Y-axis direction in Figure 1). The transistor section 70 and the diode section 80 may each have their longitudinal length in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section described later. 【0038】 The diode section 80 has an N+ type cathode region in the area in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is the region that overlaps with the cathode region when viewed from above. A P+ type collector region may be provided on the lower surface of the semiconductor substrate 10 in areas other than the cathode region. In this specification, an extension region 81, which is an extension of the diode section 80 in the Y-axis direction to the gate wiring described later, may also be included in the diode section 80. A collector region is provided on the lower surface of the extension region 81. 【0039】 The transistor section 70 has a P+ type collector region in the area in contact with the lower surface of the semiconductor substrate 10. Furthermore, the transistor section 70 has a gate structure periodically arranged on the upper surface side of the semiconductor substrate 10, which includes an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film. 【0040】 The semiconductor device 100 may have one or more pads on the semiconductor substrate 10. In this example, the semiconductor device 100 has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current sensing pad. Each pad is located near the edge 162. The vicinity of the edge 162 refers to the area between the edge 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as wires. 【0041】 A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench of the active portion 160. The semiconductor device 100 is provided with gate wiring that connects the gate pad 164 to the gate trench. In Figure 1, the gate wiring is shown with diagonal hatching. 【0042】 The gate wiring in this example has an outer gate wiring 130 and an active gate wiring 131. The outer gate wiring 130 is positioned between the active portion 160 and the edge 162 of the semiconductor substrate 10 in a top view. In this example, the outer gate wiring 130 surrounds the active portion 160 in a top view. The area surrounded by the outer gate wiring 130 in a top view may be considered the active portion 160. Furthermore, a well region is formed below the gate wiring. The well region is a P-type region with a higher density than the base region, which will be described later, and is formed from the top surface of the semiconductor substrate 10 to a position deeper than the base region. The area surrounded by the well region in a top view may be considered the active portion 160. 【0043】 The outer perimeter gate wiring 130 is connected to the gate pad 164. The outer perimeter gate wiring 130 is located above the semiconductor substrate 10. The outer perimeter gate wiring 130 may be a metal wiring containing aluminum or the like. 【0044】 The active gate wiring 131 is provided in the active section 160. By providing the active gate wiring 131 in the active section 160, variations in the wiring length from the gate pad 164 can be reduced for each region of the semiconductor substrate 10. 【0045】 The outer periphery gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active portion 160. The outer periphery gate wiring 130 and the active side gate wiring 131 are positioned above the semiconductor substrate 10. The outer periphery gate wiring 130 and the active side gate wiring 131 may be wirings formed from a semiconductor such as polysilicon doped with impurities. 【0046】 The active gate wiring 131 may be connected to the outer gate wiring 130. In this example, the active gate wiring 131 extends in the X-axis direction from one outer gate wiring 130 to the other outer gate wiring 130 that sandwiches the active section 160, crossing the active section 160 approximately in the center in the Y-axis direction. When the active section 160 is divided by the active gate wiring 131, the transistor section 70 and the diode section 80 may be arranged alternately in the X-axis direction in each divided region. 【0047】 Furthermore, the semiconductor device 100 may also include a temperature sensing unit (not shown) which is a PN junction diode made of polysilicon or the like, and a current detection unit (not shown) which simulates the operation of a transistor unit provided in the active unit 160. 【0048】 In this example, the semiconductor device 100 includes an edge termination structure 90 between the active portion 160 and the edge 162 when viewed from above. In this example, the edge termination structure 90 is positioned between the outer peripheral gate wiring 130 and the edge 162. The edge termination structure 90 mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf, which are provided in an annular shape surrounding the active portion 160. 【0049】 Figure 2 is an enlarged view of region D in Figure 1. Region D is the region including the transistor section 70, the diode section 80, and the active-side gate wiring 131. The semiconductor device 100 in this example includes a gate trench section 40, a dummy trench section 30, a well section 11, an emitter section 12, a base section 14, and a contact section 15, which are provided inside the upper surface of the semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are examples of trench sections. The semiconductor device 100 in this example also includes an emitter electrode 52 and an active-side gate wiring 131, which are provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate wiring 131 are provided separately from each other. 【0050】 An interlayer insulating film is provided between the emitter electrode 52 and the active gate wiring 131 and the upper surface of the semiconductor substrate 10, but this is omitted in Figure 2. In this example, contact holes 54 are provided in the interlayer insulating film, penetrating the film. In Figure 2, each contact hole 54 is hatched with diagonal lines. 【0051】 The emitter electrode 52 is provided above the gate trench 40, dummy trench 30, well region 11, emitter region 12, base region 14, and contact region 15. The emitter electrode 52 contacts the emitter region 12, contact region 15, and base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. The emitter electrode 52 is also connected to a dummy conductive part in the dummy trench 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to a dummy conductive part of the dummy trench 30 at its tip in the Y-axis direction. The dummy conductive part of the dummy trench 30 does not need to be connected to the emitter electrode 52 and the gate conductive part, and may be controlled to a potential different from the potential of the emitter electrode 52 and the gate conductive part. 【0052】 The active gate wiring 131 connects to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30. 【0053】 The emitter electrode 52 is formed from a material containing metal. Figure 2 shows the area in which the emitter electrode 52 is provided. For example, at least a portion of the emitter electrode 52 is formed from aluminum or an aluminum-silicon alloy, such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal formed from titanium or a titanium compound in the layer below the region formed from aluminum or the like. Furthermore, it may have a plug formed by embedding tungsten or the like in the contact hole so as to be in contact with the barrier metal and the aluminum or the like. 【0054】 The well region 11 is provided overlapping with the active gate wiring 131. The well region 11 also extends to a predetermined width in an area that does not overlap with the active gate wiring 131. In this example, the well region 11 is provided away from the Y-axis end of the contact hole 54 towards the active gate wiring 131. The well region 11 is a second conductivity type region with a higher doping concentration than the base region 14. In this example, the base region 14 is P-type, and the well region 11 is P+ type. 【0055】 Each of the transistor section 70 and the diode section 80 has multiple trench sections arranged in the direction of arrangement. In this example, the transistor section 70 has one or more gate trench sections 40 and one or more dummy trench sections 30 alternately provided along the direction of arrangement. In this example, the diode section 80 has multiple dummy trench sections 30 provided along the direction of arrangement. In this example, the diode section 80 does not have gate trench sections 40. 【0056】 The gate trench portion 40 in this example may have two linear portions 39 (the trench portion which is linear along the extension direction) that extend along the extension direction perpendicular to the alignment direction, and a tip portion 41 that connects the two linear portions 39. In Figure 2, the extension direction is the Y-axis direction. 【0057】 Preferably, at least a portion of the tip portion 41 is provided in a curved shape when viewed from above. By connecting the ends of the two straight portions 39 in the Y-axis direction with the tip portion 41, electric field concentration at the ends of the straight portions 39 can be mitigated. 【0058】 In the transistor section 70, the dummy trench section 30 is provided between each of the straight sections 39 of the gate trench section 40. There may be one dummy trench section 30 between each of the straight sections 39, or there may be multiple dummy trench sections 30. The dummy trench section 30 may have a straight shape extending in the extension direction, and like the gate trench section 40, it may have a straight section 29 and a tip section 31. The semiconductor device 100 shown in Figure 2 includes both a dummy trench section 30 with a straight shape without a tip section 31 and a dummy trench section 30 with a tip section 31. 【0059】 The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The Y-axis ends of the gate trench portion 40 and the dummy trench portion 30 are located in the well region 11 when viewed from above. In other words, at the Y-axis end of each trench portion, the bottom in the depth direction of each trench portion is covered by the well region 11. This makes it possible to mitigate electric field concentration at the bottom of each trench portion. 【0060】 In the arrangement direction, mesa portions are provided between each trench portion. A mesa portion refers to a region within the semiconductor substrate 10 that is sandwiched between trench portions. For example, the upper end of a mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of a mesa portion is the same as the depth position of the lower end of a trench portion. In this example, the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending along the trench in the extension direction (Y-axis direction). In this example, a mesa portion 60 is provided in the transistor portion 70, and a mesa portion 61 is provided in the diode portion 80. In this specification, when simply referred to as a mesa portion, it refers to mesa portion 60 and mesa portion 61, respectively. 【0061】 Each mesa portion is provided with a base region 14. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region closest to the active gate wiring 131 is defined as base region 14-e. Figure 2 shows the base region 14-e located at one end of each mesa portion in the extending direction, but a base region 14-e is also located at the other end of each mesa portion. In each mesa portion, at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15 may be provided in the region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided in the depth direction between the base region 14 and the upper surface of the semiconductor substrate 10. 【0062】 The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may have a contact region 15 exposed on the upper surface of the semiconductor substrate 10. 【0063】 Each of the contact region 15 and emitter region 12 in the mesa portion 60 extends from one trench portion to the other in the X-axis direction. As an example, the contact region 15 and emitter region 12 of the mesa portion 60 are arranged alternately along the extension direction (Y-axis direction) of the trench portion. 【0064】 In other examples, the contact region 15 and emitter region 12 of the mesa portion 60 may be arranged in a stripe pattern along the extension direction (Y-axis direction) of the trench portion. For example, the emitter region 12 may be provided in the region in contact with the trench portion, and the contact region 15 may be provided in the region sandwiched between the emitter regions 12. 【0065】 The mesa portion 61 of the diode portion 80 does not have an emitter region 12. A base region 14 and a contact region 15 may be provided on the upper surface of the mesa portion 61. In the region on the upper surface of the mesa portion 61 sandwiched between the base regions 14-e, a contact region 15 may be provided in contact with each base region 14-e. In the region on the upper surface of the mesa portion 61 sandwiched between the contact regions 15, a base region 14 may be provided. The base region 14 may be arranged in the entire region sandwiched between the contact regions 15. 【0066】 A contact hole 54 is provided above each mesa portion. The contact holes 54 are located in the region sandwiched between the base region 14-e. In this example, the contact holes 54 are provided above the contact region 15, the base region 14, and the emitter region 12. The contact holes 54 are not provided in the region corresponding to the base region 14-e and the well region 11. The contact holes 54 may be located in the center of the mesa portion 60 in the alignment direction (X-axis direction). 【0067】 In the diode section 80, an N+ type cathode region 82 is provided in the region adjacent to the lower surface of the semiconductor substrate 10. In the region on the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided, a P+ type collector region 22 may be provided. The cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. In Figure 2, the boundary between the cathode region 82 and the collector region 22 is shown by a dotted line. 【0068】 The cathode region 82 is positioned away from the well region 11 in the Y-axis direction. This ensures a distance between the cathode region 82 and the P-type region (well region 11), which has a relatively high doping concentration and is formed to a deep position, thereby improving pressure resistance. In this example, the Y-axis end of the cathode region 82 is positioned further from the well region 11 than the Y-axis end of the contact hole 54. In other examples, the Y-axis end of the cathode region 82 may be positioned between the well region 11 and the contact hole 54. 【0069】 Figure 3 shows an example of the ee cross-section in Figure 2. The ee cross-section is the XZ plane passing through the emitter region 12 and the cathode region 82. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross-section. 【0070】 The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film that includes at least one layer of insulating film such as silicate glass with impurities such as boron or phosphorus added, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with contact holes 54 as described in Figure 2. 【0071】 The emitter electrode 52 is located above the interlayer insulating film 38. The emitter electrode 52 is in contact with the upper surface 21 of the semiconductor substrate 10 through a contact hole 54 in the interlayer insulating film 38. The collector electrode 24 is located on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metallic material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (Z-axis direction) is referred to as the depth direction. 【0072】 The semiconductor substrate 10 has an N-type or N-type drift region 18. The drift region 18 is provided in both the transistor section 70 and the diode section 80. 【0073】 In the mesa portion 60 of the transistor portion 70, an N+ type emitter region 12 and a P- type base region 14 are provided in order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+ type storage region 16 may also be provided in the mesa portion 60. The storage region 16 is located between the base region 14 and the drift region 18. 【0074】 The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The doping concentration of the emitter region 12 is higher than that of the drift region 18. 【0075】 The base region 14 is located below the emitter region 12. In this example, the base region 14 is located in contact with the emitter region 12. The base region 14 may be in contact with the trenches on both sides of the mesa region 60. 【0076】 The accumulation region 16 is located below the base region 14. The accumulation region 16 is an N+ type region with a higher doping concentration than the drift region 18. In other words, the donor concentration in the accumulation region 16 is higher than that in the drift region 18. By providing a high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60. 【0077】 A P-type base region 14 is provided in the mesa portion 61 of the diode portion 80, in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. A storage region 16 may also be provided below the base region 14 in the mesa portion 61. 【0078】 In both the transistor section 70 and the diode section 80, an N+ type buffer section 20 may be provided below the drift section 18. The doping concentration in the buffer section 20 is higher than the doping concentration in the drift section 18. The buffer section 20 may have a concentration peak with a higher doping concentration than the drift section 18. The doping concentration of the concentration peak refers to the doping concentration at the peak of the concentration peak. Furthermore, the doping concentration of the drift section 18 may be the average value of the doping concentration in a region where the doping concentration distribution is nearly flat. 【0079】 The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peaks of the buffer region 20 may be located at the same depth as, for example, the chemical concentration peaks of hydrogen (proton) or phosphorus. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82. 【0080】 In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than that of the base region 14. The collector region 22 may contain the same acceptors as the base region 14, or it may contain different acceptors. The acceptors of the collector region 22 are, for example, boron. 【0081】 In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration of the cathode region 82 is higher than that of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements that serve as donors and acceptors for each region are not limited to the examples described above. The collector region 22 and the cathode region 82 are exposed to the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metallic material such as aluminum. 【0082】 One or more gate trenches 40 and one or more dummy trenches 30 are provided on the upper surface 21 of the semiconductor substrate 10. Each trench extends from the upper surface 21 of the semiconductor substrate 10, through the base region 14, and down to below the base region 14. In regions where at least one of the emitter region 12, contact region 15, and storage region 16 is provided, each trench also penetrates these doping regions. The statement that a trench penetrates a doping region is not limited to manufacturing in the order of forming the doping region before forming the trench. Manufacturing in which doping regions are formed between the trenches after the trenches have been formed is also included in the statement that a trench penetrates a doping region. 【0083】 As described above, the transistor section 70 is provided with a gate trench section 40 and a dummy trench section 30. The diode section 80 is provided with a dummy trench section 30, but not with a gate trench section 40. In this example, the boundary between the diode section 80 and the transistor section 70 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22. 【0084】 The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided covering the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench, on the inside of the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. 【0085】 The gate conductive portion 44 may be longer than the base region 14 in the depth direction. The gate trench portion 40 in this cross-section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface of the base region 14 that is in contact with the gate trench portion 40. 【0086】 The dummy trench portion 30 may have the same structure as the gate trench portion 40 in its cross-section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided covering the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is located inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed from the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 may be formed from a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction. 【0087】 In this example, the gate trench portion 40 and the dummy trench portion 30 are covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottom portions of the dummy trench portion 30 and the gate trench portion 40 may be curved (curved in cross-section) with a downward convex shape. In this specification, the depth position of the lower end of the gate trench portion 40 is x t Let's assume that. 【0088】 Figure 4 shows an example of the doping concentration distribution 300 at the ff line in Figure 3. The ff line is a line parallel to the Z axis that passes through the mesa 60. The horizontal axis in Figure 4 shows the depth position (position in the Z axis direction) within the semiconductor substrate 10. In this specification, unless otherwise specified, the upper surface 21 of the semiconductor substrate 10 is used as the reference position in the Z axis direction, and the distance from the upper surface 21 is used as the position in the Z axis direction. 【0089】 A drift region 18 is provided in the semiconductor substrate 10. The doping concentration in the drift region 18 may be approximately constant. Doping concentration N in the drift region 18 DRThis may coincide with the bulk donor concentration. In other examples, the doping concentration in the drift region 18 may be higher than the bulk donor concentration. An emitter region 12, a base region 14, and a storage region 16 are provided on the upper surface 21 side of the semiconductor substrate 10. The emitter region 12, the base region 14, and the storage region 16 may each have a peak in doping concentration. 【0090】 A buffer region 20 is provided between the drift region 18 and the bottom surface 23. The buffer region 20 has multiple doping concentration peaks 210 with higher doping concentrations than the drift region 18. In the example in Figure 4, there are four doping concentration peaks 210, but the number of doping concentration peaks 210 is not limited to this. A collector region 22 is provided between the buffer region 20 and the bottom surface 23. The collector region 22 may have doping concentration peaks. The collector region 22 is in contact with the bottom surface 23. 【0091】 When the semiconductor device 100 (transistor section 70 in this example) is turned off, the collector-emitter voltage V ce As it gradually rises, the depth position x of the PN junction on the upper surface 21 side (in this example, the PN junction formed by the base region 14 and the storage region 16) j A space charge region (also called a depletion layer) extends from the bottom surface 23. Voltage V ce When the space charge region reaches near the peak voltage of the doping concentration peak 210, the collector-emitter voltage V ce Surge voltages are more likely to occur in the time waveform. PN junction position x j This may be the position of the PN junction closest to the buffer region 20 in the depth direction, located on the upper surface 21 side of the buffer region 20. For example, in the example of Figure 4, if the storage region 16 does not exist, the position of the PN junction formed by the drift region 18 and the base region 14 is position x j This is the result. In other examples, the position x of the PN junction. jThis could be the position of the PN junction that serves as the starting point for the expansion of the depletion layer (space charge region) when the gate is in the off state (i.e., when an off voltage is applied to the gate conductive part 44) and a voltage is applied between the electrode formed on the lower surface 23 (collector electrode 24 in this example) and the electrode formed on the upper surface 21 (emitter electrode 52 in this example). For example, in the example in Figure 4, the position of the PN junction between the base region 14 and the storage region 16 (or the drift region 18 if the storage region 16 does not exist) is x j This is the result. In other examples, the position x of the PN junction. j This may be the position of a PN junction between a region electrically connected to an electrode formed on the upper surface 21 (emitter electrode 52 in this example) (base region 14 in this example) and a region that is in the opposite direction of conductivity to the said region and is located on the lower surface 23 side of the said region (storage region 16 or drift region 18 in this example). A space charge region is a region having a finite value for which the space charge density is not zero. 【0092】 In the semiconductor device 100, the voltage V is adjusted by adjusting the doping concentration distribution in the buffer region 20. ce This adjusts the lower limit position of the space charge region when it is near the peak voltage. ce Suppresses surge voltage in the time waveform of voltage V. ce The peak voltage is the avalanche breakdown voltage V of the transistor section 70. B Since it does not exceed the voltage V ce The upper limit that can be taken is the avalanche pressure resistance V B Voltage V ce It may also be the peak voltage. That is, in semiconductor device 100, the voltage V ve Avalanche pressure resistant V B In this case, the lower end position of the space charge region may be adjusted. Here, the avalanche breakdown voltage V B This may be the voltage at which, with the gate off, a positive voltage is applied between the electrode formed on the lower surface 23 (collector electrode 24 in this example) and the electrode formed on the upper surface 21 (emitter electrode 52 in this example), causing the maximum electric field strength near the PN junction to reach the critical electric field strength, resulting in avalanche breakdown due to impact ionization. Note that the avalanche breakdown voltage V is the voltage at which the maximum electric field strength near the PN junction reaches the critical electric field strength.B This can be calculated from the material of the semiconductor substrate 10 and the doping concentration distribution, or it may be a specification value set by the designer of the semiconductor device 100. 【0093】 Figure 5 is an enlarged view of the doping concentration distribution 300 in the buffer region 20. The buffer region 20 has M doping concentration peaks 210-k (where k is an integer between 1 and M, and M is an integer between 1 and M) (where M is an integer between 2 and M). In this example, doping concentration peak 210-k is the k-th doping concentration peak 210 counting from the side closest to the bottom surface 23. That is, doping concentration peak 210-1 is the doping concentration peak 210 closest to the bottom surface 23, and doping concentration peak 210-M is the doping concentration peak 210 furthest from the bottom surface 23. In this example, M=4. M may be an integer greater than or equal to 2, an integer greater than or equal to 3, or an integer greater than or equal to 4. M may be an integer less than or equal to 100, an integer less than or equal to 50, an integer less than or equal to 30, or an integer less than or equal to 10. In the example in Figure 5, the doping concentration is higher for doping concentration peaks 210 closer to the bottom surface 23, but this is not limited to this. However, the doping concentration peak 210-1 closest to the bottom surface 23 is preferably at a higher doping concentration than the other doping concentration peaks 210. The doping concentration peak 210-M furthest from the bottom surface 23 may be at a lower or higher doping concentration than the adjacent doping concentration peak 210-M-1. 【0094】 Each doping concentration peak 210-k has a vertex 211-k, an upper tail 212-k, and a lower tail 213-k. The vertex 211-k is the point where the doping concentration shows its maximum value. The depth position x of the vertex 211-k. k These can be used as the depth positions of the respective doping concentration peaks at 210-k. 【0095】 The upper tail 212-k is the region where the doping concentration decreases monotonically from the peak 211-k toward the top surface 21. The lower tail 213-k is the region where the doping concentration decreases monotonically from the peak 211-k toward the bottom surface 23. Monotonically decreasing means that the doping concentration decreases as you move away from the peak 211-k. 【0096】 When the transistor section 70 is turned off, the collector-emitter voltage V ce is the peak voltage (or avalanche breakdown voltage V) B When this happens, position x j The lower end position of the space charge region extending from the lower surface 23 is x E Let's assume the bottom end position is x. E It is preferable that it be positioned so as not to overlap with the peak 211-k of any of the doping concentration peaks 210-k. Lower end position x E It does not need to be included in the full width at half maximum of any doping concentration peak 210-k. 【0097】 The lower end position x in this example E It is located between the i-th doping concentration peak 210-i, counting from the bottom surface 23, and the (i+1)th doping concentration peak 210-i+1, counting from the bottom surface 23. The region between the two doping concentration peaks 210 may refer to the region between the two vertices 211. In the example in Figure 5, i=2. In other examples, i may be 1, and i may be any other integer. 【0098】 The distance between doping concentration peak 210-i and doping concentration peak 210-i+1 is (x i -x i+1 ) is the distance between the peaks (x) of doping concentration peak 210-i+1 and doping concentration peak 210-i+2. i+1 -x i+2 ) is greater than. In the example in Figure 5, the interpeak distance (x2-x3) between doping concentration peak 210-2 and doping concentration peak 210-3 is greater than the interpeak distance (x3-x4) between doping concentration peak 210-3 and doping concentration peak 210-4. i -xi+1 By increasing the size of the lower end position x E This makes it easier to position it away from vertex 211. Peak distance (x i -x i+1 ) is the distance between peaks (x i+1 -x i+2 It may be 1.5 times or more, 2 times or more, or 3 times or more. 【0099】 The distance between doping concentration peak 210-i and doping concentration peak 210-i+1 may be greater than any other distance between peaks. With this configuration, the lower end position x E This makes it easier to position the peaks away from vertices 211-i and 211-i+1. In the example in Figure 5, the distance between peaks (x2-x3) is greater than any of the other distances between peaks (x1-x2 and x3-x4). i -x i+1 ) may be 1.5 times, 2 times, or 3 times the longest distance between other peaks. 【0100】 Peak-to-peak distance (x i -x i+1 The peak distance (x) may be 8 μm or greater. i -x i+1 The diameter of the particle may be 10 μm or larger, and may also be 15 μm or larger. 【0101】 Bottom position x E It may be positioned in a range that does not overlap with the upper edge 212-i of the doping concentration peak 210-i. Lower end position x E It may be positioned in a range that does not overlap with the lower tail 213-i+1 of the doping concentration peak 210-i+1. This results in a collector-emitter voltage V ce The voltage rises to near the peak voltage, and the space charge region is at the lower end position x E In a state where it extends to the vicinity of, the lower end position x E This prevents the doping concentration from increasing as it approaches the target value. This allows for the suppression of surge voltage. 【0102】 The buffer region 20 may have a flat portion 220 between two vertices 211-i and 211-i+1. Let N be the minimum value of the doping concentration between the two vertices 211-i and 211-i+1. min The flat portion 220 is a region where the doping concentration is N min or more and β×N min or less between the two vertices 211-i and 211-i+1. β may be 3, may be 2, may be 1.5, or may be 1.3. The lower end position x E may be arranged in the flat portion 220. Thereby, the lower end position x E can be arranged in a region where the doping concentration is low, and the surge voltage can be suppressed. 【0103】 To arrange the lower end position x E at the position described in FIG. 5, the doping concentration distribution of the buffer region 20 is determined such that the charge carrier coefficient α represented by Equation (1) is 2000 or more and 50000 or less for any one integer i (i is an integer of 1 or more and M-1 or less). As an example, i = 2, but the integer i is not limited to this. 【Equation】 However, v sat is the saturation velocity of charge carriers (cm / s), J rate is the rated current density of the semiconductor device 100 (A / cm 2 ), V B is the avalanche breakdown voltage of the semiconductor substrate 10 (V), x i is the depth position (cm) from the upper surface 21 of the i-th doping concentration peak 210-i among the plurality of doping concentration peaks 210 in the buffer region 20, counted from the lower surface 23, x i+1 is the depth position (cm) from the upper surface 21 of the (i + 1)-th doping concentration peak 210-i+1 among the plurality of doping concentration peaks 210 in the buffer region 20, counted from the lower surface 23, x jIt is positioned on the upper surface 21 side of the buffer region 20, and the depth position (cm) from the upper surface 21 of the PN junction closest to the buffer region 20 in the depth direction, N DR This is the doping concentration ( / cm³) in the drift region 18. 3 ), ε0 is the permittivity of vacuum, which is 8.85418 × 10⁻⁶. -14 (F / cm) ε r This is the relative permittivity of the semiconductor substrate 10, which is 11.9 for silicon substrates and 6.5-10.0 for SiC substrates. q is the elementary charge, and is 1.60218 × 10⁻¹⁸ -19 (C) M is an integer between 2 and 100. Saturation velocity v sat This is the saturation velocity of holes, which become minority carriers, when the drift region 18 is of the n type as in this example. The above parameters may be based on specifications set by the designer or manufacturer of the semiconductor device 100, or they may be based on measured values. Doping concentration N DR The average value of the bulk doping concentration of the semiconductor substrate 10 may be used. Alternatively, the doping concentration N may be used. DR The doping concentration at the center in the depth direction of the drift region 18 may be used. Next, the derivation of the charge carrier coefficient α will be explained. 【0104】 Figure 6 shows an example of a circuit 400 in which the semiconductor device 100 is used. Circuit 400 is a three-phase inverter circuit, but is not limited to this. Circuit 400 includes an AC power supply 420, a rectifier circuit 410, and a capacitor C. C , and has multiple semiconductor devices 100. Rectifier circuit 410 and capacitor C C This converts the AC voltage from AC power supply 420 to DC voltage V CC The device is converted to a three-phase inverter, where each phase circuit has an upper arm and a lower arm. The semiconductor device 100-1 of the upper arm and the semiconductor device 100-2 of the lower arm are controlled to be switched on and off complementaryly. 【0105】 Figure 7 schematically shows the circuit to which one arm of semiconductor device 100 in Figure 6 is connected. Ls is the stray inductance (H), Rg is the gate resistance (Ω), Vg is the gate applied voltage (V), Vcc is the power supply voltage (V), Cc is the capacitor capacitance (F), and Lm is the load. 【0106】 Figure 8 shows the collector-emitter current I when the semiconductor device 100 shown in Figure 6 is turned off. ce , collector-emitter voltage V ce This figure shows an overview of the time waveform of voltage V. ce At time t2, the peak voltage V p This indicates that power (W) is equal to current I ce and voltage V ce This is the waveform of the product of the two. The value obtained by integrating the power (W) with respect to time (the area of ​​the shaded area in the figure) corresponds to the energy loss (J) of the semiconductor device 100. The horizontal axis represents time t0, where the voltage V ce is the on-voltage (V ce(sat) This is the time when the voltage (V) starts to increase. The power (W) also starts to increase at time t0. Time t1 is when the voltage V is increasing. ce Power supply voltage V cc This is the time that coincides with [the specified time]. Time t2 is the time when the power (W) is at its maximum value. Time t3 is the time when the voltage V ce The maximum value is V p This is the time when the current I ce Alternatively, it is the time when it can be determined that the power (W) is 0. Current I ce Alternatively, a power (W) of 0 refers to, for example, the time when each value is less than 1% of its maximum value. 【0107】 Figure 9 shows the depth position x j From the vicinity of depth position x E This figure shows an example of the distribution of electric field strength E up to a certain depth. In this example, at the time of turn-off, the space charge region is at depth position x E This shows the state reached. Figure 9 also shows the doping concentration distributions in the buffer region 20, the drift region 18, and the accumulation region 16. 【0108】 When semiconductor device 100 is turned off, the collector-emitter voltage V ce Corresponding to this, the position x of the pn junction on the upper surface 21 side of the semiconductor substrate 10 j A space charge region extends from the bottom surface 23 towards the bottom surface 23. This space charge region is also called the depletion layer. During switching, the space charge region contains 1 × 10⁻¹⁰ 13 ~1 × 10 14 / cm 3 A certain degree of holes may exist. 【0109】 Collector-emitter voltage V ce and collector-emitter current I ce Let W be the width in the depth direction of the space charge region at time t2 when the product (power) of the two factors is maximum. Note that the collector-emitter voltage V ce The width in the depth direction of the space charge region at time t3, when it is at its maximum, may be denoted as W. 【0110】 The depth position x of the end (end of the space charge region) on the lower surface 23 side of the space charge region, where the width in the depth direction is W. E Position it between two adjacent doping concentration peaks 210 in the depth direction. For example, at depth position x E It is placed between depth positions x2 and x3. The width W of the space charge region is obtained by solving the generally known Poisson equation divE=ρ and E=-gradφ (where φ is the potential inside the semiconductor device 100 at turn-off). 【0111】 Here, the collector-emitter voltage V ce The avalanche breakdown voltage V of the transistor section 70 B Since it does not exceed the voltage V ce Voltage V B Replace with . Furthermore, since the current density of the interruption current of the transistor section 70 in an inverter, etc. is generally set not to exceed the rated current density, the current density is set to the rated current density. Then, the applied voltage and voltage V B Absorbing the difference, and the lower end position x of the space charge region EHowever, we introduce a dimensionless coefficient called the "charge carrier coefficient α" to indicate whether it is located between two adjacent doping concentration peaks 210. The charge carrier coefficient α is defined by equation (2) below as a coefficient that corrects the concentration p of minority carriers (often holes) in the space charge region at the time of turn-off. 【number】 J in equation (2) rate / qv sat The term represents the hole concentration p within the space charge region. Within the space charge region, the electric field strength is, for example, 1 × 10⁻⁶. 5 Because the electric field is high, around (V / cm), the hole concentration p saturates within the space charge region, and furthermore, the concentration distribution becomes substantially uniform (a constant value). In other words, equation (2) is that when the charge carrier coefficient α is within a certain numerical range, the collector-emitter voltage V ce Avalanche pressure resistant V B This means that when a semiconductor device 100 is turned off at a voltage that does not exceed a certain level, and a current with a current density similar to the rated current density is flowing through it, the width of the space charge region is W. 【0112】 As described above, among the multiple doping concentration peaks 210 in the buffer region 20, the depth position from the upper surface 21 of the i-th doping concentration peak 210-i from the lower surface 23 is x i (cm) The depth position from the top surface 21 of the (i+1)th doping concentration peak 210-i+1 from the bottom surface 23 is x i+1 Let (cm) be the depth position x of the PN junction where the space charge region is formed on the upper surface 21 side of the buffer region 20. j Since it is formed with a width W from the lower surface 23, the depth position x of the lower end of the space charge region E This is given by equation (3). Here, the depth position x of the PN junction is j The width of the space charge region formed from the upper surface 21 is determined by the depth position x of the PN junction. j It is assumed that this is sufficiently smaller than the width of the space charge region formed from the lower surface 23 toward the lower surface. x E =xj +W ···(3) On the other hand, depth position x E x i and x i+1 If it is located between these two points, then equation (4) is obtained. x i+1 ≤x E ≤x i ...(4) By using equation (3) to transform equation (4), we obtain equation (5). x i+1 -x j ≤W ≤x i -x j ...(5) Substituting equation (2) into equation (5) and solving for α, we obtain equation (1). 【number】 In other words, the charge carrier coefficient α satisfies equation (1), and the lower end position x of the space charge region of width W is determined. E This can be placed between adjacent doping concentration peaks. 【0113】 Figure 10 shows the doping concentration distribution of the buffer region 20 according to one embodiment. The buffer region 20 in this example has four doping concentration peaks 210. On the horizontal axis of Figure 10, the bottom surface 23 is set as depth position 0, and the horizontal axis shows the depth from the bottom surface 23. In Figure 10, the collector region 22 is omitted. In Figure 10, the dashed waveform shows the net doping concentration, and the solid waveform shows the doping concentration distribution 300 obtained by subtracting the bulk doping concentration from the net doping concentration. The doping concentration distribution 300 may be the concentration distribution of the hydrogen donor. 【0114】 The parameters for the first embodiment (rated voltage 600V) shown in Figure 10 are as follows. v sat :9.00×10 6 (cm / s) Rated current density J rate :300(A / cm 2 ) ε0: 8.85 × 10-14 (F / cm) ε r :11.9 Avalanche voltage V of semiconductor device 100 B :620(V) Thickness of semiconductor substrate 10: 60 (μm) PN junction depth position x j :2(μm), Distance from the bottom surface 23 at depth position x2: 7.1 (μm) Distance from bottom surface 23 at depth position x3: 14.1 (μm) distance x2-x j : 50.9 (μm) distance x3-x j :43.9(μm) Bulk doping concentration N D0 :1.1×10 14 ( / cm 3 ), q: 1.60 × 10 -19 (C) In this example, the lower end position x of the space charge region is between doping concentration peak 210-2 and doping concentration peak 210-3. E When arranged in this manner, the charge carrier coefficient α will be between 9883 and 15090 according to equation (1). 【0115】 The parameters for a second embodiment (rated voltage 1200V), which differs from the example shown in Figure 10, are as follows. v sat :9.00×10 6 (cm / s) Rated current density J rate :200(A / cm 2 ) ε0: 8.85 × 10 -14 (F / cm) ε r :11.9 Avalanche voltage V of semiconductor device 100 B :1400(V) Thickness of semiconductor substrate 10: 110 (μm) PN junction depth position x j :2(μm), Distance from the bottom surface 23 at depth position x2: 7.1 (μm) Distance from bottom surface 23 at depth position x3: 14.1 (μm) distance x2-x j :100.9(μm) distance x3-x j :93.9(μm) Bulk doping concentration N D0 :7×10 13 ( / cm 3 ), q: 1.60 × 10 -19 (C) In this example, the lower end position x of the space charge region is between doping concentration peak 210-2 and doping concentration peak 210-3. E When arranged in this manner, the charge carrier coefficient α will be between 7988 and 10003 according to equation (1). 【0116】 Figure 11 shows the charge carrier coefficient α and the peak voltage ratio (V) in the first embodiment (rated voltage 600V). p / V cc This diagram shows the relationship between the peak voltage and the power supply voltage V. cc The collector-emitter voltage V ce Maximum peak voltage V p The ratio (V p / V cc ) In semiconductor devices with other rated voltages, the relationship between the charge carrier coefficient α and the peak voltage ratio was similar to that in the example shown in Figure 11. 【0117】 Within the range of 2000 ≤ α ≤ 50000, the peak voltage ratio is small, indicating that surge voltage is suppressed. Furthermore, the peak voltage ratio is substantially uniform with respect to the value of α on the horizontal axis. The charge carrier coefficient α may be between 2000 and 50000. In other words, each parameter may be set such that the term below, which indicates the lower limit of α in equation (1), is 2000 or greater. 【number】 Furthermore, each parameter may be set such that the following term, which indicates the upper limit of α in equation (1), is 50,000 or less. 【number】 The charge carrier coefficient α may be 3000 or more, or 5000 or more. The charge carrier coefficient α may be 30000 or less, or 20000 or less. 【0118】 Figure 12 shows the lower end position x of the space charge region. E This figure shows the doping concentration peaks 210-i and 210-i+1, positioned on either side of the doping concentration peak. In this example, i=2. 【0119】 In this specification, when the term "interpeak distance" is used, as described above, the distance between the two peaks 211 may be used. Let x2' be the depth position at the upper tail 212-i of the doping concentration peak 210-i on the lower surface 23 side where the doping concentration is 80% of the peak concentration P2. Let x3' be the depth position at the lower tail 213-i+1 of the doping concentration peak 210-i+1 on the upper surface 21 side where the doping concentration is 80% of the peak concentration P3. The distance x2'-x3' may be used as the interpeak distance L. 【0120】 Peak concentration P 2、 P3 may be determined from the net doping concentration, or from the donor concentration obtained by subtracting the bulk doping concentration from the net doping concentration. Furthermore, the positions where the peak concentrations P2 and P3 reach 80% may be determined from the net doping concentration distribution, or from the donor concentration distribution obtained by subtracting the bulk doping concentration distribution from the net doping concentration distribution. Lower end position x of the space charge region. E It may be placed in the region from depth position x2' to depth position x3'. 【0121】 The minimum doping concentration N between doping concentration peak 210-i and doping concentration peak 210-i+1. min This is the doping concentration N in the drift region 18. DR It may be 10 times or less. This allows the lower end position x of the space charge region to be EBy lowering the doping concentration in the vicinity, the surge voltage can be suppressed. Minimum value N min This is the doping concentration N in the drift region. DR It may be five times or less, and may also be three times or less. 【0122】 Lower end position x of the space charge region E This may be calculated by simulation using the structure of the semiconductor device 100 and the doping concentration in each region. In this case, the power supply voltage V is applied to the semiconductor device 100. cc Apply a current and create a collector-emitter current I ce When semiconductor device 100 is turned off while a current is flowing, the position of the lower end of the space charge region at a predetermined time is x E This is acceptable. Power supply voltage V cc The collector-emitter current I ce This current may be 0.5 to 3 times the rated current, for example, a current equivalent to twice the current density. The predetermined time is the collector-emitter voltage V ce Power supply voltage V cc From time t1, which matches the maximum value V p This refers to the point in time up to time t3, for example, time t2. The simulation may be performed using a known device simulator or a simulator that combines a device simulator and a circuit simulator. The device simulator uses Poisson's equation for the electric field E and space charge density ρ (divE=ρ) and the equation for current continuity (∂n / ∂t=(1 / q)divJ n +G n -U n ∂p / ∂t=-(1 / q)divJ p +G p -U p n is electron density, p is hole density, J n,p G is electron current density or hole current density. n,p U is the rate of electron or hole generation. n,pThe simulator may solve for the electron or hole recombination rate based on a predetermined device structure, boundary conditions, initial conditions, etc. The circuit simulator may use the solution from the device simulator to solve steady-state and transient solutions under predetermined circuit patterns, circuit constants, etc., in conjunction with the device simulator. 【0123】 Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention. 【0124】 It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of symbols] 【0125】 10...Semiconductor substrate, 11...Well region, 12...Emitter region, 14...Base region, 15...Contact region, 16...Storage region, 18...Drift region, 20...Buffer region, 21...Top surface, 22...Collector region, 23...Bottom surface, 24...Collector electrode, 29...Straight section, 30...Dummy trench section, 31...Tip section, 32...Dummy insulating film, 34...Dummy conductive section, 38...Interlayer insulating film, 39...Straight section, 40...Gate trench section, 41...Tip section, 42...Gate insulating film, 44...Gate conductive section, 52...Emit Electrode, 54...Contact hole, 60, 61...Mesa region, 70...Transistor region, 80...Diode region, 81...Extended region, 82...Cathode region, 90...Edge termination structure, 100...Semiconductor device, 130...Outer periphery gate wiring, 131...Active side gate wiring, 160...Active region, 162...Edge, 164...Gate pad, 210...Doping concentration peak, 211...Vertex, 212...Upper tail, 213...Lower tail, 220...Flat region, 300...Doping concentration distribution, 400...Circuit, 410...Rectifier circuit, 420...AC power supply

Claims

[Claim 1] A semiconductor substrate having an upper surface and a lower surface, and provided with a first conductivity type drift region, A buffer region is provided between the drift region and the lower surface, and the doping concentration is higher than that of the drift region. Equipped with, The buffer region has M doping concentration peaks located at different positions in the depth direction of the semiconductor substrate. The charge carrier coefficient α shown in equation (1) is between 2000 and 50000 for any one integer i (where i is an integer between 1 and M-1). [Math 1] however, v sat This is the saturation velocity of charge carriers (cm / s). J rate The rated current density (A / cm²) of the semiconductor device is the rated current density (A / cm²). ２ ), V B The avalanche breakdown voltage (V) of the semiconductor substrate is x i The depth position (cm) from the top surface of the i-th doping concentration peak in the buffer region, counted from the bottom surface, is x i+1 The depth position (cm) from the top surface of the (i+1)th doping concentration peak in the buffer region, counted from the bottom surface, is x j The PN junction is positioned on the upper side of the buffer region and is located at a depth position (cm) from the upper surface of the PN junction closest to the buffer region in the depth direction. N ＤＲ is the doping concentration of the drift region ( / cm ３ ) ε 0 is the permittivity of vacuum, and is 8.85418 × 10⁻⁶. -14 (F / cm) ε r The relative permittivity of the semiconductor substrate, q is the elementary charge, and is 1.60218 × 10⁻¹⁸ -19 (C) M is an integer between 2 and 100 (inclusive). A semiconductor device. [Claim 2] In the integer i, the charge carrier coefficient α is 5000 or more. The semiconductor device according to claim 1. [Claim 3] In the integer i, the charge carrier coefficient α is 20,000 or less. The semiconductor device according to claim 1 or 2. [Claim 4] The buffer region has three or more doping concentration peaks, The distance between the i-th doping concentration peak and the (i+1)th doping concentration peak, counting from the bottom surface, is greater than the distance between the (i+1)th doping concentration peak and the (i+2)th doping concentration peak. The semiconductor device according to any one of claims 1 to 3. [Claim 5] The distance between the i-th doping concentration peak and the (i+1)th doping concentration peak, counting from the lower surface, is at least twice the distance between the (i+1)th doping concentration peak and the (i+2)th doping concentration peak. The semiconductor device according to claim 4. [Claim 6] The distance between the i-th doping concentration peak and the (i+1)th doping concentration peak, counting from the bottom surface, is greater than the distance between any of the other doping concentration peaks. The semiconductor device according to any one of claims 1 to 5. [Claim 7] The distance between the i-th doping concentration peak and the (i+1)th doping concentration peak, counting from the lower surface, is 8 μm or more. The semiconductor device according to any one of claims 1 to 6. [Claim 8] The minimum doping concentration between the i-th doping concentration peak and the (i+1)-th doping concentration peak, counting from the lower surface, is 10 times or less the doping concentration in the drift region. The semiconductor device according to any one of claims 1 to 7. [Claim 9] The buffer region has three or more doping concentration peaks, In the above equation (1), i = 2. The semiconductor device according to any one of claims 1 to 8. [Claim 10] Each of the aforementioned doping concentration peaks has a peak where the doping concentration reaches its maximum value. When the semiconductor device is turned off with a power supply voltage of 0.7 times its rated voltage applied and a collector-emitter current of twice its rated current flowing, the position of the lower edge of the space charge region at the point when the collector-emitter voltage matches the power supply voltage is located between the peak of the i-th doping concentration peak and the (i+1)-th doping concentration peak, counting from the lower surface. A semiconductor device according to any one of claims 1 to 9. [Claim 11] Each of the doping concentration peaks has a lower tail where the doping concentration decreases monotonically from the peak toward the lower surface, and an upper tail where the doping concentration decreases monotonically from the peak toward the upper surface. The position of the lower end of the space charge region is located in a region that does not overlap with the upper tail of the i-th doping concentration peak. The semiconductor device according to claim 10. [Claim 12] The doping concentration shows a minimum value between the i-th doping concentration peak and the (i+1)-th doping concentration peak. The buffer region has a flat portion between the i-th doping concentration peak and the (i+1)-th doping concentration peak where the doping concentration is 2 times or less the minimum value. The position of the lower end of the space charge region is located in the flat portion. The semiconductor device according to claim 10.

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