Semiconductor equipment

Abstract

To ease an electric field intensity in a lower end of a trench part while suppressing the snapback of a diode part.SOLUTION: A semiconductor device comprises: a plurality of trench parts provided from an upper surface of a semiconductor substrate to a lower position than a base region and arranged side by side in a first direction on the upper surface of the semiconductor substrate; a first lower-end region of a second conductivity type arranged in a first depth position and provided in contact with lower ends of two or more trench parts; and a second lower-end region arranged in the first depth position and arranged in a position not overlapping the first lower-end region. The second lower-end region includes at least one of a region of a first conductivity type and a region of the second conductivity type having a lower doping concentration than the first lower-end region.SELECTED DRAWING: Figure 3

Description

[Technical Field] 【0001】 This invention relates to a semiconductor device. [Background technology] 【0002】 Conventionally, semiconductor devices having a trench gate structure are known (see, for example, Patent Documents 1-3). Patent Document 1: Japanese Unexamined Patent Publication No. 2011-181886 Patent Document 2: Japanese Unexamined Patent Publication No. 2014-75582 Patent Document 3: Japanese Unexamined Patent Publication No. 2019-91892 [Overview of the Initiative] [Problems that the invention aims to solve] 【0003】 This design suppresses snapback in the diode section while mitigating the electric field strength at the lower end of the trench section. [Means for solving the problem] 【0004】 To solve the above problems, a first embodiment of the present invention provides a semiconductor device. The semiconductor device may include a semiconductor substrate. The semiconductor substrate has an upper surface and a lower surface, and may include a drift region of a first conductivity type between the upper surface and the lower surface. The semiconductor substrate may be provided with a diode portion. In any of the above semiconductor devices, the diode portion may include a cathode region of a first conductivity type having a higher doping concentration than the drift region, provided between the lower surface of the semiconductor substrate and the drift region. In any of the above semiconductor devices, the diode portion may include a base region of a second conductivity type provided between the upper surface of the semiconductor substrate and the drift region. In any of the above semiconductor devices, the diode portion may include a plurality of trench portions provided from the upper surface of the semiconductor substrate down to below the base region and arranged in a first direction on the upper surface of the semiconductor substrate. In any of the above semiconductor devices, the diode portion may include a first lower end region of a second conductivity type, located at a first depth position and in contact with the lower ends of two or more trench portions. In any of the above semiconductor devices, the diode portion may include a second lower end region, located at the first depth position and in a position that does not overlap with the first lower end region. In any of the above semiconductor devices, the second lower end region may include at least one of a region of a first conductivity type and a region of a second conductivity type having a lower doping concentration than the first lower end region. 【0005】 In any of the above semiconductor devices, the effective dose obtained by integrating the doping concentration in the first lower end region in the depth direction is 3 × 10 11 / cm 2 The above may be the case. In any of the above semiconductor devices, the second lower end region may be a region of the first conductivity type. In any of the above semiconductor devices, the effective dose obtained by integrating the doping concentration in the depth direction is 3 × 10⁻⁶ in the second lower end region. 11 / cm 2 It may be a smaller region of the second conductivity type. 【0006】 In any of the semiconductor devices described above, the diode portion may include an intermediate region of a first conductivity type provided between the first depth position and the base region. 【0007】 In any of the semiconductor devices described above, the doping concentration of the intermediate region may be higher than the doping concentration of the drift region. 【0008】 In any of the semiconductor devices described above, the first lower end region and the second lower end region may be arranged side by side in the first direction. 【0009】 In any of the semiconductor devices described above, the diode portion may include a plurality of mesa portions each sandwiched between two of the trench portions inside the semiconductor substrate. In any of the semiconductor devices described above, the plurality of mesa portions may include one or more first mesa portions where the first lower end region is disposed in contact with the lower ends of two adjacent trench portions. In any of the semiconductor devices described above, the plurality of mesa portions may include one or more second mesa portions where the second lower end region is disposed in contact with the lower ends of two adjacent trench portions. In any of the semiconductor devices described above, the first mesa portion and the second mesa portion may be arranged side by side in the first direction. 【0010】 In any of the semiconductor devices described above, at least one of the second mesa portions may be disposed sandwiched between two of the first mesa portions in the first direction. 【0011】 Any of the semiconductor devices may include an upper surface electrode provided above the upper surface of the semiconductor substrate. In any of the semiconductor devices described above, at least one of the second mesa portions may be connected to the upper surface electrode. 【0012】 In any of the semiconductor devices described above, at least one of the first mesa portions may be insulated from the upper surface electrode. 【0013】 In any of the semiconductor devices described above, at least one of the first mesa portions may be connected to the upper electrode. 【0014】 In any of the above semiconductor devices, the plurality of mesa portions may include a third mesa portion in which the first lower end region is located in contact with the lower end of one of two adjacent trench portions, and the second lower end region is located in contact with the lower end of the other of two adjacent trench portions. In any of the above semiconductor devices, the first mesa portion, the second mesa portion, and the third mesa portion may be arranged in a line in the first direction. 【0015】 In any of the semiconductor devices described above, the third mesa portion may be located between the first mesa portion and the second mesa portion in the first direction. 【0016】 In any of the above semiconductor devices, the semiconductor substrate may be provided with a transistor portion arranged alongside the diode portion in the first direction, and having a collector region of a second conductivity type on the lower surface of the semiconductor substrate. In any of the above semiconductor devices, the transistor portion may include a plurality of mesa portions. In any of the above semiconductor devices, the first lower end region may be provided in the mesa portion of the transistor portion that is closest to the diode portion. 【0017】 Any of the above semiconductor devices may include a boundary mesa portion provided on the semiconductor substrate and positioned above the boundary between the cathode region and the collector region in the first direction. Any of the above semiconductor devices may include an upper electrode positioned above the upper surface of the semiconductor substrate. In any of the above semiconductor devices, the boundary mesa portion may be the first mesa portion connected to the upper electrode. In any of the above semiconductor devices, the boundary mesa portion may be the first mesa portion insulated from the upper electrode. 【0018】 In any of the above semiconductor devices, the doping concentration of the first lower end region of the transistor portion and the doping concentration of the first lower end region of the diode portion may be different. 【0019】 In any of the above semiconductor devices, each of the trenches may have an elongation in a second direction different from the first direction on the upper surface of the semiconductor substrate. In any of the above semiconductor devices, the first lower end region and the second lower end region may be arranged side by side in the second direction. 【0020】 In any of the above semiconductor devices, at least one of the second lower end regions may be positioned between the first lower end regions in the second direction. 【0021】 Any of the above semiconductor devices may include an upper electrode positioned above the upper surface of the semiconductor substrate. Any of the above semiconductor devices may include an interlayer insulating film positioned between the upper electrode and the semiconductor substrate, with a contact hole connecting the upper electrode and the semiconductor substrate. In any of the above semiconductor devices, at least one of the second lower end regions may have a portion that overlaps with the contact hole in a top view. 【0022】 In any of the above semiconductor devices, the diode portion may be provided between the base region and the upper surface of the semiconductor substrate and may include a second conductivity type contact region having a higher doping concentration than the base region. In any of the above semiconductor devices, at least one of the second lower end regions may have a portion that overlaps with the contact region in a top view. 【0023】 In any of the above semiconductor devices, the first lower end region and the second lower end region may be arranged side by side in both the first and second directions. 【0024】 The above summary of the invention does not enumerate all the necessary features of the present invention. Furthermore, subcombinations of these features may also constitute an invention. [Brief explanation of the drawing] 【0025】 [Figure 1] This is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention. [Figure 2] This is a magnified view of region D in Figure 1. [Figure 3] Figure 2 shows an example of an ee cross-section. [Figure 4] This figure shows another example of an ee section. [Figure 5] This figure shows another example of an ee section. [Figure 6] This figure shows an example of the arrangement of the first lower end region 201 and the second lower end region 202 in the diode section 80 in the X-axis direction. [Figure 7] This figure shows an example of the arrangement of the first lower end region 201 and the second lower end region 202 in the mesa portion 61. [Figure 8] Figure 7 shows an example of an ff cross-section. [Figure 9] Figure 7 shows an example of a cross-section of the gg section. [Figure 10] This figure shows another example of the arrangement of contact holes 54 in the mesa portion 61. [Figure 11] Figure 10 shows an example of an hh cross-section. [Figure 12] Figure 10 shows an example of a cross-section of the kk section. [Figure 13] This figure shows an example of the equivalent circuit of the diode section 80. [Figure 14] This figure shows an example of the forward conduction characteristics of the diode section 80. [Figure 15] This figure shows the relationship between the effective dose amount in the first lower region 201 and the trigger voltage VBO. [Figure 16] This figure shows an example of the forward conduction characteristics of the diode section 80. [Figure 17] This figure illustrates the effective dose in the first lower region 201. [Figure 18]This figure shows another example of the ee section in Figure 2. [Modes for carrying out the invention] 【0026】 The present invention will be described below through embodiments of the invention, but these embodiments are not intended to limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention. 【0027】 In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "top," and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the top surface, and the other surface as the bottom surface. The directions of "top" and "bottom" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted. 【0028】 In this specification, technical matters may be described using the Cartesian coordinate axes, the X, Y, and Z axes. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z and -Z axes. 【0029】 In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction. 【0030】 The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate is sometimes referred to as the top surface. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate is sometimes referred to as the bottom surface. 【0031】 As used herein, terms such as "identical" or "equal" may include cases having errors due to manufacturing variations or the like. Such errors may be, for example, within 10%. 【0032】 In this specification, the conductivity type of the doped region doped with impurities is described as P-type or N-type. In this specification, impurities may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as dopants. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor having an N-type conductivity type or a P-type conductivity type. 【0033】 In this specification, the doping concentration means the concentration of donors or acceptors in the thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charges. As an example, if the donor concentration is N D , the valence electron number of its unit ion is n D , the acceptor concentration is N A , the valence electron number of its unit ion is n A , then the net doping concentration at any position is n D ×N D -n A ×N A . In this specification, the net doping concentration may sometimes be simply referred to as the doping concentration. 【0034】 Donors have the function of supplying electrons to a semiconductor. Acceptors have the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to the impurities themselves. For example, VOH defects formed by the combination of vacancies (V), oxygen (O), and hydrogen (H) present in a semiconductor function as donors that supply electrons. In this specification, VOH defects may sometimes be referred to as hydrogen donors. 【0035】 In this specification, the semiconductor substrate has N-type bulk donors distributed throughout. Bulk donors are donors from dopants that are substantially uniformly contained within the ingot during the manufacturing of the semiconductor substrate ingot. In this example, the bulk donor is an element other than hydrogen. The bulk donor dopants are, for example, phosphorus, antimony, arsenic, selenium, or sulfur. In this example, the bulk donor is phosphorus. Bulk donors are also contained in the P-type region. The semiconductor substrate may be a wafer cut from a semiconductor ingot, or it may be a chip made by cutting a wafer into individual pieces. The semiconductor ingot is manufactured by one of the following methods: Czochralski method (CZ method), magnetic field applied Czochralski method (MCZ method), or float zone method (FZ method). hand Good. In this example, the ingot was manufactured using the MCZ method. The oxygen concentration in the substrate manufactured using the MCZ method is 1 × 10⁻¹⁶. 17 ~7×10 17 / cm 3 The oxygen concentration in a substrate manufactured by the FZ method is 1 × 10⁻⁶. 15 ~5×10 16 / cm 3 The oxygen concentration tends to generate hydrogen donors more easily. The bulk donor concentration may be the chemical concentration of bulk donors distributed throughout the semiconductor substrate, and may be a value between 90% and 100% of that chemical concentration. In this invention, each concentration may be a value at room temperature. As an example, the value at room temperature may be the value at 300K (Kelvin) (approximately 26.9°C). 【0036】 In this specification, when P+ type or N+ type is mentioned, it means a higher doping concentration than P type or N type, and when P- type or N- type is mentioned, it means a lower doping concentration than P type or N type. Furthermore, when P++ type or N++ type is mentioned in this specification, it means a higher doping concentration than P+ type or N+ type. Unless otherwise specified, the units used in this specification are SI units. Although units of length may be expressed in cm, calculations may be performed after converting to meters (m). 【0037】 In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electrical activation state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by voltage-capacitance (CV) spectroscopy. Alternatively, the carrier concentration measured by broadened resistance (SR) spectroscopy may be used as the net doping concentration. The carrier concentration measured by CV or SR spectroscopy may be the value at thermal equilibrium. Furthermore, in the N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in that region may be used as the acceptor concentration. In this specification, the doping concentration in the N-type region may be referred to as the donor concentration, and the doping concentration in the P-type region may be referred to as the acceptor concentration. 【0038】 If the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be used as the concentration of the donor, acceptor, or net doping in that region. If the concentrations of the donor, acceptor, or net doping are nearly uniform, the average value of the concentrations of the donor, acceptor, or net doping in that region may be used as the concentration of the donor, acceptor, or net doping. In this specification, concentrations per unit volume are expressed as atoms / cm³. 3 , or / cm 3 This unit is used for donor or acceptor concentrations in semiconductor substrates, or for chemical concentrations. The atom notation may be omitted. 【0039】 The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. When measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value for the crystalline state in the range where current flows. The decrease in carrier mobility occurs because carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc. 【0040】 The donor or acceptor concentrations calculated from carrier concentrations measured by the CV method or SR method may be lower than the chemical concentrations of the elements that act as donors or acceptors. For example, in silicon semiconductors, the donor concentrations of phosphorus or arsenic, or the acceptor concentration of boron, are approximately 99% of their respective chemical concentrations. On the other hand, the donor concentration of hydrogen, which also acts as a donor in silicon semiconductors, is approximately 0.1% to 10% of the hydrogen chemical concentration. 【0041】 Figure 1 is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention. In Figure 1, the positions of each component projected onto the upper surface of the semiconductor substrate 10 are shown. In Figure 1, only some components of the semiconductor device 100 are shown, and some components are omitted. 【0042】 The semiconductor device 100 comprises a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has edges 162 when viewed from above. In this specification, when simply referred to as "top view," it means viewing from the top side of the semiconductor substrate 10. In this example, the semiconductor substrate 10 has two pairs of edges 162 that face each other when viewed from above. In Figure 1, the X and Y axes are parallel to either edge 162. The Z axis is perpendicular to the top surface of the semiconductor substrate 10. 【0043】 The semiconductor substrate 10 is provided with an active area 160. The active area 160 is a region in which the main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is operating. An emitter electrode is provided above the active area 160, but it is omitted in Figure 1. The active area 160 is shown above the emitter electrode. and It may refer to overlapping areas. In addition, the area sandwiched between the active parts 160 in a top view may also be included in the active parts 160. 【0044】 The active section 160 is provided with a transistor section 70 including a transistor element such as an IGBT (Insulated Gate Bipolar Transistor) and a diode section 80 including a diode element such as a freewheeling diode (FWD). In the example shown in Figure 1, the transistor section 70 and the diode section 80 are alternately arranged along a predetermined first direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 in this example is a reverse-conducting IGBT (RC-IGBT). 【0045】 In Figure 1, the region where the transistor section 70 is located is denoted by the symbol "I," and the region where the diode section 80 is located is denoted by the symbol "F." In this specification, the second direction is defined as a direction different from the first direction in a top view. The second direction may be perpendicular to the first direction. As an example, the second direction is the Y-axis direction. The transistor section 70 and the diode section 80 may each have their longitudinal length in the Y-axis direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The Y-axis direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section described later. 【0046】 The diode section 80 has an N+ type cathode region in the area in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is the region that overlaps with the cathode region when viewed from above. A P+ type collector region may be provided on the lower surface of the semiconductor substrate 10 in areas other than the cathode region. In this specification, an extension region 81, which is an extension of the diode section 80 in the Y-axis direction to the gate wiring described later, may also be included in the diode section 80. A collector region is provided on the lower surface of the extension region 81. 【0047】 The transistor section 70 has a P+ type collector region in the area in contact with the lower surface of the semiconductor substrate 10. Furthermore, the transistor section 70 has a gate structure periodically arranged on the upper surface side of the semiconductor substrate 10, which includes an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film. 【0048】 The semiconductor device 100 may have one or more pads on the semiconductor substrate 10. In this example, the semiconductor device 100 has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current sensing pad. Each pad is located near the edge 162. The vicinity of the edge 162 refers to the area between the edge 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as wires. 【0049】 A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench of the active portion 160. The semiconductor device 100 is provided with gate wiring that connects the gate pad 164 to the gate trench. In Figure 1, the gate wiring is shown with diagonal hatching. 【0050】 The gate wiring in this example has an outer gate wiring 130 and an active gate wiring 131. The outer gate wiring 130 is positioned between the active portion 160 and the edge 162 of the semiconductor substrate 10 in a top view. In this example, the outer gate wiring 130 surrounds the active portion 160 in a top view. The area surrounded by the outer gate wiring 130 in a top view may be considered the active portion 160. Furthermore, a well region is formed below the gate wiring. The well region is a P-type region with a higher density than the base region, which will be described later, and is formed from the top surface of the semiconductor substrate 10 to a position deeper than the base region. The area surrounded by the well region in a top view may be considered the active portion 160. 【0051】 The outer perimeter gate wiring 130 is connected to the gate pad 164. The outer perimeter gate wiring 130 is located above the semiconductor substrate 10. The outer perimeter gate wiring 130 may be a metal wiring containing aluminum or the like. 【0052】 The active gate wiring 131 is provided in the active section 160. By providing the active gate wiring 131 in the active section 160, variations in the wiring length from the gate pad 164 can be reduced for each region of the semiconductor substrate 10. 【0053】 The outer periphery gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active portion 160. The outer periphery gate wiring 130 and the active side gate wiring 131 are positioned above the semiconductor substrate 10. The outer periphery gate wiring 130 and the active side gate wiring 131 may be wirings formed from a semiconductor such as polysilicon doped with impurities. 【0054】 The active gate wiring 131 may be connected to the outer gate wiring 130. In this example, the active gate wiring 131 extends in the X-axis direction from one outer gate wiring 130 to the other outer gate wiring 130 that sandwiches the active section 160, crossing the active section 160 approximately in the center in the Y-axis direction. When the active section 160 is divided by the active gate wiring 131, the transistor section 70 and the diode section 80 may be arranged alternately in the X-axis direction in each divided region. 【0055】 The semiconductor device 100 may include a temperature sensing unit (not shown) which is a PN junction diode made of polysilicon or the like, and a current detection unit (not shown) which simulates the operation of a transistor unit provided in the active unit 160. 【0056】 In this example, the semiconductor device 100 includes an edge termination structure 90 between the active portion 160 and the edge 162 when viewed from above. In this example, the edge termination structure 90 is positioned between the outer peripheral gate wiring 130 and the edge 162. The edge termination structure 90 mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf structure, which are provided in an annular shape surrounding the active portion 160. 【0057】 Figure 2 is an enlarged view of region D in Figure 1. Region D is the region including the transistor section 70, the diode section 80, and the active-side gate wiring 131. The semiconductor device 100 in this example includes a gate trench section 40, a dummy trench section 30, a well section 11, an emitter section 12, a base section 14, and a contact section 15 provided inside the upper surface of the semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are examples of trench sections. The semiconductor device 100 in this example also includes an emitter electrode 52 and an active-side gate wiring 131 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate wiring 131 are provided separately from each other. The emitter electrode 52 is an example of an upper surface electrode. 【0058】 An interlayer insulating film is provided between the emitter electrode 52 and the active gate wiring 131 and the upper surface of the semiconductor substrate 10, but this is omitted in Figure 2. In this example, contact holes 54 are provided in the interlayer insulating film, penetrating the film. In Figure 2, each contact hole 54 is hatched with diagonal lines. 【0059】 The emitter electrode 52 is provided above the gate trench 40, dummy trench 30, well region 11, emitter region 12, base region 14, and contact region 15. The emitter electrode 52 contacts the emitter region 12, contact region 15, and base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may also be connected to a dummy conductive portion of the dummy trench 30 at its tip in the Y-axis direction. 【0060】 The active gate wiring 131 connects to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30. 【0061】 The emitter electrode 52 is formed from a material containing metal. Figure 2 shows the area in which the emitter electrode 52 is provided. For example, at least a portion of the emitter electrode 52 is formed from aluminum or an aluminum-silicon alloy, such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal formed from titanium or a titanium compound in the layer below the region formed from aluminum or the like. Furthermore, it may have a plug formed by embedding tungsten or the like in the contact hole so as to be in contact with the barrier metal and the aluminum or the like. 【0062】 The well region 11 is provided overlapping with the active gate wiring 131. The well region 11 also extends to a predetermined width in an area that does not overlap with the active gate wiring 131. In this example, the well region 11 is provided away from the Y-axis end of the contact hole 54 towards the active gate wiring 131. The well region 11 is a second conductivity type region with a higher doping concentration than the base region 14. In this example, the base region 14 is P-type, and the well region 11 is P+-type. 【0063】 Each of the transistor section 70 and the diode section 80 has multiple trench sections arranged in a first direction (the X-axis direction in Figure 2). In this example, the transistor section 70 has one or more gate trench sections 40 and one or more dummy trench sections 30 alternately provided along the X-axis direction. In this example, the diode section 80 has multiple dummy trench sections 30 provided along the X-axis direction. In this example, the diode section 80 does not have gate trench sections 40. 【0064】 The gate trench section 40 in this example may have two straight sections 39 (the trench sections that are linear along the Y-axis) extending along the Y-axis perpendicular to the X-axis, and a tip section 41 connecting the two straight sections 39. In this specification, one straight section 39 is treated as one gate trench section 40. 【0065】 Preferably, at least a portion of the tip portion 41 is provided in a curved shape when viewed from above. By connecting the ends of the two straight portions 39 in the Y-axis direction with the tip portion 41, electric field concentration at the ends of the straight portions 39 can be mitigated. 【0066】 In the transistor section 70, the dummy trench section 30 is provided between each of the straight sections 39 of the gate trench section 40. There may be one dummy trench section 30 between each of the straight sections 39, or there may be multiple dummy trench sections 30. The dummy trench section 30 may have a straight shape extending in the Y-axis direction, and like the gate trench section 40, it may have a straight section 29 and a tip section 31. In this specification, one straight section 29 is treated as one dummy trench section 30. The semiconductor device 100 shown in Figure 2 includes both a dummy trench section 30 with a straight shape without a tip section 31 and a dummy trench section 30 with a tip section 31. 【0067】 The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The Y-axis ends of the gate trench portion 40 and the dummy trench portion 30 are located in the well region 11 when viewed from above. In other words, at the Y-axis end of each trench portion, the bottom in the depth direction of each trench portion is covered by the well region 11. This makes it possible to mitigate electric field concentration at the bottom of each trench portion. 【0068】 A mesa is provided between each trench in the X-axis direction. The mesa refers to the region sandwiched between the trenches within the semiconductor substrate 10. For example, the upper end of the mesa is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa is the same as the depth position of the lower end of the trench. In this example, the mesa is provided on the upper surface of the semiconductor substrate 10, extending in the Y-axis direction along the trench. In this example, a mesa 60 is provided in the transistor section 70, and a mesa 61 is provided in the diode section 80. A boundary mesa 64 may be provided at the boundary between the transistor section 70 and the diode section 80 in a top view. In the X-axis direction, the boundary between the cathode region 82 and the collector region 22 may be treated as the boundary between the transistor section 70 and the diode section 80. In this specification, when simply referred to as a mesa, it refers to the mesa 60, mesa 61, and boundary mesa 64, respectively. 【0069】 Each mesa portion is provided with a base region 14. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region closest to the active gate wiring 131 is defined as base region 14-e. Figure 2 shows the base region 14-e located at one end of each mesa portion in the Y-axis direction, but a base region 14-e is also located at the other end of each mesa portion. In each mesa portion, at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15 may be provided in the region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided in the depth direction between the base region 14 and the upper surface of the semiconductor substrate 10. 【0070】 The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may have a contact region 15 exposed on the upper surface of the semiconductor substrate 10. 【0071】 Each of the contact region 15 and emitter region 12 in the mesa portion 60 extends from one trench portion to the other in the X-axis direction. As an example, the contact region 15 and emitter region 12 of the mesa portion 60 are arranged alternately along the longitudinal direction (Y-axis direction) of the trench portion. 【0072】 In other examples, the contact region 15 and emitter region 12 of the mesa portion 60 may be arranged in a stripe pattern along the longitudinal direction (Y-axis direction) of the trench portion. For example, the emitter region 12 may be provided in the region adjacent to the trench portion, and the contact region 15 may be provided in the region sandwiched between the emitter regions 12. 【0073】 The mesa portion 61 of the diode portion 80 does not have an emitter region 12. A base region 14 and a contact region 15 may be provided on the upper surface of the mesa portion 61. In the region on the upper surface of the mesa portion 61 sandwiched between the base regions 14-e, a contact region 15 may be provided in contact with each base region 14-e. In the region on the upper surface of the mesa portion 61 sandwiched between the contact regions 15, a base region 14 may be provided. The base region 14 may be arranged in the entire region sandwiched between the contact regions 15. 【0074】 A contact hole 54 is provided above each mesa portion. The contact hole 54 is located in the region sandwiched between the base region 14-e. In this example, the contact hole 54 is provided above the contact region 15, the base region 14, and the emitter region 12. The contact hole 54 is also provided so as to penetrate the contact region 15 and the emitter region 12 and be in contact with the base region 14. The contact hole 54 is not provided in the region corresponding to the base region 14-e and the well region 11. The contact hole 54 may be located in the center of the mesa portion in the X-axis direction. 【0075】 In the diode section 80, an N+ type cathode region 82 is provided in the region adjacent to the lower surface of the semiconductor substrate 10. In the region on the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided, a P+ type collector region 22 may be provided. The cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. In Figure 2, the boundary between the cathode region 82 and the collector region 22 is shown by a dotted line. 【0076】 The cathode region 82 is positioned away from the well region 11 in the Y-axis direction. This prevents the P-type region (well region 11), which has a relatively high doping concentration and is formed to a deep position, from becoming an FWD structure due to the presence of the collector region 22 directly below it. Therefore, by ensuring a distance between the well region 11 and the cathode region 82, carrier injection from the well region 11 is reduced during FWD conduction, improving the dynamic withstand voltage from on to off. In this example, the Y-axis end of the cathode region 82 is positioned further from the well region 11 than the Y-axis end of the contact hole 54. In other examples, the Y-axis end of the cathode region 82 may be positioned between the well region 11 and the contact hole 54. 【0077】 Figure 3 shows an example of the ee cross-section in Figure 2. The ee cross-section is the XZ plane passing through the emitter region 12 and the cathode region 82. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross-section. 【0078】 The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film that includes at least one layer of insulating film such as silicate glass with impurities such as boron or phosphorus added, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with contact holes 54 as described in Figure 2. 【0079】 The emitter electrode 52 is located above the interlayer insulating film 38. The emitter electrode 52 is in contact with the upper surface 21 of the semiconductor substrate 10 through a contact hole 54 in the interlayer insulating film 38. The collector electrode 24 is located on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metallic material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (Z-axis direction) is referred to as the depth direction. 【0080】 The semiconductor substrate 10 has an N-type or N-type drift region 18. The drift region 18 is provided in both the transistor section 70 and the diode section 80. 【0081】 The mesa portion 60 of the transistor portion 70 has an N+ type emitter region 12 and P type The base region 14 is provided sequentially from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+ type storage region 16 may be provided in the mesa portion 60. The storage region 16 is located between the base region 14 and the drift region 18. 【0082】 The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The doping concentration of the emitter region 12 is higher than that of the drift region 18. 【0083】 The base region 14 is located below the emitter region 12. In this example, the base region 14 is located in contact with the emitter region 12. The base region 14 may be in contact with the trenches on both sides of the mesa region 60. 【0084】 The storage region 16 is located below the base region 14. The storage region 16 is an N-type region with a higher doping concentration than the drift region 18. That is, the donor concentration in the storage region 16 is higher than that in the drift region 18. By providing a high-concentration storage region 16 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect) can be enhanced and the on-voltage can be reduced. The storage region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60. 【0085】 The mesa portion 61 of the diode portion 80 is in contact with the upper surface 21 of the semiconductor substrate 10, P typeA base region 14 is provided. Below the base region 14, a drift region 18 is provided. In the mesa portion 61, an accumulation region 16 may be provided between the base region 14 and the drift region 18. 【0086】 In both the transistor section 70 and the diode section 80, an N-type buffer section 20 may be provided below the drift section 18. The doping concentration in the buffer section 20 is higher than the doping concentration in the drift section 18. The buffer section 20 may have a concentration peak with a higher doping concentration than the drift section 18. The doping concentration of the concentration peak refers to the doping concentration at the peak of the concentration peak. Furthermore, the doping concentration of the drift section 18 may be the average value of the doping concentration in a region where the doping concentration distribution is nearly flat. 【0087】 The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peaks of the buffer region 20 may be located at the same depth as, for example, the chemical concentration peaks of hydrogen (proton) or phosphorus. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82. 【0088】 In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than that of the base region 14. The collector region 22 may contain the same acceptors as the base region 14, or it may contain different acceptors. The acceptors of the collector region 22 are, for example, boron. 【0089】 In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration of the cathode region 82 is higher than that of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements that serve as donors and acceptors for each region are not limited to the examples described above. The collector region 22 and the cathode region 82 are exposed to the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metallic material such as aluminum. 【0090】 One or more gate trenches 40 and one or more dummy trenches 30 are provided on the upper surface 21 of the semiconductor substrate 10. In each figure, the gate trenches 40 may be denoted by the symbol G and the dummy trenches 30 by the symbol E. Each trench extends from the upper surface 21 of the semiconductor substrate 10, through the base region 14, and down to below the base region 14. In regions where at least one of the emitter region 12, contact region 15, and storage region 16 is provided, each trench also penetrates these doping regions. The statement that a trench penetrates a doping region is not limited to manufacturing in the order of forming the doping region before forming the trenches. Even when doping regions are formed between the trenches after the trenches have been formed, the trenches are still included in the statement that they penetrate the doping regions. 【0091】 As described above, the transistor section 70 is provided with a gate trench section 40 and a dummy trench section 30. In this example, the diode section 80 is provided with a dummy trench section 30, but not with a gate trench section 40. In other examples, a portion of the dummy trench section 30 of the diode section 80 may be replaced with a gate trench section 40. In this example, the boundary between the diode section 80 and the transistor section 70 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22. 【0092】 The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided covering the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench, on the inside of the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. 【0093】 The gate conductive portion 44 may be longer than the base region 14 in the depth direction. The gate trench portion 40 in this cross-section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface of the base region 14 that is in contact with the gate trench portion 40. 【0094】 The dummy trench portion 30 may have the same structure as the gate trench portion 40 in its cross-section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided covering the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is located inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed from the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 may be formed from a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction. 【0095】 In this example, the gate trench portion 40 and the dummy trench portion 30 are covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottom portions of the dummy trench portion 30 and the gate trench portion 40 may be curved (curved in cross-section) with a downward convex shape. 【0096】 The diode section 80 comprises one or more first lower end regions 201. In this example, the first lower end regions 201 are P-shaped regions. Each first lower end region 201 is in contact with the lower end of two or more trench sections (e.g., two or more dummy trench sections 30) arranged side by side in the X-axis direction. Each first lower end region 201 extends over the entire X-axis direction of at least one mesa section 61. At least one first lower end region 201 may be in contact with the lower end of three or more trench sections. In this case, the first lower end regions 201 extend over the entire X-axis direction of at least two mesa sections 61. 【0097】 Each first lower end region 201 is located at a first depth position Z1. The first lower end region 201 being located at the first depth position Z1 means that it has a portion located at the first depth position Z1. The first depth position Z1 may be a position in contact with the lower end of the trench. The first depth position Z1 may also be the position where the doping concentration distribution in the depth direction of the first lower end region 201 shows a maximum value. The first lower end region 201 may have a width in the depth direction (Z-axis direction). The width of the first lower end region 201 in the depth direction may be 0.5 μm or more, 1 μm or more, 1.5 μm or more, or 2 μm or more. The width of the first lower end region 201 in the depth direction may be measured at a position in contact with the lower end of the trench, or at the central position in the X-axis direction of the mesa 61. The width of the first lower end region 201 in the depth direction may be smaller than the width of the base region 14 in the depth direction. An N-type intermediate region is provided between the first lower end region 201 and the base region 14. The doping concentration of the intermediate region may be higher than the doping concentration of the drift region 18. In the example in Figure 3, the accumulation region 16 is the intermediate region. In other examples, the drift region 18 may be provided as the intermediate region. 【0098】 The doping concentration in the first lower region 201 may be lower or higher than the doping concentration in the base region 14. The doping concentration in the first lower region 201 may also be the same as the doping concentration in the base region 14. The potential of the first lower region 201 may be different from the potential of the emitter electrode 52. In other words, the first lower region 201 may be floating relative to the emitter electrode 52. The first lower region 201 does not need to be connected to either the base region 14 or the well region 11. 【0099】 The diode section 80 includes one or more second lower end regions 202. The second lower end region 202 is located at a first depth position Z1 and is positioned so as not to overlap with the first lower end region 201 in a top view. The second lower end region 202 may be positioned alongside the first lower end region 201 in the X-axis direction, alongside the first lower end region 201 in the Y-axis direction, or alongside the first lower end region 201 in other directions. The second lower end region 202 may be positioned alongside the first lower end region 201 in two directions in the XY plane. In the example in Figure 3, the first lower end region 201 and the second lower end region 202 are positioned side by side in the X-axis direction. 【0100】 The second lower end region 202 includes at least one of a region of the first conductivity type (N-type in this example) and a region of the second conductivity type (P-type in this example) with a lower doping concentration than the first lower end region 201. In the example of Figure 3, the second lower end region 202 is an N-type drift region 18 that remains at the first depth position Z1 of the diode portion 80 without the first lower end region 201 being provided. The second lower end region 202 may also be an N-type region with a higher doping concentration than the drift region 18. The second lower end region 202 may also be an accumulation region 16 provided at the first depth position Z1. The width of the second lower end region 202 in the depth direction may be the same as the width of the first lower end region 201 in the depth direction. 【0101】 Each second lower end region 202 may be in contact with the lower ends of two or more trench sections arranged side by side in the X-axis direction. These two or more trench sections may include dummy trench sections 30 and may include gate trench sections 40. The second lower end region 202 provided in the diode section 80 may be in contact with the lower ends of two or more dummy trench sections 30. At least one second lower end region 202 may be in contact with the lower end of a single trench section. Each second lower end region 202 may be provided over the entire X-axis direction of at least one mesa section 61, or it may be provided on a portion of one mesa section 61. At least one second lower end region 202 may be in contact with the lower ends of three or more trench sections. In this case, the second lower end region 202 is provided over the entire X-axis direction of at least two mesa sections 61. 【0102】 By providing the diode section 80 with a first lower end region 201, electric field concentration at the lower end of the trench section in contact with the first lower end region 201 can be mitigated. However, if the first lower end region 201 is provided, in the reverse conduction mode when the diode section 80 is ON, the PN junction between the N-type region such as the storage region 16 and the first lower end region 201 is reverse-biased. In this case, no current flows through the PN junction until at least one of the storage region 16 and the first lower end region 201 is completely depleted. Therefore, the forward conduction characteristics (forward voltage-current characteristics) of the diode section 80 are prone to snapback, where a small current flows until a predetermined trigger voltage is applied to the diode section 80, and a large current flows after the trigger voltage is applied. In contrast, by providing the diode section 80 with a second lower end region 202, current flows more easily through the second lower end region 202, thus suppressing snapback in the diode section 80. 【0103】 In a top view of the diode section 80, the area occupied by the first lower end region 201 may be larger or smaller than the area occupied by the second lower end region 202. The area occupied by the first lower end region 201 may be the same as the area occupied by the second lower end region 202. In the diode section 80, the area occupied by the second lower end region 202 may be 75% or less of the area of ​​the diode section 80, or 50% or less. In the diode section 80, the area occupied by the second lower end region 202 may be 10% or more of the area of ​​the diode section 80, or 20% or more. 【0104】 In the diode section 80, a mesa section 61 in which a first lower end region 201 is positioned in contact with the lower ends of two adjacent trench sections is defined as the first mesa section 61-1. In other words, the first mesa section 61-1 is provided with the first lower end region 201 extending over its entire length in the X-axis direction. The diode section 80 may be provided with one or more first mesa sections 61-1. 【0105】 In the diode section 80, a mesa section 61 in which a second lower end region 202 is positioned in contact with the lower ends of two adjacent trench sections is defined as a second mesa section 61-2. In other words, the second mesa section 61-2 has a second lower end region 202 that extends over its entire length in the X-axis direction. The diode section 80 may be provided with one or more second mesa sections 61-2. 【0106】 In this example, the first mesa portion 61-1 and the second mesa portion 61-2 are arranged side by side in the X-axis direction. The first mesa portion 61-1 and the second mesa portion 61-2 may be two adjacent mesa portions 61, or two separated mesa portions 61. The presence of the first mesa portion 61-1 in the diode portion 80 can mitigate electric field concentration near the lower ends of the two trench portions flanking the first mesa portion 61-1. Furthermore, the presence of the second mesa portion 61-2 in the diode portion 80 can suppress snapback in the reverse conduction mode. 【0107】 In the diode section 80, a first lower end region 201 is positioned in contact with the lower end of one of two adjacent trench sections, and a second lower end region 202 is positioned in contact with the lower end of the other of the two adjacent trench sections. This mesa section 61 is defined as the third mesa section 61-3. Both the first lower end region 201 and the second lower end region 202 are provided on the lower surface of the third mesa section 61-3. 【0108】 In this example, the first mesa section 61-1, the second mesa section 61-2, and the third mesa section 61-3 are arranged side by side in the X-axis direction. A third mesa section 61-3 may be placed between the first mesa section 61-1 and the second mesa section 61-2. 【0109】 At least one second mesa portion 61-2 is connected to the emitter electrode 52. The emitter electrode 52 may be connected to the second mesa portion 61-2 via a contact hole 54 in the interlayer insulating film 38. This allows the second mesa portion 61-2 to operate as a diode. All second mesa portions 61-2 may be connected to the emitter electrode 52. 【0110】 At least one first mesa portion 61-1 may be insulated from the emitter electrode 52. That is, the interlayer insulating film 38 covering the first mesa portion 61-1 does not have a contact hole 54. No current flows through the first mesa portion 61-1 that is not connected to the emitter electrode 52. All first mesa portions 61-1 may be insulated from the emitter electrode 52. In this case, snapback caused by the first mesa portions 61-1 does not occur. The amount of current flowing through the diode portion 80 can be adjusted by adjusting the ratio of the first mesa portions 61-1 and the second mesa portions 61-2. At least one first mesa portion 61-1 may be connected to the emitter electrode 52. Even in this case, since the second mesa portion 61-2 is provided, the occurrence of snapback can be suppressed. The first mesa portions 61-1 may also be connected to the emitter electrode 52 by remote contact. Remote contact refers to a configuration in which, for example, the first mesa portion 61-1 is connected to the emitter electrode 52 through the contact hole 54 only at the base region 14-e at the end of the diode portion 80 in Figure 2. Alternatively, the first mesa portion 61-1 may be connected to the emitter electrode 52 through the contact hole 54 at regular intervals in the longitudinal direction of the trench (Y-axis direction). This regular distance may be, for example, 10 times or more the mesa width in the X-axis direction, 20 times or more, or 30 times or more. The connection between the third mesa portion 61-3 and the emitter electrode 52 may be any of the configurations described for the connection between the first mesa portion 61-1 and the emitter electrode 52. 【0111】 A boundary mesa 64 may be provided above the boundary between the cathode region 82 and the collector region 22 in the X-axis direction. The boundary mesa 64 may have the same structure as the first mesa 61-1, the same structure as the second mesa 61-2, or the same structure as the third mesa 61-3. In the example shown in Figure 3, the boundary mesa 64 has the same structure as the first mesa 61-1. That is, the boundary mesa 64 is provided with a base region 14, a storage region 16, and a first lower end region 201. 【0112】 By providing a first lower end region 201 in the boundary mesa portion 64, the injection of holes from the boundary mesa portion 64 into the drift region 18 is suppressed. Holes can also be injected into the drift region 18 of the diode portion 80 from the base region 14 of the transistor portion 70. As a result, there are cases where too many holes are injected into the diode portion 80. By suppressing the injection of holes from the boundary mesa portion 64, the amount of holes injected into the diode portion 80 can be adjusted. 【0113】 The boundary mesa portion 64 may be connected to the emitter electrode 52. This stabilizes the potential at the boundary between the transistor portion 70 and the diode portion 80. In the diode portion 80, a third mesa portion 61-3 may be placed between the boundary mesa portion 64 and the second mesa portion 61-2. 【0114】 A first lower end region 201 may also be provided in the transistor section 70. Of the multiple mesa sections 60 of the transistor section 70, the mesa section 60 closest to the diode section 80 may be provided with a first lower end region 201. In other words, the lower surface of the mesa section 60 may be covered by a first lower end region 201 that is in contact with the lower ends of two adjacent trench sections. One first lower end region 201 may be provided in contact with the lower ends of all the trench sections of the transistor section 70. The first lower end region 201 may be provided over the entire X-axis direction of the transistor section 70. A second lower end region 202 may be provided in the transistor section 70. By providing a first lower end region 201 in the transistor section 70, electric field concentration near the lower end of the trench section of the transistor section 70 can be mitigated. 【0115】 The doping concentration of the first lower end region 201 of the transistor section 70 and the doping concentration of the first lower end region 201 of the diode section 80 may be the same or different. For example, the doping concentration of the first lower end region 201 of the diode section 80 may be higher than the doping concentration of the first lower end region 201 of the transistor section 70. This can further mitigate electric field concentration near the lower end of the trench section of the diode section 80. Increasing the doping concentration of the first lower end region 201 of the diode section 80 tends to increase the likelihood of snapback, but the diode section 80 in this example is provided with a second lower end region 202. Therefore, even if the doping concentration of the first lower end region 201 of the diode section 80 is increased, the occurrence of snapback can be sufficiently suppressed. The doping concentration of the first lower end region 201 of the diode section 80 may be twice or more the doping concentration of the first lower end region 201 of the transistor section 70, or it may be five times or more. 【0116】 Figure 4 shows another example of the ee cross-section. The semiconductor device 100 in this example differs from the example in Figure 3 in the arrangement of the contact holes 54. The other structures are the same as in any of the embodiments described in Figure 3. 【0117】 In the example shown in Figure 3, no contact hole 54 is provided for the first mesa portion 61-1. In this example, at least one first mesa portion 61-1 is connected to the emitter electrode 52 via the contact hole 54. All first mesa portions 61-1 may be connected to the emitter electrode 52. When the first mesa portions 61-1 are connected to the emitter electrode 52, the base region 14, storage region 16, first lower end region 201, and drift region 18, which are provided in the region below the first mesa portion 61-1, operate as thyristors. 【0118】 When a forward current flows through the second mesa portion 61-2 in reverse conduction mode, the potential of the drift region 18 rises, or a base current flows through the NPN diode with the first lower end region 201 as its base, causing the thyristor to turn on. This allows current to flow through the region where the first mesa portion 61-1 is provided, and allows more current to flow through the diode portion 80. 【0119】 In the example shown in Figure 3, no contact holes 54 are provided for the third mesa portion 61-3. In this example, at least one of the third mesa portions 61-3 may be connected to the emitter electrode 52 via the contact holes 54. All of the third mesa portions 61-3 may be connected to the emitter electrode 52. This allows more current to flow through the diode portion 80. 【0120】 Figure 5 shows another example of the ee cross-section. The semiconductor device 100 in this example differs from the example in Figure 3 or Figure 4 in the arrangement of the contact holes 54 relative to the boundary mesa 64. The other structures are the same as in any of the embodiments described in Figure 3 or Figure 4. 【0121】 In this example, the boundary mesa portion 64 is insulated from the emitter electrode 52. The other structures of the boundary mesa portion 64 are the same as those of the first mesa portion 61-1. This configuration suppresses hole injection from the boundary mesa portion 64 and allows adjustment of the amount of holes injected into the diode portion 80. Alternatively, the boundary mesa portion 64 may be in electrical remote contact with the emitter electrode 52 as described above. 【0122】 Figure 6 shows an example of the arrangement of the first lower end region 201 and the second lower end region 202 in the diode section 80 in the X-axis direction. Figure 6 shows the XZ cross-section of the semiconductor substrate 10. In Figure 6, the interlayer insulating film 38, emitter electrode 52, and collector electrode 24 are omitted. The configuration other than the arrangement of the first lower end region 201 and the second lower end region 202 is the same as in any of the embodiments described in Figures 3 to 5. 【0123】 In this example, at least one second lower end region 202 is positioned between two first lower end regions 201 in the X-axis direction. Also, at least one first lower end region 201 is positioned between two second lower end regions 202 in the X-axis direction. In other words, the first lower end regions 201 and the second lower end regions 202 are alternately arranged two or more times in the X-axis direction. By alternately arranging the first lower end regions 201 and the second lower end regions 202, it becomes easier to suppress the occurrence of snapback caused by the presence of the first lower end region 201. 【0124】 At least one second mesa portion 61-2 is positioned between two first mesa portions 61-1 in the X-axis direction. Also, at least one first mesa portion 61-1 is positioned between two second mesa portions 61-2 in the X-axis direction. A third mesa portion 61-3 may be positioned between the first mesa portion 61-1 and the second mesa portion 61-2. By alternately arranging the first mesa portions 61-1 and the second mesa portions 61-2, it becomes easier to suppress the occurrence of snapback in the first mesa portion 61-1. 【0125】 Figure 7 shows an example of the arrangement of the first lower end region 201 and the second lower end region 202 in the mesa section 61. In Figures 3 to 6, the first lower end region 201 and the second lower end region 202 were arranged side by side in the X-axis direction. In this example, the first lower end region 201 and the second lower end region 202 are arranged side by side in the Y-axis direction. This makes it possible to suppress the occurrence of snapback while mitigating electric field concentration near the lower end of the trench section. The structure other than the arrangement of the first lower end region 201 and the second lower end region 202 in the Y-axis direction is the same as in any of the embodiments described in Figures 1 to 6. 【0126】 In all mesa portions 61 of the diode portion 80, the first lower end region 201 and the second lower end region 202 may be arranged side by side in the Y-axis direction. In other examples, in some mesa portions 61 of the diode portion 80, the first lower end region 201 and the second lower end region 202 may be arranged side by side in the Y-axis direction. For example, in the first mesa portion 61-1 and the third mesa portion 61-3 described in Figures 3 to 6, the first lower end region 201 and the second lower end region 202 may be arranged side by side in the Y-axis direction. In other words, the first lower end region 201 described in Figures 3 to 6 may be arranged discretely in the Y-axis direction. In regions where the first lower end region 201 is not provided, the second lower end region 202 is provided. In the second mesa portion 61-2, the first lower end region 201 is not provided, but the second lower end region 202 is provided. In this case, the first lower end region 201 and the second lower end region 202 are arranged side by side in both the X-axis and Y-axis directions. This makes it easier to further suppress the occurrence of snapback. In addition, the first lower end region 201 and the second lower end region 202 may also be arranged side by side in the Y-axis direction in the boundary mesa portion 64 and the mesa portion 60 of the transistor portion 70. 【0127】 At least one second lower end region 202 may be positioned between two first lower end regions 201 in the Y-axis direction. Also, at least one first lower end region 201 may be positioned between two second lower end regions 202 in the Y-axis direction. In other words, the first lower end region 201 and the second lower end region 202 may be alternately positioned two or more times in the Y-axis direction. By alternately positioning the first lower end region 201 and the second lower end region 202, it becomes easier to suppress the occurrence of snapback caused by the provision of the first lower end region 201. As shown in Figure 7, the mesa portion 61 may be positioned between two well regions 11 in the Y-axis direction. The first lower end region 201 and the second lower end region 202 may be alternately positioned between the two well regions 11 in the Y-axis direction. 【0128】 In this example, multiple contact holes 54 may be discretely arranged in the Y-axis direction above the mesa portion 61. The distance Y1 between adjacent contact holes 54 in the Y-axis direction may be 10 μm or more, 100 μm or more, or 1000 μm or more. The distance Y1 may be half or less of the Y-axis length of the mesa portion 61, 1 / 4 or less, or 1 / 10 or less. The distance Y1 may be greater than, less than, or the same as the Y-axis length Y2 of a single contact hole 54. 【0129】 At least one second lower end region 202 may have a portion that overlaps with the contact hole 54 when viewed from above. The second lower end region 202 may be provided so as to cover the entire contact hole 54 when viewed from above. The first lower end region 201 may have a portion that does not overlap with the contact hole 54 when viewed from above. The first lower end region 201 may be provided so as not to overlap with the contact hole 54 at all when viewed from above. 【0130】 Figure 8 shows an example of the ff cross-section in Figure 7. The ff cross-section is the YZ plane that passes through the dummy trench portion 30 facing the contact hole 54 in the X-axis direction. As shown in Figure 8, the first lower end region 201 and the second lower end region 202 are alternately arranged in the Y-axis direction, in contact with the lower end of the dummy trench portion 30. 【0131】 Figure 9 shows an example of the gg cross-section in Figure 7. The gg cross-section is the YZ plane passing through the contact hole 54. As described above, at least one second lower end region 202 is positioned to overlap with the contact hole 54. This makes it easier to draw the hole that has passed through the second lower end region 202 to the emitter electrode 52, and makes it easier to pass current through the second lower end region 202. This further suppresses snapback. 【0132】 The mesa region 61 may be provided with a P+ type contact region 15 having a higher doping concentration than the base region 14. The contact region 15 and the base region 14 may be arranged alternately in the Y-axis direction. The contact region 15 is provided between the base region 14 and the upper surface 21 of the semiconductor substrate 10. The contact region 15 is connected to the emitter electrode 52 by a contact hole 54. 【0133】 At least one second lower end region 202 may have a portion that overlaps with the contact region 15 when viewed from above. All second lower end regions 202 may have a portion that overlaps with the contact region 15. By providing the second lower end region 202 below the contact region 15, it becomes easier to draw holes that have passed through the second lower end region 202 to the collector electrode 24, and it becomes easier to pass current through the second lower end region 202. This further suppresses snapback. 【0134】 Figure 10 shows another example of the arrangement of the contact hole 54 in the mesa portion 61. The structure other than the contact hole 54 is the same as in any of the embodiments described in Figures 1 to 9. In this example, the contact hole 54 is provided so as to overlap with two or more second lower end regions 202 aligned in the Y-axis direction. As shown in Figure 10, the mesa portion 61 may be provided with a single contact hole 54 that overlaps with all of the second lower end regions 202 provided in the mesa portion 61. In the mesa portion 61, the first lower end regions 201 located at both ends in the Y-axis direction may or may not overlap with the contact hole 54. The contact hole 54 does not overlap with the well region 11. 【0135】 Figure 11 shows an example of the hh cross-section in Figure 10. The hh cross-section is a YZ plane that passes through one second lower end region 202 and a dummy trench portion 30 facing each other in the X-axis direction. As shown in Figure 11, the first lower end region 201 and the second lower end region 202 are arranged alternately in the Y-axis direction, in contact with the lower end of the dummy trench portion 30. 【0136】 Figure 12 shows an example of the kk cross section in Figure 10. The kk cross section is the YZ plane passing through the first lower end region 201 and the second lower end region 202. In this example, the second lower end region 202 is positioned to overlap with the contact hole 54. This makes it easier to draw the hole that has passed through the second lower end region 202 to the collector electrode 24, and makes it easier to pass current through the second lower end region 202. Therefore, snapback can be further suppressed. In this example as well, as in the example in Figure 9, the mesa portion 61 may or may not be provided with a contact region 15 that overlaps with the second lower end region 202. 【0137】 Figure 13 shows an example of the equivalent circuit of the diode section 80. Figure 13 shows the circuits of the first mesa section 61-1, the second mesa section 61-2, and the regions below these mesa sections. The second mesa section 61-2 is represented by a diode D and a resistor R. Diode D is a PN junction diode including a base region 14 and a storage region 16. Resistor R is the on-resistance component in the second lower end region 202 and the drift region 18. In this example, the first mesa section 61-1 is connected to the emitter electrode 52 as shown in Figure 4. In this case, the first mesa section 61-1 and the region below it operate as a thyristor. In Figure 13, this thyristor is represented by transistors Tr1 and Tr2. Transistor Tr1 is a PNP transistor including a base region 14, a storage region 16, and a first lower end region 201. Transistor Tr2 is an NPN transistor including a storage region 16, a first lower end region 201, and a drift region 18. The base of transistor Tr2 corresponds to the first lower end region 201. 【0138】 In this example, when forward current flows through the second mesa section 61-2, the potential of the base of transistor Tr2 rises due to the resistor R, and base current is supplied to transistor Tr2. As a result, the thyristor in the first mesa section 61-1 turns on, and current flows through the first mesa section 61-1 as well. Therefore, the current flowing through the diode section 80 can be increased. 【0139】 Figure 14 shows an example of the forward conduction characteristics of the diode section 80. The horizontal axis of Figure 14 represents the anode-cathode voltage Vak (V) of the diode section 80, and the vertical axis represents the anode-cathode current Iak (A) of the diode section 80. In Figure 14, the characteristics of the comparative example are shown with a dashed line, and the characteristics of the embodiment are shown with a solid line. In the comparative example, the diode section 80 is a first mesa section 61-1 in which all mesa sections 61 are covered by a first lower end region 201. The embodiment is a diode section 80 having the structure shown in Figure 3. 【0140】 As shown in the comparative example in Figure 14, when all the mesa portions 61 of the diode section 80 are made into first mesa portions 61-1, the anode-cathode current Iak(A) is suppressed due to the snapback phenomenon until the anode-cathode voltage Vak reaches the trigger voltage VBO. In the comparative example, after the anode-cathode voltage Vak reaches the trigger voltage VBO, a snapback characteristic is observed in which a large anode-cathode current Iak(A) flows. In contrast, in the embodiment, by making some of the mesa portions 61 of the diode section 80 into second mesa portions 61-2, the normal diode characteristics are observed without showing the snapback characteristic seen in the comparative example. 【0141】 Figure 15 shows the relationship between the effective dose amount in the first lower end region 201 and the trigger voltage VBO. The horizontal axis of Figure 15 represents the effective dose amount ( / cm²) in the first lower end region 201. 2 ) and the vertical axis is the trigger voltage VBO(V) of the snapback phenomenon. The effective dose of the first lower end region 201 is the dose of dopant ions (e.g., acceptor ions) per unit area in the direction parallel to the upper surface 21 of the semiconductor substrate 10 ( / cm²) after the first lower end region 201 has been formed. 2 ) and the amount per unit area ( / cm²) of impurities (e.g., bulk donors) already present in the semiconductor substrate 10. 2The effective dose is obtained by multiplying the net doping concentration ( / cm³) of the dopant ion by the number of valence charges (electrons or holes) of the unit ion according to the type and polarity of the impurity, and then adding or subtracting the dose amount and the amount of impurity. For example, if the number of valence charges per unit ion of both the dopant and the existing impurity is 1 and the polarities are opposite (P-type and N-type), the effective dose is the dopant ion dose minus the amount of impurity. The effective dose in the first lower end region 201 is the net doping concentration ( / cm³) in the first lower end region 201. 3 ) may be the value obtained by integrating in the depth direction. When the first lower end region 201 is formed in the trench through ion implantation and diffusion processes, the effective dose may be affected by the shadow effect of the trench sidewalls and diffusion. amount The dose from the ion injector amount or doses in the semiconductor immediately after injection amount This may differ. Effective dose in Figure 15 amount These are the values ​​at each position of the first mesa portion 61-1 when the first lower end region 201 is formed with a substantially uniform depth distribution at each position in the X-axis direction, except for the end. 【0142】 In Figure 15, the characteristics of the comparative example are shown with a dashed line, and the characteristics of the example are shown with a solid line. The structures of the comparative example and the example are the same as those in Figure 14. In the comparative example, the effective dose is 3.0 × 10⁻⁶. 11 / cm 2 When it exceeds a certain value, the trigger voltage VBO increases in accordance with the effective dose. In contrast, in the embodiment, the trigger voltage VBO remains low regardless of the effective dose. In other words, in the embodiment, snapback does not occur regardless of the effective dose in the first lower end region 201. For this reason, the embodiment allows for greater flexibility in setting the effective dose in the first lower end region 201. 【0143】 The effective dose in the first lower region 201 is 3 × 10⁻⁶ 11 / cm 2The above may be sufficient. By increasing the effective dose of the first lower end region 201, electric field concentration near the lower end of the trench portion in contact with the first lower end region 201 can be mitigated. In this embodiment, a second lower end region 202 is provided alongside the first lower end region 201, so as shown in Figure 15, snapback can be suppressed even if the effective dose of the first lower end region 201 is increased. The effective dose of the first lower end region 201 is 5 × 10 11 / cm 2 The above is sufficient, 1 × 10 12 / cm 2 The above is sufficient, 5 × 10 12 / cm 2 That's fine too. 【0144】 The trigger voltage VBO corresponds to the voltage at which at least one of the first lower region 201 and the storage region 16 forming the PN junction becomes completely depleted. Therefore, as shown in the characteristics of the comparative example, the trigger voltage VBO changes according to the effective dose amount in the first lower region 201. If the width in the depth direction of the first lower region 201 is constant and the doping concentration in the first lower region 201 is uniform in the depth direction, similar characteristics can be obtained even if the horizontal axis of Figure 15 is the doping concentration in the first lower region 201. However, the width and depth direction concentration profile of the first lower region 201 can take various forms. By defining the amount of impurity in the first lower region 201 by the effective dose amount, the relationship between the amount of impurity and the trigger voltage VBO can be determined regardless of the width and depth direction concentration profile of the first lower region 201. 【0145】 Figure 16 shows an example of the forward conduction characteristics of the diode section 80. The axes in Figure 16 are on a linear scale, and the labels are the same as in Figure 14. In Figure 16, the characteristics of the embodiment shown in Figure 3 are shown with solid lines, and the characteristics of the embodiment shown in Figure 4 are shown with dashed lines. As explained in Figure 13, etc., in the embodiment shown in Figure 4, the first mesa section 61-1 operates as a thyristor. Therefore, as shown in Figure 16, in the embodiment of Figure 4, the anode-cathode current Iak flowing through the diode section 80 can be increased compared to the embodiment of Figure 3. 【0146】 Figure 17 illustrates the effective dose in the first lower end region 201. Figure 17 shows the net doping concentration distribution at the mm line shown in Figure 3. The doping concentration distribution in this example may be, for example, the carrier concentration distribution measured by the SR method using a monitor wafer or process monitor region in which a large area of ​​the first lower end region 201 is formed. The doping concentration distribution may also be calculated by thinning the individual finished product from the cathode side and obtaining a SIMS profile from the opposite side on the emitter-anode side. The mm line is a line parallel to the Z axis that passes through the lower end of the trench portion in contact with the first mesa portion 61-1. In Figure 17, the horizontal axis shows the depth position in the semiconductor substrate 10, and the vertical axis shows the net doping concentration. 【0147】 In this example, the upper end position of the first lower end region 201 is the first depth position Z1, and the lower end position of the first lower end region 201 is the second depth position Z2. The second depth position Z2 is the position of the PN junction interface between the first lower end region 201 and the drift region 18. The second depth position Z2 may be a position between the first lower end region 201 and the drift region 18 where the doping concentration shows a minimum value. 【0148】 In Figure 17, the area of ​​the hatched region corresponds to the effective dose. The effective dose may be calculated by integrating the doping concentration from the first depth position Z1 to the second depth position Z2. 【0149】 In this example, the mm line passes through the lower end of the trench section, but in other examples, the mm line may pass through the center of the first mesa section 61-1 in the X-axis direction. In this case, the upper end position of the first lower end region 201 may be the position of the PN junction interface between the first lower end region 201 and the storage region 16. If a drift region 18 is provided instead of the storage region 16, the upper end position of the first lower end region 201 may be the position of the PN junction interface between the first lower end region 201 and the drift region 18 provided above the first lower end region 201. In these cases as well, the effective dose may be the value obtained by integrating the doping concentration from the upper end position to the lower end position of the first lower end region 201. 【0150】 Figure 18 shows another example of the ee cross-section in Figure 2. The semiconductor device 100 in this example has a P-type region with a lower doping concentration than the first lower end region 201 as the second lower end region 202. The other structures are the same as any of the embodiments described in Figures 1 to 17. In this example as well, the second lower end region 202 conducts current more easily than the first lower end region 201. Therefore, snapback in the diode portion 80 can be suppressed. In addition, by providing a P-type region as the second lower end region 202, electric field concentration near the lower end of the trench portion in contact with the second lower end region 202 can be mitigated. The second lower end region 202 may have both an N-type region as shown in Figure 3, etc., and a P-type region as shown in Figure 18. For example, the second lower end region 202 may have a P-type region as shown in Figure 18 in the portion in contact with the first lower end region 201, and an N-type region as shown in Figure 3, etc., in the portion sandwiched between the P-type regions. 【0151】 The effective dose in the second lower region 202 is 3.0 × 10⁻⁶. 11 / cm 2 It can be even smaller. As shown in Figure 15, below the mesa portion 61, the effective dose is 3.0 × 10 11 / cm 2 Even with a smaller P-shaped region, snapback did not occur. Therefore, the effective dose of the second lower end region 202 was set to 3.0 × 10⁻⁶. 11 / cm 2 By making it smaller, snapback can be suppressed. The effective dose in the second lower end region 202 is 1.0 × 10⁻⁶. 11 / cm 2 The following may be true: 5.0 × 10 10 / cm 2 The following may also apply: The effective dose in the second lower region 202 is 1.0 × 10⁻⁶. 10 / cm 2 That's all. 【0152】 The effective dose in the second lower end region 202 may be obtained by integrating the doping concentration in the depth direction along the mm line, as in the example described in Figure 17. The mm line may pass through the lower end of the trench section tangent to the second mesa section 61-2, or it may pass through the center of the second mesa section 61-2 in the X-axis direction. 【0153】 In the manufacturing process of the semiconductor device 100 described in Figures 1 to 18, after forming the trench portion of each trench, and before forming the dummy insulating film 32 and dummy conductive portion 34 (or gate insulating film 42 and gate conductive portion 44), a first lower end region 201 may be formed by injecting dopant ions from the lower end of the trench portion. By performing heat treatment after injecting the dopant ions, the dopants injected into the lower end of each trench portion diffuse in the X direction, and a first lower end region 201 spanning two or more trench portions can be formed. In another example, before forming the trench portion, dopant ions may be injected from the upper surface of the semiconductor substrate 10 into the entire area where the first lower end region 201 should be formed. When an N-type region is provided as the second lower end region 202, the remaining drift region 18 may be used as the second lower end region 202 by selectively injecting P-type dopant ions into the area where the first lower end region 201 should be formed. In other examples, after injecting P-type dopant ions into the entire area where the first lower region 201 and the second lower region 202 are to be formed, the N-type second lower region 202 may be formed by counter-doping the area where the second lower region 202 is to be formed with N-type dopant ions. Alternatively, when providing a P-type region as the second lower region 202, P-type dopant ions may be selectively injected into the first lower region 201 and the second lower region 202 at different doses. In other examples, after injecting dopant ions at a uniform dose throughout the entire area where the first lower region 201 and the second lower region 202 are to be formed, P-type dopant ions may be additionally injected into the area where the first lower region 201 is to be formed. 【0154】 Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention. 【0155】 It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of symbols] 【0156】 10...Semiconductor substrate, 11...Well region, 12...Emitter region, 14...Base region, 15...Contact region, 16...Storage region, 18...Drift region, 20...Buffer region, 21...Top surface, 22...Collector region, 23...Bottom surface, 24...Collector electrode, 29...Straight section, 30...Dummy trench section, 31...Tip section, 32...Dummy insulating film, 34...Dummy conductive section, 38...Interlayer insulating film, 39...Straight section, 40...Gate trench section, 41...Tip section, 42...Gate insulating film, 44...Gate Conductive portion, 52...Emitter electrode, 54...Contact hole, 60, 61...Mesa portion, 61-1...First mesa portion, 61-2...Second mesa portion, 61-3...Third mesa portion, 64...Boundary mesa portion, 70...Transistor portion, 80...Diode portion, 81...Extended region, 82...Cathode region, 90...Edge termination structure portion, 100...Semiconductor device, 130...Outer periphery gate wiring, 131...Active side gate wiring, 160...Active portion, 162...Edge, 164...Gate pad, 201...First lower end region, 202...Second lower end region

Claims

[Claim 1] A semiconductor device comprising a semiconductor substrate having an upper surface and a lower surface, including a drift region of a first conductivity type between the upper surface and the lower surface, and having a diode portion provided therein, The aforementioned diode section is A cathode region of a first conductivity type having a higher doping concentration than the drift region is provided between the lower surface of the semiconductor substrate and the drift region, A second conductivity type base region is provided between the upper surface and the drift region of the semiconductor substrate, A plurality of trenches are provided on the semiconductor substrate from the upper surface down to below the base region and arranged in a first direction on the upper surface of the semiconductor substrate, A first lower end region of a second conductivity type is provided, positioned at a first depth and in contact with the lower ends of two or more of the trench portions, A second lower end region is positioned at the first depth position and in a position that does not overlap with the first lower end region. Equipped with, The second lower end region includes at least one of the first conductivity type region and the second conductivity type region having a lower doping concentration than the first lower end region. Semiconductor equipment. [Claim 2] The effective dose obtained by integrating the doping concentration in the first lower end region in the depth direction is 3 × 10 １１ / cm ２ That's all. The semiconductor device according to claim 1. [Claim 3] The second lower end region is the region of the first conductivity type. The semiconductor device according to claim 1. [Claim 4] In the second lower region, the effective dose obtained by integrating the doping concentration in the depth direction is 3 × 10⁻⁶ １１ / cm ２ This is a smaller region of the second conductivity type. The semiconductor device according to claim 1. [Claim 5] The diode portion further comprises an intermediate region of a first conductivity type provided between the first depth position and the base region. The semiconductor device according to claim 1. [Claim 6] The doping concentration in the intermediate region is higher than the doping concentration in the drift region. The semiconductor device according to claim 5. [Claim 7] The first lower end region and the second lower end region are arranged side by side in the first direction. The semiconductor device according to any one of claims 1 to 6. [Claim 8] The diode portion further comprises a plurality of mesa portions, each sandwiched between two of the trench portions within the semiconductor substrate. The aforementioned multiple mesa portions are, One or more first mesa portions, the first lower end region of which is positioned in contact with the lower ends of two adjacent trench portions, One or more second mesa portions, the second lower end region of which is positioned in contact with the lower ends of two adjacent trench portions, Includes, The first mesa portion and the second mesa portion are arranged side by side in the first direction. The semiconductor device according to claim 7. [Claim 9] At least one of the second mesa portions is positioned between two of the first mesa portions in the first direction. The semiconductor device according to claim 8. [Claim 10] The semiconductor substrate further comprises an upper electrode provided above the upper surface, At least one of the second mesa portions is connected to the upper electrode. The semiconductor device according to claim 8. [Claim 11] At least one of the first mesa portions is insulated from the upper electrode. The semiconductor device according to claim 10. [Claim 12] At least one of the first mesa portions is connected to the upper electrode. The semiconductor device according to claim 10. [Claim 13] Each of the plurality of mesa portions includes a third mesa portion in which the first lower end region is located in contact with the lower end of one of the two adjacent trench portions, and the second lower end region is located in contact with the lower end of the other of the two adjacent trench portions. The first mesa portion, the second mesa portion, and the third mesa portion are arranged side by side in the first direction. The semiconductor device according to claim 8. [Claim 14] The third mesa portion is located between the first mesa portion and the second mesa portion in the first direction. The semiconductor device according to claim 13. [Claim 15] The semiconductor substrate is further provided with a transistor portion arranged alongside the diode portion in the first direction, and having a collector region of a second conductivity type on the lower surface of the semiconductor substrate. The transistor section includes a plurality of the mesa sections, Of the multiple mesa portions of the transistor portion, the mesa portion closest to the diode portion is provided with the first lower end region. The semiconductor device according to claim 8. [Claim 16] A boundary mesa portion is provided on the semiconductor substrate and is positioned above the boundary between the cathode region and the collector region in the first direction, An upper electrode disposed above the upper surface of the semiconductor substrate and Furthermore, The boundary mesa portion is the first mesa portion connected to the upper electrode. The semiconductor device according to claim 15. [Claim 17] A boundary mesa portion is provided on the semiconductor substrate and is positioned above the boundary between the cathode region and the collector region in the first direction, An upper electrode disposed above the upper surface of the semiconductor substrate and Furthermore, The boundary mesa portion is the first mesa portion insulated from the upper electrode. The semiconductor device according to claim 15. [Claim 18] The doping concentration of the first lower end region of the transistor section and the doping concentration of the first lower end region of the diode section are different. The semiconductor device according to claim 15. [Claim 19] Each of the trench portions has an elongated length in a second direction different from the first direction on the upper surface of the semiconductor substrate. The first lower end region and the second lower end region are arranged side by side in the second direction. The semiconductor device according to any one of claims 1 to 5. [Claim 20] At least one of the second lower end regions is positioned between the first lower end regions in the second direction. The semiconductor device according to claim 19. [Claim 21] An upper electrode positioned above the upper surface of the semiconductor substrate, An interlayer insulating film is disposed between the upper electrode and the semiconductor substrate, and has a contact hole that connects the upper electrode and the semiconductor substrate. Furthermore, At least one of the second lower end regions has a portion that overlaps with the contact hole in a top view. The semiconductor device according to claim 19. [Claim 22] The diode portion is provided between the base region and the upper surface of the semiconductor substrate, and further comprises a second conductivity type contact region having a higher doping concentration than the base region. At least one of the second lower end regions has a portion that overlaps with the contact region in a top view. The semiconductor device according to claim 19. [Claim 23] The first lower end region and the second lower end region are arranged side by side in both the first and second directions. The semiconductor device according to claim 19.

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