Semiconductor equipment

Abstract

To provide a semiconductor device with less variation in characteristic.SOLUTION: A transistor includes an oxide semiconductor, a first conductor and a second conductor on the oxide semiconductor, a first insulator on the first conductor, a second insulator on the second conductor, a third insulator disposed on the first insulator and the second insulator and having a first opening formed overlapping with a region between the first conductor and the second conductor, a fourth insulator disposed between the first conductor and the second conductor on the oxide semiconductor, and a third conductor on the fourth insulator. A capacitor element includes the second conductor, the third insulator including a second opening reaching the second conductor, a fifth insulator disposed inside the second opening, and a fourth conductor on the fifth insulator. A plug is disposed penetrating the first insulator, the third insulator, the first conductor, and the oxide semiconductor. The plug is electrically connected to the first conductor, and the first insulator and the second insulator are metal oxide having an amorphous structure.SELECTED DRAWING: Figure 1

Description

[Technical Field] 【0001】 One aspect of the present invention relates to a transistor, a semiconductor device, and electronic equipment. Another aspect of the present invention relates to a method for manufacturing a semiconductor device. Another aspect of the present invention relates to a semiconductor wafer and a module. 【0002】 In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Semiconductor elements such as transistors, as well as semiconductor circuits, computing devices, and memory devices, are all forms of semiconductor devices. Display devices (such as liquid crystal displays and light-emitting displays), projection devices, lighting devices, electro-optical devices, energy storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices may also be considered to have semiconductor devices. 【0003】 Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the invention disclosed herein relates to a product, a method, or a method of manufacture. Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology] 【0004】 In recent years, semiconductor device development has progressed, with LSIs, CPUs, and memory being the main components used. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memory) formed on chips by processing semiconductor wafers, and electrodes that serve as connection terminals are formed on them. 【0005】 Semiconductor circuits (IC chips) such as LSIs, CPUs, and memory are mounted on circuit boards, such as printed circuit boards, and used as components in various electronic devices. 【0006】 Furthermore, the technology of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials. 【0007】 Furthermore, transistors using oxide semiconductors are known to have extremely low leakage current in the non-conductive state. For example, low-power CPUs that take advantage of the low leakage current characteristic of transistors using oxide semiconductors have been disclosed (see Patent Document 1). Also, for example, memory devices that can retain stored data for a long period of time have been disclosed that take advantage of the low leakage current characteristic of transistors using oxide semiconductors (see Patent Document 2). 【0008】 Furthermore, in recent years, with the miniaturization and weight reduction of electronic devices, there has been an increasing demand for even higher density integrated circuits. There is also a need to improve the productivity of semiconductor devices, including integrated circuits. [Prior art documents] [Patent Documents] 【0009】 [Patent Document 1] Japanese Patent Publication No. 2012-257187 [Patent Document 2] Japanese Patent Publication No. 2011-151383 [Overview of the Initiative] [Problems that the invention aims to solve] 【0010】 One aspect of the present invention aims to provide a semiconductor device with less variation in transistor characteristics. Another aspect of the present invention aims to provide a semiconductor device with good reliability. Another aspect of the present invention aims to provide a semiconductor device with good electrical characteristics. Another aspect of the present invention aims to provide a semiconductor device with a large on-current. Another aspect of the present invention aims to provide a semiconductor device that can be miniaturized or highly integrated. Another aspect of the present invention aims to provide a semiconductor device with low power consumption. 【0011】 Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other problems from the description in the specification, drawings, and claims. [Means for solving the problem] 【0012】 One aspect of the present invention is a semiconductor device having a transistor, a capacitive element, and a plug, wherein the transistor comprises an oxide semiconductor, a first conductor and a second conductor on the oxide semiconductor, a first insulator on the first conductor, a second insulator on the second conductor, a third insulator disposed on the first and second insulators and superimposed in the region between the first and second conductors with a first opening formed thereon, and a fourth insulator disposed on the oxide semiconductor and between the first and second conductors. A capacitive element comprises a second conductor, a third insulator having a second opening that reaches the second conductor, a fifth insulator disposed inside the second opening, and a fourth conductor on the fifth insulator; a plug is arranged through the first insulator, the third insulator, the first conductor, and the oxide semiconductor; the plug is electrically connected to the first conductor; and the first and second insulators are metal oxides having an amorphous structure. 【0013】 Furthermore, one aspect of the present invention is a semiconductor device having a transistor, a capacitive element, and a plug, wherein the transistor comprises an oxide semiconductor, a first conductor and a second conductor on the oxide semiconductor, a first insulator covering the first conductor and the second conductor and superimposed in the region between the first conductor and the second conductor to form a first opening, and a second insulator placed on the first insulator and superimposed in the region between the first conductor and the second conductor to form a second opening, and on the oxide semiconductor, and the first conductor and the second conductor A semiconductor device comprising a third insulator disposed between two elements and a third conductor on the third insulator, the capacitive element comprising a first insulator having a third opening formed therein between the second conductor and the second conductor, and a fourth insulator disposed inside the second insulator and the third opening and a fourth conductor on the fourth insulator, the plug being disposed through the first insulator, the second insulator, the first conductor and the oxide semiconductor, the plug being electrically connected to the first conductor, and the first insulator being a metal oxide having an amorphous structure. 【0014】 Furthermore, one aspect of the present invention is a semiconductor device having a transistor, a capacitive element, and a plug, wherein the transistor comprises an oxide semiconductor, a first conductor and a second conductor on the oxide semiconductor, a first insulator on the first conductor, a second insulator on the second conductor, a third insulator covering the first and second insulators and superimposed in the region between the first and second conductors to form a first opening, a fourth insulator disposed on the third insulator and superimposed in the region between the first and second conductors to form a second opening, and on the oxide semiconductor and between the first and second conductors A semiconductor device comprising a fifth insulator arranged in a region and a third conductor on the fifth insulator, wherein the capacitive element comprises a second conductor, a second insulator, a third insulator, and a fourth insulator having a third opening that reaches the second conductor, a sixth insulator arranged inside the third opening, and a fourth conductor on the sixth insulator, wherein the plug is arranged through the first insulator, the third insulator, the fourth insulator, the first conductor, and the oxide semiconductor, the plug is electrically connected to the first conductor, and the first insulator, the second insulator, and the third insulator are metal oxides having an amorphous structure. 【0015】 Furthermore, the above further comprises a seventh insulator and an eighth insulator, wherein the seventh insulator is placed beneath the oxide semiconductor, and the eighth insulator is in contact with the upper surface of the fourth insulator, the upper surface of the third conductor, and the upper surface of the fourth conductor, respectively, and it is preferable that the seventh insulator and the eighth insulator are metal oxides having an amorphous structure. 【0016】 Furthermore, it is preferable that the above also includes a ninth insulator, the ninth insulator covering the eighth insulator and in contact with the upper surface of the seventh insulator in a region that does not overlap with the fifth insulator, and the ninth insulator is a metal oxide having an amorphous structure. 【0017】 Furthermore, in the above, it is preferable to further include a tenth insulator and an eleventh insulator, wherein the tenth insulator is in contact with the lower surface of the seventh insulator, the eleventh insulator is in contact with the upper surface of the eighth insulator, and the tenth insulator and the eleventh insulator are silicon nitride. 【0018】 Furthermore, the above further comprises a first nitride insulator and a second nitride insulator, wherein the first nitride insulator is disposed between the first insulator and the third insulator, and the second nitride insulator is disposed between the second insulator and the third insulator, and it is preferable that the first nitride insulator and the second nitride insulator are silicon nitride. 【0019】 Furthermore, in the above configuration, it is preferable that the upper surface of the first insulator and the upper surface of the second insulator are in contact with the third insulator. 【0020】 Furthermore, in the above, the metal oxide is AlO x It is preferable that (x is any number greater than 0). 【0021】 Furthermore, one aspect of the present invention comprises a first insulating layer, a second insulating layer, a first memory cell, and a second memory cell, wherein the first memory cell comprises a first transistor, a first capacitive element, and a first plug, and the first transistor comprises a first oxide semiconductor, a first conductor and a second conductor on the first oxide semiconductor, a first insulator on the first conductor, a second insulator on the second conductor, and a third insulator disposed on the first and second insulators, with a first opening formed in the region between the first and second conductors. The first capacitive element comprises a first oxide semiconductor and a fourth insulator disposed between a first conductor and a second conductor, and a third conductor on the fourth insulator, the first capacitive element comprises a second conductor and a third insulator having a second opening that reaches the second conductor, a fifth insulator disposed inside the second opening, and a fourth conductor on the fifth insulator, the first plug is disposed through the first insulator, the third insulator, the first conductor and the first oxide semiconductor, the first plug is electrically connected to the first conductor, and the second memory cell is connected to the second transistor and The second transistor comprises a second capacitive element and a second plug, and the second transistor comprises a second oxide semiconductor, a fifth conductor and a sixth conductor on the second oxide semiconductor, a sixth insulator on the fifth conductor, a seventh insulator on the sixth conductor, an eighth insulator disposed on the sixth and seventh insulators and superimposed in the region between the fifth and sixth conductors to form a third opening, a ninth insulator disposed on the second oxide semiconductor and between the fifth and sixth conductors and a seventh conductor on the ninth insulator, and the second capacitive element is a sixth The device has an eighth insulator with a fourth opening formed therein that reaches a conductor and a sixth conductor, a tenth insulator disposed inside the fourth opening and the eighth conductor on the tenth insulator, the second plug is disposed through the sixth insulator, the ninth insulator, the fifth conductor and the second oxide semiconductor, the second plug is electrically connected to the fifth conductor, the first memory cell is provided on the first insulator layer, the second memory cell is provided on the first memory cell, the top surface of the first plug and the second plug are electrically connected, and the second insulator layer is provided on the first memory cell,The semiconductor device is arranged to cover the second memory cell, and the second insulating layer is in contact with a portion of the upper surface of the first insulating layer in regions that do not overlap with the first oxide semiconductor and the second oxide semiconductor. 【0022】 Furthermore, in the above, the first insulating layer comprises an eleventh insulator and a twelfth insulator on the eleventh insulator, and the second insulating layer comprises a thirteenth insulator and a fourteenth insulator on the thirteenth insulator, wherein the eleventh insulator and the thirteenth insulator are preferably silicon nitride, and the twelfth insulator and the fourteenth insulator are preferably metal oxides having an amorphous structure. 【0023】 Furthermore, in the above, the metal oxide is AlO x It is preferable that (x is any number greater than 0). [Effects of the Invention] 【0024】 According to one aspect of the present invention, a semiconductor device with less variation in transistor characteristics can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with a large on-current can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided. 【0025】 Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one embodiment of the present invention does not need to possess all of these effects. Other effects will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other effects from the description in the specification, drawings, and claims. [Brief explanation of the drawing] 【0026】 [Figure 1]Figure 1A is a top view of a semiconductor device according to one embodiment of the present invention. Figures 1B to 1D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 2] Figure 2 is a cross-sectional view of a semiconductor device according to one aspect of the present invention. [Figure 3] Figure 3A is a top view of a semiconductor device according to one embodiment of the present invention. Figures 3B to 3D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 4] Figure 4A illustrates the classification of IGZO crystal structures. Figure 4B illustrates the XRD spectrum of a CAAC-IGZO film. Figure 4C illustrates the micro-electron diffraction pattern of a CAAC-IGZO film. [Figure 5] Figure 5A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 5B to 5D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 6] Figure 6A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 6B to 6D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 7] Figure 7A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 7B to 7D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 8] Figure 8A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 8B to 8D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 9] Figure 9A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 9B to 9D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 10] Figure 10A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 10B to 10D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 11]Figure 11A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 11B to 11D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 12] Figure 12A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 12B to 12D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 13] Figure 13A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 13B to 13D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 14] Figure 14A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 14B to 14D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 15] Figure 15A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 15B to 15D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 16] Figure 16A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 16B to 16D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 17] Figure 17A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 17B to 17D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 18] Figure 18A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 18B to 18D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 19] Figure 19A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 19B to 19D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 20] Figure 20A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 20B to 20D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 21] Figure 21A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 21B to 21D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 22] Figure 22A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 22B to 22D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 23] Figure 23 is a top view illustrating a microwave processing apparatus according to one aspect of the present invention. [Figure 24] Figure 24 is a cross-sectional view illustrating a microwave processing apparatus according to one aspect of the present invention. [Figure 25] Figure 25 is a cross-sectional view illustrating a microwave processing apparatus according to one aspect of the present invention. [Figure 26] Figure 26 is a cross-sectional view of a semiconductor device according to one aspect of the present invention. [Figure 27] Figure 27 is a cross-sectional view of a semiconductor device according to one aspect of the present invention. [Figure 28] Figure 28A is a top view of a semiconductor device according to one aspect of the present invention. Figure 28B is a cross-sectional view of a semiconductor device according to one aspect of the present invention. [Figure 29] Figure 29 is a cross-sectional view of a semiconductor device according to one aspect of the present invention. [Figure 30] Figure 30A is a block diagram showing an example of the configuration of a storage device according to one aspect of the present invention. Figure 30B is a perspective view showing an example of the configuration of a storage device according to one aspect of the present invention. [Figure 31] Figures 31A to 31C are circuit diagrams showing an example of the configuration of a storage device according to one aspect of the present invention. [Figure 32] Figure 32 is a diagram showing various types of storage devices in a hierarchical structure. [Figure 33] Figure 33A is a block diagram of a semiconductor device according to one aspect of the present invention. Figure 33B is a perspective view of a semiconductor device according to one aspect of the present invention. [Figure 34] Figures 34A and 34B illustrate an example of an electronic component. [Figure 35]Figures 35A to 35E are schematic diagrams of a storage device according to one embodiment of the present invention. [Figure 36] Figures 36A to 36H show an electronic device according to one embodiment of the present invention. [Modes for carrying out the invention] 【0027】 The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope. Therefore, the present invention is not to be construed as being limited to the following embodiments. 【0028】 Furthermore, in drawings, size, layer thickness, or area may be exaggerated for clarity. Therefore, they are not necessarily limited to that scale. Also, the drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers or resist masks may be unintentionally reduced due to processes such as etching, but this may not be reflected in the drawings for ease of understanding. In addition, in drawings, the same reference numerals may be used in common across different drawings for the same part or parts with similar functions, and repeated explanations may be omitted. Also, when referring to similar functions, the hatch pattern may be the same, and no specific reference numeral may be assigned. 【0029】 Furthermore, in particular, in top views (also called "plan views") and perspective views, descriptions of some components may be omitted to facilitate understanding of the invention. Also, descriptions of some hidden lines may be omitted. 【0030】 Furthermore, the ordinal numbers used in this specification, such as "first," "second," etc., are for convenience only and do not indicate the order of processes or stacking. Therefore, for example, "first" can be replaced with "second" or "third," etc., as appropriate in the explanation. Also, the ordinal numbers described in this specification may not be the same as the ordinal numbers used to specify an aspect of the present invention. 【0031】 Furthermore, in this specification, terms indicating placement, such as "above" and "below," are used for convenience to explain the positional relationships between components with reference to the drawings. The positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms used are not limited to those described in the specification and can be appropriately rephrased depending on the situation. 【0032】 For example, if it is explicitly stated in this specification that X and Y are connected, then the disclosure in this specification includes cases where X and Y are electrically connected, where X and Y are functionally connected, and where X and Y are directly connected. Therefore, it is not limited to predetermined connection relationships, such as those shown in the figures or text, but also includes connection relationships other than those shown in the figures or text. Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). 【0033】 Furthermore, in this specification, a transistor is defined as an element having at least three terminals, including a gate, a drain, and a source. It also has a region where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) (hereinafter also referred to as the channel-forming region), and current can flow between the source and the drain through the channel-forming region. In this specification, the channel-forming region refers to the region through which current primarily flows. 【0034】 Furthermore, the functions of the source and drain may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, the terms source and drain may be used interchangeably in this specification. 【0035】 The channel length refers to the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or in the channel formation region, as seen in a top view of a transistor. It should be noted that the channel length is not necessarily the same in all regions of a single transistor. That is, the channel length of a single transistor may not be a single fixed value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region. 【0036】 Channel width refers to the length of the channel formation region perpendicular to the channel length direction, for example, in a top view of a transistor, where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or within the channel formation region. Note that the channel width is not necessarily the same across all regions in a single transistor. That is, the channel width of a single transistor may not be a single fixed value. Therefore, in this specification, the channel width is defined as any one value, maximum value, minimum value, or average value within the channel formation region. 【0037】 In this specification, depending on the transistor structure, the channel width in the region where the channel is actually formed (hereinafter also referred to as the "effective channel width") may differ from the channel width shown in the top view of the transistor (hereinafter also referred to as the "apparent channel width"). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may become larger than the apparent channel width, and this effect may not be negligible. For example, in a miniature transistor where the gate electrode covers the side surface of the semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width will be larger than the apparent channel width. 【0038】 In such cases, it can be difficult to estimate the effective channel width through actual measurements. For example, estimating the effective channel width from design values ​​requires the assumption that the semiconductor shape is known. Therefore, if the semiconductor shape is not precisely known, it is difficult to accurately measure the effective channel width. 【0039】 In this specification, when simply referred to as "channel width," it may refer to the apparent channel width. Alternatively, when simply referred to as "channel width," it may refer to the effective channel width. Note that channel length, channel width, effective channel width, apparent channel width, etc., can be determined by analyzing cross-sectional TEM images, etc. 【0040】 Impurities in semiconductors refer to elements other than the main components that make up the semiconductor. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities. The presence of impurities can cause problems such as an increase in the defect level density of the semiconductor or a decrease in crystallinity. In the case of oxide semiconductors, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of oxide semiconductors, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water can also function as an impurity. Furthermore, for example, the inclusion of impurities can cause oxygen vacancies (V) in oxide semiconductors. O (Also known as an oxygen vacancy) may form. 【0041】 In this specification, silicon oxide nitride refers to a material whose composition contains more oxygen than nitrogen. Similarly, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen. 【0042】 Furthermore, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." Similarly, the term "conductor" may be replaced with "conductive film" or "conductive layer." Finally, the term "semiconductor" may be replaced with "semiconductor film" or "semiconductor layer." 【0043】 Furthermore, in this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Also, "approximately parallel" means a state in which two lines are positioned at an angle of -30 degrees or more and 30 degrees or less. Also, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Also, "approximately perpendicular" means a state in which two lines are positioned at an angle of 60 degrees or more and 120 degrees or less. 【0044】 In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, when a metal oxide is used in the semiconductor layer of a transistor, that metal oxide may be referred to as an oxide semiconductor. In other words, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or oxide semiconductor. 【0045】 Furthermore, in this specification, normally off means that when no potential is applied to the gate, or when the gate is given a ground potential, the drain current flowing through the transistor per 1 μm of channel width is 1 × 10⁻¹⁶ at room temperature. -20 A or less, 1 × 10 at 85℃ -18 A or less, or 1 × 10 at 125°C -16 This means being less than or equal to A. 【0046】 (Embodiment 1) In this embodiment, an example of a semiconductor device having a transistor 200 and a capacitive element 292 according to one aspect of the present invention, and a method for manufacturing the same, will be described with reference to Figures 1 to 22. 【0047】 <Example 1 of semiconductor device configuration> The configuration of a semiconductor device having a transistor 200 and a capacitive element 292 will be explained using Figure 1. Figures 1A to 1D are top views and cross-sectional views of the semiconductor device having the transistor 200 and the capacitive element 292. Figure 1A is a top view of the semiconductor device. Figures 1B to 1D are cross-sectional views of the semiconductor device. Here, Figure 1B is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. Figure 1C is a cross-sectional view of the area indicated by the dashed line A3-A4 in Figure 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. Figure 1D is a cross-sectional view of the area indicated by the dashed line A5-A6 in Figure 1A, and is also a cross-sectional view of the capacitive element 292. Note that some elements have been omitted from the top view of Figure 1A for clarity. 【0048】 A semiconductor device according to one aspect of the present invention includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, a transistor 200 and a capacitive element 292 on the insulator 214, an insulator 280 on the transistor 200 and the capacitive element 292, an insulator 282 on the insulator 280, an insulator 284 on the insulator 282, an insulator 283 on the insulator 284, and an insulator 274 on the insulator 284. The insulators 212, 214, 280, 282, 283, 284, and 274 function as interlayer films. It also includes a conductor 240a that is electrically connected to the transistor 200 and functions as a plug, and a conductor 240b that is electrically connected to the capacitive element and functions as a plug. Furthermore, an insulator 241a is provided in contact with the side surface of the conductor 240a, which functions as a plug, and an insulator 241b is provided in contact with the side surface of the conductor 240b, which functions as a plug. In addition, a conductor 246a is provided on the insulator 274 and on the conductor 240a, electrically connected to the conductor 240a and functioning as wiring, and a conductor 246b is provided on the insulator 274 and on the conductor 240b, electrically connected to the conductor 240b and functioning as wiring. In addition, an insulator 286 is provided on the conductor 246a, on the conductor 246b, and on the insulator 274. 【0049】 Insulator 241a is provided in contact with the inner wall of the opening of insulators 282, 284, 283, and 274, a first conductor of conductor 240a is provided in contact with the side surface of insulator 241a, and a second conductor of conductor 240a is provided further inside. Insulator 241b is provided in contact with the inner wall of the opening of insulators 282, 284, 283, and 274, a first conductor of conductor 240b is provided in contact with the side surface of insulator 241b, and a second conductor of conductor 240b is provided further inside. Here, the height of the upper surface of conductor 240a and the height of the upper surface of insulator 274 in the region overlapping with conductor 246a can be made to be approximately the same. Also, the height of the upper surface of conductor 240b and the height of the upper surface of insulator 274 in the region overlapping with conductor 246b can be made to be approximately the same. Although the transistor 200 shows a configuration in which the first conductor and the second conductor of the conductor 240 (conductors 240a and 240b) are stacked, the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or as a stacked structure of three or more layers. When a structure has a stacked structure, an ordinal number may be assigned to distinguish it according to the order of formation. 【0050】 [Transistor 200] As shown in Figures 1A to 1D, the transistor 200 comprises an insulator 216 on an insulator 214, a conductor 205 (conductors 205a, 205b, and 205c) arranged to be embedded in the insulator 214 or insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, an oxide 243 (oxides 243a and 243b) on the oxide 230b, a conductor 242a on the oxide 243a, an insulator 271a on the conductor 242a, an insulator 273a on the insulator 271a, a conductor 242b on the oxide 243b, and an insulating layer on the conductor 242b. It includes a marginal body 271b, an insulator 273b on the insulator 271b, an insulator 250 (insulator 250a and insulator 250b) on the oxide 230b, a conductor 260 (conductor 260a and conductor 260b) located on the insulator 250 and overlapping with a part of the oxide 230b, an insulator 272a placed on the insulator 224, oxide 230a, oxide 230b, oxide 243a, conductor 242a, insulator 271a and insulator 273a, an insulator 272b placed on the insulator 224, oxide 230a, oxide 230b, oxide 243b, conductor 242b, insulator 271b and insulator 273b, an insulator 275a on the insulator 272a and an insulator 275b on the insulator 272b. Here, as shown in Figure 1B, the upper surface of the conductor 260 is positioned to substantially coincide with the upper surfaces of the insulator 250 and the insulator 280. The insulator 282 is in contact with the upper surfaces of the conductor 260, the insulator 250, and the insulator 280, respectively. 【0051】 In the following, oxides 230a and 230b may be collectively referred to as oxide 230. Also, insulators 250a and 250b may be collectively referred to as insulator 250. Also, insulators 271a and 271b may be collectively referred to as insulator 271. Also, insulators 272a and 272b may be collectively referred to as insulator 272. Also, insulators 273a and 273b may be collectively referred to as insulator 273. Also, insulators 275a and 275b may be collectively referred to as insulator 275. 【0052】 Insulators 280, 272, and 275 are provided with openings that reach oxide 230b. Insulator 250 and conductor 260 are arranged within these openings. Furthermore, in the channel length direction of transistor 200, conductor 260 and insulator 250 are provided between insulators 271a, 273a, conductor 242a, and oxide 243a, and insulators 271b, 273b, conductor 242b, and oxide 243b. Insulator 250 has a region in contact with the side surface of conductor 260 and a region in contact with the bottom surface of conductor 260. 【0053】 Preferably, the oxide 230 has an oxide 230a disposed on the insulator 224 and an oxide 230b disposed on top of the oxide 230a. By having oxide 230a below oxide 230b, the diffusion of impurities from structures formed below oxide 230a to oxide 230b can be suppressed. 【0054】 In the transistor 200, the oxide 230 is shown as having a configuration in which two layers of oxide 230a and oxide 230b are stacked, but the present invention is not limited to this. For example, a single layer of oxide 230b or a stacked structure of three or more layers may be provided, or oxide 230a and oxide 230b may each have a stacked structure. 【0055】 Conductor 260 functions as the first gate (also called the top gate) electrode, and conductor 205 functions as the second gate (also called the back gate) electrode. Insulator 250 functions as the first gate insulator, and insulator 224 functions as the second gate insulator. Conductor 242a functions as either the source or the drain, and conductor 242b functions as either the source or the drain. At least a portion of the region of oxide 230 that overlaps with conductor 260 functions as a channel-forming region. 【0056】 Here, an enlarged view of the vicinity of the channel formation region in FIG. 1B is shown in FIG. 2. As shown in FIG. 2, the oxide 230b has a region 230bc that functions as the channel formation region of the transistor 200, and regions 230ba and 230bb that are provided so as to sandwich the region 230bc and function as a source region or a drain region. At least a part of the region 230bc overlaps with the conductor 260. In other words, the region 230bc is provided in the region between the conductor 242a and the conductor 242b. The region 230ba is provided to overlap with the conductor 242a, and the region 230bb is provided to overlap with the conductor 242b. 【0057】 The region 230bc that functions as the channel formation region is a high-resistance region with a low carrier concentration because it has less oxygen deficiency or a lower impurity concentration than the regions 230ba and 230bb. Also, the regions 230ba and 230bb that function as the source region or the drain region are regions where the carrier concentration has increased and the resistance has been reduced due to a large amount of oxygen deficiency or a high impurity concentration such as hydrogen, nitrogen, or a metal element. That is, the regions 230ba and 230bb are regions with a high carrier concentration and low resistance compared to the region 230bc. 【0058】 Here, the carrier concentration of the region 230bc that functions as the channel formation region is preferably 18 cm -3 or less, more preferably 17 cm -3 less, even more preferably 16 cm -3 less, even more preferably 13 cm -3 less, even more preferably 12 cm -3 less, and even more preferably less. Note that the lower limit value of the carrier concentration of the region 230bc that functions as the channel formation region is not particularly limited, but for example, it can be -9 cm -3 . 【0059】 Furthermore, a region may be formed between region 230bc and region 230ba or region 230bb, where the carrier concentration is equal to or lower than that of regions 230ba and 230bb, and equal to or higher than that of region 230bc. In other words, this region functions as a junction region between region 230bc and region 230ba or region 230bb. The hydrogen concentration in this junction region may be equal to or lower than that of regions 230ba and 230bb, and equal to or higher than that of region 230bc. Also, the oxygen deficiency in this junction region may be equal to or less than that of regions 230ba and 230bb, and equal to or greater than that of region 230bc. 【0060】 Figure 2 shows an example in which regions 230ba, 230bb, and 230bc are formed in oxide 230b, but the present invention is not limited to this. For example, each of the above regions may be formed not only in oxide 230b but also in oxide 230a. 【0061】 Furthermore, in oxide 230, it can be difficult to clearly detect the boundaries between each region. The concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen, detected within each region may not be limited to stepwise changes between regions, but may also change continuously within each region. In other words, the closer a region is to the channel-forming region, the lower the concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen should be. 【0062】 In transistor 200, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor for the oxide 230 (oxide 230a and oxide 230b) which includes the channel formation region. 【0063】 Furthermore, it is preferable to use a metal oxide that functions as a semiconductor and has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large band gap in this way, the off-current of the transistor can be reduced. 【0064】 As oxide 230, for example, a metal oxide such as In-M-Zn oxide having indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) may be used. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 230. 【0065】 Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a. 【0066】 In this way, by placing oxide 230a below oxide 230b, the diffusion of impurities and oxygen from structures formed below oxide 230a to oxide 230b can be suppressed. 【0067】 Furthermore, because oxides 230a and 230b share a common element other than oxygen (as the main component), the defect level density at the interface between oxides 230a and 230b can be reduced. This minimizes the influence of interfacial scattering on carrier conduction, resulting in a high on-current. 【0068】 It is preferable that the oxide 230b is crystalline. In particular, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) as the oxide 230b. 【0069】 CAAC-OS has a highly crystalline, dense structure, and is free from impurities and defects (e.g., oxygen vacancies (V)). O CAAC-OS is a metal oxide with low oxygen vacancy (also known as oxygen vacancy). In particular, by heat-treating the CAAC-OS after its formation at a temperature that does not cause polycrystallization of the metal oxide (for example, between 400°C and 600°C), a more crystalline and dense structure can be achieved. By increasing the density of CAAC-OS in this way, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced. 【0070】 On the other hand, because it is difficult to identify clear grain boundaries in CAAC-OS, the decrease in electron mobility caused by grain boundaries is less likely to occur. Therefore, metal oxides containing CAAC-OS have stable physical properties. As a result, metal oxides containing CAAC-OS are heat resistant and highly reliable. 【0071】 In transistors using oxide semiconductors, the electrical properties can easily fluctuate and reliability may be poor if impurities or oxygen vacancies are present in the region where the channel is formed in the oxide semiconductor. Furthermore, hydrogen near the oxygen vacancy can fill the oxygen vacancy, creating a defect (hereinafter referred to as V). O Sometimes called H, it forms a channel and generates electrons that become carriers. For this reason, if the region where the channel is formed in the oxide semiconductor contains oxygen vacancies, the transistor is likely to exhibit normally-on characteristics (a characteristic in which the channel exists and current flows through the transistor even without applying voltage to the gate electrode). Therefore, in the region where the channel is formed in the oxide semiconductor, impurities, oxygen vacancies, and V are likely to be present. O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where the channel is formed has a reduced carrier concentration and is type i (intrinsed) or substantially type i. 【0072】 In contrast, by placing an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen is supplied from the insulator to the oxide semiconductor, eliminating oxygen deficiencies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source or drain region, it may cause a decrease in the on-current of transistor 200 or a decrease in the field-effect mobility. Furthermore, variations in the amount of oxygen supplied to the source or drain region within the substrate surface will result in variations in the characteristics of the semiconductor device containing the transistor. 【0073】 Therefore, in an oxide semiconductor, the region 230bc, which functions as a channel-forming region, preferably has a reduced carrier concentration and is i-type or substantially i-type, while the regions 230ba and 230bb, which function as a source region or drain region, preferably have a high carrier concentration and are n-type. In other words, oxygen vacancies in region 230bc of the oxide semiconductor, and V O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to regions 230ba and 230bb. 【0074】 Therefore, in this embodiment, with the conductor 242a and conductor 242b placed on the oxide 230b, microwave treatment is performed in an oxygen-containing atmosphere to eliminate oxygen deficiencies in region 230bc, and V O The aim is to reduce H. Here, microwave processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example. 【0075】 By performing microwave treatment in an oxygen-containing atmosphere, the oxygen gas can be converted into plasma using microwaves or high-frequency waves such as RF, and this oxygen plasma can be applied. At this time, microwaves or high-frequency waves such as RF can also be irradiated into region 230bc. Due to the action of plasma, microwaves, etc., the V of region 230bc O By cleaving H, hydrogen H is removed from region 230bc, and oxygen is lost V. OIt can be supplemented with oxygen. In other words, in region 230bc, "V O H → H + V O The following reaction occurs, which reduces the hydrogen concentration in region 230bc. Therefore, the oxygen deficiency in region 230bc, and V O This can reduce H and lower the carrier concentration. 【0076】 Furthermore, when performing microwave processing in an oxygen-containing atmosphere, microwaves, high frequencies such as RF, and oxygen plasma are shielded by conductors 242a and 242b, and do not affect regions 230ba and 230bb. In addition, the effect of oxygen plasma can be reduced by insulators 271, 273, 272, 275, and 280, which are provided covering oxide 230b and conductor 242 (conductors 242a and 242b). As a result, during microwave processing, V O This prevents a decrease in H and avoids excessive oxygen supply, thus preventing a drop in carrier concentration. 【0077】 In this way, oxygen vacancies are selectively created in the oxide semiconductor region 230bc, and V O By removing H, region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to regions 230ba and 230bb, which function as source or drain regions, can be suppressed, thereby maintaining the n-type configuration. This suppresses variations in the electrical properties of transistor 200 and prevents variations in the electrical properties of transistor 200 within the substrate plane. 【0078】 By adopting the above configuration, it is possible to provide a semiconductor device with minimal variation in transistor characteristics. Furthermore, it is possible to provide a semiconductor device with good reliability and excellent electrical characteristics. 【0079】 In Figure 1B, the side surface of the opening into which the conductor 260 is embedded, including the groove portion of the oxide 230b, is generally perpendicular to the surface of the oxide 230b being formed. However, this embodiment is not limited to this. For example, the bottom of the opening may have a gently curved surface, resulting in a U-shape. Alternatively, for example, the side surface of the opening may be inclined with respect to the surface of the oxide 230b being formed. 【0080】 Furthermore, as shown in Figure 1C, in a cross-sectional view of the transistor 200 in the channel width direction, there may be a curved surface between the side surface and the top surface of the oxide 230b. In other words, the ends of the side surface and the ends of the top surface may be curved (hereinafter also referred to as rounded). 【0081】 The radius of curvature of the curved surface is preferably greater than 0 nm and less than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or less than half the length of the region without the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and 20 nm or less, preferably 1 nm to 15 nm, and more preferably 2 nm to 10 nm. By adopting such a shape, the coverage of the oxide 230b by the insulator 250 and the conductor 260 can be improved. 【0082】 It is preferable that oxide 230 has a layered structure of multiple oxide layers with different chemical compositions. Specifically, in the metal oxide used for oxide 230a, it is preferable that the atomic ratio of element M to the main metal element is greater than the atomic ratio of element M to the main metal element in the metal oxide used for oxide 230b. Furthermore, it is preferable that the atomic ratio of element M to In in the metal oxide used for oxide 230a is greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. Furthermore, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a. 【0083】 Furthermore, it is preferable that the oxide 230b is a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies), and possess a dense structure with high crystallinity. Therefore, the extraction of oxygen from the oxide 230b by the source electrode or drain electrode can be suppressed. As a result, even when heat treatment is performed, the extraction of oxygen from the oxide 230b can be reduced, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process. 【0084】 Here, we will explain the energy levels at the junction of oxide 230a and oxide 230b. At the junction of oxide 230a and oxide 230b, the energy levels at the lower end of the conduction band of oxide 230a and oxide 230b change smoothly. In other words, the energy levels at the lower end of the conduction band at the junction of oxide 230a and oxide 230b can be said to change continuously or be continuously joined. To achieve this, it is desirable to lower the defect level density of the mixed layer formed at the interface between oxide 230a and oxide 230b. 【0085】 Specifically, by having oxides 230a and 230b share a common element other than oxygen as a main component, a mixed layer with a low defect level density can be formed. For example, if oxide 230b is In-M-Zn oxide, oxide 230a may be In-M-Zn oxide, M-Zn oxide, an oxide of element M, In-Zn oxide, indium oxide, etc. 【0086】 Specifically, for oxide 230a, a metal oxide with an atomic ratio of In:M:Zn = 1:3:4 or a similar composition, or an atomic ratio of In:M:Zn = 1:1:0.5 or a similar composition, may be used. Similarly, for oxide 230b, a metal oxide with an atomic ratio of In:M:Zn = 1:1:1 or a similar composition, or an atomic ratio of In:M:Zn = 4:2:3 or a similar composition, may be used. Note that "similar composition" includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use gallium as element M. 【0087】 Furthermore, when depositing metal oxide films by sputtering, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide film, but may also be the atomic ratio of the sputtering target used for depositing the metal oxide film. 【0088】 By configuring oxides 230a and 230b as described above, the defect level density at the interface between oxide 230a and oxide 230b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and transistor 200 can obtain a large on-current and high frequency characteristics. 【0089】 It is preferable that at least one of insulators 212, 214, 271, 272, 275, 282, 283, 284, and 286 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 into the transistor 200. Therefore, it is preferable that at least one of insulators 212, 214, 271, 272, 275, 282, 283, 284, and 286 is an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (i.e., the above impurities do not easily permeate it). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the above oxygen does not easily permeate it). 【0090】 In this specification, a barrier insulating film refers to an insulating film that has barrier properties. In this specification, barrier properties refer to the function of suppressing the diffusion of the corresponding substance (also called low permeability), or the function of capturing and fixing the corresponding substance (also called gettering). 【0091】 For insulators 212, 214, 271, 272, 275, 282, 283, 284, and 286, it is preferable to use insulators that have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, for insulators 212, 275, 283, and 286, it is preferable to use silicon nitride or the like, which has higher hydrogen barrier properties. Also, for example, for insulators 214, 271, 272, 282, and 284, it is preferable to use aluminum oxide or magnesium oxide, which have high hydrogen capture and hydrogen fixation functions. This makes it possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side via insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of impurities such as water and hydrogen from the interlayer insulating film located outside of the insulator 286 towards the transistor 200. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 224, etc., towards the substrate side via the insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 280, etc., upward from the transistor 200 via the insulator 282, etc. Thus, it is preferable to have a structure in which the transistor 200 is surrounded by insulators 212, 214, 271, 272, 275, 282, 283, 284, and 286, which have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. 【0092】 Here, it is preferable to use oxides having an amorphous structure as insulators 214, 271, 272, 282, and 284. For example, AlO x (x is any number greater than 0), or MgO yIt is preferable to use a metal oxide such as (y is any number greater than 0). In such an amorphous metal oxide, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. By using such an amorphous metal oxide as a component of the transistor 200, or by providing it around the transistor 200, hydrogen contained in the transistor 200, or hydrogen present around the transistor 200, can be captured or fixed. It is particularly preferable to capture or fix hydrogen contained in the channel formation region of the transistor 200. By using an amorphous metal oxide as a component of the transistor 200, or by providing it around the transistor 200, it is possible to manufacture a transistor 200 and a semiconductor device that have good characteristics and are highly reliable. 【0093】 Furthermore, while insulators 214, 271, 272, 282, and 284 are preferably amorphous, they may also have regions of polycrystalline structure. In addition, insulators 214, 271, 272, 282, and 284 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, a stacked structure in which a polycrystalline layer is formed on top of an amorphous layer is also possible. 【0094】 The insulators 214, 271, 272, 282, and 284 may be deposited using, for example, a sputtering method. Since sputtering does not require the use of hydrogen as a deposition gas, the hydrogen concentration of insulators 212, 214, 271, 272, 282, and 284 can be reduced. The deposition method is not limited to sputtering, and chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), atomic layer deposition (ALD), etc., may be used as appropriate. 【0095】 Furthermore, it may be preferable to lower the resistivity of insulators 212, 275, 283, and 286. For example, the resistivity of insulators 212, 275, 283, and 286 may be approximately 1 × 10⁻⁶. 13 By setting the resistivity to Ωcm, insulators 212, 275, 283, and 286 may mitigate the charge-up (charging) of conductors 205, 242, 260, or 246 during plasma-based processing in semiconductor device manufacturing processes. The resistivity of insulators 212, 275, 283, and 286 is preferably 1 × 10⁻⁶. 10 Ωcm or more, 1 × 10 15 The density should be less than or equal to Ωcm. 【0096】 Furthermore, it is preferable that insulators 216 and 280 have a lower dielectric constant than insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wiring can be reduced. For example, silicon oxide, silicon oxynitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with voids can be used as insulators 216 and 280 as appropriate. 【0097】 The conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Here, it is preferable that the conductor 205 is embedded in an opening formed in the insulator 216. 【0098】 The conductor 205 comprises conductor 205a, conductor 205b, and conductor 205c. Conductor 205a is provided in contact with the bottom surface and side wall of the opening. Conductor 205b is provided so as to be embedded in a recess formed in conductor 205a. Here, the upper surface of conductor 205b is lower than the upper surface of conductor 205a and the upper surface of insulator 216. Conductor 205c is provided in contact with the upper surface of conductor 205b and the side surface of conductor 205a. Here, the height of the upper surface of conductor 205c is approximately equal to the height of the upper surface of conductor 205a and the upper surface of insulator 216. In other words, conductor 205b is enclosed by conductors 205a and conductor 205c. 【0099】 Here, it is preferable to use conductive materials for conductors 205a and 205c that have the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use conductive materials that have the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules). 【0100】 By using conductive materials that have the function of reducing hydrogen diffusion for conductors 205a and 205c, it is possible to prevent impurities such as hydrogen contained in conductor 205b from diffusing into oxide 230 via insulator 224, etc. Furthermore, by using conductive materials that have the function of suppressing oxygen diffusion for conductors 205a and 205c, it is possible to suppress oxidation of conductor 205b and a decrease in conductivity. As conductive materials that have the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. Therefore, conductors 205a and 205c may be made of the above conductive materials in a single layer or laminate. For example, titanium nitride may be used for conductors 205a and 205c. 【0101】 Furthermore, it is preferable to use a conductive material whose main component is tungsten, copper, or aluminum for the conductor 205b. For example, tungsten may be used for the conductor 205b. 【0102】 Conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of transistor 200 can be controlled by changing the potential applied to conductor 205 independently of the potential applied to conductor 260, without linking it to the potential applied to conductor 260. In particular, by applying a negative potential to conductor 205, it is possible to increase the Vth of transistor 200 and reduce the off-current. Therefore, applying a negative potential to conductor 205 reduces the drain current when the potential applied to conductor 260 is 0V compared to not applying a negative potential. 【0103】 Furthermore, the electrical resistivity of the conductor 205 is designed considering the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 as thin as possible within the limits permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thereby suppressing the diffusion of these impurities into the oxide 230. 【0104】 Furthermore, as shown in Figure 1A, the conductor 205 should be provided in a size larger than the area that does not overlap with the conductors 242a and 242b of the oxide 230. In particular, as shown in Figure 1C, it is preferable that the conductor 205 extends to the area outside the edges of the oxide 230a and oxide 230b in the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 are superimposed on the outside of the edges of the oxide 230 in the channel width direction, with an insulator in between. With this configuration, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 which functions as the first gate electrode and the electric field of the conductor 205 which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is called a Surrounded channel (S-channel) structure. 【0105】 In this specification, an S-channel transistor refers to a transistor structure in which the channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. Furthermore, the S-channel structure disclosed in this specification is different from the Fin-type structure and the Planar-type structure. By adopting an S-channel structure, it is possible to create a transistor that has improved resistance to short-channel effects, or in other words, a transistor in which short-channel effects are less likely to occur. 【0106】 Furthermore, as shown in Figure 1C, the conductor 205 is extended to function as wiring. However, the configuration is not limited to this, and a conductor that functions as wiring may be provided beneath the conductor 205. Also, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors. 【0107】 In the transistor 200, the conductor 205 is shown as a stacked structure of conductors 205a, 205b, and 205c, but the present invention is not limited to this. For example, the conductor 205 may be provided as a single layer, two layers, or a stacked structure of four or more layers. 【0108】 Insulators 222 and 224 function as gate insulators. 【0109】 Preferably, the insulator 222 has the function of suppressing the diffusion of hydrogen (for example, at least one such as a hydrogen atom or a hydrogen molecule). Furthermore, preferably, the insulator 222 has the function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom or an oxygen molecule). For example, it is preferable that the insulator 222 has the function of suppressing the diffusion of one or both hydrogen and oxygen more effectively than the insulator 224. 【0110】 The insulator 222 may be an insulator containing an oxide of either or both of the insulating materials aluminum and hafnium. Preferably, the insulator is an oxide containing aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, by providing the insulator 222, it is possible to suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and to suppress the generation of oxygen vacancies in the oxide 230. In addition, it is possible to suppress the reaction of the conductor 205 with the oxygen contained in the insulator 224 and the oxide 230. 【0111】 Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator 222. Alternatively, these insulators may be subjected to nitriding treatment. Furthermore, the insulator 222 may be used by laminating silicon oxide, silicon oxide nitride, or silicon nitride onto these insulators. 【0112】 Furthermore, the insulator 222 may be a single-layer or multi-layer insulator containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulator, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. 【0113】 The insulator 224 in contact with the oxide 230 preferably contains excess oxygen (oxygen is removed by heating). For example, silicon oxide, silicon oxynitride, etc., can be used as appropriate for the insulator 224. By providing an oxygen-containing insulator in contact with the oxide 230, oxygen deficiency in the oxide 230 can be reduced, and the reliability of the transistor 200 can be improved. 【0114】 Specifically, as the insulator 224, it is preferable to use an oxide material from which some oxygen is desorbed upon heating, in other words, an insulating material having an excess oxygen region. An oxide that desorbs oxygen upon heating is defined as one in which the amount of oxygen molecules desorbed is 1.0 × 10⁻⁶ as determined by TDS (Thermal Desorption Spectroscopy) analysis. 18 molecular / cm² 3 Preferably 1.0 × 10 19 molecular / cm² 3 More preferably 2.0 × 10 19 molecular / cm² 3 Above, or 3.0 × 10 20 molecular / cm² 3 The oxide film is as described above. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C to 700°C, or 100°C to 400°C. 【0115】 Furthermore, during the manufacturing process of the transistor 200, it is preferable to perform a heat treatment while the surface of the oxide 230 is exposed. This heat treatment may be performed at, for example, 100°C to 600°C, more preferably 350°C to 550°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This supplies oxygen to the oxide 230, thereby preventing oxygen deficiency (V OThis can reduce the amount of oxygen absorbed. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the oxygen that has been removed. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then continuously in an atmosphere of nitrogen gas or an inert gas. Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from the absorption of water and other substances into the oxide 230. 【0116】 Furthermore, by performing an oxygenation treatment on oxide 230, oxygen deficiencies in oxide 230 are repaired by the supplied oxygen, or in other words, "V O This can accelerate the reaction "+O→null". Furthermore, the oxygen supplied reacts with the hydrogen remaining in oxide 230, removing the hydrogen as H2O (dehydration). As a result, the hydrogen remaining in oxide 230 recombines with the oxygen vacancy and V O This can suppress the formation of H. 【0117】 Furthermore, the insulators 222 and 224 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to being made of the same material, but may be made of different materials. Also, the insulator 224 may be formed in an island-like manner by being superimposed with the oxide 230a. In this case, the insulator 272 will be in contact with the side surface of the insulator 224 and the upper surface of the insulator 222. 【0118】 Oxide 243a and oxide 243b are provided on oxide 230b. Oxide 243a and oxide 243b are provided separated by the conductor 260. 【0119】 It is preferable that the oxide 243 (oxide 243a and oxide 243b) has the function of suppressing oxygen permeation. Placing oxide 243, which has the function of suppressing oxygen permeation, between the conductor 242, which functions as a source electrode or drain electrode, and oxide 230b is preferable because it reduces the electrical resistance between the conductor 242 and oxide 230b. With such a configuration, the electrical characteristics and reliability of the transistor 200 can be improved. However, if the electrical resistance between the conductor 242 and oxide 230b can be sufficiently reduced, a configuration without oxide 243 may be used. 【0120】 As oxide 243, a metal oxide containing element M may be used. In particular, element M may be aluminum, gallium, yttrium, or tin. It is preferable that oxide 243 has a higher concentration of element M than oxide 230b. Gallium oxide may also be used as oxide 243. Furthermore, metal oxides such as In-M-Zn oxide may be used as oxide 243. Specifically, in the metal oxide used for oxide 243, it is preferable that the atomic ratio of element M to In is greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. The film thickness of oxide 243 is preferably 0.5 nm to 5 nm, more preferably 1 nm to 3 nm, and even more preferably 1 nm to 2 nm. It is also preferable that oxide 243 is crystalline. When oxide 243 is crystalline, the release of oxygen from oxide 230 can be suitably suppressed. For example, if oxide 243 has a crystalline structure such as hexagonal, the release of oxygen from oxide 230 can be suppressed. 【0121】 It is preferable that the conductor 242a is provided in contact with the upper surface of the oxide 243a, and the conductor 242b is provided in contact with the upper surface of the oxide 243b. Conductors 242a and 242b function as the source electrode or drain electrode of the transistor 200, respectively. 【0122】 As the conductor 242, it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. 【0123】 Furthermore, hydrogen contained in oxide 230b, etc., may diffuse into conductor 242a or conductor 242b. In particular, by using tantalum-containing nitrides for conductor 242a and conductor 242b, hydrogen contained in oxide 230b, etc., is more likely to diffuse into conductor 242a or conductor 242b, and the diffused hydrogen may combine with nitrogen present in conductor 242a or conductor 242b. In other words, hydrogen contained in oxide 230b, etc., may be absorbed by conductor 242a or conductor 242b. 【0124】 The insulator 271a is provided in contact with the upper surface of the conductor 242a, and the insulator 271b is provided in contact with the upper surface of the conductor 242b. Preferably, the insulator 271 functions as a barrier insulating film against oxygen. Therefore, it is preferable that the insulator 271 has a function to suppress the diffusion of oxygen. For example, it is preferable that the insulator 271 has a function to suppress the diffusion of oxygen more than the insulator 280. As the insulator 271, for example, a silicon-containing nitride such as silicon nitride may be used. Furthermore, it is preferable that the insulator 271 has a function to capture impurities such as hydrogen. In that case, as the insulator 271, an amorphous metal oxide, such as aluminum oxide or magnesium oxide, may be used. In particular, it is preferable to use amorphous aluminum oxide or amorphous aluminum oxide as the insulator 271 because it may be possible to capture or fix hydrogen more effectively. This makes it possible to manufacture a transistor 200 and semiconductor device with good characteristics and high reliability. 【0125】 Insulator 273a is provided in contact with the upper surface of insulator 271a, and insulator 273b is provided in contact with the upper surface of insulator 271b. Preferably, the upper surface of insulator 273a is in contact with insulator 272a, and the side surface of insulator 273a is in contact with insulator 250. Preferably, the upper surface of insulator 273b is in contact with insulator 272b, and the side surface of insulator 273b is in contact with insulator 250. As insulator 273, it is preferable to use an insulator that has the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, it is preferable to use silicon nitride, which has higher hydrogen barrier properties, as insulator 273. 【0126】 Insulator 272a is provided in contact with oxide 230a, oxide 230b, oxide 243a, conductor 242a, insulator 271a, the side surface of insulator 273a, and the upper surface of insulator 273a, while insulator 272b is provided in contact with oxide 230a, oxide 230b, oxide 243b, conductor 242b, insulator 271b, the side surface of insulator 273b, and the upper surface of insulator 273b. Insulators 272a and 272b are also provided in contact with the upper surface of insulator 224. Preferably, insulator 272 functions as a barrier insulating film that suppresses oxygen permeation. Preferably, insulator 272 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above into insulator 224 or insulator 273, and preferably has the function of capturing impurities such as hydrogen. In that case, the insulator 272 is preferably aluminum oxide having an amorphous structure, or aluminum oxide with an amorphous structure. Metal oxides having an amorphous structure, in particular aluminum oxide having an amorphous structure, and aluminum oxide with an amorphous structure can capture or fix hydrogen present in the surroundings, thus enabling the fabrication of transistors 200 and semiconductor devices with good properties and high reliability. 【0127】 The insulator 275 is provided covering the insulator 272, and openings are formed in the regions where the insulator 250 and the conductor 260 are provided. Silicon nitride is preferably used as the insulator 275. 【0128】 Insulators 280, 224, 222, and 275 are arranged in the region sandwiched between insulators 212 and 283. By providing an insulator 272 that is in contact with insulator 275 and has the function of capturing impurities such as hydrogen, impurities such as hydrogen contained in insulators 280, 224, 275, and 273 can be captured, and the amount of hydrogen in that region can be kept constant. In this case, it is preferable to use aluminum oxide or the like as the insulator 272. 【0129】 The insulator 250 functions as a gate insulator. It is preferable that the insulator 250 be placed in contact with the upper surface of the oxide 230b. The insulator 250 can be silicon oxide, silicon oxynitride, silicon oxide nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide. In particular, silicon oxide and silicon oxynitride are preferred because they are stable with respect to heat. 【0130】 Similar to the insulator 224, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 is reduced. The film thickness of the insulator 250 is preferably between 1 nm and 20 nm. 【0131】 In Figures 1A to 1D, the insulator 250 is shown as a two-layer structure consisting of insulator 250a and insulator 250b. When the insulator 250 is a two-layer laminated structure, it is preferable that the lower layer, insulator 250a, is formed using an insulator that releases oxygen upon heating, and the upper layer, insulator 250b, is formed using an insulator that has the function of suppressing oxygen diffusion. With this configuration, it is possible to suppress the diffusion of oxygen contained in insulator 250a to the conductor 260. In other words, it is possible to suppress the reduction in the amount of oxygen supplied to the oxide 230. Furthermore, it is possible to suppress the oxidation of the conductor 260 by the oxygen contained in insulator 250a. For example, insulator 250a can be made using a material that can be used for the insulator 250 as described above, and the upper layer of insulator 250 can be made using the same material as insulator 222. Note that the insulator 250 may be a single-layer structure or a laminated structure of three or more layers. 【0132】 Furthermore, when silicon oxide or silicon oxynitride is used for insulator 250a, insulator 250b may be an insulating material that is a high-k material with a high dielectric constant. By making the gate insulator a laminated structure of insulator 250a and insulator 250b, a laminated structure that is stable against heat and has a high dielectric constant can be made. Therefore, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it becomes possible to thin the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator. 【0133】 Specifically, as the insulator 250b, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or metal oxides that can be used as oxide 230, can be used. In particular, it is preferable to use an insulator containing oxides of aluminum and hafnium, or both. For example, as the insulator 250b, a laminated structure containing silicon oxide and hafnium oxide on the silicon oxide can be used. 【0134】 Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. It is preferable that the metal oxide suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, the decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 by oxygen from the insulator 250 can be suppressed. 【0135】 Furthermore, the above-mentioned metal oxide may be configured to function as part of the first gate electrode. For example, a metal oxide that can be used as oxide 230 can be used as the above-mentioned metal oxide. In that case, the electrical resistance of the above-mentioned metal oxide can be reduced by depositing the conductor 260a by sputtering, thereby making it a conductor. This can be called an OC (Oxide Conductor) electrode. 【0136】 By having the above-mentioned metal oxide, the on-current of the transistor 200 can be improved without weakening the influence of the electric field from the conductor 260. Furthermore, by maintaining the distance between the conductor 260 and the oxide 230 through the physical thickness of the insulator 250 and the above-mentioned metal oxide, leakage current between the conductor 260 and the oxide 230 can be suppressed. In addition, by providing a laminated structure of the insulator 250 and the above-mentioned metal oxide, the physical distance between the conductor 260 and the oxide 230, and the electric field strength applied from the conductor 260 to the oxide 230 can be easily and appropriately adjusted. 【0137】 The conductor 260 functions as the first gate electrode of the transistor 200. Preferably, the conductor 260 has a conductor 260a and a conductor 260b disposed on top of the conductor 260a. For example, it is preferable that the conductor 260a is arranged to enclose the bottom and sides of the conductor 260b. Also, as shown in Figure 1B, the top surface of the conductor 260 is substantially the same as the top surface of the insulator 250. Note that although the conductor 260 is shown as a two-layer structure of conductor 260a and conductor 260b, it may also be a single-layer structure or a stacked structure of three or more layers. 【0138】 It is preferable to use a conductive material for the conductor 260a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules). 【0139】 Furthermore, because the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress the oxidation of the conductor 260b by the oxygen contained in the insulator 250, which would otherwise reduce its conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. 【0140】 Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 260b may also be in a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material. 【0141】 Furthermore, in transistor 200, the conductor 260 is formed self-aligningly to fill the openings formed in the insulator 280 and the like. By forming the conductor 260 in this way, the conductor 260 can be reliably positioned in the region between the conductors 242a and 242b without the need for alignment. 【0142】 Furthermore, as shown in Figure 1C, in the channel width direction of the transistor 200, with reference to the bottom surface of the insulator 222, the height of the bottom surface of the conductor 260 in the region where the conductor 260 and the oxide 230b do not overlap is preferably lower than the height of the bottom surface of the oxide 230b. By configuring the conductor 260, which functions as a gate electrode, to cover the side and top surfaces of the channel formation region of the oxide 230b via the insulator 250 or the like, it becomes easier to apply the electric field of the conductor 260 to the entire channel formation region of the oxide 230b. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved. With reference to the bottom surface of the insulator 222, the difference between the height of the bottom surface of the conductor 260 in the region where the oxide 230a and oxide 230b and the conductor 260 do not overlap and the height of the bottom surface of the oxide 230b is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less. 【0143】 [Capacitive element 292] The capacitive element 292 includes a conductor 242b, an insulator 293 provided on the conductor 242b, and a conductor 294 provided on the insulator 293. Here, the insulator 293 and the conductor 294 are arranged in openings formed in insulators 280, 275b, 272b, 273b, and 271b. The insulator 293 is provided in contact with the bottom surface and side walls of the opening. That is, the insulator 293 is in contact with the top surface of the conductor 242b, the side surface of the insulator 271b, the side surface of the insulator 273b, the side surface of the insulator 272b, the side surface of the insulator 275b, and the side surface of the insulator 280. Furthermore, the insulator 293 is provided so as to form a recess along the shape of the opening. The conductor 294 is provided in contact with the top surface and side surface of the insulator 293 so as to fill the recess. Note that the height of the upper surfaces of the insulator 293 and the conductor 294 may roughly coincide with the height of the upper surfaces of the insulator 280, the insulator 250, and the conductor 260. 【0144】 Here, the conductor 242b functions as the lower electrode of the capacitive element 292, the conductor 294 functions as the upper electrode of the capacitive element 292, and the insulator 293 functions as the dielectric of the capacitive element 292. In this way, the capacitive element 292 constitutes a MIM (Metal-Insulator-Metal) capacitance. Since one of the pair of electrodes of the capacitive element 292, namely the conductor 242b, also serves as the source electrode of the transistor, it is possible to reduce the area required for the placement of the transistor and the capacitive device. Furthermore, since part of the manufacturing process for the capacitive element 292 can be shared with the manufacturing process for the transistor, a highly productive semiconductor device can be created. In addition, since the insulator 293 can be provided separately from the configuration of the transistor 200, the structure and material of the insulator 293 can be appropriately selected according to the performance required for the capacitive element 292. 【0145】 It is preferable to use a high-dielectric-constant (high-k) material for the insulator 293. Examples of high-dielectric-constant (high-k) materials (materials with high relative permittivity) as insulators include gallium oxide, hafnium oxide, zirconium oxide, aluminum oxide, aluminum oxide, aluminum nitride, aluminum nitride, hafnium oxide, hafnium nitride, hafnium nitride, oxides containing aluminum and hafnium, oxides containing aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and hafnium, or nitrides containing silicon and hafnium. Alternatively, a laminated film of these high-dielectric-constant materials may be used as the insulator 293. For example, an insulating film laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used as the insulator 293. 【0146】 Furthermore, the conductor 294 may be made of a material that can be used for the conductor 260, for example. Also, the conductor 294 may have a laminated structure similar to that of the conductor 260. 【0147】 The insulator 280 is provided on the insulator 275, and openings are formed in the regions where the insulator 250 and the conductor 260 are provided. The upper surface of the insulator 280 may also be flattened. 【0148】 The insulator 280, which functions as an interlayer film, preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between the wiring can be reduced. The insulator 280 is preferably made of the same material as the insulator 216, for example. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are particularly preferred because they can easily form regions containing oxygen that is desorbed by heating. 【0149】 The insulator 280, like the insulator 224, preferably has an excess oxygen region or excess oxygen. Furthermore, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 280 is reduced. For example, the insulator 280 may be made of silicon oxides such as silicon oxide or silicon oxynitride. 【0150】 The insulator 282 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the insulator 280 from above, and preferably has the function of capturing impurities such as hydrogen. Furthermore, it is preferable that the insulator 282 functions as a barrier insulating film that suppresses the permeation of oxygen. As the insulator 282, an amorphous metal oxide, such as aluminum oxide, may be used. By providing an insulator 282 that is in contact with the insulator 280 in the region sandwiched between the insulator 212 and the insulator 283 and has the function of capturing impurities such as hydrogen, impurities such as hydrogen contained in the insulator 280 can be captured, and the amount of hydrogen in that region can be kept constant. In particular, it is preferable to use an amorphous aluminum oxide, or an amorphous aluminum oxide, as the insulator 282, as this may allow for more effective capture or fixation of hydrogen. This makes it possible to manufacture a transistor 200 and a semiconductor device with good characteristics and high reliability. 【0151】 The insulator 283 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the insulator 280 from above. The insulator 283 is placed on top of the insulator 282. Preferably, the insulator 283 is a silicon-containing nitride such as silicon nitride or silicon nitride oxide. For example, silicon nitride deposited by sputtering may be used as the insulator 283. By depositing the insulator 283 by sputtering, a silicon nitride film with high density and less susceptibility to porosity can be formed. Alternatively, as the insulator 283, silicon nitride deposited by CVD may be further laminated on top of silicon nitride deposited by sputtering. 【0152】 It is preferable that the conductors 240a and 240b are made of conductive materials mainly composed of tungsten, copper, or aluminum. Furthermore, the conductors 240a and 240b may be arranged in a laminated structure. 【0153】 Furthermore, when the conductor 240 has a laminated structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the conductor in the lower layer of the conductor 240. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. Also, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminate. In addition, it is possible to suppress the mixing of impurities such as water and hydrogen contained in the layer above the insulator 274 into the oxide 230 through the conductor 240a. 【0154】 As insulators 241a and 241b, for example, insulators such as silicon nitride, aluminum oxide, and silicon oxide nitride may be used. Since insulator 241a is provided in contact with insulators 274, 283, 284, 282, 280, 275a, 272a, 273a, and 271a, it can suppress the mixing of impurities such as water and hydrogen contained in insulator 280, etc., into the oxide 230 through conductor 240a. Similarly, since insulator 241b is provided in contact with insulators 274, 283, 284, and 282, it can suppress the mixing of impurities such as water and hydrogen contained in insulator 274, etc., into the oxide 230 through conductor 240b and conductor 294. Silicon nitride is particularly suitable because of its high blocking properties for hydrogen. Furthermore, it is possible to prevent the oxygen contained in the insulator 280 from being absorbed by the conductor 240a. Also, it is possible to prevent the oxygen contained in the insulator 274 from being absorbed by the conductor 240b. 【0155】 Furthermore, conductors 246 (conductors 246a and 246b) that function as wiring may be placed in contact with the upper surfaces of conductors 240a and 240b. It is preferable that the conductors 246 be made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductors may also be in a laminated structure, for example, a laminate of titanium or titanium nitride and the conductive material. The conductors may be formed to be embedded in openings provided in the insulator. Alternatively, an insulator 286 may be provided on the conductors 246 and on the insulator 274. 【0156】 <Component materials for semiconductor devices> The following describes the constituent materials that can be used in semiconductor devices. 【0157】 <<Substrate>> As the substrate for forming transistor 200, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon and germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides or metal oxides. Furthermore, there are substrates on which a conductor or semiconductor is provided on an insulating substrate, substrates on which a conductor or insulator is provided on a semiconductor substrate, and substrates on which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates with elements mounted on them may be used. Examples of elements mounted on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements. 【0158】 <<Insulator>> Insulators include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides. 【0159】 For example, as transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator. 【0160】 Furthermore, examples of insulators with high dielectric constants include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium. 【0161】 Insulators with low dielectric constants include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with vacancies, or resins. 【0162】 Furthermore, transistors using metal oxides in the channel formation region can have their electrical properties stabilized by surrounding them with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxide nitride, and silicon nitride can be used. 【0163】 Furthermore, the insulator that functions as a gate insulator is preferably an insulator that has a region containing oxygen that is desorbed by heating. For example, by having a silicon oxide or silicon oxynitride having a region containing oxygen that is desorbed by heating in contact with the oxide 230, the oxygen deficiency of the oxide 230 can be compensated for. 【0164】 <<Conductive material>> As the conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metallic elements, or an alloy combining the above metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used. 【0165】 Furthermore, multiple conductive layers formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with a nitrogen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material. 【0166】 Furthermore, when using an oxide in the channel formation region of a transistor, it is preferable to use a laminated structure for the conductor functioning as the gate electrode, which combines a material containing the aforementioned metal element with a conductive material containing oxygen. In this case, it is preferable to place the conductive material containing oxygen on the channel formation region side. By placing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is more easily supplied to the channel formation region. 【0167】 In particular, it is preferable to use a conductive material containing metal elements and oxygen contained in the metal oxide in which the channel is formed as the conductor that functions as the gate electrode. Alternatively, conductive materials containing the aforementioned metal elements and nitrogen may be used. For example, conductive materials containing nitrogen such as titanium nitride and tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-doped indium tin oxide may be used. In addition, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may be possible to capture hydrogen that is mixed in from an external insulator or the like. 【0168】 <<Metal Oxides>> It is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor as oxide 230. The following describes metal oxides that can be used as oxide 230. 【0169】 The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that it contains both indium and zinc. 【0170】 Here, we consider the case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. Element M can be aluminum, gallium, yttrium, or tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, it is sometimes permissible to use a combination of multiple of the aforementioned elements as element M. 【0171】 In this specification, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be called metal oxynitrides. 【0172】 <Classification of crystal structures> First, we will explain the classification of crystal structures in oxide semiconductors using Figure 4A. Figure 4A is a diagram illustrating the classification of crystal structures in oxide semiconductors, specifically IGZO (a metal oxide containing In, Ga, and Zn). 【0173】 As shown in Figure 4A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." "Amorphous" includes completely amorphous materials. "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite) (excluding single crystal and polycrystal). Note that single crystal, polycrystal, and completely amorphous materials are excluded from the "Crystalline" classification. "Crystal" includes single crystal and polycrystal materials. 【0174】 The structure within the thick frame shown in Figure 4A represents an intermediate state between "Amorphous" and "Crystal," and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as being completely different from the energetically unstable "Amorphous" and "Crystal" states. 【0175】 The crystal structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 4B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 4B will simply be referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 4B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 4B is 500 nm. 【0176】 As shown in Figure 4B, the XRD spectrum of the CAAC-IGZO film shows a peak indicating clear crystallinity. Specifically, the XRD spectrum of the CAAC-IGZO film shows a peak indicating c-axis orientation near 2θ=31°. As shown in Figure 4B, the peak near 2θ=31° is asymmetrical with respect to the angle at which the peak intensity was detected. 【0177】 Furthermore, the crystal structure of a film or substrate can be evaluated by the diffraction pattern (also called the nano-beam electron diffraction pattern) observed by nano-beam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 4C. Figure 4C shows the diffraction pattern observed by NBED with the electron beam incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 4C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In nano-beam electron diffraction, electron diffraction is performed with a probe diameter of 1 nm. 【0178】 As shown in Figure 4C, the diffraction pattern of the CAAC-IGZO film shows multiple spots indicating c-axis orientation. 【0179】 <<Oxide semiconductor structure>> Note that when focusing on the crystal structure, oxide semiconductors may be classified differently from those shown in Figure 4A. For example, oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the aforementioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors also include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), and amorphous oxide semiconductors. 【0180】 Here, we will explain the details of the CAAC-OS, nc-OS, and a-like OS mentioned above. 【0181】 [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, the c-axis of which is oriented in a specific direction. This specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If we consider the atomic arrangement as a lattice arrangement, then a crystalline region is also a region with a aligned lattice arrangement. Furthermore, CAAC-OS has regions where multiple crystalline regions are connected in the ab-plane direction, and these regions may exhibit distortion. Distortion refers to a point in the connected region where the orientation of the lattice arrangement changes between a region with a aligned lattice arrangement and another region with a aligned lattice arrangement. In short, CAAC-OS is an oxide semiconductor that is c-axis oriented and does not exhibit clear orientation in the ab-plane direction. 【0182】 Each of the multiple crystalline regions described above is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of a single minute crystal, the maximum diameter of that crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of that crystalline region may be around several tens of nanometers. 【0183】 Furthermore, in In-M-Zn oxides (where element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystalline structure (also called a layered structure) consisting of layers containing indium (In) and oxygen (hereinafter referred to as the In layer) and layers containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer). Note that indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Also, the In layer may contain Zn. This layered structure can be observed, for example, as a lattice image in high-resolution TEM images. 【0184】 When structural analysis of a CAAC-OS film is performed using an XRD instrument, for example, out-of-plane XRD measurements using θ / 2θ scanning show a peak indicating c-axis orientation at 2θ = 31° or nearby. Note that the position of the c-axis orientation peak (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS. 【0185】 Furthermore, for example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film. These spots are observed at point-symmetric positions with respect to the incident electron beam spot (also called the direct spot) that passed through the sample. 【0186】 When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the strain may have lattice arrangements such as pentagons or heptagons. Moreover, in CAAC-OS, clear grain boundaries cannot be observed even near the strain. In other words, it can be seen that the formation of grain boundaries is suppressed by the strain in the lattice arrangement. This is thought to be because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction, and the bond distance between atoms changes due to the substitution of metal atoms. 【0187】 A crystal structure in which clear grain boundaries are observed is called a polycrystal. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in transistor on-current and field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides with a suitable crystal structure for the semiconductor layer of a transistor. In addition, a structure containing Zn is preferred for the composition of CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are preferred because they suppress the generation of grain boundaries more than In oxide. 【0188】 CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. Furthermore, since the crystallinity of oxide semiconductors can decrease due to the inclusion of impurities or the generation of defects, CAAC-OS can be considered an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in OS transistors allows for greater flexibility in the manufacturing process. 【0189】 [nc-OS] nc-OS exhibits periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). In other words, nc-OS contains minute crystals. These minute crystals are also called nanocrystals because their size is, for example, between 1 nm and 10 nm, particularly between 1 nm and 3 nm. Furthermore, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductors. For example, when structural analysis of an nc-OS film is performed using an XRD instrument, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the nanocrystals (e.g., 50 nm or larger), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystal (for example, 1 nm to 30 nm), an electron diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on a direct spot. 【0190】 [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Also, a-like OS has a higher hydrogen concentration in the film compared to nc-OS and CAAC-OS. 【0191】 <<Oxide Semiconductor Composition>> Next, we will explain the details of CAC-OS mentioned above. Note that CAC-OS refers to the material composition. 【0192】 [CAC-OS] CAC-OS is a material composition in which, for example, the elements constituting the metal oxide are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide, and the regions containing these metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size, is also referred to as a mosaic or patchy state. 【0193】 Furthermore, CAC-OS is a composite metal oxide having a mosaic-like structure formed by the separation of the material into a first region and a second region, with the first region distributed within the film (hereinafter also referred to as a cloud-like structure). In other words, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed. 【0194】 Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is the region where [In] is greater than the [In] in the composition of the CAC-OS film. The second region is the region where [Ga] is greater than the [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is the region where [In] is greater than the [In] in the second region, and [Ga] is smaller than the [Ga] in the second region. The second region is the region where [Ga] is greater than the [Ga] in the first region, and [In] is smaller than the [In] in the first region. 【0195】 Specifically, the first region described above is a region whose main components are indium oxide, indium zinc oxide, etc. The second region described above is a region whose main components are gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region whose main component is In. Similarly, the second region can be rephrased as a region whose main component is Ga. 【0196】 Furthermore, a clear boundary may not be observed between the first region and the second region described above. 【0197】 For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) confirms that it has a structure in which regions mainly composed of In (first region) and regions mainly composed of Ga (second region) are unevenly distributed and mixed. 【0198】 When CAC-OS is used in a transistor, the conductivity due to the first region and the insulation due to the second region work complementaryly to give CAC-OS a switching function (on / off function). In other words, CAC-OS has conductive function in part of the material, insulating function in part of the material, and semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I) can be achieved. on This enables high field-effect mobility (μ) and good switching operation. 【0199】 Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention may include two or more of the following: amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS. 【0200】 <Transistors containing oxide semiconductors> Next, we will explain the case where the above oxide semiconductor is used in a transistor. 【0201】 By using the above-mentioned oxide semiconductor in transistors, it is possible to realize transistors with high field-effect mobility. Furthermore, it is possible to realize highly reliable transistors. 【0202】 It is preferable to use an oxide semiconductor with a low carrier concentration in the channel formation region of a transistor. For example, the carrier concentration in the channel formation region of an oxide semiconductor is 1 × 10⁻⁶. 17 cm -3 The following is preferably 1 × 10 15 cm -3 More preferably 1 × 10 13 cm -3 More preferably 1 × 10 11 cm -3 More preferably 1 × 10 10 cm -3 It is less than 1 × 10 -9 cm -3 This concludes the explanation. Furthermore, when lowering the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film should be lowered to reduce the defect level density. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that oxide semiconductors with low carrier concentrations are sometimes referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. 【0203】 Furthermore, oxide semiconductor films that are highly pure or substantially highly pure have a low defect level density, which may result in a low trap level density. 【0204】 Furthermore, charges trapped in the trap levels of oxide semiconductors can take a long time to disappear, sometimes behaving like fixed charges. Therefore, transistors in which channel formation regions are formed in oxide semiconductors with a high trap level density may exhibit unstable electrical properties. 【0205】 Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. 【0206】 <Impurities> Here, we will explain the effects of various impurities in oxide semiconductors. 【0207】 In oxide semiconductors, the presence of silicon or carbon, which are Group 14 elements, leads to the formation of defect levels in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the channel formation region of the oxide semiconductor and the concentration of silicon or carbon near the interface with the channel formation region of the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are compared by 2 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies: 【0208】 Furthermore, if an oxide semiconductor contains alkali metals or alkaline earth metals, it may form defect levels and generate carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit normally-on characteristics. For this reason, the concentration of alkali metals or alkaline earth metals in the channel formation region of the oxide semiconductor obtained by SIMS should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following: 【0209】 Furthermore, in oxide semiconductors, the presence of nitrogen generates electrons, which act as carriers, increasing the carrier concentration and making it easier for the semiconductor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Alternatively, the presence of nitrogen in oxide semiconductors can lead to the formation of trap levels. As a result, the electrical properties of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of oxide semiconductors obtained by SIMS should be set to 5 × 10⁻⁶. 19 atoms / cm 3 Less than 5 × 10 18atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 Do the following: 【0210】 Furthermore, hydrogen contained in oxide semiconductors can react with oxygen bonded to metal atoms to form water, potentially creating oxygen vacancies. When hydrogen fills these oxygen vacancies, electrons, which act as carriers, may be generated. Additionally, some of the hydrogen can combine with oxygen bonded to metal atoms to generate electrons. Therefore, transistors using oxide semiconductors containing hydrogen tend to exhibit normally-on characteristics. For this reason, it is preferable to minimize the amount of hydrogen in the channel formation region of the oxide semiconductor. Specifically, in the channel formation region of the oxide semiconductor, the hydrogen concentration obtained by SIMS should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 5 × 10 19 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Make it less than. 【0211】 By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be provided. 【0212】 <<Other Semiconductor Materials>> The semiconductor material that can be used for oxide 230 is not limited to the metal oxides described above. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used as oxide 230. For example, it is preferable to use semiconductors of elemental elements such as silicon, compound semiconductors such as gallium arsenide, or layered materials that function as semiconductors (also called atomic layer materials, two-dimensional materials, etc.) as the semiconductor material. In particular, it is preferable to use layered materials that function as semiconductors as the semiconductor material. 【0213】 In this specification, the term "layered material" refers to a group of materials having a layered crystalline structure. A layered crystalline structure is a structure in which layers formed by covalent or ionic bonds are stacked via weaker bonds than covalent or ionic bonds, such as van der Waals forces. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, it is possible to provide a transistor with a large on-current. 【0214】 Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens. Chalcogens are a general term for elements belonging to Group 16, and include oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. 【0215】 As oxide 230, it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor. Specific examples of transition metal chalcogenides applicable as oxide 230 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2). 【0216】 <Example of semiconductor device configuration 2> Using Figures 3A to 3D, a configuration of a semiconductor device having a transistor 200 and a capacitive element 292, different from the above-described <Example of Semiconductor Device Configuration 1>, will be explained. Figure 3A is a top view of the semiconductor device. Figures 3B to 3D are cross-sectional views of the semiconductor device. Here, Figure 3B is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 3A, and is also a cross-sectional view of the transistor 200 in the channel length direction. Figure 3C is a cross-sectional view of the area indicated by the dashed line A3-A4 in Figure 3A, and is also a cross-sectional view of the transistor 200 in the channel width direction. Figure 3D is a cross-sectional view of the area indicated by the dashed line A5-A6 in Figure 3A, and is also a cross-sectional view of the capacitive element 292. Note that in the top view of Figure 3A, some elements have been omitted for clarity. 【0217】 In the semiconductor devices shown in Figures 3A to 3D, structures having the same function as those constituting the semiconductor device shown in <Example of Semiconductor Device Configuration 1> are denoted by the same reference numerals. Furthermore, in this section as well, the materials used for the semiconductor device components are those described in detail in <Example of Semiconductor Device Configuration 1>. 【0218】 In the semiconductor device shown in FIGS. 3A to 3D, insulators 214, 216, 222, 224, 272, 275, 280, and 282 are patterned. Further, insulator 284 is structured to cover insulators 212, 214, 216, 222, 224, 272, 275, 280, and 282. That is, insulator 284 contacts the upper surface of insulator 282, the side surfaces of insulators 214, 216, 222, 224, 272, 275, and 280, and the upper surface of insulator 214. Further, insulator 283 is disposed to cover insulator 284. Thereby, insulators 214, 216, 222, 224, 280, and 282, including oxide 230, etc., are isolated from the outside by insulators 283, 284, 212, and 214. In other words, transistor 200 is disposed within a region sealed by insulator 284 and insulator 214. 【0219】 For example, insulators 214, 271, 275, 282, and 284 may be formed using a material having a function of capturing and fixing hydrogen. Note that the same insulator as insulator 282 can be used for insulator 284. Further, insulators 212 and 283 may be formed using a material having a function of suppressing diffusion of hydrogen and oxygen. As insulators 214, 271, 275, 282, and 284, a metal oxide having an amorphous structure, such as aluminum oxide, can be used. Typically, silicon nitride can be used as insulators 212 and 283. In particular, as insulator 284, it is preferable to use amorphous aluminum oxide or aluminum oxide having an amorphous structure because hydrogen can be more effectively captured or fixed in some cases. Thereby, a semiconductor device having a transistor 200 with good characteristics and high reliability and a capacitive element 292 can be manufactured. 【0220】 With the above configuration, it is possible to suppress hydrogen contained outside the sealed region from mixing into the sealed region. 【0221】 Also, in FIGS. 3A to 3D, the configuration in which the insulator 212 and the insulator 283 are provided as a single layer is shown, but the present invention is not limited to this. For example, each of the insulator 212 and the insulator 283 may be provided with a stacked structure of two or more layers. 【0222】 The insulator 274 is provided so as to cover the insulator 283 and functions as an interlayer film. It is preferable that the insulator 274 has a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. The insulator 274 can be provided using, for example, the same material as the insulator 280. 【0223】 <Method for manufacturing a semiconductor device> Next, a method for manufacturing a semiconductor device according to an aspect of the present invention shown in FIGS. 3A to 3D will be described using FIGS. 5A to 22D. 【0224】 A in each figure shows a top view. Also, B in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A1 - A2 shown in A of each figure, and is also a cross-sectional view in the channel length direction of the transistor 200. Further, C in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A3 - A4 in A of each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. Also, D in each figure is a cross-sectional view of the portion indicated by the dashed line A5 - A6 in A of each figure, and is also a cross-sectional view of the capacitor element 292. In the top view of A in each figure, some elements are omitted for clarity of the figure. 【0225】 Hereinafter, an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor can be formed into a film by appropriately using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. 【0226】 Sputtering methods include RF sputtering, which uses a high-frequency power supply; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrodes in pulses. RF sputtering is mainly used for depositing insulating films, while DC sputtering is mainly used for depositing conductive metal films. Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering. 【0227】 Furthermore, CVD methods can be classified into plasma-enhanced CVD (PECVD), which utilizes plasma; thermal CVD (TCVD), which utilizes heat; and photo-CVD (Photo-CVD), which utilizes light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD) depending on the source gas used. 【0228】 Plasma CVD allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing damage to the workpiece. For example, wiring, electrodes, and elements (transistors, capacitive elements, etc.) contained in semiconductor devices can become charged by receiving charge from the plasma. In this case, the accumulated charge can destroy the wiring, electrodes, and elements contained in the semiconductor device. In contrast, thermal CVD, which does not use plasma, does not cause such plasma damage, thus increasing the yield of semiconductor devices. Furthermore, because thermal CVD does not cause plasma damage during film formation, films with fewer defects can be obtained. 【0229】 Furthermore, ALD methods include thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and PEALD (Plasma Enhanced ALD), which uses plasma-excited reactants. 【0230】 Furthermore, the ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer, resulting in advantages such as the ability to deposit extremely thin films, deposit films on structures with high aspect ratios, deposit films with fewer defects such as pinholes, deposit films with excellent coverage, and deposit films at low temperatures. The PEALD method, by utilizing plasma, allows for even lower temperatures, which can be preferable in some cases. However, some precursors used in the ALD method contain impurities such as carbon. Therefore, films formed by the ALD method may contain more impurities such as carbon compared to films formed by other deposition methods. The quantitative determination of impurities can be performed using X-ray photoelectron spectroscopy (XPS). 【0231】 Unlike film deposition methods where particles emitted from a target or other source are deposited, CVD and ALD methods form films through reactions on the surface of the workpiece. Therefore, they are less affected by the shape of the workpiece and offer good step-level coverage. In particular, the ALD method is suitable for coating the surface of openings with high aspect ratios due to its excellent step-level coverage and uniform thickness. However, because the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other film deposition methods that have a faster deposition rate, such as the CVD method. 【0232】 CVD and ALD methods allow for control of the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, CVD and ALD methods can deposit films of any composition by changing the flow rate ratio of the source gases. Furthermore, CVD and ALD methods can deposit films with continuously changing compositions by changing the flow rate ratio of the source gases during film deposition. When depositing films while changing the flow rate ratio of the source gases, the time required for film deposition can be shortened compared to depositing films using multiple deposition chambers, because time spent on transport and pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices. 【0233】 First, a substrate (not shown) is prepared, and an insulator 212 is deposited on the substrate (see Figures 5A to 5D). The deposition of the insulator 212 is preferably carried out using a sputtering method. By using a sputtering method that does not require the use of hydrogen as the deposition gas, the hydrogen concentration in the insulator 212 can be reduced. However, the deposition of the insulator 212 is not limited to the sputtering method; CVD, MBE, PLD, ALD, etc., may be used as appropriate. 【0234】 In this embodiment, silicon nitride is deposited as the insulator 212 using a silicon target in a nitrogen gas-containing atmosphere by pulsed DC sputtering. By using pulsed DC sputtering, the generation of particles due to arcing on the target surface can be suppressed, resulting in a more uniform film thickness distribution. Furthermore, by using a pulsed voltage, the rise and fall of the discharge can be made steeper than with a high-frequency voltage. This allows for more efficient power supply to the electrodes, improving the sputtering rate and film quality. 【0235】 By using an insulator 212 that is impermeable to impurities such as water and hydrogen, such as silicon nitride, the diffusion of impurities such as water and hydrogen contained in the layer below the insulator 212 can be suppressed. Furthermore, by using an insulator 212 that is impermeable to copper, such as silicon nitride, even if a diffusive metal such as copper is used in the conductor layer below the insulator 212 (not shown), the diffusion of that metal upward through the insulator 212 can be suppressed. 【0236】 Next, an insulator 214 is deposited on the insulator 212 (see Figures 5A to 5D). The deposition of the insulator 214 is preferably carried out using a sputtering method. By using a sputtering method that does not require the use of hydrogen as the deposition gas, the hydrogen concentration in the insulator 214 can be reduced. However, the deposition of the insulator 214 is not limited to the sputtering method; CVD, MBE, PLD, ALD, etc., may be used as appropriate. 【0237】 In this embodiment, aluminum oxide is deposited as the insulator 214 using a pulsed DC sputtering method with an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. 【0238】 It is preferable to use an amorphous metal oxide, such as aluminum oxide, as the insulator 214, which has a high ability to capture and fix hydrogen. This allows for the capture or fixation of hydrogen contained in the insulator 216, etc., preventing the hydrogen from diffusing into the oxide 230. In particular, it is preferable to use amorphous aluminum oxide, or aluminum oxide with an amorphous structure, as the insulator 214, as this may allow for more effective capture or fixation of hydrogen. This makes it possible to manufacture a transistor 200 and semiconductor device with good properties and high reliability. 【0239】 Next, an insulator 216 is deposited on the insulator 214. The deposition of the insulator 216 is preferably carried out using a sputtering method. By using a sputtering method that does not require the use of hydrogen as the deposition gas, the hydrogen concentration in the insulator 216 can be reduced. However, the deposition of the insulator 216 is not limited to the sputtering method; CVD, MBE, PLD, ALD, etc., may be used as appropriate. 【0240】 In this embodiment, silicon oxide is deposited as the insulator 216 using a silicon target in an atmosphere containing oxygen gas by pulsed DC sputtering. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. 【0241】 It is preferable that the insulator 212, the insulator 214, and the insulator 216 are continuously formed without being exposed to the atmosphere. For example, a multi-chamber film forming apparatus may be used. Thereby, the insulator 212, the insulator 214, and the insulator 216 can be formed while reducing hydrogen in the film, and furthermore, it is possible to reduce the mixing of hydrogen into the film during the intervals between the respective film forming steps. 【0242】 Next, an opening reaching the insulator 214 is formed in the insulator 216. The opening includes, for example, a groove, a slit, and the like. Also, there may be a case where the opening part refers to the region where the opening is formed. The opening may be formed using wet etching, but dry etching is more preferable for microfabrication. Further, it is preferable to select the insulator 214 as an insulating film that functions as an etching stopper film when forming a groove by etching the insulator 216. For example, when silicon oxide or silicon oxynitride is used for the insulator 216 forming the groove, the insulator 214 may use silicon nitride, aluminum oxide, or hafnium oxide. 【0243】 As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having a parallel plate electrode can be used. The capacitively coupled plasma etching apparatus having a parallel plate electrode may be configured to apply a high-frequency voltage to one of the parallel plate electrodes. Or it may be configured to apply a plurality of different high-frequency voltages to one of the parallel plate electrodes. Or it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel plate electrodes. Or it may be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes. Or a dry etching apparatus having a high-density plasma source can be used. The dry etching apparatus having a high-density plasma source can use, for example, an inductively coupled plasma (ICP) etching apparatus or the like. 【0244】 After the opening is formed, a conductive film 205A is deposited (see Figures 5A to 5D). The conductive film 205A preferably contains a conductor that has the function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc., can be used. Alternatively, a laminated film can be formed of a conductor that has the function of suppressing oxygen permeation and a tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum-tungsten alloy. The conductive film 205A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. 【0245】 In this embodiment, titanium nitride is deposited as the conductive film 205A. By using such a metal nitride as a layer beneath the conductor 205b, oxidation of the conductor 205b by the insulator 216 and the like can be suppressed. Furthermore, even if a highly diffusive metal such as copper is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205a. 【0246】 Next, a conductive film 205B is deposited (see Figures 5A to 5D). As the conductive film 205B, tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum-tungsten alloy, etc., can be used. The conductive film can be deposited using methods such as plating, sputtering, CVD, MBE, PLD, and ALD. In this embodiment, tungsten is deposited as the conductive film 205B. 【0247】 Next, a CMP (Chemical Mechanical Polishing) treatment is performed to remove a portion of the conductive films 205A and 205B, exposing the insulator 216 (see Figures 6A to 6D). As a result, the conductors 205a and 205b remain only in the openings. Note that this CMP treatment may remove a portion of the insulator 216. 【0248】 Next, etching is performed to remove the upper part of the conductor 205b (see Figures 7A to 7D). As a result, the upper surface of the conductor 205b is lower than the upper surface of the conductor 205a and the upper surface of the insulator 216. Dry etching or wet etching can be used for etching the conductor 205b, but dry etching is preferable for microfabrication. 【0249】 Next, a conductive film 205C is formed on the insulator 216, conductor 205a, and conductor 205b (see Figures 8A to 8D). It is desirable that the conductive film 205C, like the conductive film 205A, contains a conductor that has the function of suppressing oxygen permeation. 【0250】 In this embodiment, titanium nitride is deposited as the conductive film 205C. By using such a metal nitride as the upper layer of the conductor 205b, oxidation of the conductor 205b by the insulator 222 and the like can be suppressed. Furthermore, even if a highly diffusive metal such as copper is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205c. 【0251】 Next, a CMP treatment is performed to remove a portion of the conductive film 205C, exposing the insulator 216 (see Figures 9A to 9D). As a result, the conductors 205a, 205b, and 205c remain only in the openings. This allows for the formation of a conductor 205 with a flat top surface. Furthermore, the conductor 205b is enclosed by the conductors 205a and 205c. Therefore, it is possible to prevent impurities such as hydrogen from conductor 205b from diffusing out of conductors 205a and 205c, and to prevent oxygen from entering from outside conductors 205a and 205c and oxidizing conductor 205b. Note that a portion of the insulator 216 may be removed during this CMP treatment. 【0252】 Next, an insulator 222 is deposited on the insulator 216 and the conductor 205 (see Figures 10A to 10D). It is preferable to deposit an insulator 222 containing an oxide of either or both aluminum and hafnium. Preferably, the insulator containing an oxide of either or both aluminum and hafnium is an aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). An insulator containing an oxide of either or both aluminum and hafnium has barrier properties against oxygen, hydrogen, and water. Because the insulator 222 has barrier properties against hydrogen and water, the diffusion of hydrogen and water contained in the structure surrounding the transistor 200 into the transistor 200 through the insulator 222 is suppressed, thereby suppressing the formation of oxygen vacancies in the oxide 230. 【0253】 The insulator 222 can be deposited using sputtering, CVD, MBE, PLD, ALD, or other methods. In this embodiment, hafnium oxide is deposited as the insulator 222 using sputtering. By using a sputtering method that does not require hydrogen as the deposition gas, the hydrogen concentration in the insulator 222 can be reduced. 【0254】 Next, it is preferable to perform a heat treatment. The heat treatment should be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas should be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then further in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen. 【0255】 Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from moisture or other substances being incorporated into the insulator 222 and the like. 【0256】 In this embodiment, as a heat treatment, after the insulator 222 is formed, a nitrogen gas to oxygen gas flow rate ratio of 4 slm:1 slm is used, and the treatment is performed at a temperature of 400°C for 1 hour. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. Furthermore, when an oxide containing hafnium is used as the insulator 222, a portion of the insulator 222 may crystallize as a result of this heat treatment. The heat treatment can also be performed at a later time, such as after the insulator 224 is formed. 【0257】 Next, an insulator 224 is deposited on the insulator 222 (see Figures 10A to 10D). The insulator 224 can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, silicon oxide is deposited as the insulator 224 using the sputtering method. By using a sputtering method that does not require the use of hydrogen as the deposition gas, the hydrogen concentration in the insulator 224 can be reduced. Since the insulator 224 will come into contact with the oxide 230a in a later step, it is preferable that the hydrogen concentration is reduced in this way. 【0258】 Here, in order to form an excess oxygen region in the insulator 224, plasma treatment containing oxygen may be performed under reduced pressure. For the plasma treatment containing oxygen, it is preferable to use a device that has a power supply that generates high-density plasma using microwaves, for example. Alternatively, the substrate side may have a power supply that applies RF (Radio Frequency). By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently guided into the insulator 224. Alternatively, after performing plasma treatment containing an inert gas using this device, plasma treatment containing oxygen may be performed to replenish the desorbed oxygen. By appropriately selecting the conditions of the plasma treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed. In that case, heating treatment does not need to be performed. 【0259】 Here, aluminum oxide may be deposited on the insulator 224, for example by sputtering, and then CMP treatment may be performed until it reaches the insulator 224. This CMP treatment can planarize and smooth the surface of the insulator 224. Placing the aluminum oxide on the insulator 224 and performing the CMP treatment makes it easier to detect the end point of the CMP treatment. In addition, the CMP treatment may polish a part of the insulator 224, causing the film thickness of the insulator 224 to become thinner, but this can be corrected by adjusting the film thickness during the deposition of the insulator 224. By planarizing and smoothing the surface of the insulator 224, it may be possible to prevent deterioration of the coverage rate of the oxide film deposited later and prevent a decrease in the yield of the semiconductor device. Furthermore, it is preferable to deposit aluminum oxide on the insulator 224 by sputtering, as this allows oxygen to be added to the insulator 224. 【0260】 Next, oxide films 230A and 230B are sequentially deposited on the insulator 224 (see Figures 10A to 10D). It is preferable to deposit oxide films 230A and 230B continuously without exposing them to the atmosphere. By depositing the films without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmosphere from adhering to oxide films 230A and 230B, and to keep the vicinity of the interface between oxide films 230A and 230B clean. 【0261】 The oxide films 230A and 230B can be deposited using sputtering, CVD, MBE, PLD, ALD, and other methods. 【0262】 For example, when depositing oxide films 230A and 230B by sputtering, oxygen or a mixture of oxygen and a noble gas is used as the sputtering gas. By increasing the proportion of oxygen in the sputtering gas, the excess oxygen in the deposited oxide film can be increased. Furthermore, when depositing the above oxide films by sputtering, the above-mentioned In-M-Zn oxide target can be used. 【0263】 In particular, during the formation of the oxide film 230A, some of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas should be 70% or more, preferably 80% or more, and more preferably 100%. 【0264】 Furthermore, when the oxide film 230B is formed by sputtering, if the proportion of oxygen in the sputtering gas is set to be more than 30% but 100% or less, preferably 70% or more but 100%, an oxygen-rich oxide semiconductor is formed. Transistors using an oxygen-rich oxide semiconductor in the channel formation region can achieve relatively high reliability. However, the present invention is not limited to this. When the oxide film 230B is formed by sputtering, if the proportion of oxygen in the sputtering gas is set to be 1% or more but 30% or less, preferably 5% or more but 20%, an oxygen-deficient oxide semiconductor is formed. Transistors using an oxygen-deficient oxide semiconductor in the channel formation region can achieve relatively high field-effect mobility. In addition, the crystallinity of the oxide film can be improved by performing film formation while heating the substrate. 【0265】 In this embodiment, oxide film 230A is deposited by sputtering using an oxide target with an In:Ga:Zn ratio of 1:3:4. Oxide film 230B is deposited by sputtering using an oxide target with an In:Ga:Zn ratio of 4:2:4.1. Note that each oxide film may be formed according to the desired properties of oxide 230a and oxide 230b by appropriately selecting the deposition conditions and atomic ratios. 【0266】 Next, an oxide film 243A is deposited on the oxide film 230B (see Figures 10A to 10D). The oxide film 243A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable that the atomic ratio of Ga to In in the oxide film 243A is greater than the atomic ratio of Ga to In in the oxide film 230B. In this embodiment, the oxide film 243A is deposited by sputtering using an oxide target with an atomic ratio of In:Ga:Zn = 1:3:4. 【0267】 Furthermore, it is preferable to deposit the insulator 222, insulator 224, oxide film 230A, oxide film 230B, and oxide film 243A by sputtering without exposure to the atmosphere. For example, a multi-chamber type deposition apparatus can be used. This allows for the deposition of the insulator 222, insulator 224, oxide film 230A, oxide film 230B, and oxide film 243A with reduced hydrogen content in the films, and further reduces the incorporation of hydrogen into the films between each deposition process. 【0268】 Next, it is preferable to perform a heat treatment. The heat treatment should be performed within a temperature range in which oxide films 230A, 230B, and 243A do not undergo polycrystallization, and should be performed between 250°C and 650°C, preferably between 400°C and 600°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas should be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen. 【0269】 Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from the incorporation of water and other substances into the oxide film 230A, oxide film 230B, and oxide film 243A, etc. 【0270】 In this embodiment, the heat treatment involves treating the oxide film at 550°C for 1 hour in a nitrogen atmosphere, followed by a continuous treatment at 550°C for 1 hour in an oxygen atmosphere. This heat treatment can remove impurities such as water and hydrogen from oxide films 230A, 230B, and 243A. Furthermore, this heat treatment can improve the crystallinity of oxide film 230B, resulting in a denser, more compact structure. This reduces the diffusion of oxygen or impurities within oxide film 230B. 【0271】 Next, a conductive film 242A is deposited on the oxide film 243A (see Figures 10A to 10D). The conductive film 242A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. For example, tantalum nitride can be deposited as the conductive film 242A using sputtering. Before depositing the conductive film 242A, a heat treatment may be performed. This heat treatment may be performed under reduced pressure, and the conductive film 242A may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 243A can be removed, and the moisture and hydrogen concentrations in the oxide film 230A, oxide film 230B, and oxide film 243A can be further reduced. The temperature of the heat treatment is preferably between 100°C and 400°C. In this embodiment, the temperature of the heat treatment is set to 200°C. 【0272】 Next, an insulating film 271A is deposited on the conductive film 242A (see Figures 10A to 10D). The insulating film 271A can be deposited using sputtering, CVD, MBE, PLD, or ALD. It is preferable to use an insulating film 271A that has the function of suppressing oxygen permeation. For example, aluminum oxide or silicon nitride can be deposited as the insulating film 271A by sputtering. 【0273】 Next, an insulating film 273A is deposited on the insulating film 271A (see Figures 10A to 10D). The insulating film 273A can be deposited using sputtering, CVD, MBE, PLD, or ALD. For example, silicon nitride or silicon oxide can be deposited as the insulating film 273A by sputtering. 【0274】 Furthermore, it is preferable to deposit the conductive film 242A, insulating film 271A, and insulating film 273A by sputtering without exposure to the atmosphere. For example, a multi-chamber type deposition apparatus can be used. This allows for the deposition of the conductive film 242A, insulating film 271A, and insulating film 273A with reduced hydrogen content in the films, and also reduces the incorporation of hydrogen into the films between each deposition process. In addition, if a hard mask is provided on the insulating film 273A, the film forming the hard mask can also be deposited continuously without exposure to the atmosphere. 【0275】 Next, using lithography, the oxide film 230A, oxide film 230B, oxide film 243A, conductive film 242A, insulating film 271A, and insulating film 273A are processed into island-like structures to form oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, insulating layer 271B, and insulating layer 273B (see Figures 11A to 11D). This processing can be performed using either dry etching or wet etching. Dry etching is suitable for microfabrication. Furthermore, the oxide film 230A, oxide film 230B, oxide film 243A, conductive film 242A, insulating film 271A, and insulating layer 271B may be processed under different conditions. Note that in this process, the film thickness in areas of the insulator 224 that do not overlap with oxide 230a may become thinner. Furthermore, in this process, the insulator 224 may be superimposed with the oxide 230a and processed into an island-like structure. 【0276】 In lithography, the resist is first exposed through a mask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Then, the conductor, semiconductor, or insulator can be processed into a desired shape by etching through the resist mask. For example, the resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. Alternatively, immersion technology can be used, where a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. In addition, electron beams or ion beams can be used instead of the aforementioned light. When using electron beams or ion beams, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching. 【0277】 Furthermore, a hard mask made of an insulator or conductor may be used beneath the resist mask. When using a hard mask, an insulating film or conductive film that serves as the hard mask material is formed on the conductive film 242A, a resist mask is formed on top of it, and a hard mask of the desired shape can be formed by etching the hard mask material. Etching of the conductive film 242A, etc., may be performed after removing the resist mask, or it may be performed while the resist mask remains. In the latter case, the resist mask may disappear during etching. The hard mask may also be removed by etching after etching of the conductive film 242A, etc. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask. In this embodiment, insulating layers 271B and 273B are used as hard masks. On the other hand, if insulating layer 271B functions sufficiently as a hard mask, insulating layer 273B is not necessarily required. In that case, the formation of insulating film 273A becomes unnecessary. Furthermore, when insulating layer 273B is not provided and insulating layer 271B is used as a hard mask, it is preferable to appropriately adjust the film thickness of insulating layer 271B to suppress the disappearance of insulating layer 271B during etching of conductive film 242A, etc. 【0278】 Here, the insulating layers 271B and 273B function as masks for the conductive layer 242B, so as shown in Figures 11B to 11D, the conductive layer 242B does not have a curved surface between its side and top surfaces. As a result, the conductors 242a and 242b shown in Figure 3B have angular ends where their side and top surfaces intersect. The angular shape of the ends where the side and top surfaces of the conductor 242 intersect increases the cross-sectional area of ​​the conductor 242 compared to when the ends have a curved surface. This reduces the resistance of the conductor 242, allowing the on-current of the transistor 200 to be increased. 【0279】 Furthermore, oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, insulating layer 271B, and insulating layer 273B are formed so that at least a portion of them overlaps with the conductor 205. In addition, it is preferable that the sides of oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, insulating layer 271B, and insulating layer 273B are approximately perpendicular to the upper surface of the insulator 222. By having the sides of oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, insulating layer 271B, and insulating layer 273B approximately perpendicular to the upper surface of the insulator 222, it becomes possible to reduce the area and increase the density when providing multiple transistors 200. Alternatively, the angle between the sides of oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, insulating layer 271B, and insulating layer 273B and the upper surface of insulator 222 may be low. In this case, the angle between the sides of oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, insulating layer 271B, and insulating layer 273B and the upper surface of insulator 222 is preferably 60 degrees or more and less than 70 degrees. By adopting such a shape, the coverage of insulator 272, insulator 275, etc. can be improved in subsequent processes, and defects such as porosity can be reduced. 【0280】 Furthermore, by-products generated in the etching process may form in layers on the sides of oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, insulating layer 271B, and insulating layer 273B. In this case, the layered by-products will be formed between oxide 230a, oxide 230b, oxide 243, conductor 242, insulator 271, and insulators 273 and 272. Similarly, layered by-products may also be formed on insulator 224. Even if insulator 272 is deposited with the layered by-products formed on insulator 224, the addition of oxygen to insulator 224 will be hindered by the layered by-products. Therefore, it is preferable to remove the layered by-products formed in contact with the upper surface of insulator 224. 【0281】 Next, an insulating film 272A is deposited on the insulator 224, oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, insulating layer 271B, and insulating layer 273B (see Figures 12A to 12D). The insulating film 272A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, aluminum oxide is deposited as the insulating film 272A by sputtering. 【0282】 The insulating film 272A is preferably formed using a sputtering method. By depositing the insulating film 272A using a sputtering method, oxygen can be added to the insulator 224 and the insulating layer 273B. At this time, since the insulating layer 271B is provided in contact with the upper surface of the conductive layer 242B, oxidation of the conductive layer 242B can be reduced. 【0283】 Next, an insulating film 275A is deposited on the insulating film 272A (see Figures 12A to 12D). The insulating film 275A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, silicon nitride is deposited as the insulating film 275A by sputtering. 【0284】 Next, an insulating film that will become an insulator 280 is deposited on the insulating film 275A. This insulating film can be deposited using sputtering, CVD, MBE, PLD, ALD, or the like. For example, a silicon oxide film can be deposited as the insulating film using sputtering. By depositing the insulating film that will become the insulator 280 using sputtering in an oxygen-containing atmosphere, an insulator 280 containing excess oxygen can be formed. Furthermore, by using a sputtering method that does not require the use of hydrogen as the deposition gas, the hydrogen concentration in the insulator 280 can be reduced. Note that a heat treatment may be performed before depositing the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulating film 275A can be removed, and the moisture and hydrogen concentrations in the oxide 230a, oxide 230b, oxide layer 243B, and insulator 224 can be further reduced. The heat treatment conditions described above can be used for this heat treatment. 【0285】 Next, the insulating film that will become the insulator 280 is subjected to CMP treatment to form an insulator 280 with a flat top surface (see Figures 12A to 12D). Alternatively, silicon nitride may be deposited on the insulator 280 by, for example, a sputtering method, and the silicon nitride may be subjected to CMP treatment until it reaches the insulator 280. 【0286】 Next, a portion of the insulator 280, a portion of the insulating film 275A, a portion of the insulating film 272A, a portion of the insulating layer 273B, a portion of the insulating layer 271B, a portion of the conductive layer 242B, a portion of the oxide layer 243B, and a portion of the oxide 230b are processed to form an opening that reaches the oxide 230b. It is preferable that the opening be formed so as to overlap with the conductor 205. The formation of the opening creates insulators 275a, 275b, 272a, 272b, 273a, 273b, 271a, 271b, conductors 242a, conductors 242b, oxide 243a, and oxide 243b (see Figures 13A to 13D). 【0287】 When forming the above-mentioned opening, the upper part of the oxide 230b is removed. By removing a portion of the oxide 230b, a groove is formed in the oxide 230b. Depending on the depth of the groove, the groove may be formed in the opening formation step or in a step different from the opening formation step. 【0288】 Furthermore, processing of a portion of the insulator 280, a portion of the insulating film 275A, a portion of the insulating film 272A, a portion of the insulating layer 273B, a portion of the insulating layer 271B, a portion of the conductive layer 242B, a portion of the oxide layer 243B, and a portion of the oxide 230b can be carried out using either a dry etching method or a wet etching method. Processing by dry etching is suitable for microfabrication. In addition, each of these processes may be carried out under different conditions. For example, a portion of the insulator 280 may be processed by dry etching, a portion of the insulating film 275A, a portion of the insulating film 272A, a portion of the insulating layer 273B, and a portion of the insulating layer 271B may be processed by wet etching, and a portion of the oxide layer 243B, a portion of the conductive layer 242B, and a portion of the oxide 230b may be processed by dry etching. Also, the processing of a portion of the oxide layer 243B and a portion of the conductive layer 242B and the processing of a portion of the oxide 230b may be carried out under different conditions. 【0289】 Here, it is preferable to remove impurities that have adhered to or diffused into the surface of oxide 230a, oxide 230b, etc. It is also preferable to remove damaged areas formed on the surface of oxide 230b by the dry etching described above. Examples of such impurities include those resulting from components contained in insulator 280, part of insulating film 275A, part of insulating film 272A, part of insulating layer 273B, part of insulating layer 271B, and conductive layer 242B, components contained in materials used in the apparatus used to form the above-mentioned openings, and components contained in the gas or liquid used for etching. Examples of such impurities include aluminum, silicon, tantalum, fluorine, and chlorine. 【0290】 In particular, impurities such as aluminum or silicon inhibit the CAAC-OS conversion of oxide 230b. Therefore, it is preferable that impurity elements that inhibit CAAC-OS conversion, such as aluminum or silicon, are reduced or removed. For example, the concentration of aluminum atoms in oxide 230b and its vicinity should be 5.0 atomic% or less, preferably 2.0 atomic% or less, more preferably 1.5 atomic% or less, even more preferably 1.0 atomic% or less, and even more preferably less than 0.3 atomic%. 【0291】 Furthermore, the region of a metal oxide where CAAC-OS formation is inhibited by impurities such as aluminum or silicon, resulting in a pseudo-amorphous-like oxide semiconductor (a-like OS), is sometimes called the non-CAAC region. In the non-CAAC region, the density of the crystal structure is reduced, therefore V O A large amount of H is formed, making it easier for the transistor to become normally-on. Therefore, it is preferable that the non-CAAC region of oxide 230b is reduced or removed. 【0292】 In contrast, it is preferable that the oxide 230b has a layered CAAC structure. In particular, it is preferable that the CAAC structure extends to the lower end of the drain of the oxide 230b. Here, in the transistor 200, the conductor 242a or conductor 242b, and its vicinity, function as a drain. That is, it is preferable that the oxide 230b near the lower end of the conductor 242a (conductor 242b) has a CAAC structure. In this way, even at the drain end, which significantly affects the drain breakdown voltage, the damaged region of the oxide 230b is removed and a CAAC structure is present, which further suppresses fluctuations in the electrical characteristics of the transistor 200. Furthermore, the reliability of the transistor 200 can be improved. 【0293】 To remove the impurities mentioned above, a cleaning process is performed. Cleaning methods include wet cleaning using a cleaning solution, plasma treatment using plasma, and heat treatment. These cleaning methods may be combined as appropriate. Note that the grooves may become deeper as a result of this cleaning process. 【0294】 For wet cleaning, cleaning may be performed using aqueous solutions of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, etc., diluted with carbonated water or distilled water, distilled water, carbonated water, etc. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, distilled water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate. 【0295】 In this specification, an aqueous solution obtained by diluting commercially available hydrofluoric acid with pure water may be referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting commercially available ammonia water with pure water may be referred to as diluted ammonia water. The concentration and temperature of the aqueous solution may be adjusted as appropriate depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water should be 0.01% to 5%, preferably 0.1% to 0.5%. The hydrogen fluoride concentration of the diluted hydrofluoric acid should be 0.01 ppm to 100 ppm, preferably 0.1 ppm to 10 ppm. 【0296】 Furthermore, it is preferable to use a frequency of 200 kHz or higher, preferably 900 kHz or higher, for ultrasonic cleaning. Using this frequency can reduce damage to oxides such as 230b. 【0297】 Furthermore, the above cleaning process may be performed multiple times, and the cleaning solution may be changed each time. For example, the first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and the second cleaning process may be performed using pure water or carbonated water. 【0298】 In this embodiment, the cleaning process involves wet cleaning using diluted hydrofluoric acid, followed by wet cleaning using pure water or carbonated water. This cleaning process removes impurities that have adhered to the surface or diffused into the interior of oxides 230a and 230b. Furthermore, it can improve the crystallinity of oxide 230b. 【0299】 Previously, due to processes such as dry etching or the cleaning treatment described above, the film thickness of the insulator 224 in the region that overlaps with the opening and does not overlap with the oxide 230b may become thinner than the film thickness of the insulator 224 in the region that overlaps with the oxide 230b. 【0300】 Heat treatment may be performed after etching or cleaning as described above. The heat treatment should be performed at a temperature of 100°C to 450°C, preferably 350°C to 400°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This supplies oxygen to oxides 230a and 230b, thereby eliminating oxygen deficiency V O This can reduce the amount of waste. Furthermore, this heat treatment can improve the crystallinity of oxide 230b. The heat treatment may also be carried out under reduced pressure. Alternatively, the heat treatment may be performed in an oxygen atmosphere, followed by continuous heat treatment in a nitrogen atmosphere without exposure to the atmosphere. 【0301】 Next, insulating film 250A (insulating film 250Aa and insulating film 250Ab) is deposited (see Figures 14A to 14D). A heat treatment may be performed before depositing insulating film 250Aa, and this heat treatment may be carried out under reduced pressure, allowing for continuous deposition of insulating film 250Aa without exposure to the atmosphere. Furthermore, it is preferable to carry out this heat treatment in an atmosphere containing oxygen. By performing such a treatment, moisture and hydrogen adsorbed on the surface of oxide 230b can be removed, and the moisture and hydrogen concentrations in oxide 230a and oxide 230b can be further reduced. The temperature of the heat treatment is preferably between 100°C and 400°C. 【0302】 The insulating film 250Aa can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD. Furthermore, it is preferable to deposit the insulating film 250A using a deposition method that utilizes a gas with reduced or removed hydrogen atoms. This allows for a reduction in the hydrogen concentration of the insulating film 250Aa. Since the insulating film 250Aa will become an insulator 250a that comes into contact with the oxide 230b in a later step, such a reduction in hydrogen concentration is preferable. 【0303】 Furthermore, it is preferable to deposit the insulating film 250Aa using the ALD method. The thickness of the insulator 250, which functions as the gate insulating film of the miniaturized transistor 200, needs to be extremely thin (for example, about 5 nm to 30 nm) and have minimal variation. In contrast, the ALD method is a film deposition method that alternately introduces a precursor and a reactant (oxidizing agent), and the film thickness can be adjusted by the number of times this cycle is repeated, thus enabling precise film thickness adjustment. Therefore, the accuracy of the gate insulating film required by the miniaturized transistor 200 can be achieved. Also, as shown in Figures 14B and 14C, the insulating film 250Aa needs to be deposited with good coverage on the bottom and side surfaces of the opening formed by the insulator 280, etc. Since atomic layers can be deposited one by one on the bottom and side surfaces of the opening, the insulating film 250Aa can be deposited with good coverage on the opening. 【0304】 Furthermore, for example, when depositing an insulating film 250Aa using the PECVD method, the hydrogen-containing deposition gas is decomposed in the plasma, generating a large amount of hydrogen radicals. The reduction reaction of the hydrogen radicals extracts oxygen from the oxide 230b, resulting in V OWhen H is formed, the hydrogen concentration in oxide 230b increases. However, by depositing the insulating film 250Aa using the ALD method, the generation of hydrogen radicals can be suppressed both when the precursor is introduced and when the reactant is introduced. Therefore, by depositing the insulating film 250Aa using the ALD method, it is possible to prevent the hydrogen concentration in oxide 230b from increasing. 【0305】 Preferably, the insulating film 250Aa is formed using an insulator that releases oxygen upon heating, and the insulating film 250Ab is formed using an insulator that has the function of suppressing oxygen diffusion. With this configuration, the diffusion of oxygen contained in the insulator 250a to the conductor 260 can be suppressed. In other words, the reduction in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 by oxygen contained in the insulator 250a can be suppressed. 【0306】 Specifically, as the insulating film 250Ab, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or metal oxides that can be used as oxide 230 can be used. In particular, it is preferable to use an insulator containing oxides of aluminum and hafnium, or both. 【0307】 In this embodiment, silicon oxide is deposited as insulating film 250Aa by the PEALD method, and hafnium oxide is deposited as insulating film 250Ab by the thermal ALD method. 【0308】 Next, microwave treatment is performed in an oxygen-containing atmosphere (see FIGS. 14A to 14D). Here, the dotted lines shown in FIGS. 14B to 14D indicate microwaves, high-frequency waves such as RF, oxygen plasma, or oxygen radicals. For the microwave treatment, it is preferable to use a microwave treatment apparatus having a power source for generating high-density plasma using microwaves. Further, the microwave treatment apparatus may have a power source for applying RF to the substrate side. By using high-density plasma, high-density oxygen radicals can be generated. Further, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently introduced into the oxide 230b. Further, the above microwave treatment is preferably performed under reduced pressure, and the pressure may be 60 Pa or more, preferably 133 Pa or more, more preferably 200 Pa or more, and still more preferably 400 Pa or more. Further, the oxygen flow rate ratio (O2 / O2+Ar) is preferably 50% or less, preferably 10% or more and 30% or less. Further, the treatment temperature may be 750° C. or less, preferably 500° C. or less, for example, about 400° C. Further, after the oxygen plasma treatment, heat treatment may be continuously performed without exposing to the outside air. 【0309】 As shown in FIGS. 14B to 14D, by performing microwave treatment in an oxygen-containing atmosphere, oxygen gas can be plasmaized using microwaves or high-frequency waves such as RF, and the oxygen plasma can be made to act on the region between the conductors 242a and 242b of the oxide 230b. At this time, microwaves or high-frequency waves such as RF can also be irradiated to the region 230bc shown in FIG. 2. That is, microwaves, high-frequency waves such as RF, oxygen plasma, etc. can be made to act on the region 230bc. By the action of plasma, microwaves, etc., the V O H is divided, and hydrogen H can be removed from the region 230bc. That is, in the region 230bc, the reaction of "V O H→H+V O " occurs, and the hydrogen concentration in the region 230bc can be reduced. Therefore, the oxygen deficiency in the region 230bc and V OBy reducing H, the carrier concentration can be lowered. Furthermore, by supplying oxygen radicals generated in the oxygen plasma or oxygen contained in the insulator 250 to the oxygen vacancy formed in region 230bc, the oxygen vacancy in region 230bc can be further reduced, and the carrier concentration can be lowered. 【0310】 On the other hand, conductors 242a and 242b are provided on regions 230ba and 230bb shown in Figure 2. As shown in Figures 14B, 14C, and 14D, conductors 242a and 242b shield against the effects of microwaves, high-frequency waves such as RF, and oxygen plasma, so these effects do not extend to regions 230ba and 230bb. As a result, microwave processing does not cause V O This prevents a decrease in H and avoids excessive oxygen supply, thus preventing a drop in carrier concentration. 【0311】 In this way, oxygen vacancies are selectively created in the oxide semiconductor region 230bc, and V O By removing H, region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to regions 230ba and 230bb, which function as source or drain regions, can be suppressed, thereby maintaining the n-type configuration. This suppresses variations in the electrical properties of transistor 200 and prevents variations in the electrical properties of transistor 200 within the substrate plane. 【0312】 Therefore, it is possible to provide a semiconductor device with less variation in transistor characteristics. Furthermore, it is possible to provide a semiconductor device with good reliability. Additionally, it is possible to provide a semiconductor device with good electrical characteristics. 【0313】 In the process shown in Figures 14A to 14D, microwave treatment was performed after the deposition of the insulating film 250Ab, but the present invention is not limited thereto. For example, microwave treatment may be performed after the deposition of the insulating film 250Aa, or before the deposition of the insulating film 250Aa, or both before the deposition of the insulating film 250Aa and after the deposition of the insulating film 250Ab, or both after the deposition of the insulating film 250Aa and after the deposition of the insulating film 250Ab. 【0314】 Furthermore, when the insulating film 250A has the two-layer structure described above, microwave treatment can be performed to deposit silicon oxide for insulating film 250Aa using the PEALD method, and hafnium oxide for insulating film 250Ab using the thermal ALD method. Here, it is preferable to perform the microwave treatment, PEALD deposition of silicon oxide, and thermal ALD deposition of hafnium oxide continuously without exposure to the atmosphere. For example, a multi-chamber type processing apparatus can be used. Alternatively, the microwave treatment may be replaced with the treatment of plasma-excited reactant (oxidizing agent) in a PEALD apparatus. Here, oxygen gas can be used as the reactant (oxidizing agent). 【0315】 Alternatively, a heat treatment may be performed while maintaining a reduced pressure state after microwave treatment. By performing such a treatment, hydrogen can be efficiently removed from the insulating film 250A, oxide 230b, and oxide 230a. In addition, some of the hydrogen may be gettered by the conductor 242 (conductor 242a and conductor 242b). Alternatively, the step of performing a heat treatment while maintaining a reduced pressure state after microwave treatment may be repeated multiple times. By repeating the heat treatment, hydrogen can be removed even more efficiently from the insulating film 250A, oxide 230b, and oxide 230a. The heat treatment temperature is preferably 300°C to 500°C. 【0316】 Furthermore, by modifying the film quality of the insulating film 250A through microwave treatment, the diffusion of hydrogen, water, impurities, etc. can be suppressed. Therefore, in subsequent processes such as deposition of a conductive film that becomes the conductor 260, or post-treatment such as heat treatment, the diffusion of hydrogen, water, impurities, etc., into oxides 230b, oxides 230a, etc., through the insulator 250 can be suppressed. 【0317】 Next, a conductive film to become conductor 260a and a conductive film to become conductor 260b are deposited in sequence. The conductive films to become conductor 260a and conductor 260b can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, the conductive film to become conductor 260a is deposited using the ALD method, and the conductive film to become conductor 260b is deposited using the CVD method. 【0318】 Next, by CMP treatment, the insulating film 250A, the conductive film that will become the conductor 260a, and the conductive film that will become the conductor 260b are polished until the insulator 280 is exposed, thereby forming the insulator 250 (insulator 250a and insulator 250b) and the conductor 260 (conductor 260a and conductor 260b) (see Figures 15A to 15D). As a result, the insulator 250 is positioned to cover the openings that reach the oxide 230b and the inner walls (side walls and bottom surface) of the grooves in the oxide 230b. The conductor 260 is positioned to fill the openings and grooves via the insulator 250. 【0319】 Next, a portion of insulator 280, a portion of insulator 275b, a portion of insulator 272b, a portion of insulator 273b, and a portion of insulator 271b are processed to form an opening that reaches the conductor 242b (see Figures 16A to 16D). The processing of a portion of insulator 280, a portion of insulator 275b, a portion of insulator 272b, a portion of insulator 273b, and a portion of insulator 271b can be performed using either a dry etching method or a wet etching method. Dry etching is suitable for microfabrication. Furthermore, the processing may be performed under different conditions. For example, a portion of insulator 280 may be processed using the dry etching method, while a portion of insulator 275b, a portion of insulator 272b, a portion of insulator 273b, and a portion of insulator 271b may be processed using the wet etching method. 【0320】 Next, an insulating film 293A is deposited (see Figures 17A to 17D). The insulating film 293A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. Examples of insulating films 293A include gallium oxide, hafnium oxide, zirconium oxide, aluminum oxide, aluminum oxide nitride, aluminum nitride, hafnium oxide nitride, hafnium nitride, oxides containing aluminum and hafnium, oxides containing aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and hafnium, or nitrides containing silicon and hafnium. Alternatively, a laminate of these films may be used as the insulating film 293A. In this embodiment, an insulating film 293A is used in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in that order. 【0321】 Next, the conductive film 294A is deposited (see Figures 17A to 17D). The conductive film 294A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, the lower layer of the conductive film 294A is deposited using the ALD method, and the upper layer of the conductive film 294A is deposited using the CVD method. 【0322】 Next, the insulating film 293A and the conductive film 294A are polished by CMP treatment until the insulator 280 is exposed, thereby forming the insulator 293 and the conductor 294 (see Figures 18A to 18D). As a result, the insulator 293 is positioned to cover the inner walls (side walls and bottom surface) of the groove of the opening that reaches the conductor 242. The conductor 294 is positioned to fill the opening and the groove via the insulator 293. 【0323】 Next, a heat treatment may be performed under the same conditions as the heat treatment described above. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400°C for 1 hour. This heat treatment can reduce the moisture concentration and hydrogen concentration in the insulators 250, 293, and 280. After the heat treatment, the film deposition of the insulator 282 may be carried out continuously without exposure to the atmosphere. 【0324】 Next, an insulator 282 is formed on the insulator 250, the conductor 260, the insulator 293, the conductor 294, and the insulator 280 (see Figures 19A to 19D). The insulator 282 can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable to deposit the insulator 282 using sputtering. By using a sputtering method that does not require the use of hydrogen as the deposition gas, the hydrogen concentration in the insulator 282 can be reduced. Furthermore, by depositing the insulator 282 in an oxygen-containing atmosphere using sputtering, oxygen can be added to the insulator 280 while the film is being deposited. This allows the insulator 280 to contain excess oxygen. At this time, it is preferable to deposit the insulator 282 while heating the substrate. 【0325】 In this embodiment, aluminum oxide is deposited as the insulator 282 using a pulsed DC sputtering method with an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. 【0326】 Next, a portion of insulator 282, a portion of insulator 280, a portion of insulator 275, a portion of insulator 272, a portion of insulator 224, a portion of insulator 222, and a portion of insulator 216 are processed to form an opening that reaches insulator 214 (see Figures 20A to 20D). The opening may be formed to surround transistor 200 and capacitive element 292. Alternatively, the opening may be formed to surround multiple transistors 200 and multiple capacitive elements 292. Thus, a portion of the side surface of insulator 282, a portion of the side surface of insulator 280, a portion of the side surface of insulator 275, a portion of the side surface of insulator 272, a portion of the side surface of insulator 224, a portion of the side surface of insulator 222, and a portion of the side surface of insulator 216 are exposed in the opening. 【0327】 The processing of parts of insulator 282, insulator 280, insulator 275, insulator 272, insulator 224, insulator 222, and insulator 216 can be carried out by dry etching or wet etching. Dry etching is suitable for microfabrication. Furthermore, these processes may be carried out under different conditions. Note that in this process, the film thickness of the region of insulator 214 that overlaps with the above-mentioned opening may become thinner. 【0328】 Next, the insulators 282, 280, 275, 272, 224, 222, and 216 are covered to form the insulator 284 (see Figures 21B to 21D). It is preferable to form the insulator 284 using the same conditions as for the insulator 282. For example, the film deposition of the insulator 284 can be carried out using sputtering, CVD, MBE, PLD, ALD, etc. 【0329】 Specifically, for the insulator 284, it is preferable to deposit aluminum oxide by sputtering, for example. By depositing the insulator 284 in an oxygen-containing atmosphere using the sputtering method, oxygen can be added to the insulator 280 while the film is being deposited. At this time, it is preferable to deposit the insulator 284 while heating the substrate. Furthermore, since the insulator 282 is formed in contact with the upper surface of the conductor 260 and the upper surface of the conductor 294, it is possible to suppress the absorption of oxygen contained in the insulator 280 into the conductor 260 and the conductor 294 during the film deposition process of the insulator 284. As shown in Figures 21B to 21D, the insulator 284 is in contact with the insulator 214 at the bottom surface of the opening. In other words, the transistor 200 and the capacitive element 292 are enclosed on the top and sides by the insulator 284 and on the bottom by the insulator 214. 【0330】 Next, an insulator 283 is formed on the insulator 284 (see Figures 21B to 21D). The insulator 283 can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. The insulator 283 may also be multilayered. For example, silicon nitride may be deposited using sputtering, and then silicon nitride may be deposited on the silicon nitride using CVD. As shown in Figures 21B to 21D, the insulator 283 is configured to enclose the insulator 284. In this way, by enclosing the transistor 200 and the capacitive element 292 with the highly barrier insulators 283, 284, and 214, it is possible to prevent moisture and hydrogen from entering from the outside. 【0331】 Next, an insulating film, which will become an insulating film 274, is deposited on the insulating film 284. This insulating film can be deposited using sputtering, CVD, MBE, PLD, ALD, or the like. For example, silicon oxide can be deposited using the CVD method. Furthermore, it is preferable to deposit this insulating film using a deposition method that uses a gas in which hydrogen atoms have been reduced or removed. This makes it possible to reduce the hydrogen concentration of the insulating film. 【0332】 Next, the insulating film that will become the insulator 274 is subjected to CMP treatment to form an insulator 274 with a flat top surface (see Figures 22B to 22D). 【0333】 Next, a heat treatment may be performed. In this embodiment, the treatment is carried out at a temperature of 400°C for 1 hour in a nitrogen atmosphere. This heat treatment allows the oxygen added by the formation of the insulator 282 to diffuse into the insulators 280 and 250, as shown in Figure 2, and selectively supply it to the channel formation region of the oxide 230. Note that this heat treatment may be performed not only after the formation of the insulator 274, but also after the formation of the insulator 282, after the formation of the insulator 284, etc. 【0334】 Next, openings reaching the conductor 242 are formed in insulators 271a, 273a, 272a, 275a, 280, 282, 284, 283, and 274. In addition, openings reaching the conductor 294 are formed in insulators 282, 284, 283, and 274 (see Figures 22A, 22B, and 22D). These openings may be formed using lithography. Note that in Figure 22A, the shape of the opening is circular in a top view, but it is not limited to this. For example, the opening may be approximately circular, such as an ellipse, polygonal, such as a quadrilateral, or a polygonal shape with rounded corners, such as a quadrilateral, in a top view. 【0335】 Next, an insulating film to form the insulator 241 is deposited, and the insulating film is anisotropically etched to form the insulator 241. (See Figures 22A, 22B, and 22D.) The insulating film to form the insulator 241 can be deposited using sputtering, CVD, MBE, PLD, or ALD. It is preferable to use an insulating film that has the function of suppressing oxygen permeation as the insulating film to form the insulator 241. For example, it is preferable to deposit aluminum oxide using the ALD method. Alternatively, it is preferable to deposit silicon nitride using the PEALD method. Silicon nitride is preferred because it has high blocking properties for hydrogen. 【0336】 Furthermore, for the anisotropic etching of the insulating film that will become the insulator 241, a dry etching method, for example, can be used. By providing the insulator 241 on the side walls of the opening, the permeation of oxygen from the outside can be suppressed, and oxidation of the conductors 240a and 240b that will be formed next can be prevented. In addition, it is possible to prevent impurities such as water and hydrogen from diffusing to the outside from the conductors 240a and 240b. 【0337】 Next, conductive films that will become conductor 240a and conductor 240b are deposited. It is desirable that the conductive films that will become conductor 240a and conductor 240b have a laminated structure containing a conductor that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, a laminate of tantalum nitride, titanium nitride, etc., and tungsten, molybdenum, copper, etc., can be formed. The conductive film that will become conductor 240 can be deposited using sputtering, CVD, MBE, PLD, or ALD methods. 【0338】 Next, by performing a CMP treatment, a portion of the conductive film that will become conductors 240a and 240b is removed, exposing the upper surface of the insulator 274. As a result, the conductive film remains only in the openings, making it possible to form conductors 240a and 240b with flat upper surfaces (see Figures 22A, 22B, and 22D). Note that this CMP treatment may remove a portion of the upper surface of the insulator 274. 【0339】 Next, a conductive film to become conductor 246 is deposited. The conductive film to become conductor 246 can be deposited using methods such as sputtering, CVD, MBE, PLD, or ALD. 【0340】 Next, the conductive film that will become the conductor 246 is processed by lithography to form conductor 246a that contacts the upper surface of conductor 240a, and conductor 246b that contacts the upper surface of conductor 240b. At this time, a portion of the insulator 274 in the region where the conductors 246a and 246b do not overlap with the insulator 274 may be removed (see Figures 3A, 3B, and 3D). 【0341】 Next, an insulator 286 is deposited on the conductor 246 and the insulator 274 (see Figures 3B to 3D). The insulator 286 can be deposited using sputtering, CVD, MBE, PLD, or ALD. The insulator 286 may also be multilayered. For example, silicon nitride may be deposited using sputtering, and then silicon nitride may be deposited on top of the silicon nitride using CVD. 【0342】 Based on the above, a semiconductor device having the transistor 200 and the capacitive element 292 shown in Figures 3A to 3D can be fabricated. 【0343】 <Microwave Processing Equipment> The following describes a microwave processing apparatus that can be used in the manufacturing method of the semiconductor device described above. 【0344】 First, we will explain the configuration of a manufacturing equipment that minimizes the inclusion of impurities during the manufacturing of semiconductor devices and other equipment, using Figures 23, 24, and 25. 【0345】 Figure 23 schematically shows a top view of a single-wafer multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 includes an atmospheric substrate supply chamber 2701 equipped with a cassette port 2761 for housing substrates and an alignment port 2762 for aligning substrates; an atmospheric substrate transport chamber 2702 for transporting substrates from the atmospheric substrate supply chamber 2701; a load lock chamber 2703a for loading substrates and switching the pressure inside the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure; an unload lock chamber 2703b for unloading substrates and switching the pressure inside the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure; a transport chamber 2704 for transporting substrates in a vacuum; and chambers 2706a, 2706b, 2706c, and 2706d. 【0346】 In addition, the atmospheric-side substrate transfer chamber 2702 is connected to the load lock chamber 2703a and the unload lock chamber 2703b. The load lock chamber 2703a and the unload lock chamber 2703b are connected to the transfer chamber 2704, and the transfer chamber 2704 is connected to the chambers 2706a, 2706b, 2706c, and 2706d. 【0347】 Note that gate valves GV are provided at the connection parts of each chamber. Except for the atmospheric-side substrate supply chamber 2701 and the atmospheric-side substrate transfer chamber 2702, each chamber can be independently maintained in a vacuum state. In addition, a transfer robot 2763a is provided in the atmospheric-side substrate transfer chamber 2702, and a transfer robot 2763b is provided in the transfer chamber 2704. The substrate can be transferred within the manufacturing apparatus 2700 by the transfer robot 2763a and the transfer robot 2763b. 【0348】 The back pressure (total pressure) of the transfer chamber 2704 and each chamber is, for example, 1×10 -4 Pa or less, preferably 3×10 -5 Pa or less, and more preferably 1×10 -5 Pa or less. Also, the partial pressure of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 18 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, and more preferably 3×10 -6 Pa or less. Also, the partial pressure of gas molecules (atoms) with an m / z of 28 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, and more preferably 3×10 -6 Pa or less. Also, the partial pressure of gas molecules (atoms) with an m / z of 44 in the transfer chamber 2704 and each chamber is, for example, 3×10<00​​​​​​​​The total pressure and partial pressure in the transport chamber 2704 and each chamber can be measured using a mass spectrometer. For example, a quadrupole mass spectrometer (also known as Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc. can be used. 【0350】 Furthermore, it is desirable that the transport chamber 2704 and each chamber be configured to minimize external or internal leaks. For example, the leak rate of the transport chamber 2704 and each chamber should be 3 × 10⁻⁶. -6 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 The rate should be less than or equal to / s. Also, for example, the leak rate of a gas molecule (atom) with m / z 18 is 1 × 10⁻⁶. -7 Pa·m 3 / s or less, preferably 3 × 10 -8 Pa·m 3 The rate should be less than or equal to / s. Also, for example, the leak rate of a gas molecule (atom) with m / z 28 is 1 × 10⁻⁶. -5 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 The rate should be less than or equal to / s. Also, for example, the leak rate of a gas molecule (atom) with m / z 44 is 3 × 10⁻⁶. -6 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 Set to / s or less. 【0351】 The leak rate can be derived from the total pressure and partial pressure measured using the mass spectrometer mentioned above. The leak rate depends on both external and internal leaks. External leaks are caused by gas flowing in from outside the vacuum system through tiny holes or faulty seals. Internal leaks are caused by leaks from valves and other partitions within the vacuum system, or by gases released from internal components. To keep the leak rate below the values ​​mentioned above, countermeasures must be taken from both external and internal leaks. 【0352】 For example, the opening and closing parts of the conveying chamber 2704 and each chamber may be sealed with metal gaskets. Preferably, the metal gaskets are made of metal coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets offer better adhesion than O-rings, reducing external leakage. Furthermore, using a passivated metal coated with iron fluoride, aluminum oxide, or chromium oxide suppresses the release of impurity-containing gases from the metal gasket, thereby reducing internal leakage. 【0353】 Furthermore, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which emit less gas containing impurities, are used as components of the manufacturing apparatus 2700. Alternatively, the aforementioned components may be coated with an alloy containing iron, chromium, and nickel. Alloys containing iron, chromium, and nickel are rigid, heat-resistant, and suitable for processing. Here, reducing the surface area by reducing surface irregularities of the components through polishing or other means can reduce the amount of gas emitted. 【0354】 Alternatively, the components of the aforementioned manufacturing apparatus 2700 may be coated with iron fluoride, aluminum oxide, chromium oxide, or the like. 【0355】 The components of the manufacturing apparatus 2700 are preferably made of metal as much as possible. For example, when installing viewing windows made of quartz or the like, it is advisable to thinly coat the surface with iron fluoride, aluminum oxide, chromium oxide, etc., to suppress the release of gases. 【0356】 The adsorbed substances present in the transport chamber 2704 and each chamber do not affect the pressure in the transport chamber 2704 and each chamber because they are adsorbed onto the inner walls, but they cause gas release when the transport chamber 2704 and each chamber are evacuated. Therefore, although there is no correlation between the leak rate and the exhaust rate, it is important to use a pump with high exhaust capacity to desorb as much of the adsorbed substances present in the transport chamber 2704 and each chamber as possible and evacuate them in advance. In addition, the transport chamber 2704 and each chamber may be baked to promote the desorption of adsorbed substances. Baking can increase the desorption rate of adsorbed substances by about 10 times. Baking should be performed at a temperature between 100°C and 450°C. At this time, if the adsorbed substances are removed while introducing an inert gas into the transport chamber 2704 and each chamber, the desorption rate of water and other substances that are difficult to desorb by exhaust alone can be further increased. In addition, the desorption rate of adsorbed substances can be further increased by heating the introduced inert gas to approximately the same temperature as the baking temperature. It is preferable to use a noble gas as the inert gas here. 【0357】 Alternatively, it is preferable to increase the pressure in the transport chamber 2704 and each chamber by introducing an inert gas such as a heated noble gas or oxygen, and then exhaust the transport chamber 2704 and each chamber again after a certain period of time. By introducing a heated gas, adsorbed substances can be removed from the transport chamber 2704 and each chamber, thereby reducing the amount of impurities present in the transport chamber 2704 and each chamber. This process is most effective when repeated 2 to 30 times, preferably 5 to 15 times. Specifically, the pressure in the transport chamber 2704 and each chamber can be increased to 0.1 Pa to 10 kPa, preferably 1 Pa to 1 kPa, and more preferably 5 Pa to 100 Pa by introducing an inert gas or oxygen with a temperature of 40°C to 400°C, preferably 50°C to 200°C, and the pressure can be maintained for 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. Subsequently, the transport chamber 2704 and each chamber are evacuated for a period of 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes. 【0358】 Next, chambers 2706b and 2706c will be described using the schematic cross-sectional diagrams shown in Figure 24. 【0359】 Chambers 2706b and 2706c are chambers capable of performing microwave processing on an object to be processed. The only difference between chambers 2706b and 2706c is the atmosphere used during microwave processing. Other configurations are common to both chambers, and will therefore be described together below. 【0360】 Chambers 2706b and 2706c each have a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. Outside chambers 2706b and 2706c are a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high-frequency power supply 2816, a vacuum pump 2817, and a valve 2818. 【0361】 The high-frequency generator 2803 is connected to the mode converter 2805 via a waveguide 2804. The mode converter 2805 is connected to the slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 is positioned in contact with the dielectric plate 2809. The gas supply source 2801 is connected to the mode converter 2805 via a valve 2802. Gas is then supplied to chambers 2706b and 2706c through a gas pipe 2806 that passes through the mode converter 2805, waveguide 2807, and dielectric plate 2809. The vacuum pump 2817 has the function of exhausting gas and other substances from chambers 2706b and 2706c via a valve 2818 and an exhaust port 2819. The high-frequency power supply 2816 is connected to the substrate holder 2812 via a matching box 2815. 【0362】 The substrate holder 2812 has the function of holding the substrate 2811. For example, the substrate holder 2812 has the function of electrostatically or mechanically chucking the substrate 2811. The substrate holder 2812 also functions as an electrode to which power is supplied from the high-frequency power supply 2816. Furthermore, the substrate holder 2812 has an internal heating mechanism 2813 and has the function of heating the substrate 2811. 【0363】 As the vacuum pump 2817, for example, a dry pump, mechanical booster pump, ion pump, titanium sublimation pump, cryopump, or turbomolecular pump can be used. In addition to the vacuum pump 2817, a cryotrap may also be used. Using a cryopump and cryotrap is particularly preferable because it allows for efficient water removal. 【0364】 Furthermore, the heating mechanism 2813 may be, for example, a heating mechanism that uses a resistance heating element. Alternatively, it may be a heating mechanism that heats by heat conduction or thermal radiation from a heated medium such as a gas. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA performs heat treatment using a high-temperature gas. An inert gas is used as the gas. 【0365】 Furthermore, the gas supply source 2801 may be connected to the purifier via a mass flow controller. It is preferable to use a gas with a dew point of -80°C or lower, preferably -100°C or lower. For example, oxygen gas, nitrogen gas, and noble gases (such as argon gas) may be used. 【0366】 For example, silicon oxide (quartz), aluminum oxide (alumina), or yttrium oxide (yttria) may be used as the dielectric plate 2809. Furthermore, another protective layer may be formed on the surface of the dielectric plate 2809. The protective layer may be made of magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide. Since the dielectric plate 2809 will be exposed to particularly high-density regions of the high-density plasma 2810 described later, providing a protective layer can mitigate damage. As a result, an increase in particles during processing can be suppressed. 【0367】 The high-frequency generator 2803 has the function of generating microwaves in frequencies such as 0.3 GHz to 3.0 GHz, 0.7 GHz to 1.1 GHz, or 2.2 GHz to 2.8 GHz. The microwaves generated by the high-frequency generator 2803 are transmitted to the mode converter 2805 via the waveguide 2804. In the mode converter 2805, the microwaves transmitted as TE mode are converted to TEM mode. The microwaves are then transmitted to the slot antenna plate 2808 via the waveguide 2807. The slot antenna plate 2808 is provided with multiple slot holes, and the microwaves pass through these slot holes and the dielectric plate 2809. This generates an electric field below the dielectric plate 2809, thereby generating a high-density plasma 2810. The high-density plasma 2810 contains ions and radicals depending on the type of gas supplied from the gas supply source 2801. For example, oxygen radicals are present. 【0368】 At this time, the substrate 2811 can be modified by ions and radicals generated in the high-density plasma 2810, which can alter films and other structures on the substrate 2811. It is preferable to apply a bias to the substrate 2811 using a high-frequency power supply 2816. For example, an RF (Radio Frequency) power supply with frequencies such as 13.56 MHz or 27.12 MHz can be used as the high-frequency power supply 2816. By applying a bias to the substrate, ions in the high-density plasma 2810 can efficiently reach deep into the openings of films and other structures on the substrate 2811. 【0369】 For example, oxygen radical treatment using high-density plasma 2810 can be performed by introducing oxygen from gas supply source 2801 in chamber 2706b or chamber 2706c. 【0370】 Next, chambers 2706a and 2706d will be explained using the schematic cross-sectional diagrams shown in Figure 25. 【0371】 Chambers 2706a and 2706d are chambers capable of irradiating the workpiece with electromagnetic waves, for example. The only difference between chambers 2706a and 2706d is the type of electromagnetic wave they emit. Since many other components are common to both, they will be described together below. 【0372】 Chambers 2706a and 2706d each have one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust port 2830. Outside chambers 2706a and 2706d, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided. 【0373】 The gas supply source 2821 is connected to the gas inlet 2823 via valve 2822. The vacuum pump 2828 is connected to the exhaust port 2830 via valve 2829. The lamp 2820 is positioned opposite the substrate holder 2825. The substrate holder 2825 has the function of holding the substrate 2824. The substrate holder 2825 also has an internal heating mechanism 2826 that has the function of heating the substrate 2824. 【0374】 For lamp 2820, any light source having the function of emitting electromagnetic waves such as infrared light, visible light, or ultraviolet light may be used. For example, any light source having the function of emitting electromagnetic waves with peaks in wavelengths of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm may be used. 【0375】 For example, lamp 2820 can be a light source such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. 【0376】 For example, electromagnetic waves emitted from the lamp 2820 can be partially or entirely absorbed by the substrate 2824, thereby modifying the film on the substrate 2824. For example, defects can be created or reduced, or impurities can be removed. Furthermore, if the substrate 2824 is heated during the process, the creation or reduction of defects or the removal of impurities can be performed more efficiently. 【0377】 Alternatively, for example, the substrate holder 2825 may be heated by electromagnetic waves emitted from the lamp 2820, thereby heating the substrate 2824. In this case, the substrate holder 2825 does not need to have a heating mechanism 2826 inside. 【0378】 For vacuum pump 2828, refer to the description for vacuum pump 2817. For heating mechanism 2826, refer to the description for heating mechanism 2813. For gas supply source 2821, refer to the description for gas supply source 2801. 【0379】 By using the above manufacturing apparatus, it is possible to suppress the mixing of impurities into the object to be processed and to modify the film 【0380】 (Embodiment 2) In this embodiment, one form of the semiconductor device will be described using FIGS. 26 to 29. 【0381】 [Storage device 2] An example of a semiconductor device (storage device) according to one aspect of the present invention is shown in FIG. 26. 【0382】 [Configuration example of memory device]< FIG. 26 is a cross-sectional view of a semiconductor device having a memory device 290. FIG. 26 corresponds to a cross-sectional view in the channel length direction of the transistor 200. The memory device 290 shown in FIG. 26 has a different configuration of the conductor 240 from the semiconductor device having the transistor 200 and the capacitor element 292 shown in FIGS. 3A to 3D described in <Configuration example 2 of semiconductor device>. That is, the conductor 240 is connected to the conductor 242a, and further penetrates the conductor 242a, the oxide 243a, the oxides 230a and 230b, the insulator 224, and the insulator 222, and is connected to the conductor 166. 【0383】 In the semiconductor device shown in FIG. 26, the same reference numerals are assigned to the structures having the same functions as the structures constituting the semiconductor device shown in the previous embodiment. In this item as well, the materials described in detail in the previous embodiment can be used for the constituent materials of the semiconductor device. 【0384】 A wiring layer may be provided on the memory device 290. For example, in FIG. 26, insulators 160 and 162 are provided as interlayer films on the transistor 200 and the capacitor element 292. Further, a conductor 166 electrically connected to the transistor 200 is embedded in the insulators 160 and 162. The conductor 166 functions as a plug or wiring. 【0385】 A wiring layer may be provided on the insulator 162 and the conductor 166. For example, in Figure 26, insulators 163 and 164 are provided. Conductors 168 are embedded in insulators 163 and 164. Conductors 168 function as plugs or wiring. 【0386】 It is preferable to use insulators with a low dielectric constant for insulators 162 and 164. For example, insulators 162 and 164 can be insulators that can be used for insulator 280, etc. 【0387】 Insulators 160 and 163 should be insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen. For example, insulators 160 and 163 should be insulators that can be used for insulator 283, etc. 【0388】 The memory devices 290 may also be configured in a stacked arrangement. Figure 27 shows a cross-sectional view of a configuration in which five layers of memory devices 290 are stacked. As shown in Figure 27, the memory devices 290 are electrically connected to each other via the conductors 240 and 166. 【0389】 As shown in Figure 27, multiple memory devices (memory devices 290_1 to 290_5) may be enclosed and sealed with insulator 284 and insulator 214. Enclosing multiple memory devices in a single seal simplifies the process. Furthermore, by depositing a film on part of the structure constituting the transistor 200 and part of the structure provided around the transistor 200 using the sputtering method, the hydrogen concentration of the transistor 200 can be reduced. Therefore, even when a different transistor 200 is fabricated above the transistor 200, the hydrogen concentration of the transistor 200 located below can be kept low. Thus, when a stacked configuration of memory devices 290 is used, the hydrogen concentration in the transistor 200 can be reduced by enclosing multiple memory devices in a single seal, without individually sealing the memory devices 290. 【0390】 Furthermore, the sealing of multiple memory devices with insulators 284 and 214 may be performed by encompassing all of the multiple memory devices, or by encompassing them one by one. 【0391】 The multiple memory devices 290 may be arranged in the direction of the channel length, in the direction of the channel width, or in a matrix. Furthermore, they may be arranged without any particular order, depending on the design. 【0392】 Furthermore, if the same material is used for both insulator 214 and insulator 282, either insulator 214 or insulator 282 may be omitted. This reduces the number of manufacturing steps. 【0393】 As shown in Figure 27, by stacking multiple memory devices (memory devices 290_1 to 290_5), memory devices can be integrated and arranged without increasing the area occupied by the memory devices. In other words, a 3D memory device can be constructed. 【0394】 Note that while Figure 27 illustrates a configuration where each layer has one memory device, it is not limited to this configuration. Each layer may contain multiple memory devices, and these multiple memory devices may be arranged in the direction of the channel length, the direction of the channel width, or in a matrix. Furthermore, they may be arranged without any particular pattern depending on the design. 【0395】 <Examples of memory devices> In the following section, using Figures 28A, 28B, and 29, an example of a semiconductor device having a transistor 200 and a capacitive element 292 according to one aspect of the present invention, different from that shown in the previous <Example of Memory Device Configuration>, will be described. In the semiconductor device shown in Figures 28A, 28B, and 29, the same reference numerals will be used for structures having the same function as those constituting the semiconductor device shown in the previous embodiment and Figure 26. In this section, the materials used for the transistor 200 and the capacitive element 292 can be those described in detail in the previous embodiment and the previous <Example of Memory Device Configuration>. 【0396】 <<Differential Example of Memory Device 1>> Below, an example of a semiconductor device having a memory device 600 will be described using Figures 28A and 28B. The memory device 600 has transistors 200a and 200b, a capacitive element 292a, and a capacitive element 292b. 【0397】 Figure 28A is a top view of a semiconductor device having a memory device 600. Figure 28B is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 28A, and is also a cross-sectional view of transistors 200a and 200b in the channel length direction. Note that some elements have been omitted from the top view of Figure 28A for clarity. 【0398】 As shown in Figure 28B, the memory device 600 has a line-symmetric configuration with respect to the dashed line A3-A4 as the axis of symmetry. One of the source or drain electrodes of transistor 200a and one of the source or drain electrodes of transistor 200b are combined into the conductor 242c. Furthermore, the conductor that is electrically connected to transistor 200a and functions as a plug, and the conductor that is electrically connected to transistor 200b and functions as a plug, are both combined into the conductor 240c. In this way, by configuring the connections between the two transistors, two capacitive devices, wiring, and plugs as described above, a semiconductor device that can be miniaturized or highly integrated can be provided. 【0399】 The configurations and effects of transistors 200a, 200b, 292a, and 292b can be seen in the semiconductor device configuration examples shown in Figures 3A to 3D and Figure 26. 【0400】 <<Modified Memory Device 2>> Figure 29 shows an example in which the memory unit 470 has a transistor layer 413 having a transistor 200T and four memory device layers 415 (memory device layers 415_1 to 415_4). 【0401】 Each of the memory device layers 415_1 to 415_4 has a plurality of memory devices 420. For example, the memory devices 420 can be the memory device 290 shown in Figure 26, or the memory devices 600 shown in Figures 28A and 28B. 【0402】 The memory device 420 is electrically connected to the memory device 420 on a different memory device layer 415 and the transistor 200T on the transistor layer 413 via the conductors 424 and 166. 【0403】 The memory unit 470 is sealed by insulators 212, 214, 282, 284, and 283 (for convenience, this will be referred to as the sealing structure below). An insulator 274 is provided around insulator 283. In addition, a conductor 440 is provided on insulators 274, 212, and 214, and is electrically connected to the element layer 411. 【0404】 Furthermore, it is preferable that insulators 212 and 283 are materials that have a high blocking function for hydrogen. In addition, it is preferable that insulators 214 and 282 are materials that have the function of capturing or fixing hydrogen. 【0405】 For example, materials that have a high blocking property for hydrogen include silicon nitride or silicon nitride oxide. Materials that have the function of capturing or fixing hydrogen include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate). 【0406】 There are no particular limitations on the crystal structure of the materials used for insulators 212, 214, 282, and 283, but they may be amorphous or crystalline. For example, an amorphous aluminum oxide film is preferable as a material that has the function of capturing or fixing hydrogen. Amorphous aluminum oxide may capture and fix hydrogen in greater quantities than highly crystalline aluminum oxide. 【0407】 Furthermore, an insulator 280 is provided inside the sealing structure. The insulator 280 has the function of releasing oxygen upon heating. Alternatively, the insulator 280 has an excess oxygen region. 【0408】 Here, the excess oxygen in the insulator 280 can be considered in relation to the diffusion of hydrogen in the oxide semiconductor in contact with the insulator 280, as described below. 【0409】 Hydrogen present in an oxide semiconductor diffuses to other structures via the insulator 280 in contact with the oxide semiconductor. This hydrogen diffusion occurs when excess oxygen in the insulator 280 reacts with hydrogen in the oxide semiconductor to form an OH bond, which then diffuses through the insulator 280. When the hydrogen atom with the OH bond reaches a material that has the function of capturing or fixing hydrogen (typically the insulator 282), the hydrogen atom reacts with oxygen atoms bonded to atoms in the insulator 282 (e.g., metal atoms), and is captured or fixed within the insulator 282. On the other hand, it is presumed that the oxygen atom of the excess oxygen that had the OH bond remains in the insulator 280 as excess oxygen. In other words, there is a high probability that the excess oxygen in the insulator 280 plays a bridging role in this hydrogen diffusion. 【0410】 To satisfy the above model, the semiconductor device manufacturing process is one of the important factors. 【0411】 As an example, an insulator 280 containing excess oxygen is formed on an oxide semiconductor, and then an insulator 282 is formed. After that, it is preferable to perform a heat treatment. Specifically, this heat treatment is carried out at a temperature of 350°C or higher, preferably 400°C or higher, in an atmosphere containing oxygen, a nitrogen atmosphere, or a mixed atmosphere of oxygen and nitrogen. The heat treatment time is 1 hour or more, preferably 4 hours or more, and more preferably 8 hours or more. 【0412】 The above heat treatment allows hydrogen in the oxide semiconductor to diffuse outward through insulators 280 and 282. In other words, the absolute amount of hydrogen present in the oxide semiconductor and in the vicinity of the oxide semiconductor can be reduced. 【0413】 After the above heat treatment, an insulator 284 is formed. Since the insulator 284 is a material with high hydrogen blocking properties, it can suppress hydrogen that has diffused outward or hydrogen present in the outside from entering the interior, specifically the oxide semiconductor or the insulator 280 side. 【0414】 The above heat treatment is illustrated as being performed after the formation of the insulator 282, but is not limited to this. For example, the heat treatment may be performed after the formation of the transistor layer 413, or after the formation of memory device layers 415_1 to 415_3. When hydrogen is diffused outward by the heat treatment, it diffuses upward or sideways to the transistor layer 413. Similarly, when the heat treatment is performed after the formation of memory device layers 415_1 to 415_3, the hydrogen diffuses upward or sideways. 【0415】 Furthermore, by following the above manufacturing process, the insulator 214 and the insulator 284 are bonded together, thereby forming the aforementioned sealing structure. 【0416】 As described above, by using the above structure and fabrication process, a semiconductor device using an oxide semiconductor with reduced hydrogen concentration can be provided. For example, the oxide 230b contained in transistor 200T or memory device 420 has a hydrogen concentration obtained by SIMS of 1 × 10⁻¹⁶. 20 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 It has a region that is less than [a certain value]. 【0417】 Based on the above, a semiconductor device with good reliability can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. 【0418】 The configurations and methods shown in this embodiment can be used in appropriate combination with the configurations, structures, and methods shown in other embodiments. 【0419】 (Embodiment 3) In this embodiment, a transistor using an oxide as a semiconductor (hereinafter sometimes referred to as an OS transistor) and a memory device to which a capacitive element is applied (hereinafter sometimes referred to as an OS memory device) according to one aspect of the present invention will be described with reference to Figures 30A, 30B and 31A to 31C. The OS memory device is a memory device having at least a capacitive element and an OS transistor that controls the charging and discharging of the capacitive element. Since the off-current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a non-volatile memory. 【0420】 <Example of storage device configuration> Figure 30A shows an example of the configuration of an OS memory device. The storage device 1400 has peripheral circuits 1411 and a memory cell array 1470. The peripheral circuits 1411 have row circuits 1420, column circuits 1430, output circuits 1440, and control logic circuits 1460. 【0421】 The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, etc. The precharge circuit has the function of precharging the wiring. The sense amplifier has the function of amplifying the data signal read from the memory cell. The above wiring is connected to the memory cells of the memory cell array 1470, and will be described in more detail later. The amplified data signal is output to the outside of the storage device 1400 as the data signal RDATA via the output circuit 1440. The row circuit 1420 includes, for example, a row decoder, a word line driver circuit, etc., and can select the row to access. 【0422】 The memory device 1400 is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 from an external source. The memory device 1400 also receives control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA from an external source. The address signal ADDR is input to the row decoder and column decoder, and the data signal WDATA is input to the write circuit. 【0423】 The control logic circuit 1460 processes externally input control signals (CE, WE, RE) to generate control signals for the row decoder and column decoder. Control signal CE is the chip enable signal, control signal WE is the write enable signal, and control signal RE is the read enable signal. The signals processed by the control logic circuit 1460 are not limited to these; other control signals may be input as needed. 【0424】 The memory cell array 1470 has multiple memory cells MC arranged in a matrix and multiple wirings. The number of wirings connecting the memory cell array 1470 to the row circuit 1420 is determined by the configuration of the memory cells MC and the number of memory cells MC in each row. Similarly, the number of wirings connecting the memory cell array 1470 to the column circuit 1430 is determined by the configuration of the memory cells MC and the number of memory cells MC in each row. 【0425】 Although Figure 30A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, this embodiment is not limited to this. For example, as shown in Figure 30B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470. 【0426】 Figures 31A to 31C illustrate an example of a memory cell configuration that can be applied to the above-mentioned memory cell MC. 【0427】 [DOSRAM] Figures 31A to 31C show examples of the circuit configuration of a DRAM memory cell. In this specification, a DRAM using a 1OS transistor, 1 capacitance element type memory cell is sometimes referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in Figure 31A has a transistor M1 and a capacitance element CA. The transistor M1 has a gate (sometimes called a top gate) and a back gate. 【0428】 The first terminal of transistor M1 is connected to the first terminal of capacitive element CA, the second terminal of transistor M1 is connected to wiring BIL, the gate of transistor M1 is connected to wiring WOL, and the back gate of transistor M1 is connected to wiring BGL. The second terminal of capacitive element CA is connected to wiring CAL. 【0429】 Wiring BIL functions as a bit line, and wiring WOL functions as a word line. Wiring CAL functions as wiring to apply a predetermined potential to the second terminal of the capacitive element CA. During data writing and reading, wiring LL may be at ground potential or low-level potential. Wiring BGL functions as wiring to apply a potential to the back gate of transistor M1. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M1 can be increased or decreased. 【0430】 Here, the memory cell 1471 shown in Figure 31A corresponds to the memory device shown in Figure 26. In other words, transistor M1 corresponds to transistor 200, and capacitive element CA corresponds to capacitive element 292. 【0431】 Furthermore, the memory cell MC is not limited to memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may be configured such that the back gate of transistor M1 is connected to wiring WOL instead of wiring BGL, as shown in memory cell 1472 in Figure 31B. Alternatively, the memory cell MC may be a memory cell composed of a single-gate transistor, i.e., a transistor M1 without a back gate, as shown in memory cell 1473 in Figure 31C. 【0432】 When the semiconductor device shown in the above embodiment is used as a memory cell 1471, etc., transistor 200 can be used as transistor M1 and capacitive element 292 can be used as capacitive element CA. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very small. In other words, the written data can be held by transistor M1 for a long time, so the frequency of memory cell refresh can be reduced. Furthermore, the refresh operation of the memory cell can be made unnecessary. In addition, because the leakage current is very small, multi-level data or analog data can be held in memory cells 1471, 1472, and 1473. 【0433】 Furthermore, in DOSRAM, by configuring the sense amplifier to overlap the memory cell array 1470 as described above, the bit lines can be shortened. This reduces the bit line capacitance and thus the memory cell retention capacity can be reduced. 【0434】 The configuration of the peripheral circuit 1411, memory cell array 1470, etc., as shown in this embodiment is not limited to the above. The arrangement or function of these circuits, and the wiring, circuit elements, etc. connected to them, may be changed, deleted, or added as necessary. 【0435】 Generally, various types of memory are used in semiconductor devices such as computers, depending on the application. Figure 32 shows the different types of memory in a hierarchical structure. Memory located higher up in the hierarchy requires faster access speeds, while memory located lower down requires larger storage capacity and higher recording density. In Figure 32, from the top down, the memory is shown as registers integrated into the processing unit such as the CPU, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory. 【0436】 Memory integrated as registers into arithmetic processing units such as CPUs is frequently accessed by the arithmetic processing unit because it is used for temporary storage of calculation results. Therefore, faster operating speed is required than storage capacity. Registers also have the function of holding configuration information for the arithmetic processing unit. 【0437】 SRAM is used, for example, as a cache. A cache has the function of duplicating and storing some of the information held in main memory. By duplicating frequently used data in the cache, the speed of accessing that data can be increased. 【0438】 DRAM is used, for example, in main memory. Main memory has the function of holding programs and data read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm². 2 That is the case. 【0439】 3D NAND memory is used, for example, in storage. Storage has the function of holding data that needs to be stored long-term, as well as various programs used by the processing unit. Therefore, storage requires a large storage capacity and high recording density rather than just operating speed. The recording density of memory devices used in storage is approximately 0.6 to 6.0 Gbit / mm². 2 That is the case. 【0440】 A storage device according to one aspect of the present invention has a high operating speed and can retain data for a long period of time. This storage device is suitably used as a storage device located in a boundary region 901 that includes both the layer where the cache is located and the layer where the main memory is located. Furthermore, this storage device is suitably used as a storage device located in a boundary region 902 that includes both the layer where the main memory is located and the layer where the storage is located. 【0441】 The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. 【0442】 (Embodiment 4) In this embodiment, Figures 33A and 33B show an example of a chip 1200 on which the semiconductor device of the present invention is mounted. Multiple circuits (systems) are mounted on the chip 1200. This technology of integrating multiple circuits (systems) onto a single chip is sometimes called a System on Chip (SoC). 【0443】 As shown in Figure 33A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog processing units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like. 【0444】 The chip 1200 is provided with bumps (not shown) and connects to the first surface of the printed circuit board (PCB) 1201, as shown in Figure 33B. In addition, multiple bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and connect to the motherboard 1203. 【0445】 The motherboard 1203 may be equipped with storage devices such as DRAM 1221 and flash memory 1222. For example, the DOSRAM shown in the previous embodiment can be used for the DRAM 1221. Also, for example, the NOSRAM shown in the previous embodiment can be used for the flash memory 1222. 【0446】 The CPU 1211 preferably has multiple CPU cores. Similarly, the GPU 1212 preferably has multiple GPU cores. The CPU 1211 and GPU 1212 may each have memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and GPU 1212 may be provided on the chip 1200. The aforementioned DOSRAM can be used for this memory. The GPU 1212 is suitable for parallel computation of a large amount of data and can be used for image processing and multiply-accumulate operations. By providing the GPU 1212 with an image processing circuit and a multiply-accumulate operation circuit using the oxide semiconductor of the present invention, it becomes possible to perform image processing and multiply-accumulate operations with low power consumption. 【0447】 Furthermore, because the CPU 1211 and GPU 1212 are located on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, enabling high-speed data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculations have been performed on the GPU 1212. 【0448】 The analog arithmetic unit 1213 includes one or both an A / D (analog-to-digital) conversion circuit and a D / A (digital-to-analog) conversion circuit. Alternatively, the analog arithmetic unit 1213 may also be provided with the above-mentioned sum-of-accumulate circuit. 【0449】 The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222. 【0450】 Interface 1215 has interface circuits for connecting to external devices such as display devices, speakers, microphones, cameras, and controllers. Controllers include mice, keyboards, and game controllers. Such interfaces can include USB (Universal Serial Bus) and HDMI (High-Definition Multimedia Interface). 【0451】 The network circuit 1216 includes a network circuit such as a LAN (Local Area Network). It may also include a circuit for network security. 【0452】 The above-mentioned circuits (systems) can be formed on chip 1200 using the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, there is no need to increase the number of manufacturing processes, and chip 1200 can be manufactured at a low cost. 【0453】 A PCB 1201 equipped with a chip 1200 having a GPU 1212, a motherboard 1203 equipped with DRAM 1221, and flash memory 1222 can be called a GPU module 1204. 【0454】 The GPU module 1204 has a chip 1200 that uses SoC technology, which allows for a smaller size. Furthermore, its excellent image processing capabilities make it suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable game consoles. Additionally, the multiply-accumulate circuit using the GPU 1212 enables the execution of techniques such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN), allowing the chip 1200 to be used as an AI chip, or the GPU module 1204 as an AI system module. 【0455】 The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. 【0456】 (Embodiment 5) This embodiment shows an example of an electronic component and electronic device incorporating the storage device and other components described in the above embodiment. 【0457】 <Electronic Components> First, an example of an electronic component incorporating the memory device 720 will be explained using Figures 34A and 34B. 【0458】 Figure 34A shows a perspective view of an electronic component 700 and a circuit board (mounted board 704) on which the electronic component 700 is mounted. The electronic component 700 shown in Figure 34A has a memory device 720 inside a mold 711. Figure 34A is partially omitted to show the inside of the electronic component 700. The electronic component 700 has a land 712 on the outside of the mold 711. The land 712 is electrically connected to an electrode pad 713, and the electrode pad 713 is electrically connected to the memory device 720 by a wire 714. The electronic component 700 is mounted, for example, on a printed circuit board 702. Multiple such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounted board 704. 【0459】 The storage device 720 includes a drive circuit layer 721 and a storage circuit layer 722. 【0460】 Figure 34B shows a perspective view of the electronic component 730. The electronic component 730 is an example of a SiP (System in package) or MCM (Multi Chip Module). The electronic component 730 has an interposer 731 on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple storage devices 720 are provided on the interposer 731. 【0461】 Electronic component 730 shows an example where the memory device 720 is used as high-bandwidth memory (HBM). Furthermore, the semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, GPU, or FPGA. 【0462】 The package substrate 732 can be a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like. The interposer 731 can be a silicon interposer, a resin interposer, or the like. 【0463】 The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "redistribution substrate" or "intermediate substrate". In addition, through electrodes may be provided on the interposer 731, and these through electrodes may be used to electrically connect the integrated circuits and the package substrate 732. Furthermore, in silicon interposers, TSVs (Through Silicon Vias) can be used as through electrodes. 【0464】 It is preferable to use a silicon interposer as the interposer 731. Since silicon interposers do not require active elements, they can be manufactured at a lower cost than integrated circuits. On the other hand, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring, which is difficult with resin interposers. 【0465】 In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM. 【0466】 Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer. 【0467】 Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 730. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the heights of the memory device 720 and the semiconductor device 735. 【0468】 To mount the electronic component 730 onto another substrate, electrodes 733 may be provided at the bottom of the package substrate 732. Figure 34B shows an example where the electrodes 733 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved. 【0469】 The electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. For example, mounting methods such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be used. 【0470】 This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. 【0471】 (Embodiment 6) This embodiment describes application examples of a memory device using the semiconductor device shown in the previous embodiment. The semiconductor device shown in the previous embodiment can be applied to memory devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including video cameras), recording and playback devices, navigation systems, etc.). Here, "computer" includes tablet computers, notebook computers, desktop computers, and large computers such as server systems. Alternatively, the semiconductor device shown in the previous embodiment can be applied to various removable memory devices such as memory cards (e.g., SD cards), USB memory, and SSDs (solid-state drives). Figures 35A to 35E schematically show some configuration examples of removable memory devices. For example, the semiconductor device shown in the previous embodiment can be processed into a packaged memory chip and used in various storage devices and removable memories. 【0472】 Figure 35A is a schematic diagram of a USB memory device. The USB memory device 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a circuit board 1104. The circuit board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the circuit board 1104. The semiconductor device shown in the above embodiment can be incorporated into the memory chip 1105, etc. 【0473】 Figure 35B is a schematic diagram of the external appearance of an SD card, and Figure 35C is a schematic diagram of the internal structure of an SD card. The SD card 1110 has a housing 1111, a connector 1112, and a circuit board 1113. The circuit board 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the circuit board 1113. By providing a memory chip 1114 on the back side of the circuit board 1113, the capacity of the SD card 1110 can be increased. Alternatively, a wireless chip with wireless communication functionality may be provided on the circuit board 1113. This allows for reading and writing data to the memory chip 1114 via wireless communication between the host device and the SD card 1110. The semiconductor device shown in the above embodiment can be incorporated into the memory chip 1114, etc. 【0474】 Figure 35D is a schematic diagram of the external appearance of the SSD, and Figure 35E is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a circuit board 1153. The circuit board 1153 is housed in the housing 1151. For example, memory chips 1154, 1155, and a controller chip 1156 are mounted on the circuit board 1153. Memory chip 1155 is the work memory for the controller chip 1156, and for example, a DOSRAM chip can be used. The capacity of the SSD 1150 can be increased by also providing memory chips 1154 on the back side of the circuit board 1153. Semiconductor devices as shown in the above embodiment can be incorporated into memory chips 1154, etc. 【0475】 This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. 【0476】 (Embodiment 7) A semiconductor device according to one aspect of the present invention can be used as a processor such as a CPU or GPU, or as a chip. Figures 36A to 36H show specific examples of electronic devices equipped with a processor such as a CPU or GPU, or as a chip according to one aspect of the present invention. 【0477】 <Electronic Equipment and Systems> A GPU or chip according to one aspect of the present invention can be installed in various electronic devices. Examples of electronic devices include, for example, electronic devices with relatively large screens such as television equipment, monitors for desktop or notebook information terminals, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, e-book readers, mobile phones, portable game consoles, portable information terminals, and sound playback devices. Furthermore, by installing a GPU or chip according to one aspect of the present invention in an electronic device, artificial intelligence can be incorporated into the electronic device. 【0478】 An electronic device according to one aspect of the present invention may have an antenna. By receiving a signal with the antenna, the display unit can display images, information, etc. Furthermore, if the electronic device has an antenna and a secondary battery, the antenna may be used for contactless power transmission. 【0479】 An electronic device according to one aspect of the present invention may have sensors (including those with the function of measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation). 【0480】 An electronic device according to one aspect of the present invention can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on. Figures 36A to 36H show examples of electronic devices. 【0481】 [Information terminal] Figure 36A illustrates a mobile phone (smartphone), which is a type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102. For input interfaces, a touch panel is provided on the display unit 5102, and buttons are provided on the housing 5101. 【0482】 The information terminal 5100 can execute applications utilizing artificial intelligence by applying a chip according to one aspect of the present invention. Examples of applications utilizing artificial intelligence include applications that recognize conversations and display the content of those conversations on the display unit 5102, applications that recognize characters, figures, etc., entered by the user on the touch panel provided on the display unit 5102 and display them on the display unit 5102, and applications that perform biometric authentication such as fingerprints and voiceprints. 【0483】 Figure 36B illustrates a notebook-type information terminal 5200. The notebook-type information terminal 5200 comprises a main unit 5201, a display unit 5202, and a keyboard 5203. 【0484】 The notebook-type information terminal 5200, like the information terminal 5100 described above, can run applications utilizing artificial intelligence by applying a chip according to one embodiment of the present invention. Examples of applications utilizing artificial intelligence include design support software, document editing software, and automatic menu generation software. Furthermore, the notebook-type information terminal 5200 can be used to develop new artificial intelligence. 【0485】 In the above, smartphones and notebook computers were used as examples of electronic devices, illustrated in Figures 36A and 36B, respectively. However, other types of information terminals can also be used. Examples of other types of information terminals include PDAs (Personal Digital Assistants), desktop computers, and workstations. 【0486】 [Game console] Figure 36C shows a portable game console 5300, which is an example of a game console. The portable game console 5300 includes a casing 5301, casing 5302, casing 5303, a display unit 5304, a connection unit 5305, operation keys 5306, etc. Casings 5302 and 5303 can be detached from casing 5301. By attaching the connection unit 5305 provided on casing 5301 to another casing (not shown), the video output from the display unit 5304 can be output to another video device (not shown). In this case, casings 5302 and 5303 can each function as operation units. This allows multiple players to play the game simultaneously. The chips shown in the above embodiment can be incorporated into the chips provided on the circuit boards of casings 5301, casing 5302, and casing 5303. 【0487】 Figure 36D also shows a home console 5400, which is an example of a game console. A controller 5402 is connected to the home console 5400 either wirelessly or via a wired connection. 【0488】 By applying a GPU or chip according to one aspect of the present invention to game consoles such as the handheld game console 5300 and the home game console 5400, a low-power game console can be realized. Furthermore, because the low power consumption reduces heat generation from the circuit, the impact of heat on the circuit itself, peripheral circuits, and modules can be minimized. 【0489】 Furthermore, by applying a GPU or chip according to one aspect of the present invention to the portable game console 5300, a portable game console 5300 with artificial intelligence can be realized. 【0490】 Normally, the progression of a game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are determined by the game's program. However, by applying artificial intelligence to the 5300 handheld game console, it becomes possible to create expressions that are not limited to the game's program. For example, it becomes possible to express changes in the content of questions asked by the player, the game's progress, the time of day, and the behavior of characters appearing in the game. 【0491】 Furthermore, when playing games that require multiple players on the 5300 handheld game console, artificial intelligence can be used to create anthropomorphic game players. By using AI-generated game players as opponents, it becomes possible to play the game even by a single player. 【0492】 Figures 36C and 36D illustrate a portable game console and a home game console as examples of game consoles, but the game consoles to which the GPU or chip of one aspect of the present invention is applied are not limited to these. Examples of game consoles to which the GPU or chip of one aspect of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities. 【0493】 [Large computer] A GPU or chip according to one aspect of the present invention can be applied to a large computer. 【0494】 Figure 36E shows the supercomputer 5500, an example of a large-scale computer. Figure 36F shows the rack-mount computer 5502, which is part of the supercomputer 5500. 【0495】 The supercomputer 5500 comprises a rack 5501 and a plurality of rack-mount type computers 5502. The plurality of computers 5502 are housed in the rack 5501. In addition, each computer 5502 is provided with a plurality of circuit boards 5504, on which the GPU or chip described in the above embodiment can be mounted. 【0496】 The Supercomputer 5500 is a large computer primarily used for scientific and technical computing. Scientific and technical computing requires high-speed processing of enormous calculations, resulting in high power consumption and significant heat generation from the chip. By applying a GPU or chip according to one aspect of the present invention to the Supercomputer 5500, a low-power supercomputer can be realized. Furthermore, the reduced power consumption reduces heat generation from the circuit, thereby minimizing the impact of heat on the circuit itself, peripheral circuits, and modules. 【0497】 Figures 36E and 36F illustrate a supercomputer as an example of a large computer, but the large computers to which the GPU or chip according to one aspect of the present invention is applied are not limited to this. Examples of large computers to which the GPU or chip according to one aspect of the present invention is applied include service-providing computers (servers) and large general-purpose computers (mainframes). 【0498】 [Mobile] A GPU or chip according to one aspect of the present invention can be applied to a mobile vehicle and the area around the driver's seat of the vehicle. 【0499】 Figure 36G shows the area around the windshield inside an automobile, which is an example of a moving object. In Figure 36G, display panels 5701, 5702, and 5703 mounted on the dashboard are shown, as well as a display panel 5704 mounted on the pillar. 【0500】 Display panels 5701 to 5703 can display various information such as the speedometer, tachometer, mileage, fuel gauge, gear status, and air conditioning settings. Furthermore, the display items and layout on the display panels can be changed as needed to suit the user's preferences, enhancing the design. Display panels 5701 to 5703 can also be used as lighting devices. 【0501】 The display panel 5704 can display images from an imaging device (not shown) installed in the vehicle, thereby compensating for the blind spots obstructed by the pillars. In other words, by displaying images from an imaging device installed on the outside of the vehicle, blind spots can be compensated for, thereby enhancing safety. Furthermore, by displaying images that compensate for unseen areas, safety checks can be performed more naturally and without discomfort. The display panel 5704 can also be used as a lighting device. 【0502】 A GPU or chip according to one aspect of the present invention can be applied as a component of artificial intelligence, and for example, the chip can be used in an autonomous driving system for an automobile. The chip can also be used in systems that perform tasks such as road guidance and hazard prediction. Display panels 5701 to 5704 may be configured to display information such as road guidance and hazard prediction. 【0503】 Although automobiles are described above as an example of a mobile device, mobile devices are not limited to automobiles. For example, mobile devices can also include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), and by applying a chip according to one aspect of the present invention to these mobile devices, a system utilizing artificial intelligence can be provided. 【0504】 [electric appliances] Figure 36H shows an example of an electrical appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 includes a casing 5801, a refrigerator door 5802, a freezer door 5803, etc. 【0505】 By applying a chip according to one aspect of the present invention to an electric refrigerator 5800, an electric refrigerator 5800 equipped with artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator 5800 can have functions such as automatically generating menus based on the ingredients stored in the electric refrigerator 5800 and their expiration dates, and automatically adjusting the temperature to suit the ingredients stored in the electric refrigerator 5800. 【0506】 While electric refrigerators and freezers were described as an example of electrical appliances, other examples of electrical appliances include vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cooktops, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audiovisual equipment. 【0507】 The electronic devices described in this embodiment, their functions, examples of artificial intelligence applications, and their effects can be appropriately combined with descriptions of other electronic devices. 【0508】 This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. [Explanation of symbols] 【0509】 160: insulator, 162: insulator, 163: insulator, 164: insulator, 166: conductor, 168: conductor, 200: transistor, 200a: transistor, 200b: transistor, 200T: transistor, 205: conductor, 205a: conductor, 205A: conductive film, 205b: conductor, 205B: conductive film, 205c: conductor, 205C: conductive film, 212: insulator, 214: insulator, 216: insulator, 222: insulator, 224: insulator, 230: oxide, 230a: oxide, 230A: oxide film, 230b: oxide, 230B: oxide film, 230ba: region 230bb: Region, 230bc: Region, 240: Conductor, 240a: Conductor, 240b: Conductor, 240c: Conductor, 241: Insulator, 241a: Insulator, 241b: Insulator, 242: Conductor, 242a: Conductor, 242A: Conductive film, 242b: Conductor, 242B: Conductive layer, 242c: Conductor, 243: Oxide, 243a: Oxide, 243A: Oxide film, 243b: Oxide, 243B: Oxide layer, 246: Conductor, 246a: Conductor, 246b: Conductor, 250: Insulator, 250a: Insulator, 250A: Insulating film, 250Aa: Insulating film, 250Ab: Insulating film Edge film, 250b: insulator, 260: conductor, 260a: conductor, 260b: conductor, 271: insulator, 271a: insulator, 271A: insulating film, 271b: insulator, 271B: insulating layer, 272: insulator, 272a: insulator, 272A: insulating film, 272b: insulator, 273: insulator, 273a: insulator, 273A: insulating film, 273b: insulator, 273B: insulating layer, 274: insulator, 275: insulator, 275a: insulator, 275A: insulating film, 275b: insulator, 280: insulator, 282: insulator, 283: insulator, 284: insulator, 286: insulator, 290: Memory device, 290_1: Memory device, 290_5: Memory device, 292: Capacitive element, 292a: Capacitive element, 292b: Capacitive element, 293: Insulator, 293A: Insulating film, 294: Conductor, 294A: Conductive film, 411: Element layer, 413: Transistor layer, 415: Memory device layer, 415_1: Memory device layer, 415_3: Memory device layer, 415_4: Memory device layer, 420: Memory device, 424: Conductor, 440: Conductor, 470: Memory unit, 600: Memory device, 700: Electronic component, 702: Printed circuit board,704: Mounting board, 711: Mold, 712: Land, 713: Electrode pad, 714: Wire, 720: Memory device, 721: Drive circuit layer, 722: Memory circuit layer, 730: Electronic component, 731: Interposer, 732: Package substrate, 733: Electrode, 735: Semiconductor device, 901: Boundary region, 902: Boundary region,

Claims

[Claim 1] It comprises a first insulating layer, a second insulating layer, a first memory cell, and a second memory cell. The first memory cell comprises a first transistor, a first capacitive element, and a first plug. The first transistor described above is The first oxide semiconductor and, The first conductor and the second conductor on the first oxide semiconductor, The first insulator on the first conductor, The second insulator on the second conductor, A third insulator is disposed on the first insulator and the second insulator, and a first opening is formed in the region between the first conductor and the second conductor, A fourth insulator is disposed on the first oxide semiconductor and between the first conductor and the second conductor, The present invention comprises a third conductor on the fourth insulator, The first capacitive element is, The above-mentioned second conductor and, The third insulator has a second opening formed therein that reaches the second conductor, A fifth insulator disposed inside the second opening, The fifth insulator has a fourth conductor, The first plug is positioned to penetrate the first insulator, the third insulator, the first conductor, and the first oxide semiconductor. The first plug is electrically connected to the first conductor, The second memory cell comprises a second transistor, a second capacitive element, and a second plug. The second transistor described above is The second oxide semiconductor, The fifth conductor and the sixth conductor on the second oxide semiconductor, The sixth insulator on the fifth conductor, The seventh insulator on the sixth conductor, An eighth insulator is placed on the sixth and seventh insulators, and a third opening is formed in the region between the fifth and sixth conductors, A ninth insulator is disposed on the second oxide semiconductor and between the fifth conductor and the sixth conductor, The ninth insulator has a seventh conductor, The second capacitive element is, The sixth conductor mentioned above, The eighth insulator has a fourth opening formed that reaches the sixth conductor, A tenth insulator disposed inside the fourth opening, The invention comprises an eighth conductor on the tenth insulator, The second plug is positioned to penetrate the sixth insulator, the ninth insulator, the fifth conductor, and the second oxide semiconductor. The second plug is electrically connected to the fifth conductor. The first memory cell is provided on the first insulating layer, The second memory cell is provided on the first memory cell, The upper surface of the first plug and the second plug are electrically connected. The second insulating layer is arranged to cover the first memory cell and the second memory cell. The second insulating layer is in contact with a portion of the upper surface of the first insulating layer in a region that does not overlap with the first oxide semiconductor and the second oxide semiconductor. The ninth insulator covers the eighth insulator and, in a region where it does not overlap with the fifth insulator, is in contact with the upper surface of the seventh insulator. The semiconductor device wherein the ninth insulator is a metal oxide having an amorphous structure.

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