Semiconductor equipment

Abstract

To provide a semiconductor device in which the reliability of a Ni-plated layer can be improved in a structure in which the Ni-plated layer is formed on an electrode exposed from an opening of an organic insulating layer.SOLUTION: A semiconductor device includes a chip having a side surface, an electrode formed on the chip, an inorganic insulating layer covering the electrode, an organic insulating layer covering the inorganic insulating layer, having a second opening, and exposing an inner peripheral edge of the inorganic insulating layer in a region between a first opening and the second opening, and a metal layer covering the electrode in the first opening and covering the inner peripheral edge of the inorganic insulating layer in the second opening. The organic insulating layer has a second outer wall existing inside a first outer wall of the inorganic insulating layer. The second outer wall is formed along the side surface with a space on the inside from the side surface.SELECTED DRAWING: Figure 2

Description

[Technical Field] 【0001】 This invention relates to a semiconductor device. [Background technology] 【0002】 Patent Document 1 (Figure 4) discloses a semiconductor device comprising a semiconductor substrate, an aluminum film (electrode), a polyimide film (organic insulating layer), and a Ni plating film (Ni plating layer). The aluminum film is formed on the semiconductor substrate. The polyimide film is formed on the aluminum film and has an opening that exposes the aluminum film. The Ni plating film is formed on the aluminum film exposed through the opening in the polyimide film. [Prior art documents] [Patent Documents] 【0003】 [Patent Document 1] International Publication No. 2018 / 167925A1 [Overview of the project] [Problems that the invention aims to solve] 【0004】 Organic insulating layers have poor adhesion to nickel. Therefore, when a metal layer is formed on an electrode exposed through an opening in the organic insulating layer, the metal layer forms a gap extending toward the electrode between itself and the organic insulating layer. As a result, the connection of the metal layer to the electrode becomes insufficient, reducing the reliability of the metal layer. 【0005】 One embodiment of the present invention provides a semiconductor device in which the reliability of a metal layer can be improved in a structure in which a metal layer is formed on an electrode exposed from an opening in an organic insulating layer. [Means for solving the problem] 【0006】 One embodiment of the present invention provides a semiconductor device including a chip, an electrode formed on the chip, an inorganic insulating layer covering the electrode and having a first opening exposing the electrode, an organic insulating layer covering the inorganic insulating layer and having a second opening spaced from the first opening and surrounding the first opening, the organic insulating layer exposing an inner peripheral edge of the inorganic insulating layer in a region between the first opening and the second opening, and a Ni plating layer covering the electrode in the first opening and covering the inner peripheral edge of the inorganic insulating layer in the second opening. 【0007】 According to this semiconductor device, the Ni plating layer covers the inner peripheral edge of the inorganic insulating layer, which has a higher adhesion to Ni compared to the organic insulating layer. Thereby, the gap formation region can be moved away from the electrode, and at the same time, the formation of a gap extending toward the electrode can be suppressed. Compared with a structure in which the inner peripheral edge of the inorganic insulating layer is not exposed, the gap formation region between the organic insulating layer can be reduced. Therefore, the reliability of the Ni plating layer can be improved. 【0008】 One embodiment of the present invention provides a semiconductor device including a chip, an electrode formed on the chip, an inorganic insulating layer covering the electrode and having a first opening exposing the electrode, an organic insulating layer covering the inorganic insulating layer and having a second opening spaced from the first opening and surrounding the first opening, the organic insulating layer exposing an inner peripheral edge of the inorganic insulating layer in a region between the first opening and the second opening, and a metal layer covering the electrode in the first opening and covering the inner peripheral edge of the inorganic insulating layer in the second opening. 【0009】 According to this semiconductor device, the metal layer covers the inner peripheral edge of the inorganic insulating layer, which has a higher adhesion to the metal layer compared to the organic insulating layer. Thereby, the gap formation region can be moved away from the electrode, and at the same time, the formation of a gap extending toward the electrode can be suppressed. Compared with a structure in which the inner peripheral edge of the inorganic insulating layer is not exposed, the gap formation region between the organic insulating layer can be reduced. Therefore, the reliability of the metal layer can be improved. 【0010】 The above-mentioned, or further other objects, features, and effects of the present invention will be clarified by the description of the embodiments described below with reference to the accompanying drawings. 【Brief Description of the Drawings】 【0011】 [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view showing a cross-section along line II-II shown in FIG. 1 together with an outer surface plating layer according to a first exemplary form. [Figure 3] FIG. 3 is an enlarged view of region III shown in FIG. 2. [Figure 4A] FIG. 4A is a corresponding view of FIG. 3, and is an enlarged view showing an outer surface plating layer according to a second exemplary form. [Figure 4B] FIG. 4B is a corresponding view of FIG. 3, and is an enlarged view showing an outer surface plating layer according to a third exemplary form. [Figure 4C] FIG. 4C is a corresponding view of FIG. 3, and is an enlarged view showing an outer surface plating layer according to a fourth exemplary form. [Figure 4D] FIG. 4D is a corresponding view of FIG. 3, and is an enlarged view showing an outer surface plating layer according to a fifth exemplary form. [Figure 5A] FIG. 5A is a cross-sectional view for explaining an example of a manufacturing method of the semiconductor device shown in FIG. 1. [Figure 5B] FIG. 5B is a cross-sectional view showing the process after FIG. 5A. [Figure 5C] FIG. 5C is a cross-sectional view showing the process after FIG. 5B. [Figure 5D] FIG. 5D is a cross-sectional view showing the process after FIG. 5C. [Figure 5E] FIG. 5E is a cross-sectional view showing the process after FIG. 5D. [Figure 5F] FIG. �F is a cross-sectional view showing the process after FIG. 5E. [Figure 5G] FIG. 5G is a cross-sectional view showing the process after FIG. 5F. [Figure 5H] FIG. 5H is a cross-sectional view showing the process after FIG. 5G. [Figure 5I]Figure 5I is a cross-sectional view showing a process after Figure 5H. [Figure 5J] Figure 5J is a cross-sectional view showing a process after Figure 5I. [Figure 5K] Figure 5K is a cross-sectional view showing a process after Figure 5J. [Figure 5L] Figure 5L is a cross-sectional view showing a process after Figure 5K. [Figure 5M] Figure 5M is a cross-sectional view showing a process after Figure 5L. [Figure 5N] Figure 5N is a cross-sectional view showing a process after Figure 5M. [Figure 5O] Figure 5O is a cross-sectional view showing a process after Figure 5N. [Figure 6] Figure 6 is a corresponding diagram to Figure 2, and is a cross-sectional view showing a semiconductor device according to a second embodiment of the present invention together with the outer plating layer according to the first embodiment. [Figure 7] Figure 7 is an enlarged view of area VII shown in Figure 6. [Figure 8A] Figure 8A is a corresponding diagram to Figure 7, and is an enlarged view showing the outer plating layer according to the second embodiment. [Figure 8B] Figure 8B is a corresponding diagram to Figure 7, and is an enlarged view showing the outer plating layer according to the third embodiment. [Figure 8C] Figure 8C is a corresponding diagram to Figure 7, and is an enlarged view showing the outer plating layer according to the fourth embodiment. [Figure 8D] Figure 8D is a corresponding diagram to Figure 7, and is an enlarged view showing the outer plating layer according to the fifth embodiment example. [Figure 9] Figure 9 is a plan view showing a semiconductor device according to a third embodiment of the present invention. [Figure 10] Figure 10 is an enlarged view of region X shown in Figure 9. [Figure 11] Figure 11 is a cross-sectional view along the line XI-XI shown in Figure 10. [Figure 12] Figure 12 is a cross-sectional view along the line XII-XII shown in Figure 9. [Figure 13] Figure 13 is an enlarged view of region XIII shown in Figure 12. [Figure 14] Figure 14 is an enlarged view of region XIV shown in Figure 12. [Figure 15] Figure 15 is a corresponding diagram to Figure 12 and is a cross-sectional view showing a semiconductor device according to the fourth embodiment of the present invention. [Figure 16] Figure 16 is an enlarged view of region XVI shown in Figure 15. [Figure 17] Figure 17 is an enlarged view of region XVII shown in Figure 15. [Figure 18] Figure 18 is a plan view from one side of a semiconductor package into which the semiconductor devices according to the first to fourth embodiments are incorporated. [Figure 19] Figure 19 is a plan view of the semiconductor package shown in Figure 18, viewed from the other side. [Figure 20] Figure 20 is a perspective view of the semiconductor package shown in Figure 18. [Figure 21] Figure 21 is an exploded perspective view of the semiconductor package shown in Figure 18. [Figure 22] Figure 22 is a cross-sectional view along the line XXII-XXII shown in Figure 18. [Figure 23] Figure 23 is a circuit diagram of the semiconductor package shown in Figure 18. [Modes for carrying out the invention] 【0012】 Figure 1 is a plan view showing a semiconductor device 1 according to the first embodiment of the present invention. Figure 2 is a cross-sectional view showing the cross-section along the line II-II shown in Figure 1, together with the outer plating layer 42 according to the first embodiment. Figure 3 is an enlarged view of region III shown in Figure 2. 【0013】 Referring to Figures 1 to 3, in this embodiment, the semiconductor device 1 consists of a SiC semiconductor device including a SiC chip 2 (chip). The SiC chip 2 contains a hexagonal SiC single crystal. The hexagonal SiC single crystal has multiple polytypes, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, 6H-SiC single crystals, etc. In this embodiment, the SiC chip 2 consists of a 4H-SiC single crystal, but this does not exclude other polytypes. 【0014】 The SiC chip 2 is formed in a rectangular parallelepiped shape. The SiC chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and sides 5A, 5B, 5C, and 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrilateral shape (square in this form) when viewed from their normal direction Z in a plan view (hereinafter simply referred to as "plan view"). 【0015】 The thickness of the SiC chip 2 may be 40 μm or more and 300 μm or less. The thickness of the SiC chip 2 may be 40 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, or 250 μm or more and 300 μm or less. Preferably, the thickness of the SiC chip 2 is 60 μm or more and 150 μm or less. 【0016】 The first main surface 3 and the second main surface 4 face the c-plane of the SiC single crystal. The first main surface 3 faces the silicon plane ((0001) plane) of the SiC single crystal, and the second main surface 4 faces the carbon plane ((000-1) plane) of the SiC single crystal. The second main surface 4 may consist of a rough surface having either grinding marks or annealing marks, or both. The annealing marks are laser irradiation marks. The second main surface 4 may also be an ohmic surface having annealing marks. 【0017】 The first principal surface 3 and the second principal surface 4 may have an off-angle that is inclined with respect to the c-plane of the SiC single crystal in a predetermined off-direction at a predetermined off-angle. The off-direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle is preferably inclined at an angle of 0° to 10° in the off-direction. The off-angle may be 0° to 6°. The off-angle may be 0° to 2°, 2° to 4°, or 4° to 6°. 【0018】 The off-angle is preferably greater than 0° and 4.5° or less. The off-angle may be 3° or more and 4.5° or less. In this case, the off-angle is preferably 3° or more and 3.5° or less, or 3.5° or more and 4° or less. The off-angle may be 1.5° or more and 3° or less. In this case, the off-angle is preferably 1.5° or more and 2° or less, or 2° or more and 2.5° or less. 【0019】 Sides 5A to 5D include the first side 5A, the second side 5B, the third side 5C, and the fourth side 5D. The first side 5A and the second side 5B extend along the first direction X and face the second direction Y which intersects the first direction X. The third side 5C and the fourth side 5D extend along the second direction Y and face the first direction X. Specifically, the second direction Y is perpendicular to the first direction X. 【0020】 The first side surface 5A and the second side surface 5B are formed by the a-plane of the SiC single crystal. The first side surface 5A and the second side surface 5B may form inclined surfaces that are inclined in the c-axis direction (【0001】 direction) of the SiC single crystal with respect to the normal direction Z, when the normal direction Z is taken as the reference direction. The first side surface 5A and the second side surface 5B may be inclined at an angle corresponding to the off-angle with respect to the normal direction Z, when the normal direction Z is taken as 0°. The angle corresponding to the off-angle may be equal to the off-angle, or it may be an angle greater than 0° and less than the off-angle. 【0021】 The third side surface 5C and the fourth side surface 5D are formed by the m-plane of the SiC single crystal. The third side surface 5C and the fourth side surface 5D extend planar along the normal direction Z. Specifically, the third side surface 5C and the fourth side surface 5D are formed substantially perpendicular to the first main surface 3 and the second main surface 4. 【0022】 The side surfaces 5A to 5D may be composed of cleavage surfaces or grinding surfaces. The length of the side surfaces 5A to 5D may be 0.1 mm or more and 10 mm or less. The length of the side surfaces 5A to 5D is preferably 0.5 mm or more and 2.5 mm or less. 【0023】 In this form, the SiC chip 2 has a laminated structure including an n + -type SiC substrate 6 and an n-type SiC epitaxial layer 7. The second main surface 4 of the SiC chip 2 and a part of the side surfaces 5A to 5D are formed by the SiC substrate 6. The first main surface 3 of the SiC chip 2 and a part of the side surfaces 5A to 5D are formed by the SiC epitaxial layer 7. 【0024】 The n-type impurity concentration of the SiC epitaxial layer 7 is less than the n-type impurity concentration of the SiC substrate 6. The n-type impurity concentration of the SiC substrate 6 may be 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less. The n-type impurity concentration of the SiC epitaxial layer 7 may be 1.0×10 15 cm -3 or more and 1.0×10 18 cm -3 or less. 【0025】 The thickness of the SiC substrate 6 may be 40 μm or more and 250 μm or less. The thickness of the SiC substrate 6 may be 40 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, or 200 μm or more and 250 μm or less. The thickness of the SiC substrate 6 is preferably 40 μm or more and 150 μm or less. By thinning the SiC substrate 6, the resistance value of the SiC substrate 6 can be reduced. 【0026】 The thickness of the SiC epitaxial layer 7 may be 1 μm or more and 50 μm or less. The thickness of the SiC epitaxial layer 7 may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less. Preferably, the thickness of the SiC epitaxial layer 7 is 5 μm or more and 15 μm or less. 【0027】 The SiC chip 2 includes an active region 8 and an outer region 9. The active region 8 is a region containing an SBD (Schottky Barrier Diode) as an example of a functional device (diode). In a plan view, the active region 8 is formed in the central part of the SiC chip 2, spaced inward from the sides 5A to 5D. In a plan view, the active region 8 is formed in a rectangular shape with four sides parallel to the sides 5A to 5D. 【0028】 The outer region 9 is the region outside the active region 8. The outer region 9 is formed in the region between the sides 5A to 5D and the active region 8. In a plan view, the outer region 9 is formed in an annular shape (specifically, an endless shape) surrounding the active region 8. 【0029】 The semiconductor device 1 includes an n-type diode region 10 formed on the surface layer of the first main surface 3 in the active region 8. The diode region 10 is formed in the central part of the first main surface 3. The planar shape of the diode region 10 is arbitrary. The diode region 10 may be formed in a rectangular shape with four sides parallel to the sides 5A to 5D in a plan view. 【0030】 In this embodiment, the diode region 10 is formed using a portion of the SiC epitaxial layer 7. The n-type impurity concentration in the diode region 10 is equal to the n-type impurity concentration in the SiC epitaxial layer 7. The n-type impurity concentration in the diode region 10 may exceed the n-type impurity concentration in the SiC epitaxial layer 7. In this case, the diode region 10 is formed by introducing n-type impurities into the surface layer of the SiC epitaxial layer 7. 【0031】 In the outer region 9, a guard region 11 containing p-type impurities is formed on the surface layer of the first main surface 3. The p-type impurities in the guard region 11 may or may not be activated. The guard region 11 is formed in a band shape extending along the diode region 10 in a plan view. Specifically, the guard region 11 is formed in an annular shape (specifically, endlessly) surrounding the diode region 10 in a plan view. 【0032】 As a result, the guard region 11 is formed as a guard ring region. The guard region 11 defines the active region 8 (diode region 10). The planar shape of the active region 8 (diode region 10) is adjusted by the planar shape of the guard region 11. The guard region 11 may be formed as a polygonal ring or a ring in plan view. 【0033】 The semiconductor device 1 includes a main surface insulating layer 12 formed on a first main surface 3. The main surface insulating layer 12 may have a laminated structure including a silicon oxide layer and a silicon nitride layer. The main surface insulating layer 12 may have a single-layer structure consisting of a silicon oxide layer or a silicon nitride layer. In this embodiment, the main surface insulating layer 12 has a single-layer structure consisting of a silicon oxide layer. 【0034】 The main surface insulating layer 12 has a contact opening 13 that exposes the diode region 10. The contact opening 13 also exposes the inner peripheral edge of the guard region 11. The planar shape of the contact opening 13 is arbitrary. The contact opening 13 may be divided into a rectangular shape with four sides parallel to the sides 5A to 5D in a plan view. 【0035】 The periphery of the main surface insulating layer 12 is exposed from the sides 5A to 5D. In this configuration, the periphery of the main surface insulating layer 12 is continuous with the sides 5A to 5D. The periphery of the main surface insulating layer 12 may be formed with a gap inward from the sides 5A to 5D. In this case, the main surface insulating layer 12 exposes the portion located in the outer region 9 on the first main surface 3. 【0036】 The thickness of the main surface insulating layer 12 may be 0.1 μm or more and 10 μm or less. The thickness of the main surface insulating layer 12 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. Preferably, the thickness of the main surface insulating layer 12 is 0.5 μm or more and 5 μm or less. 【0037】 The semiconductor device 1 includes a first main surface electrode 21 (electrode) formed on a first main surface 3. The first main surface electrode 21 is connected to a diode region 10 and a guard region 11 within a contact opening 13. The first main surface electrode 21 extends from the contact opening 13 onto the main surface insulating layer 12. The periphery of the first main surface electrode 21 is formed on the main surface insulating layer 12 with a gap inward from the sides 5A to 5D. As a result, the first main surface electrode 21 exposes the periphery of the main surface insulating layer 12. 【0038】 The thickness T1 of the first main surface electrode 21 may be 10 μm or more and 100 μm or less. The thickness T1 may be 10 μm or more and 20 μm or less, 20 μm or more and 40 μm or less, 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, or 80 μm or more and 100 μm or less. It is preferable that the thickness T1 is 20 μm or more and 60 μm or less. 【0039】 Specifically, the first main surface electrode 21 has a laminated structure including a barrier electrode 22 and a main electrode 23 stacked in this order from the first main surface 3 side. The barrier electrode 22 is formed in a film-like manner along the first main surface 3 and the main surface insulating layer 12. The barrier electrode 22 forms a Schottky junction with the diode region 10. This forms an SBD having the first main surface electrode 21 as the anode and the diode region 10 as the cathode. In other words, the first main surface electrode 21 is the anode electrode of the SBD. 【0040】 The barrier electrode 22 may include at least one of the following layers: Ti layer, Pd layer, Cr layer, V layer, Mo layer, W layer, Pt layer, and Ni layer. The thickness of the barrier electrode 22 may be 0.01 μm or more and 1 μm or less. The thickness of the barrier electrode 22 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less. 【0041】 The main electrode 23 is formed as a film on the barrier electrode 22. The main electrode 23 covers the entire main surface of the barrier electrode 22. The main electrode 23 consists of an Al-based metal layer. Specifically, the main electrode 23 includes at least one of the following: a pure Al layer (an Al layer with a purity of 99% or more), an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer. 【0042】 The main electrode 23 may have a laminated structure in which two or more of the following are stacked in any order: a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer. The main electrode 23 may have a single-layer structure consisting of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer. It is preferable that the main electrode 23 has a single-layer structure consisting of an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer. 【0043】 The thickness of the main electrode 23 exceeds the thickness of the barrier electrode 22. The thickness of the main electrode 23 may be 10 μm or more and 100 μm or less. The thickness of the main electrode 23 may be 10 μm or more and 20 μm or less, 20 μm or more and 40 μm or less, 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, or 80 μm or more and 100 μm or less. Preferably, the thickness of the main electrode 23 is 20 μm or more and 60 μm or less. Since the thickness of the barrier electrode 22 is extremely small compared to the thickness of the main electrode 23, the thickness T1 of the first main surface electrode 21 is approximated by the thickness of the main electrode 23. 【0044】 The semiconductor device 1 includes an insulating layer 24 that covers the first main surface electrode 21 on the first main surface 3. In Figure 1, the insulating layer 24 is shown by hatching. Specifically, the insulating layer 24 is formed on the main surface insulating layer 12. The periphery of the insulating layer 24 is formed with a gap inward from the sides 5A to 5D. As a result, the insulating layer 24 exposes the periphery of the main surface insulating layer 12. 【0045】 The periphery of the insulating layer 24 is divided into a dicing street 25 between it and sides 5A to 5D. The dicing street 25 prevents the insulating layer 24 from being physically cut when cutting the semiconductor device 1 from the wafer. This allows for smooth cutting of the semiconductor device 1 from the wafer while simultaneously suppressing peeling and degradation of the insulating layer 24. As a result, the insulating layer 24 can properly protect objects to be protected, such as the SiC chip 2 and the first main surface electrode 21. 【0046】 The width of the dicing street 25 may be 1 μm or more and 25 μm or less. The width of the dicing street 25 is the width in the direction perpendicular to the direction in which the dicing street 25 extends. The width of the dicing street 25 may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, or 20 μm or more and 25 μm or less. 【0047】 The insulating layer 24 has a pad opening 26 that exposes the first main surface electrode 21. The pad opening 26 exposes the first main surface electrode 21 within the region surrounded by the contact opening 13 in a plan view. The pad opening 26 may surround the contact opening 13 in a region outside the contact opening 13 in a plan view. The planar shape of the pad opening 26 is arbitrary. The pad opening 26 may be formed in a rectangular shape with four sides parallel to the sides 5A to 5D in a plan view. 【0048】 Specifically, the insulating layer 24 has a laminated structure including an inorganic insulating layer 30 and an organic insulating layer 31, which are stacked in this order from the SiC chip 2 side. The inorganic insulating layer 30 is formed in a film-like manner along the main surface insulating layer 12 and the first main surface electrode 21. The inorganic insulating layer 30 includes a first inner wall 32 and a first outer wall 33. The first inner wall 32 of the inorganic insulating layer 30 defines a first opening 34 that exposes a portion of the first main surface electrode 21. The first opening 34 forms a portion of the pad opening 26. 【0049】 The first opening 34 is located within the region surrounded by the contact opening 13 in a plan view. The first opening 34 may also surround the contact opening 13 from the outside in a plan view. The planar shape of the first opening 34 is arbitrary. The first opening 34 may be located in a rectangular shape with four sides parallel to the sides 5A to 5D in a plan view. 【0050】 The first outer wall 33 of the inorganic insulating layer 30 is formed with a gap inward from the sides 5A to 5D, exposing the peripheral edge of the main surface insulating layer 12. The inorganic insulating layer 30 partitions a portion of the dicing street 25 between itself and the sides 5A to 5D. The first outer wall 33 may be formed in a rectangular shape with four sides parallel to the sides 5A to 5D in a plan view. 【0051】 The angle formed between the first inner wall 32 (the first outer wall 33) and the main surface of the first main surface electrode 21 within the inorganic insulating layer 30 may be 30° or more and 90° or less. It is preferable that the angle formed between the first inner wall 32 (the first outer wall 33) and the main surface of the first main surface electrode 21 within the inorganic insulating layer 30 is 45° or more and less than 90°. The angle of the first inner wall 32 (the first outer wall 33) is defined by the angle formed between the straight line connecting the lower end portion and the upper end portion of the first inner wall 32 (the first outer wall 33) and the main surface of the first main surface electrode 21. 【0052】 The inorganic insulating layer 30 has a property of high adhesion to Ni. The inorganic insulating layer 30 includes at least one of a silicon oxide layer and a silicon nitride layer. The inorganic insulating layer 30 may have a laminated structure including a silicon oxide layer and a silicon nitride layer laminated in this order from the SiC chip 2 side. The inorganic insulating layer 30 may have a single-layer structure composed of a silicon oxide layer or a silicon nitride layer. It is preferable that the inorganic insulating layer 30 contains an insulating material different from the main surface insulating layer 12. In this form, the inorganic insulating layer 30 has a single-layer structure composed of a silicon nitride layer. 【0053】 It is preferable that the thickness T2 of the inorganic insulating layer 30 is less than the thickness T1 of the first main surface electrode 21 (T2 < T1). The thickness T2 may be 0.1 μm or more and 10 μm or less. The thickness T2 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. It is preferable that the thickness T2 is 1 μm or more and 5 μm or less. It is particularly preferable that the thickness T2 is 1 μm or more and 2 μm or less. 【0054】 The organic insulating layer 31 is formed in a film shape on the inorganic insulating layer 30. The organic insulating layer 31 includes a second inner wall 35 and a second outer wall 36. The second inner wall 35 of the organic insulating layer 31 defines a second opening 37 that exposes a part of the first main surface electrode 21. In this form, the second inner wall 35 is formed in a curved shape recessed toward the inorganic insulating layer 30 side. 【0055】 Referring to Figure 3, the second opening 37 communicates with the first opening 34 of the inorganic insulating layer 30, forming a pad opening 26 between them. In a plan view, the second opening 37 is located within the region surrounded by the contact opening 13. In a plan view, the second opening 37 may surround the contact opening 13 from the outside. The planar shape of the second opening 37 is arbitrary. In a plan view, the second opening 37 may be located in a rectangular shape with four sides parallel to the sides 5A to 5D. 【0056】 The second opening 37 surrounds the first opening 34 at a distance from it, exposing a portion of the inorganic insulating layer 30. Specifically, the organic insulating layer 31 exposes a portion of the main surface of the inorganic insulating layer 30 as an inner peripheral edge 38 in the region between the first opening 34 and the second opening 37. 【0057】 The width W of the inner peripheral edge 38 of the inorganic insulating layer 30 may be greater than 0 μm and less than or equal to 10 μm. The width W may be greater than 0 μm and less than or equal to 1 μm, 1 μm or more and less than or equal to 2 μm, 2 μm or more and less than or equal to 4 μm, 4 μm or more and less than or equal to 6 μm, 6 μm or more and less than or equal to 8 μm, or 8 μm or more and less than or equal to 10 μm. It is preferable that the width W is 1 μm or more and less than or equal to 5 μm. The width W is arbitrary, but it is preferable that it is less than or equal to the thickness T2 of the inorganic insulating layer 30 (W ≤ T2). It is particularly preferable that the width W is 1 μm or more and less than or equal to 2 μm. 【0058】 In this configuration, the second outer wall 36 of the organic insulating layer 31 is formed in a curved shape that is recessed toward the inorganic insulating layer 30. The second outer wall 36 is formed on the inorganic insulating layer 30 with a gap inward from the sides 5A to 5D, and partitions a part of the dicing street 25 between itself and the sides 5A to 5D. As a result, the organic insulating layer 31 exposes the peripheral edge of the main surface insulating layer 12. The second outer wall 36 may be formed in a rectangular shape with four sides parallel to the sides 5A to 5D in a plan view. 【0059】 The second outer wall 36 of the organic insulating layer 31 may be formed on the main surface insulating layer 12 across the first outer wall 33 of the inorganic insulating layer 30. In this case, the dicing street 25 is partitioned by the second outer wall 36 of the organic insulating layer 31. 【0060】 The angle formed between the second inner wall 35 (second outer wall 36) of the organic insulating layer 31 and the main surface of the inorganic insulating layer 30 within the organic insulating layer 31 may be 30° or more and 90° or less. It is preferable that the angle formed between the second inner wall 35 (second outer wall 36) and the main surface of the inorganic insulating layer 30 within the organic insulating layer 31 is 45° or more and less than 90°. The angle of the second inner wall 35 (second outer wall 36) is defined by the angle formed between the straight line connecting the lower end portion and the upper end portion of the second inner wall 35 (second outer wall 36) and the main surface of the inorganic insulating layer 30. 【0061】 The organic insulating layer 31 has a property of having lower adhesion to Ni compared to the inorganic insulating layer 30. The organic insulating layer 31 contains a negative-type or positive-type photosensitive resin. The organic insulating layer 31 may contain at least one of polyimide, polyamide, and polybenzoxazole. In this form, the organic insulating layer 31 contains polyimide. 【0062】 It is preferable that the organic insulating layer 31 has a thickness T3 (T2 < T3) that exceeds the thickness T2 of the inorganic insulating layer 30. The ratio T3 / T2 of the thickness T3 of the organic insulating layer 31 to the thickness T2 of the inorganic insulating layer 30 may be more than 1 and 10 or less. The ratio T3 / T2 may be more than 1 and 2 or less, 2 or more and 4 or less, 4 or more and 6 or less, 6 or more and 8 or less, or 8 or more and 10 or less. It is preferable that the ratio T3 / T2 is 2 or more and 6 or less. 【0063】 The thickness T3 may be 1 μm or more and 50 μm or less. The thickness T3 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less. It is preferable that the thickness T3 is 5 μm or more and 30 μm or less. 【0064】 The semiconductor device 1 includes a rough surface region 39 formed on the exposed surface of the first main surface electrode 21 that is exposed from the pad opening 26 (first opening 34 of the inorganic insulating layer 30). The rough surface region 39 includes a depression formed in the region directly below the first inner wall 32 of the inorganic insulating layer 30. As a result, the first inner wall 32 of the inorganic insulating layer 30 includes a portion that overhangs the rough surface region 39. 【0065】 The semiconductor device 1 includes a pad electrode 40 formed within a pad opening 26. The pad electrode 40 includes a Ni plating layer (metal layer) 41 formed on a first main surface electrode 21 within the pad opening 26. The Ni plating layer 41 covers the first main surface electrode 21 within the first opening 34 and covers the inner peripheral edge 38 of the inorganic insulating layer 30 within the second opening 37. The Ni plating layer 41 has an outer surface formed at a distance from the main surface of the organic insulating layer 31 (insulating layer 24) toward the first main surface electrode 21. In this embodiment, the Ni plating layer 41 covers the organic insulating layer 31 within the second opening 37. 【0066】 Referring to Figure 3, the Ni plating layer 41 has a first portion 41A that covers the first main surface electrode 21 and a second portion 41B that covers the inner peripheral edge 38 of the inorganic insulating layer 30. The first portion 41A of the Ni plating layer 41 covers the first main surface electrode 21 by filling the rough surface region 39 within the first opening 34. The first portion 41A covers the entire area of ​​the first inner wall 32 of the inorganic insulating layer 30 and protrudes from the opening end of the first opening 34 toward the opening end of the second opening 37. The first portion 41A has a first connecting portion that is connected to the first inner wall 32 of the inorganic insulating layer 30 and extends in the thickness direction of the inorganic insulating layer 30. 【0067】 The second portion 41B of the Ni plating layer 41 is drawn out from the first portion 41A toward the organic insulating layer 31 within the second opening 37. The second portion 41B is formed in an arc shape, starting from the opening end of the first opening 34 and extending toward the organic insulating layer 31. 【0068】 The second portion 41B covers the inner peripheral edge 38 of the inorganic insulating layer 30 within the second opening 37. As a result, the second portion 41B faces the first main surface electrode 21 across the inner peripheral edge 38 of the inorganic insulating layer 30. The second portion 41B is connected to the main surface of the inorganic insulating layer 30 and has a second connection portion extending in the width direction of the inorganic insulating layer 30. 【0069】 In this form, the second portion 41B further covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37. The second portion 41B covers the region on the inorganic insulating layer 30 side with respect to the middle portion of the second inner wall 35 of the organic insulating layer 31. In other words, the second portion 41B covers the organic insulating layer 31 such that the exposed area of the second inner wall 35 (organic insulating layer 31) exceeds the hidden area of the second inner wall 35 (organic insulating layer 31). Thus, the Ni plating layer 41 is formed such that the first portion 41A and the second portion 41B engage from different two directions with the opening end of the first opening 34. 【0070】 The Ni plating layer 41 has a thickness T4 (T2 < T4) that exceeds the thickness T2 of the inorganic insulating layer 30. The thickness T4 is less than the thickness T3 of the organic insulating layer 31 (T4 < T3). The thickness T4 exceeds the value obtained by adding the width W of the inner peripheral edge 38 to the thickness T2 of the inorganic insulating layer 30 (T2 + W < T4). This is the condition for the Ni plating layer 41 to contact the second inner wall 35 of the organic insulating layer 31. The thickness T4 is defined by the thickness of the Ni plating layer 41 with respect to the main surface of the first main surface electrode 21. 【0071】 The ratio T4 / T2 of the thickness T4 of the Ni plating layer 41 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than or equal to 5. The ratio T4 / T2 may be greater than 1 and less than or equal to 2, greater than or equal to 2 and less than or equal to 3, greater than or equal to 3 and less than or equal to 4, or greater than or equal to 4 and less than or equal to 5. 【0072】 The thickness T4 may be 0.1 μm or more and 15 μm or less. The thickness T4 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 3 μm or less, 3 μm or more and 6 μm or less, 6 μm or more and 9 μm or less, 9 μm or more and 12 μm or less, or 12 μm or more and 15 μm or less. The thickness T4 is preferably 2 μm or more and 8 μm or less. 【0073】 The pad electrode 40 is made of a metal material different from the Ni plating layer 41 and includes an outer plating layer 42 that covers the outer surface of the Ni plating layer 41 in the second opening 37. The outer plating layer 42 has a thickness T5 (T5 < T4) less than the thickness T4 of the Ni plating layer 41. The outer plating layer 42 covers the second inner wall 35 of the organic insulating layer 31 in the second opening 37. 【0074】 The outer plating layer 42 has a terminal surface 42A that is externally connected via a conductive bonding material (e.g., solder). The terminal surface 42A is located on the Ni plating layer 41 side with respect to the main surface of the organic insulating layer 31 (the opening end of the second opening 37). Thereby, the outer plating layer 42 exposes a part of the second inner wall 35 of the organic insulating layer 31. 【0075】 In this form, the outer plating layer 42 has a laminated structure including a Pd plating layer 43 and an Au plating layer 44 laminated in this order from the Ni plating layer 41 side. The Pd plating layer 43 is formed in a film shape along the outer surface of the Ni plating layer 41. The Pd plating layer 43 covers the Ni plating layer 41 at an interval from the opening end of the second opening 37 toward the inorganic insulating layer 30 side. The Pd plating layer 43 covers the second inner wall 35 of the organic insulating layer 31 in the second opening 37. 【0076】 The Pd plating layer 43 has a thickness less than the thickness T4 of the Ni plating layer 41. The thickness of the Pd plating layer 43 may be 0.01 μm or more and 1 μm or less. The thickness of the Pd plating layer 43 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less. 【0077】 The Au plating layer 44 is formed in a film-like manner along the outer surface of the Pd plating layer 43. The Au plating layer 44 covers the Pd plating layer 43 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. The Au plating layer 44 covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37. 【0078】 The Au plating layer 44 has a thickness less than the thickness T4 of the Ni plating layer 41. The thickness of the Au plating layer 44 may be 0.01 μm or more and 1 μm or less. The thickness of the Au plating layer 44 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less. 【0079】 The outer plating layer 42 can take on various forms as shown in Figures 4A to 4D. 【0080】 Figure 4A is a corresponding diagram to Figure 3 and is an enlarged view showing the outer plating layer 42 according to the second embodiment. The differences from the outer plating layer 42 according to the first embodiment will be explained below. 【0081】 Referring to Figure 4A, in this embodiment, the outer plating layer 42 has a single-layer structure consisting of an Au plating layer 44. The Au plating layer 44 is formed in a film-like manner along the outer surface of the Ni plating layer 41. The Au plating layer 44 covers the Ni plating layer 41 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. The Au plating layer 44 covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37. 【0082】 Figure 4B is a corresponding diagram to Figure 3 and is an enlarged view showing the outer plating layer 42 according to the third embodiment. The differences from the outer plating layer 42 according to the first embodiment will be explained below. 【0083】 Referring to Figure 4B, in this embodiment, the outer plating layer 42 has a single-layer structure consisting of a Pd plating layer 43. The Pd plating layer 43 is formed in a film-like manner along the outer surface of the Ni plating layer 41. The Pd plating layer 43 covers the Ni plating layer 41 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. The Pd plating layer 43 covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37. 【0084】 Figure 4C is a corresponding diagram to Figure 3 and is an enlarged view showing the outer plating layer 42 according to the fourth embodiment. The differences from the outer plating layer 42 according to the first embodiment will be explained below. 【0085】 Referring to Figure 4C, in this configuration, the outer plating layer 42 has a single-layer structure consisting of an Ag plating layer 45. The Ag plating layer 45 is formed in a film-like manner along the outer surface of the Ni plating layer 41. The Ag plating layer 45 covers the Ni plating layer 41 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. The Ag plating layer 45 covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37. 【0086】 The Ag plating layer 45 has a thickness less than the thickness T4 of the Ni plating layer 41. The thickness of the Ag plating layer 45 may be 0.01 μm or more and 1 μm or less. The thickness of the Ag plating layer 45 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less. 【0087】 Figure 4D is a corresponding diagram to Figure 3 and is an enlarged view showing the outer plating layer 42 according to the fifth embodiment. The differences from the outer plating layer 42 according to the first embodiment will be explained below. 【0088】 Referring to Figure 4D, the outer plating layer 42 has a laminated structure including a Pd plating layer 43, an Au plating layer 44, and an Ag plating layer 45, which are stacked in this order from the Ni plating layer 41 side. 【0089】 The Pd plating layer 43 is formed in a film-like manner along the outer surface of the Ni plating layer 41. The Pd plating layer 43 covers the Ni plating layer 41 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. The Pd plating layer 43 covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37. 【0090】 The Au plating layer 44 is formed in a film-like manner along the outer surface of the Pd plating layer 43. The Au plating layer 44 covers the Pd plating layer 43 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. The Au plating layer 44 covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37. 【0091】 The Ag plating layer 45 is formed in a film-like manner along the outer surface of the Au plating layer 44. The Ag plating layer 45 covers the Au plating layer 44 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. The Ag plating layer 45 covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37. 【0092】 Referring again to Figure 2, the semiconductor device 1 includes a second main surface electrode (back surface electrode) 46 formed on the second main surface 4. The second main surface electrode 46 covers the entire area of ​​the second main surface 4. The second main surface electrode 46 forms ohmic contact with the second main surface 4. The second main surface electrode 46 is formed as the cathode electrode of the SBD. 【0093】 The second main surface electrode 46 includes at least one of a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer. The second main surface electrode 46 may have a laminated structure in which at least two of the Ti layer, Ni layer, Pd layer, Au layer, and Ag layer are stacked in any order. The second main surface electrode 46 may have a single-layer structure consisting of a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer. It is preferable that the second main surface electrode 46 includes a Ti layer as an ohmic electrode. In this embodiment, the second main surface electrode 46 has a laminated structure including a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer stacked in this order from the second main surface 4 side. 【0094】 Figures 5A to 5O are cross-sectional views illustrating an example of a manufacturing method for the semiconductor device 1 shown in Figure 1. 【0095】 Referring to Figure 5A, first, a SiC epitaxial wafer 50, which will serve as the base for the SiC chip 2, is prepared. The SiC epitaxial wafer 50 has a stacked structure including a SiC wafer 51 and a SiC epitaxial layer 52. The SiC wafer 51 serves as the base for the SiC substrate 6. The SiC epitaxial layer 52 serves as the base for the SiC epitaxial layer 7. The SiC epitaxial layer 52 is formed by epitaxial growth of SiC from the main surface of the SiC wafer 51. 【0096】 The SiC epitaxial wafer 50 has a first wafer main surface 53 on one side and a second wafer main surface 54 on the other side. The first wafer main surface 53 and the second wafer main surface 54 correspond to the first main surface 3 and the second main surface 4 of the SiC chip 2, respectively. 【0097】 The SiC epitaxial wafer 50 has multiple device regions 55 corresponding to each semiconductor device 1, and cutting lines 56 that demarcate the multiple device regions 55. In Figure 5A, one device region 55 is shown, and the other regions are not shown (the same applies to Figures 5B to 5O below). The multiple device regions 55 are arranged in a matrix along the first direction X and the second direction Y. The cutting lines 56 are arranged in a grid extending along the first direction X and the second direction Y. 【0098】 Next, referring to Figure 5B, the main parts of the functional device are formed in each device region 55. In this configuration, n-type impurities and / or p-type impurities are selectively introduced into the surface layer of the first wafer main surface 53 to form an n-type diode region 10 and a p-type guard region 11. The n-type impurities and / or p-type impurities are introduced into the surface layer of the first wafer main surface 53 by an ion implantation method via an ion implantation mask (not shown). 【0099】 Next, referring to Figure 5C, the main surface insulating layer 12 is formed on the first wafer main surface 53. The main surface insulating layer 12 may be formed by CVD (Chemical Vapor Deposition) and / or oxidation treatment (e.g., thermal oxidation treatment). 【0100】 Next, referring to Figure 5D, a resist mask 57 having a predetermined pattern is formed on the main surface insulating layer 12. The resist mask 57 exposes the area in the main surface insulating layer 12 where the contact openings 13 are to be formed, and covers the other areas. Next, the unnecessary portion of the main surface insulating layer 12 is removed by an etching method via the resist mask 57. The etching method may be a wet etching method and / or a dry etching method. As a result, the contact openings 13 are formed in the main surface insulating layer 12. 【0101】 Next, referring to Figure 5E, a base electrode layer 58, which will serve as the base for the first main surface electrode 21, is formed on the main surface insulating layer 12. The base electrode layer 58 has a laminated structure including a barrier electrode 22 and a main electrode 23, which are stacked in this order from the main surface insulating layer 12 side. The barrier electrode 22 and the main electrode 23 may be formed by sputtering and / or vapor deposition, respectively. 【0102】 Next, referring to Figure 5F, a resist mask 59 having a predetermined pattern is formed on the base electrode layer 58. The resist mask 59 exposes the area on the base electrode layer 58 where the first main surface electrode 21 is to be formed, and covers the other areas. Next, the unnecessary portion of the base electrode layer 58 is removed by an etching method via the resist mask 59. The etching method may be a wet etching method and / or a dry etching method. As a result, the first main surface electrode 21 is formed on the main surface insulating layer 12. 【0103】 Next, referring to Figure 5G, an inorganic insulating layer 30 is formed on the main surface insulating layer 12 so as to cover the first main surface electrode 21. In this embodiment, the inorganic insulating layer 30 has a single-layer structure consisting of a silicon nitride layer. The inorganic insulating layer 30 may also have a laminated structure including a silicon oxide layer and a silicon nitride layer stacked in this order from the SiC epitaxial wafer 50 side. The inorganic insulating layer 30 may be formed by the CVD method. 【0104】 Next, referring to Figure 5H, a resist mask 60 having a predetermined pattern is formed on the inorganic insulating layer 30. The resist mask 60 exposes the areas in the inorganic insulating layer 30 where the first opening 34 and dicing street 25 are to be formed, and covers the areas other than those. 【0105】 Next, any unwanted portions of the inorganic insulating layer 30 are removed by etching through the resist mask 60. The etching method may be wet etching and / or dry etching. This forms a first opening 34 that exposes the first main surface electrode 21, and dicing streets 25 that extend in a grid pattern along the planned cutting line 56, in the inorganic insulating layer 30. 【0106】 Next, referring to Figure 5I, an organic insulating layer 31 is formed on the main surface insulating layer 12 so as to cover the first main surface electrode 21 and the inorganic insulating layer 30. The organic insulating layer 31 is formed by applying polyimide, as an example of a photosensitive resin, to the first wafer main surface 53 side. 【0107】 Next, referring to Figure 5J, the organic insulating layer 31 is exposed in a pattern corresponding to the second aperture 37 and the dicing street 25, and then developed. This forms the second aperture 37, which exposes the first main surface electrode 21, and the dicing street 25, which extends in a grid pattern along the planned cutting line 56, on the organic insulating layer 31. 【0108】 The second opening 37 of the organic insulating layer 31 is formed to surround the first opening 34 of the inorganic insulating layer 30, with a gap between them. This results in the formation of an organic insulating layer 31 that exposes the inner peripheral edge 38 of the inorganic insulating layer 30 in the region between the first opening 34 and the second opening 37. 【0109】 Next, referring to Figure 5K, a rough surface region 39 is formed on the portion of the first main surface electrode 21 that is exposed from the first opening 34 and the second opening 37. The rough surface region 39 is formed by a zincate treatment method (zinc substitution treatment method) on the exposed portion of the first main surface electrode 21. 【0110】 Next, referring to Figure 5L, the Ni plating layer 41 is formed on the portion of the first main surface electrode 21 that is exposed from the first opening 34 and the second opening 37. The Ni plating layer 41 is formed by depositing Ni from the first main surface electrode 21 by electroplating or electroless plating (electroless plating in this embodiment). This forms a Ni plating layer 41 that covers the first main surface electrode 21 within the first opening 34 and covers the inner peripheral edge 38 of the inorganic insulating layer 30 within the second opening 37. The specific structure of the Ni plating layer 41 is as described above, so a further explanation is omitted. 【0111】 Next, referring to Figure 5M, the outer plating layer 42 is formed on the outer surface of the Ni plating layer 41 within the second opening 37. The outer plating layer 42 includes at least one of the Pd plating layer 43, the Au plating layer 44, and the Ag plating layer 45. The outer plating layer 42 is formed by depositing any of the materials from Pd, Au, and Ag from the first main surface electrode 21 by electroplating or electroless plating (electroless plating in this embodiment). 【0112】 Next, referring to Figure 5N, the SiC epitaxial wafer 50 is thinned to a desired thickness by grinding the second wafer main surface 54. The second wafer main surface 54 may be ground by the CMP (Chemical Mechanical Polishing) method. After the grinding process of the second wafer main surface 54, annealing may be performed on the second wafer main surface 54. The annealing may be performed by laser irradiation. As a result, the second wafer main surface 54 (second main surface 4) becomes an ohmic surface. 【0113】 Next, referring to Figure 5O, a second main surface electrode 46 is formed on the second wafer main surface 54. The second main surface electrode 46 may be formed by sputtering, vapor deposition, and / or plating. Subsequently, the SiC epitaxial wafer 50 is cut or cleaved along the dicing street 25 to cut out a plurality of semiconductor devices 1. The semiconductor device 1 is manufactured through the process including the above. 【0114】 As described above, the semiconductor device 1 includes a SiC chip 2, a first main surface electrode 21, an inorganic insulating layer 30, an organic insulating layer 31, and a Ni plating layer 41. The first main surface electrode 21 is formed on the SiC chip 2. The inorganic insulating layer 30 covers the first main surface electrode 21 and has a first opening 34 that exposes the first main surface electrode 21. The organic insulating layer 31 covers the inorganic insulating layer 30 and has a second opening 37 that surrounds the first opening 34 at a distance from the first opening 34, exposing the inner peripheral edge 38 of the inorganic insulating layer 30 in the region between the first opening 34 and the second opening 37. The Ni plating layer 41 is connected to the first main surface electrode 21 within the first opening 34 and covers the inner peripheral edge 38 of the inorganic insulating layer 30 within the second opening 37. 【0115】 The inorganic insulating layer 30 has high adhesion to Ni, while the organic insulating layer 31 has lower adhesion to Ni compared to the inorganic insulating layer 30. Therefore, for example, if the inorganic insulating layer 30 is absent, or if the organic insulating layer 31 is formed flush with the inorganic insulating layer 30, the Ni plating layer 41 forms a gap between itself and the organic insulating layer 31 that extends toward the first main surface electrode 21. As a result, the connection of the Ni plating layer 41 to the first main surface electrode 21 becomes insufficient, and the reliability of the Ni plating layer 41 decreases. 【0116】 Therefore, the semiconductor device 1 employs a structure in which an organic insulating layer 31 is formed that exposes the inner peripheral edge 38 of an inorganic insulating layer 30 having high adhesion to Ni, and a Ni plating layer 41 covers the inner peripheral edge 38 of the inorganic insulating layer 30. In this case, the Ni plating layer 41 forms a first connection portion extending in the thickness direction of the inorganic insulating layer 30 and a second connection portion extending in the width direction of the inorganic insulating layer 30 between itself and the inorganic insulating layer 30. 【0117】 This allows the gap formation region to be moved away from the first main surface electrode 21, while simultaneously effectively suppressing the formation of gaps extending toward the first main surface electrode 21. Furthermore, compared to the case where the inner peripheral edge 38 of the inorganic insulating layer 30 is absent, the gap formation region between it and the organic insulating layer 31 can be reduced. Thus, the reliability of the Ni plating layer 41 can be improved. 【0118】 In semiconductor device 1, the second portion 41B of the Ni plating layer 41 covers the region on the inorganic insulating layer 30 side of the intermediate portion of the second inner wall 35 of the organic insulating layer 31. In other words, the second portion 41B of the Ni plating layer 41 covers the organic insulating layer 31 such that the concealed area of ​​the second inner wall 35 (organic insulating layer 31) is less than the exposed area of ​​the second inner wall 35 (organic insulating layer 31). With such a Ni plating layer 41, the area where gaps are formed can be appropriately reduced. 【0119】 The semiconductor device 1 further includes an outer plating layer 42 that covers the outer surface of the Ni plating layer 41. With this structure, the formation of a gap between the organic insulating layer 31 and the Ni plating layer 41 is suppressed, so that the entry of the plating solution into the gap can be suppressed. This suppresses abnormal film formation of the outer plating layer 42 starting from the gap. As a result, poor connection of the Ni plating layer 41 caused by abnormal film formation of the outer plating layer 42 can be suppressed, and at the same time, peeling (poor connection) of the outer plating layer 42 can be suppressed. 【0120】 The outer plating layer 42 specifically includes at least one of the Pd plating layer 43, the Au plating layer 44, and the Ag plating layer 45. Therefore, poor connectivity of the Ni plating layer 41 caused by abnormal film formation of the Pd plating layer 43, the Au plating layer 44, and the Ag plating layer 45 can be suppressed. At the same time, peeling (poor connectivity) of the Pd plating layer 43, the Au plating layer 44, and the Ag plating layer 45 can be suppressed. 【0121】 Figure 6 is a corresponding diagram to Figure 2, and is a cross-sectional view showing a semiconductor device 61 according to a second embodiment of the present invention together with the outer plating layer 42 according to the first embodiment. Figure 7 is an enlarged view of region VII shown in Figure 6. Hereinafter, structures corresponding to the structures described for the semiconductor device 1 will be given the same reference numerals and their descriptions will be omitted. 【0122】 Referring to Figures 6 and 7, the organic insulating layer 31 exposes the inner peripheral edge 38 of the inorganic insulating layer 30 in the region between the first opening 34 and the second opening 37. The width W of the inner peripheral edge 38 of the inorganic insulating layer 30 is arbitrary, but it is preferable that it exceeds the thickness T2 of the inorganic insulating layer 30 (T2 <W)。 【0123】 The ratio W / T2 of the width W of the inner edge 38 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than or equal to 10. The ratio W / T2 may be greater than 1 and less than or equal to 2, 2 to 4, 4 to 6, 6 to 8, or 8 to 10. Preferably, the ratio W / T2 is 2 to 5. The width W may be greater than 0 μm and less than or equal to 10 μm. The width W may be greater than 0 μm and less than or equal to 2 μm, 2 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, or 8 μm to 10 μm. 【0124】 The Ni plating layer 41 is formed on the first main surface electrode 21 within the pad opening 26. The Ni plating layer 41 covers the first main surface electrode 21 within the first opening 34 and covers the inner peripheral edge 38 of the inorganic insulating layer 30 within the second opening 37. The Ni plating layer 41 has an outer surface formed at a distance from the main surface of the organic insulating layer 31 (insulating layer 24) toward the first main surface electrode 21. The Ni plating layer 41 covers the inner peripheral edge 38 of the inorganic insulating layer 30 at a distance from the organic insulating layer 31 within the second opening 37. 【0125】 The Ni plating layer 41 specifically has a first portion 41A that covers the first main surface electrode 21, and a second portion 41B that covers the inner peripheral edge 38 of the inorganic insulating layer 30. The first portion 41A of the Ni plating layer 41 covers the first main surface electrode 21 by filling the rough surface region 39 within the first opening 34. The first portion 41A covers the entire area of ​​the first inner wall 32 of the inorganic insulating layer 30 within the first opening 34 and protrudes from the opening end of the first opening 34 toward the opening end of the second opening 37. The first portion 41A has a first connecting portion that is connected to the first inner wall 32 of the inorganic insulating layer 30 and extends in the thickness direction of the inorganic insulating layer 30. 【0126】 The second portion 41B of the Ni plating layer 41 is drawn out from the first portion 41A toward the organic insulating layer 31 within the second opening 37. The second portion 41B is formed in an arc shape, starting from the opening end of the first opening 34 and extending toward the second inner wall 35 of the organic insulating layer 31. 【0127】 The second part 41B covers the inner peripheral edge 38 of the inorganic insulating layer 30 within the second opening 37. In this form, the second part 41B partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 at an interval from the second inner wall 35 of the organic insulating layer 31 to the first inner wall 32 side of the inorganic insulating layer 30 within the second opening 37 such that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. 【0128】 Thereby, the Ni plating layer 41 exposes a part of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire second inner wall 35 of the organic insulating layer 31. The second part 41B faces the first main surface electrode 21 across the inner peripheral edge 38 of the inorganic insulating layer 30. The second part 41B is connected to the main surface of the inorganic insulating layer 30 and has a second connection portion extending in the width direction of the inorganic insulating layer 30. 【0129】 The Ni plating layer 41 has a thickness T4 (T2 < T4) exceeding the thickness T2 of the inorganic insulating layer 30. The thickness T4 is less than the thickness T3 of the organic insulating layer 31 (T4 < T3). The thickness T4 is less than the value (T2 + W) obtained by adding the width W of the inner peripheral edge 38 to the thickness T2 of the inorganic insulating layer 30 (T4 < T2 + W). This is the condition for the Ni plating layer 41 to expose the second inner wall 35 of the organic insulating layer 31. The thickness T4 is defined by the thickness of the Ni plating layer 41 with reference to the main surface of the first main surface electrode 21. 【0130】 The ratio T4 / T2 of the thickness T4 of the Ni plating layer 41 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than or equal to 5. The ratio T4 / T2 may be greater than 1 and less than or equal to 2, greater than or equal to 2 and less than or equal to 3, greater than or equal to 3 and less than or equal to 4, or greater than or equal to 4 and less than or equal to 5. The thickness T4 may be greater than or equal to 0.1 μm and less than or equal to 10 μm. The thickness T4 may be greater than or equal to 0.1 μm and less than or equal to 1 μm, greater than or equal to 1 μm and less than or equal to 2 μm, greater than or equal to 2 μm and less than or equal to 4 μm, greater than or equal to 4 μm and less than or equal to 6 μm, greater than or equal to 6 μm and less than or equal to 8 μm, or greater than or equal to 8 μm and less than or equal to 10 μm. 【0131】 The outer plating layer 42 covers the outer surface of the Ni plating layer 41 within the second opening 37. The outer plating layer 42 has a thickness T5 (T5 < T4) less than the thickness T4 of the Ni plating layer 41. In this form, the outer plating layer 42 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 at an interval from the second inner wall 35 of the organic insulating layer 31 toward the first inner wall 32 of the inorganic insulating layer 30 within the second opening 37. 【0132】 The outer plating layer 42 has a terminal surface 42A that is externally connected via a conductive bonding material (e.g., solder). The terminal surface 42A is located on the Ni plating layer 41 side with respect to the main surface of the organic insulating layer 31 (the opening end of the second opening 37). Thereby, the outer plating layer 42 exposes a part of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire second inner wall 35 of the organic insulating layer 31 within the second opening 37. 【0133】 Specifically, the outer plating layer 42 has a laminated structure including a Pd plating layer 43 and an Au plating layer 44 laminated in this order from the Ni plating layer 41 side. The Pd plating layer 43 is formed in a film shape along the outer surface of the Ni plating layer 41. The Pd plating layer 43 covers the Ni plating layer 41 at an interval from the opening end of the second opening 37 toward the inorganic insulating layer 30 side. The Pd plating layer 43 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 at an interval from the second inner wall 35 of the organic insulating layer 31 toward the first inner wall 32 of the inorganic insulating layer 30 within the second opening 37 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. Thereby, the Pd plating layer 43 exposes a part of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire second inner wall 35 of the organic insulating layer 31 within the second opening 37. 【0134】 The Pd plating layer 43 has a thickness less than the thickness T4 of the Ni plating layer 41. The thickness of the Pd plating layer 43 may be 0.01 μm or more and 1 μm or less. The thickness of the Pd plating layer 43 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less. 【0135】 The Au plating layer 44 is formed in a film-like manner along the outer surface of the Pd plating layer 43. The Au plating layer 44 covers the Pd plating layer 43 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. Within the second opening 37, the Au plating layer 44 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 with a gap from the second inner wall 35 of the organic insulating layer 31 toward the first inner wall 32 of the inorganic insulating layer 30, so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. As a result, within the second opening 37, the Au plating layer 44 exposes a part of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire second inner wall 35 of the organic insulating layer 31. 【0136】 The Au plating layer 44 has a thickness less than the thickness T4 of the Ni plating layer 41. The thickness of the Au plating layer 44 may be 0.01 μm or more and 1 μm or less. The thickness of the Au plating layer 44 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less. 【0137】 In this embodiment, an example was described in which an outer plating layer 42 is formed that exposes the entire second inner wall 35 of the organic insulating layer 31. However, an outer plating layer 42 that covers only a portion of the second inner wall 35 of the organic insulating layer 31 may also be used. In this case, at least one of the Pd plating layer 43 and the Au plating layer 44 may cover a portion of the second inner wall 35 of the organic insulating layer 31. The outer plating layer 42 can take various forms as shown in Figures 8A to 8D. 【0138】 Figure 8A is a corresponding diagram to Figure 7 and is an enlarged view showing the outer plating layer 42 according to the second embodiment. The differences from the outer plating layer 42 according to the first embodiment will be explained below. 【0139】 Referring to Figure 8A, in this embodiment, the outer plating layer 42 has a single-layer structure consisting of an Au plating layer 44. The Au plating layer 44 is formed in a film-like manner along the outer surface of the Ni plating layer 41. Within the second opening 37, the Au plating layer 44 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30, leaving a gap between the second inner wall 35 of the organic insulating layer 31 and the first inner wall 32 of the inorganic insulating layer 30, such that a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. 【0140】 The Au plating layer 44 covers the Ni plating layer 41 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. As a result, the Au plating layer 44 exposes a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire second inner wall 35 of the organic insulating layer 31 within the second opening 37. The Au plating layer 44 may also cover a portion of the second inner wall 35 of the organic insulating layer 31. 【0141】 Figure 8B is a corresponding diagram to Figure 7 and is an enlarged view showing the outer plating layer 42 according to the third embodiment. The differences from the outer plating layer 42 according to the first embodiment will be explained below. 【0142】 Referring to Figure 8B, in this embodiment, the outer plating layer 42 has a single-layer structure consisting of a Pd plating layer 43. The Pd plating layer 43 is formed in a film-like manner along the outer surface of the Ni plating layer 41. Within the second opening 37, the Pd plating layer 43 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30, leaving a gap between the second inner wall 35 of the organic insulating layer 31 and the first inner wall 32 of the inorganic insulating layer 30, such that a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. 【0143】 The Pd plating layer 43 covers the Ni plating layer 41 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. As a result, the Pd plating layer 43 exposes a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire second inner wall 35 of the organic insulating layer 31 within the second opening 37. The Pd plating layer 43 may also cover a portion of the second inner wall 35 of the organic insulating layer 31. 【0144】 Figure 8C is a corresponding diagram to Figure 7 and is an enlarged view showing the outer plating layer 42 according to the fourth embodiment. The differences from the outer plating layer 42 according to the first embodiment will be explained below. 【0145】 Referring to Figure 8C, in this embodiment, the outer plating layer 42 has a single-layer structure consisting of an Ag plating layer 45. The Ag plating layer 45 is formed in a film-like manner along the outer surface of the Ni plating layer 41. Within the second opening 37, the Ag plating layer 45 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30, leaving a gap between the second inner wall 35 of the organic insulating layer 31 and the first inner wall 32 of the inorganic insulating layer 30, such that a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. 【0146】 The Ag plating layer 45 covers the Ni plating layer 41 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. As a result, the Ag plating layer 45 exposes a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire second inner wall 35 of the organic insulating layer 31 within the second opening 37. The Ag plating layer 45 may also cover a portion of the second inner wall 35 of the organic insulating layer 31. 【0147】 The Ag plating layer 45 has a thickness less than the thickness T4 of the Ni plating layer 41. The thickness of the Ag plating layer 45 may be 0.01 μm or more and 1 μm or less. The thickness of the Ag plating layer 45 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less. 【0148】 Figure 8D is a corresponding diagram to Figure 7 and is an enlarged view showing the outer plating layer 42 according to the fifth embodiment. The differences from the outer plating layer 42 according to the first embodiment will be explained below. 【0149】 Referring to Figure 8D, the outer plating layer 42 has a laminated structure including a Pd plating layer 43, an Au plating layer 44, and an Ag plating layer 45, which are stacked in this order from the Ni plating layer 41 side. 【0150】 The Pd plating layer 43 is formed in a film-like manner along the outer surface of the Ni plating layer 41. Within the second opening 37, the Pd plating layer 43 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30, leaving a gap between the second inner wall 35 of the organic insulating layer 31 and the first inner wall 32 of the inorganic insulating layer 30, such that a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. The Pd plating layer 43 covers the Ni plating layer 41, leaving a gap between the opening end of the second opening 37 and the inorganic insulating layer 30. As a result, within the second opening 37, the Pd plating layer 43 exposes a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire second inner wall 35 of the organic insulating layer 31. 【0151】 The Au plating layer 44 is formed in a film-like manner along the outer surface of the Pd plating layer 43. Within the second opening 37, the Au plating layer 44 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30, leaving a gap between the second inner wall 35 of the organic insulating layer 31 and the first inner wall 32 of the inorganic insulating layer 30, so that a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. The Au plating layer 44 covers the Pd plating layer 43, leaving a gap between the opening end of the second opening 37 and the inorganic insulating layer 30. As a result, within the second opening 37, the Au plating layer 44 exposes a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire second inner wall 35 of the organic insulating layer 31. 【0152】 The Ag plating layer 45 is formed in a film-like manner along the outer surface of the Au plating layer 44. Within the second opening 37, the Ag plating layer 45 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30, leaving a gap from the second inner wall 35 of the organic insulating layer 31 toward the first inner wall 32 of the inorganic insulating layer 30, such that a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. The Ag plating layer 45 covers the Au plating layer 44, leaving a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. As a result, within the second opening 37, the Ag plating layer 45 exposes a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire second inner wall 35 of the organic insulating layer 31. At least one of the Pd plating layer 43, Au plating layer 44, and Ag plating layer 45 may cover a portion of the second inner wall 35 of the organic insulating layer 31. 【0153】 As described above, the semiconductor device 61 can achieve the same effects as those described for the semiconductor device 1. In particular, the Ni plating layer 41 of the semiconductor device 61 covers the inner peripheral edge 38 of the inorganic insulating layer 30 at a distance from the organic insulating layer 31 within the second opening 37. This prevents the formation of undesirable gaps between the organic insulating layer 31 and the Ni plating layer 41. Therefore, the reliability of the Ni plating layer 41 can be reliably improved. 【0154】 Furthermore, the semiconductor device 61 includes an outer plating layer 42 that covers the outer surface of the Ni plating layer 41. With this structure, no gap is formed between the organic insulating layer 31 and the Ni plating layer 41, so the outer plating layer 42 can be properly formed along the outer surface of the Ni plating layer 41. Therefore, poor connectivity of the Ni plating layer 41 caused by abnormal film formation of the outer plating layer 42 can be properly suppressed, and at the same time, peeling (poor connectivity) of the outer plating layer 42 can be properly suppressed. 【0155】 The outer plating layer 42 specifically includes at least one of the Pd plating layer 43, the Au plating layer 44, and the Ag plating layer 45. Therefore, poor connectivity of the Ni plating layer 41 caused by abnormal film formation of the Pd plating layer 43, the Au plating layer 44, and the Ag plating layer 45 can be suppressed. At the same time, peeling (poor connectivity) of the Pd plating layer 43, the Au plating layer 44, and the Ag plating layer 45 can be suppressed. 【0156】 Figure 9 is a plan view showing the semiconductor device 101 according to the third embodiment. Figure 10 is an enlarged view of region X shown in Figure 9. Figure 11 is a cross-sectional view along the line XI-XI shown in Figure 10. Figure 12 is a cross-sectional view along the line XII-XII shown in Figure 9. Figure 13 is an enlarged view of region XIII shown in Figure 12. Figure 14 is an enlarged view of region XIV shown in Figure 12. Hereafter, structures corresponding to the structures described for semiconductor device 1 will be given the same reference numerals and their descriptions will be omitted. 【0157】 Referring to Figures 9 to 14, semiconductor device 101 is a SiC semiconductor device in which a MISFET (Metal Insulator Semiconductor Field Effect Transistor), as an example of a functional device, is formed in the active region 8 instead of an SBD. 【0158】 The semiconductor device 101 includes a SiC chip 2, a main surface insulating layer 12, a first main surface electrode 21, an insulating layer 24, a pad electrode 40, and a second main surface electrode (back surface electrode) 46. In Figure 9, the insulating layer 24 is shown by hatching. The first main surface 3 and the second main surface 4 of the SiC chip 2 are formed in a square shape (rectangular in this embodiment) in plan view. 【0159】 The first side surface 5A and the second side surface 5B extend along the first direction X and face the second direction Y which intersects the first direction X. The first side surface 5A and the second side surface 5B form the short side of the SiC chip 2. The third side surface 5C and the fourth side surface 5D extend along the second direction Y and face the first direction X. The third side surface 5C and the fourth side surface 5D form the long side of the SiC chip 2. 【0160】 The length of the first side surface 5A (second side surface 5B) may be 0.1 mm or more and 8 mm or less. Preferably, the length of the first side surface 5A (second side surface 5B) is 0.1 mm or more and 2.5 mm or less. The length of the third side surface 5C (fourth side surface 5D) may be 0.2 mm or more and 16 mm or less. Preferably, the length of the third side surface 5C (fourth side surface 5D) is 0.5 mm or more and 5 mm or less. 【0161】 The SiC chip 2 has a multilayer structure including a SiC substrate 6 and a SiC epitaxial layer 7, similar to the first embodiment. The SiC substrate 6 is formed as the drain region of the MISFET. The SiC epitaxial layer 7 is formed as the drift region of the MISFET. 【0162】 In this configuration, the SiC epitaxial layer 7 has different n-type impurity concentrations along the normal direction Z. Specifically, the SiC epitaxial layer 7 includes a high-concentration region 102 with a high n-type impurity concentration, and a low-concentration region 103 with a lower n-type impurity concentration than the high-concentration region 102. 【0163】 The high-concentration region 102 is formed in the region on the first main surface 3 side. The low-concentration region 103 is formed in the region on the second main surface 4 side relative to the high-concentration region 102. The thickness of the high-concentration region 102 is less than the thickness of the low-concentration region 103. The thickness of the high-concentration region 102 is less than half the total thickness of the SiC epitaxial layer 7. 【0164】 The n-type impurity concentration in the high-concentration region 102 is 1.0 × 10⁻⁶. 16 cm -3 The above 1.0 × 10 18 cm -3 The following may also apply: The n-type impurity concentration in the low-concentration region 103 is 1.0 × 10⁻⁶. 15 cm -3 The above 1.0 × 10 16 cm -3 The following may also be true. Of course, the n-type impurity concentration of the SiC epitaxial layer 7 is 1.0 × 10⁻⁶. 15 cm -3 The above 1.0 × 10 18 cm -3 The SiC substrate 6 may have a concentration gradient in which the n-type impurity concentration gradually decreases toward the first main surface 3, within the following range. 【0165】 The active region 8 is formed in the central part of the SiC chip 2, spaced inward from the sides 5A to 5D in a plan view. The active region 8 is formed in a rectangular shape with four sides parallel to the sides 5A to 5D in a plan view. On the other hand, the outer region 9 is formed in a rectangular ring shape surrounding the active region 8 in a plan view. 【0166】 The semiconductor device 101 includes a plurality of trench gate structures 104 formed on the first main surface 3 in the active region 8. Each of the plurality of trench gate structures 104 is formed in a strip shape extending along the first direction X and is formed with gaps in the second direction Y. In a plan view, the plurality of trench gate structures 104 are formed in a stripe shape extending along the first direction X. 【0167】 In this configuration, the multiple trench gate structures 104 extend in a band-like shape from the periphery of one side (the third side surface 5C) to the periphery of the other side (the fourth side surface 5D) in the active region 8. The multiple trench gate structures 104 traverse the intermediate portion between the periphery of one side and the periphery of the other side in the active region 8. 【0168】 The length of each trench gate structure 104 may be 1 mm or more and 10 mm or less. The length of each trench gate structure 104 may be 1 mm or more and 2 mm or less, 2 mm or more and 4 mm or less, 4 mm or more and 6 mm or less, 6 mm or more and 8 mm or less, or 8 mm or more and 10 mm or less. Preferably, the length of each trench gate structure 104 is 2 mm or more and 6 mm or less. The total length per unit area of ​​one trench gate structure 104 is 0.5 μm / μm 2 More than 0.75μm / μm 2 The following is also acceptable. 【0169】 Each trench gate structure 104 includes a gate trench 105, a gate insulating layer 106, and a gate electrode 107. In Figure 10, the gate insulating layer 106 and the gate electrode 107 are indicated by hatching. 【0170】 The gate trench 105 is formed in the SiC epitaxial layer 7. The gate trench 105 includes side walls and a bottom wall. The side walls forming the long sides of the gate trench 105 are formed by the a-plane of the SiC single crystal. The side walls forming the short sides of the gate trench 105 are formed by the m-plane of the SiC single crystal. 【0171】 The side walls of the gate trench 105 may extend along the normal direction Z. The angle that the side walls of the gate trench 105 make with respect to the first main surface 3 within the SiC chip 2 may be between 90° and 95° (for example, between 91° and 93°). The side walls of the gate trench 105 may be formed substantially perpendicular to the first main surface 3. The gate trench 105 may be formed in a tapered shape, with the opening width narrowing from the first main surface 3 towards the bottom wall. 【0172】 The bottom wall of the gate trench 105 is located in the high-concentration region 102. The bottom wall of the gate trench 105 faces the c-plane of the SiC single crystal. The bottom wall of the gate trench 105 has an off-angle inclined in the a-axis direction with respect to the c-plane of the SiC single crystal. The bottom wall of the gate trench 105 may be formed parallel to the first main surface 3. The bottom wall of the gate trench 105 may be formed in a curved shape toward the second main surface 4. 【0173】 The gate trench 105 has a first depth D1. The first depth D1 may be 0.5 μm or more and 3 μm or less. The first depth D1 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less. 【0174】 The width of the gate trench 105 along the second direction Y may be 0.1 μm or more and 2 μm or less. The width of the gate trench 105 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less. 【0175】 The opening edge of the gate trench 105 includes an inclined portion that slopes downward from the first main surface 3 toward the inside of the gate trench 105. The opening edge of the gate trench 105 is the portion that connects the first main surface 3 and the side wall of the gate trench 105. The inclined portion of the gate trench 105 is formed in a curved shape that is recessed toward the SiC chip 2. The inclined portion of the gate trench 105 may also be formed in a curved shape toward the gate trench 105. The inclined portion of the gate trench 105 mitigates electric field concentration toward the opening edge of the gate trench 105. 【0176】 The gate insulating layer 106 comprises at least one of silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, and tantalum oxide. The gate insulating layer 106 may have a laminated structure in which silicon oxide layers and silicon nitride layers are stacked in any order. The gate insulating layer 106 may have a single-layer structure consisting of silicon oxide layers or silicon nitride layers. In this embodiment, the gate insulating layer 106 has a single-layer structure consisting of silicon oxide layers. 【0177】 The gate insulating layer 106 is formed in a film-like manner along the inner wall of the gate trench 105, and defines the recess space within the gate trench 105. The gate insulating layer 106 includes a first region 108, a second region 109, and a third region 110. The first region 108 is formed along the side wall of the gate trench 105. The second region 109 is formed along the bottom wall of the gate trench 105. The third region 110 partially covers the first main surface 3 through the opening edge of the gate trench 105. 【0178】 The thickness of the first region 108 may be between 0.01 μm and 0.2 μm. The thickness of the second region 109 may be between 0.05 μm and 0.5 μm. The thickness of the second region 109 may exceed the thickness of the first region 108. The thickness of the third region 110 may be between 0.05 μm and 0.5 μm. The thickness of the third region 110 may exceed the thickness of the first region 108. 【0179】 The gate insulating layer 106 includes a bulge 111 that bulges inward into the gate trench 105 at the opening edge. The bulge 111 is formed at the connection between the first region 108 and the third region 110 of the gate insulating layer 106. The bulge 111 is formed in a curved shape that curves inward into the gate trench 105. The bulge 111 narrows the opening of the gate trench 105 at the opening edge. A gate insulating layer 106 without a bulge 111 may be formed. A gate insulating layer 106 with a uniform thickness may be formed. 【0180】 The gate electrode 107 is embedded in the gate trench 105, with the gate insulating layer 106 in between. Specifically, the gate electrode 107 is embedded in a recess space partitioned by the gate insulating layer 106 within the gate trench 105. The gate electrode 107 has an electrode surface that is exposed from the opening of the gate trench 105. The electrode surface of the gate electrode 107 is formed in a curved shape that is recessed toward the bottom wall of the gate trench 105. The electrode surface of the gate electrode 107 is narrowed by the bulge 111 of the gate insulating layer 106. 【0181】 The gate electrode 107 is made of a conductive material other than a metallic material. Preferably, the gate electrode 107 is made of conductive polysilicon. In this embodiment, the gate electrode 107 contains p-type polysilicon to which p-type impurities have been added. 【0182】 The p-type impurity concentration of gate electrode 107 is 1.0 × 10⁻⁶. 18 cm -3 The above 1.0 × 10 22 cm -3 The following may also apply: The p-type impurities in the gate electrode 107 may include at least one of boron, aluminum, indium, and gallium. The sheet resistance of the gate electrode 107 may be between 10Ω / □ and 500Ω / □ (approximately 200Ω / □ in this configuration). The thickness of the gate electrode 107 may be between 0.5μm and 3μm. 【0183】 The semiconductor device 101 includes a first low-resistance layer 112 that covers the gate electrode 107. The first low-resistance layer 112 covers the gate electrode 107 within the gate trench 105. The first low-resistance layer 112 forms part of the trench gate structure 104. 【0184】 The first low-resistance layer 112 includes a conductive material having a sheet resistance less than that of the gate electrode 107. The sheet resistance of the first low-resistance layer 112 may be between 0.01 Ω / □ and 10 Ω / □. The thickness of the first low-resistance layer 112 may be between 0.01 μm and 3 μm. Preferably, the thickness of the first low-resistance layer 112 is less than the thickness of the gate electrode 107. 【0185】 The first low-resistance layer 112 specifically includes a polyside layer. The polyside layer is formed by silicideizing the surface portion of the gate electrode 107 with a metallic material. In other words, the electrode surface of the gate electrode 107 is formed by the first low-resistance layer 112. Specifically, the polyside layer consists of a p-type polyside layer containing p-type impurities added to the gate electrode 107. The polyside layer preferably has a resistivity of 10 μΩ·cm or more and 110 μΩ·cm or less. 【0186】 The sheet resistance within the gate trench 105, in which the gate electrode 107 and the first low-resistance layer 112 are embedded, is less than the sheet resistance of the gate electrode 107 alone. Preferably, the sheet resistance within the gate trench 105 is less than or equal to the sheet resistance of n-type polysilicon doped with n-type impurities. The sheet resistance within the gate trench 105 is approximated by the sheet resistance of the first low-resistance layer 112. The sheet resistance within the gate trench 105 may be between 0.01 Ω / □ and 10 Ω / □. Preferably, the sheet resistance within the gate trench 105 is less than 10 Ω / □. 【0187】 The first low-resistance layer 112 may contain at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, and WSi2. In particular, NiSi, CoSi2, and TiSi2 among these species are suitable as polyside layers for forming the first low-resistance layer 112 because their resistivity values ​​and temperature dependence are relatively small. Most preferably, the first low-resistance layer 112 is made of CoSi2, which has the property of diffusing little to other regions. 【0188】 The first low-resistance layer 112 includes a contact portion that contacts the gate insulating layer 106. Specifically, the contact portion of the first low-resistance layer 112 is in contact with the third region 110 (bulge portion 111) of the gate insulating layer 106. This suppresses the current path between the first low-resistance layer 112 and the SiC epitaxial layer 7. In particular, designing the contact portion of the first low-resistance layer 112 to connect to a relatively thick corner of the gate insulating layer 106 is effective in reducing the risk of current path formation. 【0189】 By embedding p-type polysilicon, which has a different work function than n-type polysilicon, in the gate trench 105, the gate threshold voltage Vth can be increased by about 1V. However, p-type polysilicon has a sheet resistance that is several tens of times (approximately 20 times) higher than that of n-type polysilicon. Therefore, when p-type polysilicon is used as the material for the gate electrode 107, energy loss increases with the increase in parasitic resistance (hereinafter simply referred to as "gate resistance") within the gate trench 105. 【0190】 Therefore, in the semiconductor device 101, a first low-resistance layer 112 (p-type polysilicon) is formed on the gate electrode 107 (p-type polysilicon). The first low-resistance layer 112 allows for an increase in the gate threshold voltage Vth while reducing the sheet resistance in the gate trench 105. 【0191】 For example, a structure having the first low-resistance layer 112 can reduce the sheet resistance to less than 1 / 100th compared to a structure without the first low-resistance layer 112. A structure having the first low-resistance layer 112 can reduce the sheet resistance to less than 1 / 5th compared to a gate electrode 107 containing n-type polysilicon. 【0192】 This reduces gate resistance, allowing current to be efficiently diffused along the trench gate structure 104. In other words, the first low-resistance layer 112 is formed as a current-diffusing layer that diffuses current within the gate trench 105. In particular, in the case of a gate trench 105 having a length on the order of millimeters (1 mm or more), current transmission takes time, but the first low-resistance layer 112 can appropriately suppress switching delay. 【0193】 The structure having the first low-resistance layer 112 eliminates the need to increase the p-type impurity concentration in the SiC epitaxial layer 7 to raise the gate threshold voltage Vth. Therefore, the gate threshold voltage Vth can be appropriately increased while suppressing an increase in channel resistance. 【0194】 The semiconductor device 101 includes a plurality of trench source structures 121, each formed in the region between a plurality of adjacent trench gate structures 104. The plurality of trench source structures 121 are formed with spacing in the second direction Y, sandwiching one trench gate structure 104 between them. 【0195】 Each of the multiple trench source structures 121 is formed in a strip-like shape extending along the first direction X. In a plan view, each of the multiple trench source structures 121 is formed in a stripe-like shape extending along the first direction X. 【0196】 The pitch PS between the central parts of adjacent trench source structures 121 in the second direction Y may be 1 μm or more and 5 μm or less. The pitch PS may be 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, or 4 μm or more and 5 μm or less. Preferably, the pitch PS is 1.5 μm or more and 3 μm or less. 【0197】 Each trench source structure 121 includes a source trench 122, a source insulating layer 123, and a source electrode 124. In Figure 10, the source electrode 124 is indicated by hatching. 【0198】 The source trench 122 is formed in the SiC epitaxial layer 7. The source trench 122 includes side walls and a bottom wall. The side walls forming the long sides of the source trench 122 are formed by the a-plane of the SiC single crystal. The side walls forming the short sides of the source trench 122 are formed by the m-plane of the SiC single crystal. 【0199】 The bottom wall of source trench 122 is located in the high-concentration region 102. The bottom wall of source trench 122 is located in the region on the second main surface 4 side relative to the bottom wall of gate trench 105. With respect to the normal direction Z, the bottom wall of source trench 122 is located in the region between the bottom wall of gate trench 105 and the low-concentration region 103. 【0200】 The bottom wall of the source trench 122 faces the c-plane of the SiC single crystal. The bottom wall of the source trench 122 has an off-angle inclined in the a-axis direction with respect to the c-plane of the SiC single crystal. The bottom wall of the source trench 122 may be formed parallel to the first main surface 3. The bottom wall of the source trench 122 may be formed in a curved shape toward the second main surface 4. 【0201】 The source trench 122 has a second depth D2 that exceeds the first depth D1 of the gate trench 105. The ratio DS / DG of the second depth D2 to the first depth D1 may be 1.5 or more, provided that the source trench 122 is located within the high-concentration region 102. Preferably, the ratio DS / DG is 2 or more. 【0202】 The second depth D2 may be 0.5 μm or more and 10 μm or less. The second depth D2 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. A source trench 122 having a second depth D2 that is approximately equal to the first depth D1 may be formed. 【0203】 The source trench 122 includes a first trench section 125 and a second trench section 126. The first trench section 125 is formed on the opening side of the source trench 122. The first trench section 125 has a first width W1 with respect to the second direction Y. The first trench section 125 may be formed in a tapered shape, with the first width W1 narrowing from the first main surface 3 toward the bottom wall side. 【0204】 The first trench portion 125 is preferably formed in the region of the gate trench 105 on the side of the first main surface 3 relative to the bottom wall. In other words, the depth of the first trench portion 125 is preferably less than the first depth D1 of the gate trench 105. The first trench portion 125 may be formed across the bottom wall of the gate trench 105. In other words, the depth of the first trench portion 125 may exceed the first depth D1 of the gate trench 105. 【0205】 The depth of the first trench 125 may be 0.1 μm or more and 2 μm or less. The depth of the first trench 125 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less. 【0206】 The first width W1 of the first trench portion 125 may be greater than or equal to the width of the gate trench 105, or less than the width of the gate trench 105. Preferably, the first width W1 exceeds the width of the gate trench 105. The first width W1 may be 0.1 μm or more and 2 μm or less. The first width W1 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less. 【0207】 The second trench 126 is formed on the bottom wall side of the source trench 122. The second trench 126 is formed in the region between the first trench 125 and the bottom of the SiC epitaxial layer 7 with respect to the normal direction Z, and crosses the bottom wall of the gate trench 105. With respect to the normal direction Z, it is preferable that the depth of the second trench 126 with respect to the first trench 125 exceeds the first depth D1 of the gate trench 105. 【0208】 The second trench section 126 has a second width W2 that is less than the first width W1 with respect to the second direction Y. The second width W2 may be greater than or equal to the width of the gate trench 105, or it may be less than the width of the gate trench 105, given the condition that it is less than the first width W1. 【0209】 The second width W2 may be 0.1 μm or more and less than 2 μm. The second width W2 may be 0.1 μm or more and less than 2 μm. The second width W2 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, or 1.5 μm or more and less than 2 μm. Of course, a second trench portion 126 having a second width W2 that is approximately equal to the first width W1 may be formed. 【0210】 Preferably, the overall opening width of the source trench 122 is formed to be approximately the same as the opening width of the gate trench 105. The opening width of the source trench 122 being approximately the same as the opening width of the gate trench 105 means that the opening width of the source trench 122 falls within ±20% of the opening width of the gate trench 105. 【0211】 The side walls of the second trench portion 126 may extend along the normal direction Z. The angle that the side walls of the second trench portion 126 make with respect to the first main surface 3 within the SiC chip 2 may be 90° or more and 95° or less (for example, 91° or more and 93° or less). The side walls of the second trench portion 126 may be formed substantially perpendicular to the first main surface 3. The second trench portion 126 may be formed in a tapered shape, with the second width W2 narrowing from the first trench portion 125 toward the bottom wall. 【0212】 The source insulating layer 123 comprises at least one of silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, or tantalum oxide. The source insulating layer 123 may have a laminated structure in which silicon oxide layers and silicon nitride layers are stacked in any order. The source insulating layer 123 may have a single-layer structure consisting of silicon oxide layers or silicon nitride layers. In this embodiment, the source insulating layer 123 has a single-layer structure consisting of silicon oxide layers. 【0213】 The source insulating layer 123 is formed in a film-like manner along the inner wall of the source trench 122, and defines the recess space within the source trench 122. Specifically, the source insulating layer 123 is formed in a film-like manner along the inner wall of the source trench 122 so as to expose the first trench portion 125 and cover the second trench portion 126. 【0214】 As a result, the source insulating layer 123 defines a recess space within the second trench portion 126. The source insulating layer 123 has a side wall window portion 127 that exposes the first trench portion 125. 【0215】 The source insulating layer 123 includes a first region 128 and a second region 129. The first region 128 is formed along the side wall of the source trench 122. The second region 129 is formed along the bottom wall of the source trench 122. The thickness of the first region 128 is less than the thickness of the second region 129. The thickness of the first region 128 may be between 0.01 μm and 0.2 μm. The thickness of the second region 129 may be between 0.05 μm and 0.5 μm. 【0216】 The thickness of the first region 128 may be approximately equal to the thickness of the first region 128 of the gate insulating layer 106. The thickness of the second region 129 may be approximately equal to the thickness of the second region 129 of the gate insulating layer 106. A source insulating layer 123 having a uniform thickness may be formed. 【0217】 The source electrode 124 is embedded in the source trench 122 with the source insulating layer 123 in between. Specifically, the source electrode 124 is embedded in the first trench section 125 and the second trench section 126 with the source insulating layer 123 in between. 【0218】 The source electrode 124 is embedded in a recess space partitioned by the second trench portion 126 on the bottom wall side of the source trench 122. The source electrode 124 has a side wall contact portion 130 that is in contact with the side wall of the first trench portion 125, which is exposed from the side wall window portion 127 on the opening side of the source trench 122. 【0219】 The source electrode 124 has an electrode surface that is exposed from the opening of the source trench 122. The electrode surface of the source electrode 124 is formed in a curved shape that is recessed toward the bottom wall of the source trench 122. The electrode surface of the source electrode 124 may be formed parallel to the first main surface 3. 【0220】 With respect to the normal direction Z, the thickness of the source electrode 124 may be 0.5 μm or more and 10 μm or less. The thickness of the source electrode 124 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. 【0221】 The source electrode 124 is made of a conductive material other than a metallic material. Preferably, the source electrode 124 is made of conductive polysilicon. In this embodiment, the source electrode 124 contains p-type polysilicon to which p-type impurities have been added. 【0222】 The p-type impurity concentration of source electrode 124 is 1.0 × 10⁻⁶. 18 cm -3 The above 1.0 × 10 22 cm -3 The following is also possible: The p-type impurity concentration of the source electrode 124 is preferably equal to the p-type impurity concentration of the gate electrode 107. The p-type impurities of the source electrode 124 may include at least one of boron, aluminum, indium, and gallium. 【0223】 The semiconductor device 101 includes a second low-resistance layer 131 that covers the source electrode 124. The second low-resistance layer 131 covers the source electrode 124 within the source trench 122. The second low-resistance layer 131 forms part of the trench-source structure 121. The second low-resistance layer 131 has a structure similar to that of the first low-resistance layer 112. The description of the second low-resistance layer 131 is based on the description of the first low-resistance layer 112. 【0224】 The semiconductor device 101 includes a p-type body region 141 formed on the surface layer of the first main surface 3 in the active region 8. The body region 141 defines the active region 8. The p-type impurity concentration in the body region 141 is less than the p-type impurity concentration in the gate electrode 107 and the source electrode 124. The peak value of the p-type impurity concentration in the body region 141 is 1.0 × 10⁻⁶. 17 cm -3 The above 1.0 × 10 19 cm -3The following is also acceptable. 【0225】 The body region 141 covers the side walls of the gate trench 105 and the source trench 122 in the surface layer portion of the first main surface 3. The body region 141 is formed in the region on the first main surface 3 side relative to the bottom wall of the gate trench 105. The body region 141 faces the gate electrode 107 across the gate insulating layer 106. 【0226】 The body region 141 is formed in the region on the first trench portion 125 side relative to the second trench portion 126. The body region 141 covers the first trench portion 125. The body region 141 is connected to the side wall contact portion 130 of the source electrode 124 exposed from the first trench portion 125. As a result, the body region 141 is source-grounded within the SiC chip 2. The body region 141 may also cover a portion of the second trench portion 126. In this case, the body region 141 may face the source electrode 124 with a portion of the source insulating layer 123 in between. 【0227】 The semiconductor device 101 has n formed on the surface layer of the body region 141 + It includes a source region 142 of type n. The source region 142 is formed along the gate trench 105. The peak value of the n-type impurity concentration in the source region 142 exceeds the peak value of the n-type impurity concentration in the high-concentration region 102. The peak value of the n-type impurity concentration in the source region 142 is 1.0 × 10⁻⁶. 18 cm -3 The above 1.0 × 10 21 cm -3 The following is also acceptable. 【0228】 The source region 142 covers the side walls of the gate trench 105 and the source trench 122 on the surface of the body region 141. The source region 142 faces the gate electrode 107 across the gate insulating layer 106. Preferably, the source region 142 faces the first low-resistance layer 112 across the gate insulating layer 106. 【0229】 The source region 142 is further formed in the region on the first trench portion 125 side relative to the second trench portion 126. The source region 142 covers the first trench portion 125. The source region 142 is connected to the side wall contact portion 130 of the source electrode 124 exposed from the first trench portion 125. As a result, the source region 142 is source-grounded within the SiC chip 2. 【0230】 In this embodiment, the source region 142 has a concealed portion hidden by the third region 110 of the gate insulating layer 106 on the first main surface 3, and an exposed portion exposed from the third region 110. The entire source region 142 may be covered by the third region 110. 【0231】 In the source region 142, the portion along the side wall of the gate trench 105 defines the channel of the MISFET between it and the high-concentration region 102 within the body region 141. The ON / OFF state of the channel is controlled by the gate electrode 107. 【0232】 The semiconductor device 101 has p formed on the surface layer of the first main surface 3 in the active region 8. + It includes multiple contact regions 143 of type p-type. The peak value of the p-type impurity concentration in each contact region 143 exceeds the peak value of the p-type impurity concentration in the body region 141. The peak value of the p-type impurity concentration in each contact region 143 is 1.0 × 10⁻⁶. 18 cm -3 The above 1.0 × 10 21 cm -3 The following is also acceptable. 【0233】 Multiple contact regions 143 are formed in regions along multiple source trenches 122. Specifically, multiple contact regions 143 are formed in a one-to-many relationship with respect to a single corresponding source trench 122. Multiple contact regions 143 are formed at intervals along the corresponding source trenches 122. Multiple contact regions 143 are formed at intervals from the gate trench 105. 【0234】 Each contact region 143 covers the corresponding first trench portion 125. Each contact region 143 is interposed between the sidewall contact portion 130 of the source electrode 124 and the source region 142 in the corresponding first trench portion 125. Each contact region 143 is further interposed between the sidewall contact portion 130 of the source electrode 124 and the body region 141 in the corresponding first trench portion 125. 【0235】 As a result, each contact region 143 is electrically connected to the source electrode 124, the body region 141, and the source region 142. Each contact region 143 is source-grounded within the SiC chip 2. 【0236】 In each contact region 143, the portion covering the first trench 125 extends toward the gate trench 105. In each contact region 143, the portion covering the first trench 125 is formed in the region on the first main surface 3 side relative to the bottom of the body region 141. In each contact region 143, the portion covering the first trench 125 may extend to the intermediate region between the gate trench 105 and the source trench 122. 【0237】 Each contact region 143 further covers the corresponding second trench portion 126. Each contact region 143 faces the source electrode 124 across the source insulating layer 123 in the corresponding second trench portion 126. 【0238】 Each contact region 143 further covers the bottom wall of the corresponding source trench 122. Each contact region 143 faces the source electrode 124 across the bottom wall of the corresponding source trench 122. The bottom of each contact region 143 may be formed parallel to the bottom wall of the corresponding source trench 122. 【0239】 The semiconductor device 101 includes a plurality of p-type deep well regions 144 formed on the surface layer of the first main surface 3 in the active region 8. The peak value of the p-type impurity concentration in each deep well region 144 is less than the peak value of the p-type impurity concentration in the contact region 143. 【0240】 The peak value of the p-type impurity concentration in each deep well region 144 may be greater than or equal to the peak value of the p-type impurity concentration in the body region 141, or less than the peak value of the p-type impurity concentration in the body region 141. The peak value of the p-type impurity concentration in each deep well region 144 is 1.0 × 10⁻⁶ 17 cm -3 The above 1.0 × 10 19 cm -3 The following is also acceptable. 【0241】 Multiple deep well regions 144 are formed in a one-to-one correspondence with multiple source trenches 122. Each deep well region 144 is formed in a strip shape extending along the corresponding source trench 122 in a plan view. Each deep well region 144 is formed in a high-density region 102. Each deep well region 144 is formed in the region on the second main surface 4 side relative to the body region 141. Each deep well region 144 is connected to the body region 141. 【0242】 Each deep well region 144 includes a portion that covers the corresponding second trench region 126. Each deep well region 144 includes a portion that covers the corresponding second trench region 126, flanking the contact region 143. Each deep well region 144 further includes a portion that covers the bottom wall of the corresponding source trench 122. Each deep well region 144 includes a portion that covers the bottom wall of the corresponding source trench 122, flanking the contact region 143. 【0243】 Each deep well region 144 has a bottom located on the second main surface 4 side with respect to the bottom wall of the gate trench 105. The bottom of each deep well region 144 may be formed parallel to the bottom wall of each source trench 122. The plurality of deep well regions 144 are preferably formed at a constant depth. 【0244】 Each deep well region 144 forms a pn junction with the high concentration region 102. From this pn junction, a depletion layer spreads toward the gate trench 105. The depletion layer may overlap the bottom wall of the gate trench 105. 【0245】 In the semiconductor device 101 including only the pn junction diode, due to the structure without trenches, the problem of electric field concentration in the SiC chip 2 is less. Each deep well region 144 makes the trench gate type MISFET approach the structure of the pn junction diode. Thereby, in the trench gate type MISFET, the electric field in the SiC chip 2 can be relaxed. 【0246】 According to the deep well region 144 having a bottom on the second main surface 4 side with respect to the bottom wall of the gate trench 105, the electric field concentration with respect to the gate trench 105 can be appropriately relaxed by the depletion layer. Narrowing the pitch PS between the plurality of source trenches 122 (deep well regions 144) is effective in relaxing the electric field concentration and improving the breakdown voltage. 【0247】 The plurality of deep well regions 144 are preferably formed at a constant depth. Thereby, it is possible to suppress the breakdown voltage (for example, the breakdown withstand) of the SiC chip 2 from being limited by each deep well region 144, so that the breakdown voltage can be appropriately improved. 【0248】 By using the source trench 122, the deep well region 144 can be appropriately formed in a relatively deep region of the SiC chip 2. Since the deep well region 144 can be formed along the source trench 122, variations in the depths of the plurality of deep well regions 144 can be appropriately suppressed. 【0249】 In this form, a part of the high-concentration region 102 is interposed in the region between the plurality of deep well regions 144. Thereby, the JFET (Junction Field Effect Transistor) resistance can be reduced in the region between the plurality of deep well regions 144. 【0250】 In this form, the bottom of each deep well region 144 is located in the high-concentration region 102. Thereby, a current path can be formed in the lateral direction parallel to the first main surface 3 in the region directly below each deep well region 144 in the high-concentration region 102. As a result, the current spreading resistance can be reduced. The low-concentration region 103 increases the breakdown voltage of the SiC chip 2 in such a structure. 【0251】 The main surface insulating layer 12 covers the entire area of the first main surface 3. The main surface insulating layer 12 covers the source region 142 and the contact region 143 in the active region 8. Specifically, the main surface insulating layer 12 covers the entire area of the source region 142 and the entire area of the contact region 143 in a cross-sectional view along the second direction Y in the active region 8. The main surface insulating layer 12 covers the entire area of the source region 142 and the entire area of the contact region 143 in a plan view. 【0252】 More specifically, the main surface insulating layer 12 covers the source electrode 124 across the first trench portion 125 in the active region 8. The main surface insulating layer 12 covers the sidewall contact portion 130 of the source electrode 124 on the first main surface 3. 【0253】 The main surface insulating layer 12 has a plurality of contact openings 151 that expose a plurality of source electrodes 124 in the active region 8. The plurality of contact openings 151 are formed in a one-to-one correspondence relationship with the plurality of source electrodes 124. Each contact opening 151 may be formed in a strip shape extending along the trench source structure 121. In a plan view, each contact opening 151 is formed within a region surrounded by the side walls of the source trench 122 (first trench portion 125). 【0254】 Each contact opening 151 exposes the source electrode 124 at a distance from the side wall of the source trench 122 (first trench portion 125) toward the inside of the source trench 122. The contact opening 151 exposes only the source electrode 124. The opening edge of the contact opening 151 is formed in a curved shape toward the inside of the contact opening 151. 【0255】 A recess 152 is formed on the electrode surface of the source electrode 124, recessed toward the bottom wall of the source trench 122. The recess 152 may be formed in a strip shape extending along the trench source structure 121. In a plan view, the recess 152 is formed within the region surrounded by the side walls of the source trench 122 (first trench portion 125). 【0256】 The recess 152 is formed at a distance from the side wall of the source trench 122 (first trench portion 125) inward from the source trench 122. The recess 152 exposes the second low-resistance layer 131. The recess 152 may penetrate the second low-resistance layer 131. The contact opening 151 communicates with the recess 152 of the source electrode 124. 【0257】 The periphery of the main surface insulating layer 12 is exposed from the sides 5A to 5D. In this configuration, the periphery of the main surface insulating layer 12 is continuous with the sides 5A to 5D. The periphery of the main surface insulating layer 12 may be formed with a gap inward from the sides 5A to 5D. In this case, the main surface insulating layer 12 exposes the portion located in the outer region 9 on the first main surface 3. 【0258】 The thickness of the main surface insulating layer 12 may be 0.1 μm or more and 10 μm or less. The thickness of the main surface insulating layer 12 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. Preferably, the thickness of the main surface insulating layer 12 is 0.5 μm or more and 5 μm or less. 【0259】 The first main surface electrode 21 is formed on the main surface insulating layer 12. The thickness T1 of the first main surface electrode 21 may be 1 μm or more and 100 μm or less. The thickness T1 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 40 μm or less, 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, or 80 μm or more and 100 μm or less. It is preferable that the thickness T1 is 20 μm or more and 60 μm or less. 【0260】 The first main surface electrode 21 includes a gate main surface electrode 153, a gate wiring electrode 154, and a source main surface electrode 155. A gate voltage is applied to the gate main surface electrode 153 (gate wiring electrode 154). The gate voltage may be between 10V and 50V (for example, around 30V). A source voltage is applied to the source main surface electrode 155. The source voltage may be a reference voltage (for example, GND voltage). 【0261】 The gate main surface electrode 153 is formed in the active region 8. The gate main surface electrode 153 is formed in the region on the first side surface 5A side in a plan view. Specifically, the gate main surface electrode 153 is formed in the central part of the first side surface 5A in a plan view. The gate main surface electrode 153 may also be formed at the corner connecting any two of the sides 5A to 5D in a plan view. The gate main surface electrode 153 may be formed in a square shape in a plan view. 【0262】 The gate wiring electrode 154 is drawn out from the gate main surface electrode 153 and extends in a strip along the periphery of the active region 8. In this embodiment, the gate wiring electrode 154 extends along the first side surface 5A, the third side surface 5C, and the fourth side surface 5D, partitioning the interior of the active region 8 from three directions. The gate wiring electrode 154 is electrically connected to the gate electrode 107 via the main surface insulating layer 12. Electrical signals from the gate main surface electrode 153 are transmitted to the gate electrode 107 via the gate wiring electrode 154. 【0263】 The source main electrode 155 is formed in the active region 8, spaced apart from the gate main electrode 153 and the gate wiring electrode 154. The source main electrode 155 covers the region demarcated by the gate main electrode 153 and the gate wiring electrode 154, and is formed in a C-shape in plan view. 【0264】 The source main surface electrode 155 is electrically connected to the source electrode 124 via a contact opening 151. In other words, in this configuration, the source main surface electrode 155, made of a metallic material, is electrically connected to the source electrode 124, made of conductive polysilicon. 【0265】 The first main surface electrode 21 (gate main surface electrode 153, gate wiring electrode 154, and source main surface electrode 155) each has a stacked structure including a barrier electrode 22 and a main electrode 23 stacked in this order from the SiC chip 2 side. 【0266】 In this embodiment, the barrier electrode 22 includes at least one of a Ti layer and a TiN layer. Preferably, the barrier electrode 22 has a laminated structure including a Ti layer and a TiN layer stacked in this order from the SiC chip 2 side. The barrier electrode 22 may also have a single-layer structure consisting of a Ti layer or a TiN layer. 【0267】 The thickness of the barrier electrode 22 may be 0.01 μm or more and 1 μm or less. The thickness of the barrier electrode 22 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less. 【0268】 The main electrode 23 is formed as a film on the barrier electrode 22. The main electrode 23 covers the entire main surface of the barrier electrode 22. The main electrode 23 has a resistance value less than the resistance value of the barrier electrode 22. The main electrode 23 consists of an Al-based metal layer. Specifically, the main electrode 23 includes at least one of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer. 【0269】 The main electrode 23 may have a laminated structure in which two or more of the following are stacked in any order: a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer. The main electrode 23 may have a single-layer structure consisting of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer. It is preferable that the main electrode 23 has a single-layer structure consisting of an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer. 【0270】 The thickness of the main electrode 23 exceeds the thickness of the barrier electrode 22. The thickness of the main electrode 23 may be 10 μm or more and 100 μm or less. The thickness of the main electrode 23 may be 10 μm or more and 20 μm or less, 20 μm or more and 40 μm or less, 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, or 80 μm or more and 100 μm or less. Preferably, the thickness of the main electrode 23 is 20 μm or more and 60 μm or less. Since the thickness of the barrier electrode 22 is extremely small compared to the thickness of the main electrode 23, the thickness T1 of the first main surface electrode 21 is approximated by the thickness of the main electrode 23. 【0271】 The insulating layer 24 covers the first main surface electrode 21 on the first main surface 3. In FIG. 9, the insulating layer 24 is shown by hatching. Specifically, the insulating layer 24 is formed on the main surface insulating layer 12. The periphery of the insulating layer 24 is formed at an interval inward from the side surfaces 5A to 5D. Thereby, the insulating layer 24 exposes the peripheral portion of the main surface insulating layer 12. 【0272】 The periphery of the insulating layer 24 demarcates the dicing street 25 between the side surfaces 5A to 5D. According to the dicing street 25, when cutting out the semiconductor device 101 from the wafer, it is not necessary to physically cut the insulating layer 24. Thereby, the semiconductor device 101 can be smoothly cut out from the wafer, and at the same time, peeling and deterioration of the insulating layer 24 can be suppressed. As a result, the insulating layer 24 can appropriately protect the objects to be protected such as the SiC chip 2 and the first main surface electrode 21. 【0273】 The width of the dicing street 25 may be 1 μm or more and 25 μm or less. The width of the dicing street 25 is the width in a direction orthogonal to the direction in which the dicing street 25 extends. The width of the dicing street 25 may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, or 20 μm or more and 25 μm or less. 【0274】 The insulating layer 24 has a pad opening 26 that exposes the first main surface electrode 21. In this form, the pad opening 26 includes a gate pad opening 161 that exposes the gate main surface electrode 153 and a source pad opening 162 that exposes the source main surface electrode 155. The gate pad opening 161 may be formed in a polygonal shape having four sides parallel to the side surfaces 5A to 5D in plan view. The source pad opening 162 may be formed in a polygonal shape having four sides parallel to the side surfaces 5A to 5D in plan view. The planar shape of the gate pad opening 161 and the planar shape of the source pad opening 162 are arbitrary. 【0275】 Specifically, the insulating layer 24 has a laminated structure including an inorganic insulating layer 30 and an organic insulating layer 31, which are stacked in this order from the SiC chip 2 side. The inorganic insulating layer 30 is formed in a film-like manner along the main surface insulating layer 12, the gate main surface electrode 153, and the source main surface electrode 155. The inorganic insulating layer 30 includes the first gate inner wall 163, the first source inner wall 164, and the first outer wall 165. Hereinafter, the first gate inner wall 163, the first source inner wall 164, and the first outer wall 165 may be collectively referred to as the first wall surface. 【0276】 The inner wall 163 of the first gate defines a first gate opening 166 that exposes a portion of the gate main surface electrode 153. The first gate opening 166 forms a portion of the gate pad opening 161. The first gate opening 166 has a planar shape similar to the planar shape of the gate main surface electrode 153 and exposes the inner portion of the gate main surface electrode 153. The planar shape of the first gate opening 166 is arbitrary. The first gate opening 166 may be divided into a polygonal shape having four sides parallel to the sides 5A to 5D in a plan view. 【0277】 The inner wall 164 of the first source defines a first source opening 167 that exposes a portion of the source main surface electrode 155. The first source opening 167 forms a portion of the source pad opening 162. The first source opening 167 has a planar shape similar to the planar shape of the source main surface electrode 155 and exposes the inner portion of the source main surface electrode 155. The planar shape of the first source opening 167 is arbitrary. The first source opening 167 may be divided into a polygonal shape having four sides parallel to the sides 5A to 5D in a plan view. 【0278】 The first outer wall 165 of the inorganic insulating layer 30 is formed with a gap inward from the sides 5A to 5D, and partitions a portion of the dicing street 25 between itself and the sides 5A to 5D. As a result, the inorganic insulating layer 30 exposes the peripheral edge of the main surface insulating layer 12. The first outer wall 165 may be formed in a rectangular shape with four sides parallel to the sides 5A to 5D in a plan view. 【0279】 The angle formed between the first wall surface of the inorganic insulating layer 30 and the main surface of the first main surface electrode 21 within the inorganic insulating layer 30 may be 30° or more and 90° or less. It is preferable that the angle formed between the first wall surface and the main surface of the first main surface electrode 21 within the inorganic insulating layer 30 is 45° or more and less than 90°. The angle of the first wall surface is defined by the angle formed between the straight line connecting the lower end portion and the upper end portion of the first wall surface and the main surface of the first main surface electrode 21. 【0280】 The inorganic insulating layer 30 has a property of high adhesion to Ni. The inorganic insulating layer 30 includes at least one of a silicon oxide layer and a silicon nitride layer. The inorganic insulating layer 30 may have a laminated structure including a silicon oxide layer and a silicon nitride layer laminated in this order from the SiC chip 2 side. The inorganic insulating layer 30 may have a single-layer structure composed of a silicon oxide layer or a silicon nitride layer. It is preferable that the inorganic insulating layer 30 includes an insulating material different from the main surface insulating layer 12. In this form, the inorganic insulating layer 30 has a single-layer structure composed of a silicon nitride layer. 【0281】 It is preferable that the thickness T2 of the inorganic insulating layer 30 is less than the thickness T1 of the first main surface electrode 21 (T2 < T1). The thickness T2 may be 0.1 μm or more and 10 μm or less. The thickness T2 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. It is preferable that the thickness T2 is 1 μm or more and 5 μm or less. It is particularly preferable that the thickness T2 is 1 μm or more and 2 μm or less. 【0282】 The organic insulating layer 31 is formed in a film shape on the inorganic insulating layer 30. The organic insulating layer 31 includes a second gate inner wall 168, a second source inner wall 169, and a second outer wall 170. Hereinafter, the second gate inner wall 168, the second source inner wall 169, and the second outer wall 170 may be collectively referred to as the second wall surface. 【0283】 Referring to Figure 13, in this embodiment, the inner wall 168 of the second gate is formed in a curved shape that is recessed toward the inorganic insulating layer 30. The inner wall 168 of the second gate defines a second gate opening 171 that exposes a portion of the gate main surface electrode 153. The second gate opening 171 has a planar shape similar to the planar shape of the gate main surface electrode 153 and exposes the inner portion of the gate main surface electrode 153. The planar shape of the second gate opening 171 is arbitrary. The second gate opening 171 may be defined as a polygonal shape having four sides parallel to the sides 5A to 5D in a plan view. 【0284】 The second gate opening 171 communicates with the first gate opening 166 of the inorganic insulating layer 30, forming a gate pad opening 161 between it and the first gate opening 166. The second gate opening 171 surrounds the first gate opening 166 at a distance from it, exposing a portion of the inorganic insulating layer 30. Specifically, the organic insulating layer 31 exposes a portion of the main surface of the inorganic insulating layer 30 as the inner gate edge 172 in the region between the first gate opening 166 and the second gate opening 171. 【0285】 The width WG of the inner peripheral edge 172 of the gate may be greater than 0 μm and less than or equal to 10 μm. The width WG may be greater than 0 μm and less than or equal to 1 μm, 1 μm or more and less than or equal to 2 μm, 2 μm or more and less than or equal to 4 μm, 4 μm or more and less than or equal to 6 μm, 6 μm or more and less than or equal to 8 μm, or 8 μm or more and less than or equal to 10 μm. The width WG is preferably 1 μm or more and less than or equal to 5 μm. The width WG is arbitrary, but it is preferably less than or equal to the thickness T2 of the inorganic insulating layer 30 (WG ≤ T2). The width WG is particularly preferably 1 μm or more and less than or equal to 2 μm. 【0286】 Referring to Figure 14, in this embodiment, the inner wall 169 of the second source is formed in a curved shape that is recessed toward the inorganic insulating layer 30. The inner wall 169 of the second source defines a second source opening 173 that exposes a portion of the source main surface electrode 155. The second source opening 173 has a planar shape similar to the planar shape of the source main surface electrode 155 and exposes the inner portion of the source main surface electrode 155. The planar shape of the second source opening 173 is arbitrary. The second source opening 173 may be defined as a polygonal shape having four sides parallel to the sides 5A to 5D in a plan view. 【0287】 The second source opening 173 communicates with the first source opening 167 of the inorganic insulating layer 30, forming a source pad opening 162 between it and the first source opening 167. The second source opening 173 surrounds the first source opening 167 at a distance from it, exposing a portion of the inorganic insulating layer 30. Specifically, the organic insulating layer 31 exposes a portion of the main surface of the inorganic insulating layer 30 as the source inner periphery 174 in the region between the first source opening 167 and the second source opening 173. 【0288】 The width WS of the inner peripheral edge 174 of the source may be greater than 0 μm and less than or equal to 10 μm. The width WS may be greater than 0 μm and less than or equal to 1 μm, 1 μm or more and less than or equal to 2 μm, 2 μm or more and less than or equal to 4 μm, 4 μm or more and less than or equal to 6 μm, 6 μm or more and less than or equal to 8 μm, or 8 μm or more and less than or equal to 10 μm. The width WS is preferably 1 μm or more and less than or equal to 5 μm. The width WS is arbitrary, but is preferably less than or equal to the thickness T2 of the inorganic insulating layer 30 (WS ≤ T2). The width WS is particularly preferably 1 μm or more and less than or equal to 2 μm. 【0289】 In this form, the second outer wall 170 of the organic insulating layer 31 is formed in a curved shape that is recessed toward the inorganic insulating layer 30 side. The second outer wall 170 is formed on the inorganic insulating layer 30 at an interval inward from the side surfaces 5A to 5D, and partitions a part of the dicing street 25 between the side surfaces 5A to 5D. Thereby, the organic insulating layer 31 exposes the peripheral portion of the main surface insulating layer 12. The second outer wall 170 may be formed in a rectangular shape having four sides parallel to the side surfaces 5A to 5D in plan view. 【0290】 The second outer wall 170 of the organic insulating layer 31 may be formed on the main surface insulating layer 12 across the first outer wall 165 of the inorganic insulating layer 30. In this case, the dicing street 25 is partitioned by the second outer wall 170 of the organic insulating layer 31. 【0291】 The angle formed between the second wall surface of the organic insulating layer 31 and the main surface of the inorganic insulating layer 30 within the organic insulating layer 31 may be 30° or more and 90° or less. Preferably, the angle formed between the second wall surface and the main surface of the inorganic insulating layer 30 within the organic insulating layer 31 is 45° or more and less than 90°. The angle of the second wall surface is defined by the angle formed between the straight line connecting the lower end portion and the upper end portion of the second wall surface and the main surface of the inorganic insulating layer 30. 【0292】 The organic insulating layer 31 has a property of having lower adhesion to Ni compared to the inorganic insulating layer 30. The organic insulating layer 31 contains a negative-type or positive-type photosensitive resin. The organic insulating layer 31 may contain at least one of polyimide, polyamide, and polybenzoxazole. In this form, the organic insulating layer 31 contains polyimide. 【0293】 Preferably, the organic insulating layer 31 has a thickness T3 (T2 < T3) that exceeds the thickness T2 of the inorganic insulating layer 30. The ratio T3 / T2 of the thickness T3 of the organic insulating layer 31 to the thickness T2 of the inorganic insulating layer 30 may be more than 1 and 10 or less. The ratio T3 / T2 may be more than 1 and 2 or less, 2 or more and 4 or less, 4 or more and 6 or less, 6 or more and 8 or less, 8 or more and 10 or less. Preferably, the ratio T3 / T2 is 2 or more and 6 or less. 【0294】 The thickness T3 may be 1 μm or more and 50 μm or less. The thickness T3 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less. Preferably, the thickness T3 is 5 μm or more and 30 μm or less. 【0295】 In this embodiment, the roughened surface region 39 of the first main surface electrode 21 includes a gate roughened surface region 175 and a source roughened surface region 176. The gate roughened surface region 175 is formed on the exposed surface of the gate main surface electrode 153 that is exposed from the gate pad opening 161 (the first gate opening 166 of the inorganic insulating layer 30). The gate roughened surface region 175 includes a depression formed in the region directly below the first gate inner wall 163. As a result, the first gate inner wall 163 includes a portion that overhangs the gate roughened surface region 175. 【0296】 The source roughening region 176 is formed on the exposed surface of the source main surface electrode 155 that is exposed from the source pad opening 162 (first source opening 167 of the inorganic insulating layer 30). The source roughening region 176 includes a depression formed in the region directly below the first source inner wall 164. As a result, the first source inner wall 164 includes a portion that overhangs the source roughening region 176. 【0297】 In this embodiment, the pad electrode 40 includes a gate pad electrode 181 and a source pad electrode 182. The gate pad electrode 181 includes a first Ni plating layer (metal layer) 183 formed on the gate main surface electrode 153 within the gate pad opening 161. The first Ni plating layer 183 corresponds to the Ni plating layer 41 according to the first embodiment. 【0298】 The first Ni plating layer 183 covers the gate main surface electrode 153 within the first gate opening 166 and covers the inner gate periphery 172 of the inorganic insulating layer 30 within the second gate opening 171. The first Ni plating layer 183 has an outer surface formed with a gap between the main surface of the organic insulating layer 31 (insulating layer 24) and the gate main surface electrode 153. The first Ni plating layer 183 covers the organic insulating layer 31 within the second gate opening 171. 【0299】 Referring to Figure 13, the first Ni plating layer 183 specifically has a first portion 183A that covers the gate main surface electrode 153, and a second portion 183B that covers the inner peripheral edge 172 of the gate of the inorganic insulating layer 30. 【0300】 The first portion 183A of the first Ni plating layer 183 fills the gate rough surface region 175 within the first gate opening 166 and covers the gate main surface electrode 153. The first portion 183A covers the entire area of ​​the first gate inner wall 163 of the inorganic insulating layer 30 and protrudes from the opening end of the first gate opening 166 toward the opening end of the second gate opening 171. The first portion 183A is connected to the first gate inner wall 163 of the inorganic insulating layer 30 and has a first connecting portion that extends in the thickness direction of the inorganic insulating layer 30. 【0301】 The second portion 183B of the first Ni plating layer 183 is drawn out from the first portion 183A toward the organic insulating layer 31 within the second gate opening 171. The second portion 183B is formed in an arc shape that extends toward the organic insulating layer 31, starting from the opening end of the first gate opening 166. 【0302】 The second portion 183B covers the inner gate periphery 172 of the inorganic insulating layer 30 within the second gate opening 171. As a result, the second portion 183B faces the gate main surface electrode 153 across the inner gate periphery 172 of the inorganic insulating layer 30. The second portion 183B has a second connecting portion that is connected to the main surface of the inorganic insulating layer 30 and extends in the width direction of the inorganic insulating layer 30. 【0303】 In this form, the second part 183B further covers the second gate inner wall 168 of the organic insulating layer 31 within the second gate opening 171. The second part 183B covers the region on the side of the inorganic insulating layer 30 with respect to the middle part of the second gate inner wall 168 of the organic insulating layer 31. In other words, the second part 183B covers the organic insulating layer 31 such that the exposed area of the second gate inner wall 168 (organic insulating layer 31) exceeds the hidden area of the second gate inner wall 168 (organic insulating layer 31). Thus, the first Ni plating layer 183 is formed such that the first part 183A and the second part 183B engage from different two directions at the opening end of the first gate opening 166. 【0304】 The first Ni plating layer 183 has a thickness T4 (T2 < T4) that exceeds the thickness T2 of the inorganic insulating layer 30. The thickness T4 is less than the thickness T3 of the organic insulating layer 31 (T3 < T4). The thickness T4 exceeds the value (T2 + WG) obtained by adding the width WG of the gate inner periphery 172 to the thickness T2 of the inorganic insulating layer 30 (T2 + WG < T4). This is the condition for the first Ni plating layer 183 to contact the second gate inner wall 168 of the organic insulating layer 31. The thickness T4 is defined by the thickness of the first Ni plating layer 183 with respect to the main surface of the gate main surface electrode 153. 【0305】 The ratio T4 / T2 of the thickness T4 of the first Ni plating layer 183 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than or equal to 5. The ratio T4 / T2 may be greater than 1 and less than or equal to 2, greater than or equal to 2 and less than or equal to 3, greater than or equal to 3 and less than or equal to 4, or greater than or equal to 4 and less than or equal to 5. 【0306】 The thickness T4 may be 0.1 μm or more and 15 μm or less. The thickness T4 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 3 μm or less, 3 μm or more and 6 μm or less, 6 μm or more and 9 μm or less, 9 μm or more and 12 μm or less, or 12 μm or more and 15 μm or less. The thickness T4 is preferably 2 μm or more and 8 μm or less. 【0307】 The gate pad electrode 181 is made of a metal material different from the first Ni plating layer 183, and includes a first outer surface plating layer 184 that covers the outer surface of the first Ni plating layer 183 within the second gate opening 171. The first outer surface plating layer 184 corresponds to the outer surface plating layer 42 according to the first embodiment. 【0308】 The first outer surface plating layer 184 has a thickness T5 (T5 < T4) less than the thickness T4 of the first Ni plating layer 183. The first outer surface plating layer 184 covers the second gate inner wall 168 of the organic insulating layer 31 within the second gate opening 171. 【0309】 The first outer surface plating layer 184 has a gate terminal surface 185A that is externally connected via a conductive bonding material (e.g., solder). The gate terminal surface 185A is located on the side of the first Ni plating layer 183 with respect to the main surface of the organic insulating layer 31 (the opening end of the second gate opening 171). Thereby, the first outer surface plating layer 184 exposes a part of the second gate inner wall 168 of the organic insulating layer 31. 【0310】 Specifically, the first outer surface plating layer 184 has a laminated structure including a first Pd plating layer 185 and a first Au plating layer 186 laminated in this order from the side of the first Ni plating layer 183. The first Pd plating layer 185 and the first Au plating layer 186 respectively correspond to the Pd plating layer 43 and the Au plating layer 44 according to the first embodiment. 【0311】 The first Pd plating layer 185 is formed in a film shape along the outer surface of the first Ni plating layer 183. The first Pd plating layer 185 covers the first Ni plating layer 183 at an interval from the opening end of the second gate opening 171 toward the inorganic insulating layer 30 side. The first Pd plating layer 185 covers the second gate inner wall 168 of the organic insulating layer 31 within the second gate opening 171. 【0312】 The first Pd plating layer 185 has a thickness less than the thickness T4 of the first Ni plating layer 183. The thickness of the first Pd plating layer 185 may be 0.01 μm or more and 1 μm or less. The thickness of the first Pd plating layer 185 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less. 【0313】 The first Au plating layer 186 is formed in a film-like manner along the outer surface of the first Pd plating layer 185. The first Au plating layer 186 covers the first Pd plating layer 185 with a gap from the opening end of the second gate opening 171 toward the inorganic insulating layer 30. The first Au plating layer 186 covers the inner wall 168 of the second gate of the organic insulating layer 31 within the second gate opening 171. 【0314】 The first Au plating layer 186 has a thickness less than the thickness T4 of the first Ni plating layer 183. The thickness of the first Au plating layer 186 may be 0.01 μm or more and 1 μm or less. The thickness of the first Au plating layer 186 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less. 【0315】 In this embodiment, an example was described in which the first outer plating layer 184 has a laminated structure including a first Pd plating layer 185 and a first Au plating layer 186. However, the first outer plating layer 184 may be adopted that has a similar configuration to any one of the outer plating layers 42 related to the second to fourth embodiments shown in Figures 4A to 4D above. 【0316】 The source pad electrode 182 includes a second Ni plating layer (metal layer) 193 formed on the source main surface electrode 155 within the source pad opening 162. The second Ni plating layer 193 corresponds to the Ni plating layer 41 according to the first embodiment. 【0317】 The second Ni plating layer 193 covers the source main surface electrode 155 within the first source opening 167 and covers the source inner peripheral edge 174 of the inorganic insulating layer 30 within the second source opening 173. The second Ni plating layer 193 has an outer surface formed with a gap between the main surface of the organic insulating layer 31 (insulating layer 24) and the source main surface electrode 155. The second Ni plating layer 193 covers the organic insulating layer 31 within the second source opening 173. 【0318】 Referring to Figure 14, the second Ni plating layer 193 specifically has a first portion 193A that covers the source main surface electrode 155, and a second portion 193B that covers the source inner peripheral edge 174 of the inorganic insulating layer 30. 【0319】 The first portion 193A of the second Ni plating layer 193 fills the source rough surface region 176 within the first source opening 167 and covers the source main surface electrode 155. The first portion 193A covers the entire first source inner wall 164 of the inorganic insulating layer 30 and protrudes from the opening end of the first source opening 167 toward the opening end of the second source opening 173. The first portion 193A is connected to the first source inner wall 164 of the inorganic insulating layer 30 and has a first connecting portion that extends in the thickness direction of the inorganic insulating layer 30. 【0320】 The second portion 193B of the second Ni plating layer 193 is drawn out from the first portion 193A toward the organic insulating layer 31 within the second source opening 173. The second portion 193B is formed in an arc shape that extends toward the organic insulating layer 31, starting from the opening end of the first source opening 167. 【0321】 The second portion 193B covers the inner peripheral edge 174 of the source of the inorganic insulating layer 30 within the second source opening 173. As a result, the second portion 193B faces the source main surface electrode 155 across the inner peripheral edge 174 of the source of the inorganic insulating layer 30. The second portion 193B has a second connecting portion that is connected to the main surface of the inorganic insulating layer 30 and extends in the width direction of the inorganic insulating layer 30. 【0322】 In this form, the second part 193B further covers the second source inner wall 169 of the organic insulating layer 31 within the second source opening 173. The second part 193B covers the region on the inorganic insulating layer 30 side with respect to the middle part of the second source inner wall 169 of the organic insulating layer 31. In other words, the second part 193B covers the organic insulating layer 31 such that the exposed area of the second source inner wall 169 (organic insulating layer 31) exceeds the concealed area of the second source inner wall 169 (organic insulating layer 31). Thus, the second Ni plating layer 193 is formed such that the first part 193A and the second part 193B engage from different two directions with the opening end of the first source opening 167. 【0323】 The second Ni plating layer 193 has a thickness T4 (T2 < T4) that exceeds the thickness T2 of the inorganic insulating layer 30. The thickness T4 is less than the thickness T3 of the organic insulating layer 31 (T3 < T4). The thickness T4 exceeds the value obtained by adding the width WS of the source inner periphery 174 to the thickness T2 of the inorganic insulating layer 30 (T2 + WS < T4). This is the condition for the second Ni plating layer 193 to contact the second source inner wall 169 of the organic insulating layer 31. The thickness T4 is defined by the thickness of the second Ni plating layer 193 with respect to the main surface of the source main surface electrode 155. 【0324】 The ratio T4 / T2 of the thickness T4 of the second Ni plating layer 193 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than or equal to 5. The ratio T4 / T2 may be greater than 1 and less than or equal to 2, greater than or equal to 2 and less than or equal to 3, greater than or equal to 3 and less than or equal to 4, or greater than or equal to 4 and less than or equal to 5. 【0325】 The thickness T4 may be 0.1 μm or more and 15 μm or less. The thickness T4 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 3 μm or less, 3 μm or more and 6 μm or less, 6 μm or more and 9 μm or less, 9 μm or more and 12 μm or less, or 12 μm or more and 15 μm or less. The thickness T4 is preferably 2 μm or more and 8 μm or less. 【0326】 The source pad electrode 182 is made of a metal material different from the second Ni plating layer 193, and includes a second outer surface plating layer 194 that covers the outer surface of the second Ni plating layer 193 within the second source opening 173. The second outer surface plating layer 194 corresponds to the outer surface plating layer 42 according to the first embodiment. 【0327】 The second outer surface plating layer 194 has a thickness T5 (T5 < T4) less than the thickness T4 of the second Ni plating layer 193. The second outer surface plating layer 194 covers the second source inner wall 169 of the organic insulating layer 31 within the second source opening 173. 【0328】 The second outer surface plating layer 194 has a source terminal surface 194A that is externally connected via a conductive bonding material (e.g., solder). The source terminal surface 194A is located on the side of the second Ni plating layer 193 with respect to the main surface of the organic insulating layer 31 (the opening end of the second source opening 173). Thereby, the second outer surface plating layer 194 exposes a part of the second source inner wall 169 of the organic insulating layer 31. 【0329】 Specifically, the second outer surface plating layer 194 has a laminated structure including a second Pd plating layer 195 and a second Au plating layer 196 laminated in this order from the side of the second Ni plating layer 193. The second Pd plating layer 195 and the second Au plating layer 196 respectively correspond to the Pd plating layer 43 and the Au plating layer 44 according to the first embodiment. 【0330】 The second Pd plating layer 195 is formed in a film shape along the outer surface of the second Ni plating layer 193. The second Pd plating layer 195 covers the second Ni plating layer 193 at an interval from the opening end of the second source opening 173 toward the inorganic insulating layer 30 side. The second Pd plating layer 195 covers the second source inner wall 169 of the organic insulating layer 31 within the second source opening 173. 【0331】 The second Pd plating layer 195 has a thickness less than the thickness T4 of the second Ni plating layer 193. The thickness of the second Pd plating layer 195 may be 0.01 μm or more and 1 μm or less. The thickness of the second Pd plating layer 195 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less. 【0332】 The second Au plating layer 196 is formed in a film-like manner along the outer surface of the second Pd plating layer 195. The second Au plating layer 196 covers the second Pd plating layer 195 with a gap from the opening end of the second source opening 173 toward the inorganic insulating layer 30. The second Au plating layer 196 covers the second source inner wall 169 of the organic insulating layer 31 within the second source opening 173. 【0333】 The second Au plating layer 196 has a thickness less than the thickness T4 of the second Ni plating layer 193. The thickness of the second Au plating layer 196 may be 0.01 μm or more and 1 μm or less. The thickness of the second Au plating layer 196 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less. 【0334】 In this embodiment, an example was described in which the second outer plating layer 194 has a laminated structure including a second Pd plating layer 195 and a second Au plating layer 196. However, a second outer plating layer 194 having a similar configuration to any one of the outer plating layers 42 in the second to fourth embodiment examples shown in Figures 4A to 4D above may be adopted. 【0335】 The second main surface electrode 46 covers the entire area of ​​the second main surface 4. The second main surface electrode 46 forms ohmic contact with the second main surface 4. The second main surface electrode 46 is formed as a drain electrode. 【0336】 The second main surface electrode 46 includes at least one of a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer. The second main surface electrode 46 may have a laminated structure in which at least two of the Ti layer, Ni layer, Pd layer, Au layer, and Ag layer are stacked in any order. The second main surface electrode 46 may have a single-layer structure consisting of a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer. It is preferable that the second main surface electrode 46 includes a Ti layer as an ohmic electrode. In this embodiment, the second main surface electrode 46 has a laminated structure including a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer stacked in this order from the second main surface 4 side. 【0337】 As described above, the semiconductor device 101, which includes a MISFET instead of an SBD, can achieve the same effects as those described for semiconductor device 1. 【0338】 Figure 15 is a corresponding diagram to Figure 12 and is a cross-sectional view showing a semiconductor device 201 according to the fourth embodiment of the present invention. Figure 16 is an enlarged view of region XVI shown in Figure 15. Figure 17 is an enlarged view of region XVII shown in Figure 15. Hereafter, structures corresponding to the structures described for the semiconductor device 101 (see Figures 9 to 14) will be given the same reference numerals and their descriptions will be omitted. 【0339】 Referring to Figures 15 to 17, the organic insulating layer 31 exposes the inner gate edge 172 of the inorganic insulating layer 30 in the region between the first gate opening 166 and the second gate opening 171. Preferably, the width WG of the inner gate edge 172 exceeds the thickness T2 of the inorganic insulating layer 30 (T2 <WG)。 【0340】 The ratio WG / T2 of the width WG of the gate inner periphery 172 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than or equal to 10. The ratio WG / T2 may be greater than 1 and less than or equal to 2, 2 to less than or equal to 4, 4 to less than or equal to 6, 6 to less than or equal to 8, or 8 to less than or equal to 10. Preferably, the ratio WG / T2 is 2 to less than or equal to 5. The width WG may be greater than 0 μm and less than or equal to 10 μm. The width WG may be greater than 0 μm and less than or equal to 2 μm, 2 μm to less than or equal to 4 μm, 4 μm to less than or equal to 6 μm, 6 μm to less than or equal to 8 μm, or 8 μm to less than or equal to 10 μm. 【0341】 The first Ni plating layer 183 is formed on the gate main surface electrode 153 within the gate pad opening 161. The first Ni plating layer 183 covers the gate main surface electrode 153 within the first gate opening 166 and covers the inner gate periphery 172 of the inorganic insulating layer 30 within the second gate opening 171. The first Ni plating layer 183 has an outer surface formed with a gap from the main surface of the organic insulating layer 31 (insulating layer 24) toward the gate main surface electrode 153. The first Ni plating layer 183 covers the inner gate periphery 172 of the inorganic insulating layer 30 with a gap from the organic insulating layer 31 within the second gate opening 171. 【0342】 Referring to Figure 16, the first Ni plating layer 183 specifically has a first portion 183A that covers the gate main surface electrode 153, and a second portion 183B that covers the inner peripheral edge 172 of the gate of the inorganic insulating layer 30. 【0343】 The first portion 183A of the first Ni plating layer 183 fills the gate roughening region 175 within the first gate opening 166 and covers the gate main surface electrode 153. The first portion 183A covers the entire area of ​​the first gate inner wall 163 of the inorganic insulating layer 30 within the first gate opening 166 and protrudes from the opening end of the first gate opening 166 toward the opening end of the second gate opening 171. The first portion 183A is connected to the first gate inner wall 163 of the inorganic insulating layer 30 and has a first connecting portion that extends in the thickness direction of the inorganic insulating layer 30. 【0344】 The second part 183B of the first Ni plating layer 183 is drawn from the first part 183A toward the organic insulating layer 31 within the second gate opening 171. The second part 183B is formed in an arc shape that extends from the opening end of the first gate opening 166 toward the second gate inner wall 168 of the organic insulating layer 31. 【0345】 The second part 183B covers the gate inner peripheral edge 172 of the inorganic insulating layer 30 within the second gate opening 171. In this form, the second part 183B partially covers the gate inner peripheral edge 172 of the inorganic insulating layer 30 at an interval from the second gate inner wall 168 of the organic insulating layer 31 toward the first gate inner wall 163 of the inorganic insulating layer 30 within the second gate opening 171 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. 【0346】 As a result, the first Ni plating layer 183 exposes a part of the gate inner peripheral edge 172 of the inorganic insulating layer 30 and the entire area of the second gate inner wall 168 of the organic insulating layer 31. The second part 183B faces the gate main surface electrode 153 with the gate inner peripheral edge 172 of the inorganic insulating layer 30 interposed therebetween. The second part 183B is connected to the main surface of the inorganic insulating layer 30 and has a second connection portion that extends in the width direction of the inorganic insulating layer 30. 【0347】 The first Ni plating layer 183 has a thickness T4 (T2 < T4) that exceeds the thickness T2 of the inorganic insulating layer 30. The thickness T4 is less than the value (T2 + WG) obtained by adding the width WG of the gate inner peripheral edge 172 to the thickness T2 of the inorganic insulating layer 30 (T4 < T2 + WG). This is a condition for the first Ni plating layer 183 to expose the second gate inner wall 168 of the organic insulating layer 31. The thickness T4 is defined by the thickness of the first Ni plating layer 183 with respect to the main surface of the gate main surface electrode 153. 【0348】 The ratio T4 / T2 of the thickness T4 of the first Ni plating layer 183 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and not more than 5. The ratio T4 / T2 may be greater than 1 and not more than 2, not less than 2 and not more than 3, not less than 3 and not more than 4, or not less than 4 and not more than 5. The thickness T4 may be not less than 0.1 μm and not more than 10 μm. The thickness T4 may be not less than 0.1 μm and not more than 1 μm, not less than 1 μm and not more than 2 μm, not less than 2 μm and not more than 4 μm, not less than 4 μm and not more than 6 μm, not less than 6 μm and not more than 8 μm, or not less than 8 μm and not more than 10 μm. 【0349】 The first outer surface plating layer 184 covers the outer surface of the first Ni plating layer 183 within the second gate opening 171. The first outer surface plating layer 184 has a thickness T5 (T5 < T4) less than the thickness T4 of the first Ni plating layer 183. In this form, the first outer surface plating layer 184 partially covers the gate inner peripheral edge 172 of the inorganic insulating layer 30 at a distance from the second gate inner wall 168 of the organic insulating layer 31 toward the first gate inner wall 163 of the inorganic insulating layer 30 within the second gate opening 171 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. 【0350】 The first outer surface plating layer 184 has a gate terminal surface 184A that is externally connected via a conductive bonding material (e.g., solder). The gate terminal surface 184A is located on the side of the first Ni plating layer 183 with respect to the main surface of the organic insulating layer 31 (the opening end of the second gate opening 171). Thereby, the first outer surface plating layer 184 exposes a part of the gate inner peripheral edge 172 of the inorganic insulating layer 30 and the entire second gate inner wall 168 of the organic insulating layer 31 within the second gate opening 171. 【0351】 Specifically, the first outer surface plating layer 184 has a laminated structure including a first Pd plating layer 185 and a Pd plating layer 186 laminated in this order from the side of the first Ni plating layer 183. The first Pd plating layer 185 is formed in a film shape along the outer surface of the first Ni plating layer 183. The first Pd plating layer 185 covers the first Ni plating layer 183 at a distance from the opening end of the second gate opening 171 toward the inorganic insulating layer 30 side. 【0352】 The first Pd plating layer 185 partially covers the inner gate edge 172 of the inorganic insulating layer 30 within the second gate opening 171, leaving a gap between the second gate inner wall 168 of the organic insulating layer 31 and the first gate inner wall 163 of the inorganic insulating layer 30, such that a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. As a result, the first Pd plating layer 185 exposes a portion of the inner gate edge 172 of the inorganic insulating layer 30 and the entire second gate inner wall 168 of the organic insulating layer 31 within the second gate opening 171. 【0353】 The first Pd plating layer 185 has a thickness less than the thickness T4 of the first Ni plating layer 183. The thickness of the first Pd plating layer 185 may be 0.01 μm or more and 1 μm or less. The thickness of the first Pd plating layer 185 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less. 【0354】 The Pd plating layer 186 is formed in a film-like manner along the outer surface of the first Pd plating layer 185. The Pd plating layer 186 covers the first Pd plating layer 185 with a gap between it and the inorganic insulating layer 30 from the opening end of the second gate opening 171. 【0355】 The Pd plating layer 186 partially covers the inner gate edge 172 of the inorganic insulating layer 30 within the second gate opening 171, leaving a gap between the second gate inner wall 168 of the organic insulating layer 31 and the first gate inner wall 163 of the inorganic insulating layer 30, such that a portion of the inner periphery 38 of the inorganic insulating layer 30 is exposed. As a result, the Pd plating layer 186 exposes a portion of the inner gate edge 172 of the inorganic insulating layer 30 and the entire second gate inner wall 168 of the organic insulating layer 31 within the second gate opening 171. 【0356】 The Pd plating layer 186 has a thickness less than the thickness T4 of the first Ni plating layer 183. The thickness of the Pd plating layer 186 may be 0.01 μm or more and 1 μm or less. The thickness of the Pd plating layer 186 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less. 【0357】 In this embodiment, an example was described in which the first outer plating layer 184 has a laminated structure including the first Pd plating layer 185 and the Pd plating layer 186. However, the first outer plating layer 184 may be adopted that has a similar configuration to any one of the outer plating layers 42 in the second to fourth embodiment examples shown in Figures 8A to 8D above. 【0358】 The organic insulating layer 31 exposes the source inner periphery 174 of the inorganic insulating layer 30 in the region between the first source opening 167 and the second source opening 173. In this embodiment, the width WS of the source inner periphery 174 exceeds the thickness T2 of the inorganic insulating layer 30 (T2 <WS)。 【0359】 The ratio WS / T2 of the width WS of the gate inner periphery 172 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than or equal to 10. The ratio WS / T2 may be greater than 1 and less than or equal to 2, 2 to less than or equal to 4, 4 to less than or equal to 6, 6 to less than or equal to 8, or 8 to less than or equal to 10. Preferably, the ratio WS / T2 is 2 to less than or equal to 5. The width WS may be greater than 0 μm and less than or equal to 10 μm. The width WS may be greater than 0 μm and less than or equal to 2 μm, 2 μm to less than or equal to 4 μm, 4 μm to less than or equal to 6 μm, 6 μm to less than or equal to 8 μm, or 8 μm to less than or equal to 10 μm. 【0360】 The second Ni plating layer 193 is formed on the source main surface electrode 155 within the source pad opening 162. The second Ni plating layer 193 covers the source main surface electrode 155 within the second source opening 173 and covers the source inner peripheral edge 174 of the inorganic insulating layer 30 within the second source opening 173. The second Ni plating layer 193 has an outer surface formed with a gap from the main surface of the organic insulating layer 31 (insulating layer 24) toward the source main surface electrode 155. The second Ni plating layer 193 covers the source inner peripheral edge 174 of the inorganic insulating layer 30 with a gap from the organic insulating layer 31 within the second source opening 173. 【0361】 Referring to Figure 17, the second Ni plating layer 193 specifically has a first portion 193A that covers the source main surface electrode 155, and a second portion 193B that covers the source inner peripheral edge 174 of the inorganic insulating layer 30. 【0362】 The first portion 193A of the second Ni plating layer 193 fills the source rough surface region 176 within the first source opening 167 and covers the source main surface electrode 155. The first portion 193A covers the entire first source inner wall 164 of the inorganic insulating layer 30 within the first source opening 167 and protrudes from the opening end of the first source opening 167 toward the opening end of the second source opening 173. The first portion 193A is connected to the first source inner wall 164 of the inorganic insulating layer 30 and has a first connecting portion that extends in the thickness direction of the inorganic insulating layer 30. 【0363】 The second portion 193B of the second Ni plating layer 193 is drawn out from the first portion 193A toward the organic insulating layer 31 within the second source opening 173. The second portion 193B is formed in an arc shape, starting from the opening end of the first source opening 167 and extending toward the second source inner wall 169 of the organic insulating layer 31. 【0364】 The second part 193B covers the source inner peripheral edge 174 of the inorganic insulating layer 30 within the second source opening 173. In this form, the second part 193B partially covers the source inner peripheral edge 174 of the inorganic insulating layer 30 at an interval from the second source inner wall 169 of the organic insulating layer 31 to the first source inner wall 164 side of the inorganic insulating layer 30 within the second source opening 173 such that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. 【0365】 Thereby, the second Ni plating layer 193 exposes a part of the source inner peripheral edge 174 of the inorganic insulating layer 30 and the entire second source inner wall 169 of the organic insulating layer 31. The second part 193B faces the source main surface electrode 155 with the source inner peripheral edge 174 of the inorganic insulating layer 30 interposed therebetween. The second part 193B is connected to the main surface of the inorganic insulating layer 30 and has a second connection part extending in the width direction of the inorganic insulating layer 30. 【0366】 The second Ni plating layer 193 has a thickness T4 (T2 < T4) exceeding the thickness T2 of the inorganic insulating layer 30. The thickness T4 is less than the thickness T3 of the organic insulating layer 31 (T3 < T4). The thickness T4 is less than the value (T2 + WS) obtained by adding the width WS of the source inner peripheral edge 174 to the thickness T2 of the inorganic insulating layer 30 (T4 < T2 + WS). This is the condition for the second Ni plating layer 193 to expose the second source inner wall 169 of the organic insulating layer 31. The thickness T4 is defined by the thickness of the second Ni plating layer 193 with respect to the main surface of the source main surface electrode 155. 【0367】 The ratio T4 / T2 of the thickness T4 of the second Ni plating layer 193 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than or equal to 5. The ratio T4 / T2 may be greater than 1 and less than or equal to 2, greater than or equal to 2 and less than or equal to​​​The second outer plating layer 194 covers the outer surface of the second Ni plating layer 193 within the second source opening 173. The second outer plating layer 194 has a thickness T5 (T5 < T4) that is less than the thickness T4 of the second Ni plating layer 193. In this form, the second outer plating layer 194 partially covers the source inner peripheral edge 174 of the inorganic insulating layer 30 at an interval from the second source inner wall 169 of the organic insulating layer 31 toward the first source inner wall 164 of the inorganic insulating layer 30 within the second source opening 173 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. 【0369】 The second outer plating layer 194 has a source terminal surface 194A that is externally connected via a conductive bonding material (e.g., solder). The source terminal surface 194A is located on the side of the second Ni plating layer 193 with respect to the main surface of the organic insulating layer 31 (the opening end of the second source opening 173). Thereby, the second outer plating layer 194 exposes a part of the source inner peripheral edge 174 of the inorganic insulating layer 30 and the entire area of the second source inner wall 169 of the organic insulating layer 31 within the second source opening 173. 【0370】 Specifically, the second outer plating layer 194 has a laminated structure including a second Pd plating layer 195 and a second Au plating layer 196 laminated in this order from the side of the second Ni plating layer 193. The second Pd plating layer 195 is formed in a film shape along the outer surface of the second Ni plating layer 193. The second Pd plating layer 195 covers the second Ni plating layer 193 at an interval from the opening end of the second source opening 173 toward the inorganic insulating layer 30 side. 【0371】 The second Pd plating layer 195 partially covers the source inner peripheral edge 174 of the inorganic insulating layer 30 at an interval from the second source inner wall 169 of the organic insulating layer 31 toward the first source inner wall 164 of the inorganic insulating layer 30 within the second source opening 173 so that a part of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. Thereby, the second Pd plating layer 195 exposes a part of the source inner peripheral edge 174 of the inorganic insulating layer 30 and the entire area of the second source inner wall 169 of the organic insulating layer 31 within the second source opening 173. 【0372】 The second Pd plating layer 195 has a thickness less than the thickness T4 of the second Ni plating layer 193. The thickness of the second Pd plating layer 195 may be 0.01 μm or more and 1 μm or less. The thickness of the second Pd plating layer 195 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less. 【0373】 The second Au plating layer 196 is formed in a film-like manner along the outer surface of the second Pd plating layer 195. The second Au plating layer 196 covers the second Pd plating layer 195 with a gap from the opening end of the second source opening 173 toward the inorganic insulating layer 30. 【0374】 The second Au plating layer 196 partially covers the source inner periphery 174 of the inorganic insulating layer 30 within the second source opening 173, leaving a gap between the second source inner wall 169 of the organic insulating layer 31 and the first source inner wall 164 of the inorganic insulating layer 30, such that a portion of the inner periphery 38 of the inorganic insulating layer 30 is exposed. As a result, the second Au plating layer 196 exposes a portion of the source inner periphery 174 of the inorganic insulating layer 30 and the entire second source inner wall 169 of the organic insulating layer 31 within the second source opening 173. 【0375】 The second Au plating layer 196 has a thickness less than the thickness T4 of the second Ni plating layer 193. The thickness of the second Au plating layer 196 may be 0.01 μm or more and 1 μm or less. The thickness of the second Au plating layer 196 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less. 【0376】 In this embodiment, an example was described in which the second outer plating layer 194 has a laminated structure including a second Pd plating layer 195 and a second Au plating layer 196. However, a second outer plating layer 194 having a similar configuration to any one of the outer plating layers 42 in the second to fourth embodiment examples shown in Figures 8A to 8D above may be adopted. 【0377】 As described above, the semiconductor device 201 can produce the same effects as those described for the semiconductor device 101. The semiconductor device 201 can produce the same effects as those described for the semiconductor device 61. 【0378】 Figure 18 is a plan view of a semiconductor package 301, into which semiconductor devices (not shown in reference numerals) according to the first to fourth embodiments are incorporated, viewed from one side. Figure 19 is a plan view of the semiconductor package 301 shown in Figure 18, viewed from the other side. Figure 20 is a perspective view of the semiconductor package 301 shown in Figure 18. Figure 21 is an exploded perspective view of the semiconductor package 301 shown in Figure 18. Figure 22 is a cross-sectional view along the line XXII-XXII shown in Figure 18. Figure 23 is a circuit diagram of the semiconductor package 301 shown in Figure 18. 【0379】 Referring to Figures 18 to 23, the semiconductor package 301 in this embodiment has a form referred to as a power guard. The semiconductor package 301 includes a resin package body 302. The package body 302 consists of a mold resin containing a filler (e.g., an insulating filler) and a matrix resin. The matrix resin is preferably made of epoxy resin. 【0380】 The package body 302 has a first main surface 303 (first surface) on one side, a second main surface 304 (second surface) on the other side, and sides 305A to 305D connecting the first main surface 303 and the second main surface 304. The first main surface 303 and the second main surface 304 are formed in a quadrilateral shape (rectangular in this form) when viewed from the direction of their normal Z in a plan view. 【0381】 Sides 305A to 305D include the first side 305A, the second side 305B, the third side 305C, and the fourth side 305D. The first side 305A and the second side 305B extend along the first direction X and face the second direction Y which intersects the first direction X. The first side 305A and the second side 305B form the long side of the package body 302. The third side 305C and the fourth side 305D extend along the second direction Y and face the first direction X. The third side 305C and the fourth side 305D form the short side of the package body 302. Specifically, the second direction Y is perpendicular to the first direction X. 【0382】 The semiconductor package 301 includes a first metal plate 310 disposed within the package body 302. The first metal plate 310 is positioned on the first main surface 303 side of the package body 302 and integrally includes a first heat dissipation portion 311 and a first terminal portion 312. The first heat dissipation portion 311 is positioned within the package body 302 so as to be exposed from the first main surface 303. The first heat dissipation portion 311 is formed in a rectangular shape extending along a first direction X in a plan view. The first heat dissipation portion 311 has a planar area less than the planar area of ​​the first main surface 303 and is exposed from the first main surface 303 with a gap inward from the side surfaces 305A to 305D. 【0383】 The first terminal portion 312 is exposed from the first side surface 305A. Specifically, the first terminal portion 312 extends in a strip shape from the first heat dissipation portion 311 toward the first side surface 305A, penetrates the first side surface 305A, and is drawn out to the outside of the package body 302. The first heat dissipation portion 311 is located on the fourth side surface 305D side with respect to the central line LC that crosses the center of the first side surface 305A (second side surface 305B) in the second direction Y. 【0384】 The first terminal portion 312 has a first length L1 with respect to the second direction Y. The width of the first terminal portion 312 in the first direction X is less than the width of the first heat dissipation portion 311 in the first direction X. The first terminal portion 312 is connected to the first heat dissipation portion 311 via a bent portion 313 that is bent from the first main surface 303 side to the second main surface 304 side within the package body 302. As a result, the first terminal portion 312 is exposed from the first side surface 305A with a gap between the first main surface 303 and the second main surface 304 side. 【0385】 The semiconductor package 301 includes a second metal plate 320 disposed within the package body 302. The second metal plate 320 is positioned on the second main surface 304 side of the package body 302 at a distance from the first metal plate 310, and integrally includes a second heat dissipation section 321 and a second terminal section 322. The second heat dissipation section 321 is positioned within the package body 302 so as to be exposed from the second main surface 304. The second heat dissipation section 321 is formed in a rectangular shape extending along the first direction X in a plan view. The second heat dissipation section 321 has a planar area less than the planar area of ​​the second main surface 304 and is exposed from the second main surface 304 at a distance inward from the side surfaces 305A to 305D. 【0386】 The second terminal portion 322 is exposed from the first side surface 305A. Specifically, the second terminal portion 322 extends in a strip shape from the second heat dissipation portion 321 toward the first side surface 305A, penetrates the first side surface 305A, and is drawn out to the outside of the package body 302. The second terminal portion 322 is located on the third side surface 305C side with respect to the central line LC. 【0387】 In this embodiment, the second terminal portion 322 has a second length L2 that is different from the first length L1 of the first terminal portion 312 with respect to the second direction Y. The first terminal portion 312 and the second terminal portion 322 are distinguished by their shape (length). The second length L2 of the second terminal portion 322 may be greater than or less than the first length L1. Of course, a second terminal portion 322 having a second length L2 equal to the first length L1 may also be formed. 【0388】 The width of the second terminal portion 322 in the first direction X is less than the width of the second heat dissipation portion 321 in the first direction X. The second terminal portion 322 is connected to the second heat dissipation portion 321 via a bent portion 323 that is bent from the second main surface 304 side to the first main surface 303 side within the package body 302. As a result, the second terminal portion 322 is exposed from the second side surface 305B with a gap between the second main surface 304 and the first main surface 303 side. 【0389】 The second terminal portion 322 is drawn out from a different thickness position than the first terminal portion 312 with respect to the normal direction Z. In this embodiment, the second terminal portion 322 is formed with a gap between it and the first terminal portion 312 toward the second main surface 304. The second terminal portion 322 does not face the first terminal portion 312 with respect to the first direction X. 【0390】 The semiconductor package 301 includes one or more (five in this embodiment) control terminals 330 located within the package body 302. The control terminals 330 are exposed from the second side surface 305B, which is opposite to the first side surface 305A, where the first terminal portion 312 and the second terminal portion 322 are exposed. The control terminals 330 are located on the third side surface 305C side with respect to the central line LC. In a plan view, the control terminals 330 are aligned in a straight line with the second terminal portion 322 of the second metal plate 320. The arrangement of the control terminals 330 is arbitrary. 【0391】 Each of the control terminals 330 is formed in a strip shape extending along the second direction Y. Specifically, each of the control terminals 330 includes an internal connection part 331, an external connection part 332, and a strip-shaped part 333. The internal connection part 331 is located inside the package body 302. The external connection part 332 is located outside the package body 302. 【0392】 The strip-shaped portion 333 extends in a strip shape from the internal connection portion 331, through the second side surface 305B, toward the external connection portion 332. The strip-shaped portion 333 may have a curved portion 334 that is recessed toward the second main surface 304 in the portion located outside the package body 302. Of course, a strip-shaped portion 333 without the curved portion 334 may also be formed. 【0393】 The multiple control terminals 330 are drawn out from different thickness positions with respect to the normal direction Z than the first heat dissipation section 311 and the second heat dissipation section 321. In this embodiment, the multiple control terminals 330 are spaced apart from the first heat dissipation section 311 and the second heat dissipation section 321 and are located in the region between the first heat dissipation section 311 and the second heat dissipation section 321. 【0394】 The semiconductor package 301 includes an SBD chip 341 and a MISFET chip 342 disposed within the package body 302. The SBD chip 341 consists of one of the semiconductor devices (reference numerals omitted) according to the first to second embodiments. The MISFET chip 342 consists of one of the semiconductor devices (reference numerals omitted) according to the third to fourth embodiments. 【0395】 The SBD chip 341 is located within the package body 302 in the space sandwiched between the first heat dissipation section 311 and the second heat dissipation section 321. The SBD chip 341 is located on the fourth side 305D of the package body 302 with respect to the central line LC. The SBD chip 341 is positioned on the second heat dissipation section 321 with the second main surface electrode 46 facing the second heat dissipation section 321. 【0396】 The MISFET chip 342 is positioned within the package body 302, spaced apart from the SBD chip 341, in a space sandwiched between the first heat dissipation section 311 and the second heat dissipation section 321. The MISFET chip 342 is positioned on the third side surface 305C of the package body 302 with respect to the central line LC. The MISFET chip 342 is positioned on the second heat dissipation section 321 with its second main surface electrode 46 facing the second heat dissipation section 321. 【0397】 The semiconductor package 301 includes a first conductive bonding material 343 and a second conductive bonding material 344. The first conductive bonding material 343 and the second conductive bonding material 344 each include solder or metal paste, respectively. The first conductive bonding material 343 is interposed between the second main surface electrode 46 and the second heat dissipation section 321 of the SBD chip 341, connecting the SBD chip 341 and the second heat dissipation section 321 thermally, mechanically, and electrically. The second conductive bonding material 344 is interposed between the second main surface electrode 46 and the second heat dissipation section 321 of the MISFET chip 342, connecting the MISFET chip 342 and the second heat dissipation section 321 thermally, mechanically, and electrically. 【0398】 As a result, the cathode of the SBD chip 341 is electrically connected to the drain of the MISFET chip 342. In other words, the second metal plate 320 (second heat dissipation section 321) functions as the cathode-drain terminal for the SBD chip 341 and the MISFET chip 342. 【0399】 The semiconductor package 301 includes a first metal spacer 351 and a second metal spacer 352. In this embodiment, the first metal spacer 351 and the second metal spacer (plate-shaped member) 352 each consist of a plate-shaped member containing copper. The second metal spacer 352 has a thickness equal to that of the first metal spacer 351. 【0400】 The first metal spacer 351 is interposed between the SBD chip 341 and the first heat dissipation section 311, separating the SBD chip 341 from the first heat dissipation section 311. The second metal spacer 352 is interposed between the MISFET chip 342 and the first heat dissipation section 311, separating the MISFET chip 342 from the first heat dissipation section 311. In this embodiment, the first metal spacer 351 and the second metal spacer 352 are separate components, but they may be integrally formed. 【0401】 The semiconductor package 301 includes a third conductive bonding material 353 and a fourth conductive bonding material 354. The third conductive bonding material 353 and the fourth conductive bonding material 354 each include solder or metal paste. Preferably, the third conductive bonding material 353 and the fourth conductive bonding material 354 each consist of solder. 【0402】 The third conductive bonding material 353 is interposed between the pad electrode 40 of the SBD chip 341 and the first metal spacer 351, connecting the SBD chip 341 and the first metal spacer 351 thermally, mechanically, and electrically. The fourth conductive bonding material 354 is interposed between the source pad electrode 182 of the MISFET chip 342 and the second metal spacer 352, connecting the MISFET chip 342 and the second metal spacer 352 thermally, mechanically, and electrically. 【0403】 The semiconductor package 301 includes a fifth conductive bonding material 355 and a sixth conductive bonding material 356. The fifth conductive bonding material 355 and the sixth conductive bonding material 356 each include solder or metal paste, respectively. The fifth conductive bonding material 355 is interposed between the first heat dissipation section 311 and the first metal spacer 351, and connects the first heat dissipation section 311 and the first metal spacer 351 thermally, mechanically, and electrically. The sixth conductive bonding material 356 is interposed between the first heat dissipation section 311 and the second metal spacer 352, and connects the first heat dissipation section 311 and the second metal spacer 352 thermally, mechanically, and electrically. 【0404】 As a result, the anode of the SBD chip 341 is electrically connected to the source of the MISFET chip 342. In other words, the first metal plate 310 (first heat dissipation section 311) functions as an anode-source terminal for the SBD chip 341 and the MISFET chip 342. 【0405】 The semiconductor package 301 includes one or more (five in this embodiment) wires 357. The wires 357 are also called bonding wires. The wires 357 may consist of gold wire, copper wire, or aluminum wire. The multiple wires 357 are connected to the gate pad electrodes 181 and the internal connection portions 331 of the multiple control terminals 330 of the MISFET chip 342, respectively. 【0406】 As a result, the gate of the MISFET chip 342 is electrically connected to multiple control terminals 330. In other words, each of the multiple control terminals 330 functions as a gate terminal of the MISFET chip 342. The conductor 357 does not need to connect all of the control terminals 330 and the gate pad electrode 181. Any control terminal 330 may be electrically open. 【0407】 As described above, the semiconductor package 301 connects the first conductive bonding material 343 to the pad electrode 40 of the SBD chip 341. The pad electrode 40 of the SBD chip 341 includes a Ni plating layer 41 and an outer plating layer 42, as described in the first and second embodiments. This allows the first conductive bonding material 343 to be properly connected to the pad electrode 40 of the SBD chip 341. Thus, the SBD chip 341 can be properly connected to the first heat dissipation section 311 and the second heat dissipation section 321 thermally, mechanically, and electrically. 【0408】 If the SBD chip 341 does not have an organic insulating layer 31, cracks or delamination may occur in the pad electrodes 40, etc., of the SBD chip 341 due to fillers contained in the package body 302. This type of problem is called filler attack and is one of the factors that reduces the reliability of the pad electrodes 40, etc. Therefore, in the SBD chip 341, an organic insulating layer 31 is formed on top of the inorganic insulating layer 30. As a result, the organic insulating layer 31 acts as a cushion against the fillers, so the pad electrodes 40, etc., can be properly protected from filler attack. 【0409】 Furthermore, as described in the first and second embodiments, the SBD chip 341 has a structure in which the Ni plating layer 41 is connected to the inner peripheral edge 38 of the inorganic insulating layer 30, in a structure equipped with an organic insulating layer 31. This effectively suppresses cracks and peeling of the Ni plating layer 41 (outer plating layer 42) caused by filler attack. 【0410】 According to the semiconductor package 301, the second conductive bonding material 344 is connected to the source pad electrode 182 of the MISFET chip 342. The source pad electrode 182 of the MISFET chip 342 includes a second Ni plating layer 193 and a second outer plating layer 194, as described in the third and fourth embodiments. This allows the second conductive bonding material 344 to be properly connected to the source pad electrode 182 of the MISFET chip 342. Thus, the MISFET chip 342 can be properly connected thermally, mechanically, and electrically to the first heat dissipation section 311 and the second heat dissipation section 321. 【0411】 If the MISFET chip 342 does not have an organic insulating layer 31, cracks or delamination may occur in the source pad electrode 182, etc., of the MISFET chip 342 due to fillers contained in the package body 302. This type of problem is called filler attack and is one of the factors that reduces the reliability of the source pad electrode 182, etc. Therefore, in the MISFET chip 342, an organic insulating layer 31 is formed on top of the inorganic insulating layer 30. As a result, the organic insulating layer 31 acts as a cushion against fillers, so that the source pad electrode 182, etc., can be properly protected from filler attack. 【0412】 Furthermore, as described in the third and fourth embodiments, the MISFET chip 342 has a structure in which the second Ni plating layer 193 is connected to the first source inner wall 164 of the inorganic insulating layer 30, in a structure equipped with an organic insulating layer 31. This effectively suppresses cracks and peeling of the second Ni plating layer 193 (second outer plating layer 194) caused by filler attack. The MISFET chip 342 can achieve the same effects on the gate pad electrode 181 side as on the source pad electrode 182 side. 【0413】 In this embodiment, an example was described in which the semiconductor package 301 includes an SBD chip 341 and a MISFET chip 342. However, a semiconductor package 301 including only one of the SBD chip 341 and the MISFET chip 342 may be used. A semiconductor package 301 including multiple SBD chips 341 and / or multiple MISFET chips 342 may also be used. 【0414】 Embodiments of the present invention can be carried out in yet other forms. 【0415】 In the third and fourth embodiments described above, if increasing the gate threshold voltage Vth is not a concern, the gate electrode 107 may contain n-type polysilicon doped with n-type impurities instead of p-type polysilicon. In this case, a first low-resistance layer 112 made of n-type polyside is formed. With such a structure, the gate resistance can be further reduced. 【0416】 In the third and fourth embodiments described above, n-type polysilicon with added n-type impurities may be included instead of p-type polysilicon. In the third and fourth embodiments described above, a structure may be adopted in which either or both of the first low-resistance layer 112 and the second low-resistance layer 131 are not formed. 【0417】 In the aforementioned third and fourth embodiments, n + Instead of a drain region of type p +A collector region of type may be employed. This structure allows for the provision of an IGBT (Insulated Gate Bipolar Transistor) instead of a MISFET. In this case, in the third and fourth embodiments described above, the "source" of the MISFET is replaced with the "emitter" of the IGBT, and the "drain" of the MISFET is replaced with the "collector" of the IGBT. 【0418】 In each of the embodiments described above, a Si chip made of a Si single crystal may be used instead of the SiC chip 2. In other words, the semiconductor device (reference numerals omitted) in each of the embodiments described above may be a Si semiconductor device. In each of the embodiments described above, a structure in which the conductivity type of each semiconductor portion is reversed may be adopted. In other words, the p-type portion may be made n-type, and the n-type portion may be made p-type. 【0419】 The following are examples of features extracted from this specification and drawings. [A1] to [A19], [B1] to [B15], and [C1] to [C16] below provide a semiconductor device that can improve the reliability of the Ni plating layer in a structure in which a Ni plating layer is formed on an electrode exposed from an opening in an organic insulating layer. 【0420】 [A1] A semiconductor device comprising: a chip; an electrode formed on the chip; an inorganic insulating layer covering the electrode and having a first opening that exposes the electrode; an organic insulating layer covering the inorganic insulating layer and having a second opening that surrounds the first opening at a distance from the first opening, exposing the inner edge of the inorganic insulating layer in the region between the first and second openings; and a Ni plating layer covering the electrode within the first opening and covering the inner edge of the inorganic insulating layer within the second opening. 【0421】 [A2] The semiconductor device according to A1, wherein the Ni plating layer covers the organic insulating layer within the second opening. 【0422】 [A3] The semiconductor device according to A2, wherein the Ni plating layer is formed with a gap from the opening end of the second opening toward the inorganic insulating layer. 【0423】 [A4] The semiconductor device according to A2 or A3, wherein the Ni plating layer covers the organic insulating layer in the second opening such that the exposed area of ​​the organic insulating layer exceeds the concealed area of ​​the organic insulating layer. 【0424】 [A5] The semiconductor device according to any one of A2 to A4, wherein the inner periphery of the inorganic insulating layer has a width less than or equal to the thickness of the inorganic insulating layer. 【0425】 [A6] The semiconductor device according to any one of A2 to A5, further comprising an outer plating layer that covers the outer surface of the Ni plating layer within the second opening. 【0426】 [A7] The semiconductor device according to A6, wherein the outer plating layer covers the organic insulating layer within the second opening. 【0427】 [A8] The semiconductor device according to A6 or A7, wherein the outer plating layer covers the Ni plating layer with a gap from the opening end of the second opening toward the inorganic insulating layer. 【0428】 [A9] The semiconductor device according to any one of A6 to A8, wherein the outer plating layer has a thickness less than the thickness of the Ni plating layer. 【0429】 [A10] The semiconductor device according to A1, wherein the Ni plating layer covers the inner periphery of the inorganic insulating layer at a distance from the organic insulating layer within the second opening. 【0430】 [A11] The semiconductor device according to A10, wherein the Ni plating layer is formed with a gap from the opening end of the second opening toward the inorganic insulating layer. 【0431】 [A12] The semiconductor device according to A10 or A11, wherein the inner periphery of the inorganic insulating layer has a width exceeding the thickness of the inorganic insulating layer. 【0432】 [A13] The semiconductor device according to any one of A10 to A12, further comprising an outer plating layer that covers the outer surface of the Ni plating layer within the second opening. 【0433】 [A14] The semiconductor device according to A13, wherein the outer plating layer covers the inner periphery of the inorganic insulating layer. 【0434】 [A15] The semiconductor device according to A13 or A14, wherein the outer plating layer covers the Ni plating layer at a distance from the organic insulating layer. 【0435】 [A16] The semiconductor device according to any one of A13 to A15, wherein the outer plating layer covers the Ni plating layer with a gap from the opening end of the second opening toward the inorganic insulating layer. 【0436】 [A17] The semiconductor device according to any one of A13 to A16, wherein the outer plating layer has a thickness less than the thickness of the Ni plating layer. 【0437】 [A18] The semiconductor device described in any one of A1 to A17, wherein the chip is a SiC chip. 【0438】 [A19] A semiconductor package comprising: a resin package body having a first surface on one side, a second surface on the other side, and a side; a first metal plate having a first heat dissipation portion exposed from the first surface and a first terminal portion exposed from the side, and disposed within the package body; a second metal plate having a second heat dissipation portion exposed from the second surface and a second terminal portion exposed from the side, and disposed within the package body at a distance from the first metal plate toward the second surface; and a semiconductor device according to any one of A1 to A18 disposed within the package body in the space sandwiched between the first heat dissipation portion and the second heat dissipation portion. 【0439】 [B1] A chip, an electrode formed on the chip, an inorganic insulating layer covering the electrode and having a first opening that exposes the electrode, an organic insulating layer covering the inorganic insulating layer and having a second opening that surrounds the first opening at a distance from the first opening, exposing the inner edge of the inorganic insulating layer in the region between the first and second openings, and a Ni plating layer covering the electrode within the first opening and covering the inner edge of the inorganic insulating layer within the second opening, A semiconductor device wherein the organic insulating layer has a second outer wall located inward from the first outer wall of the inorganic insulating layer. 【0440】 [B2] The semiconductor device according to B1, wherein the Ni plating layer is formed with a gap from the opening end of the second opening toward the inorganic insulating layer. 【0441】 [B3] The semiconductor device according to B1 or B2, further comprising an outer plating layer that covers the outer surface of the Ni plating layer within the second opening. 【0442】 [B4] The semiconductor device according to B3, wherein the outer plating layer has a thickness less than the thickness of the Ni plating layer. 【0443】 [B5] The semiconductor device according to any one of B1 to B4, wherein the inner periphery of the inorganic insulating layer has a width exceeding the thickness of the inorganic insulating layer. 【0444】 [B6] The semiconductor device according to any one of B1 to B5, wherein the second outer wall of the organic insulating layer is formed in a curved shape that is recessed toward the inorganic insulating layer side. 【0445】 [B7] The semiconductor device according to any one of items B1 to B6, wherein the chip is a SiC chip. 【0446】 [B8] The semiconductor device according to any one of B1 to B7, further comprising a transistor formed on the chip. 【0447】 [B9] The semiconductor device according to B8, wherein the transistor includes a plurality of unit cells extending in a stripe shape. 【0448】 [B10] The semiconductor device according to B9, wherein the transistor includes a plurality of trench gate structures extending in a stripe-like manner along the plurality of unit cells. 【0449】 [B11] The chip has a rectangular shape in plan view, The semiconductor device according to B10, wherein the plurality of trench gate structures extend along the short side of the chip. 【0450】 [B12] The semiconductor device according to any one of B1 to B10, wherein the chip has a rectangular shape in plan view. 【0451】 [B13] The chip has a second main surface opposite to the first main surface covered by the electrode, The second main surface further includes a back surface electrode, The semiconductor device according to any one of B1 to B12, wherein the back electrode includes a Ti layer. 【0452】 [B14] The chip has a second main surface opposite to the first main surface covered by the electrode, The second main surface further includes a back surface electrode, The semiconductor device according to any one of B1 to B12, wherein the back electrode includes a Ni layer. 【0453】 [B15] A resin package body, A plate-shaped member containing copper is placed inside the package body, The package includes, The electrode includes a source pad electrode, A semiconductor package in which the plate-shaped member is electrically connected to the source pad electrode. 【0454】 [C1] A chip having sides, An electrode formed on the aforementioned chip, An inorganic insulating layer covers the electrode and exposes the electrode through the first opening, An organic insulating layer covering the inorganic insulating layer, having a second opening with an opening end formed at a distance from the opening end of the first opening, and exposing the inner peripheral edge of the inorganic insulating layer in the region between the first opening and the second opening, The invention includes a Ni plating layer that covers the electrode within the first opening and covers the inner peripheral edge of the inorganic insulating layer within the second opening, The organic insulating layer has a second outer wall located inward from the first outer wall of the inorganic insulating layer. The second outer wall is formed along a cutting line with a gap inward from the side surface, in a semiconductor device. 【0455】 [C2] The semiconductor device according to C1, wherein the first outer wall of the inorganic insulating layer is formed with a gap inward from the side surface. 【0456】 [C3] The semiconductor device according to C1 or C2, wherein the Ni plating layer is formed with a gap from the opening end of the second opening toward the inorganic insulating layer. 【0457】 [C4] The semiconductor device according to any one of C1 to C3, further comprising an outer plating layer that covers the outer surface of the Ni plating layer within the second opening. 【0458】 [C5] The semiconductor device according to C4, wherein the outer plating layer has a thickness less than the thickness of the Ni plating layer. 【0459】 [C6] The semiconductor device according to any one of C1 to C5, wherein the inner periphery of the inorganic insulating layer has a width exceeding the thickness of the inorganic insulating layer. 【0460】 [C7] The semiconductor device according to any one of C1 to C6, wherein the second outer wall of the organic insulating layer is formed in a curved shape that is recessed toward the inorganic insulating layer. 【0461】 [C8] The chip is a SiC chip, and the semiconductor device is as described in any one of C1 to C7. 【0462】 [C9] The semiconductor device according to any one of C1 to C8, further comprising a transistor formed on the chip. 【0463】 [C10] The semiconductor device according to C9, wherein the transistor includes a plurality of unit cells extending in a stripe shape. 【0464】 [C11] The semiconductor device according to C10, wherein the transistor includes a plurality of trench gate structures extending in a stripe-like manner along the plurality of unit cells. 【0465】 [C12] The chip has a rectangular shape in plan view, The semiconductor device according to C11, wherein the plurality of trench gate structures extend along the short side of the chip. 【0466】 [C13] The semiconductor device according to any one of C1 to C11, wherein the chip has a rectangular shape in a plan view. 【0467】 [C14] The tip has a second main surface opposite to the first main surface covered by the electrode, The second main surface further includes a back surface electrode, The aforementioned back electrode is a semiconductor device according to any one of C1 to C13, including a Ti layer. 【0468】 [C15] The tip has a second main surface opposite to the first main surface covered by the electrode, The second main surface further includes a back surface electrode, The aforementioned back electrode is a semiconductor device according to any one of C1 to C13, comprising a Ni layer. 【0469】 [C16] A resin package body, A plate-shaped member containing copper is placed inside the package body, The package body includes a semiconductor device described in any one of C1 to C15, The electrode includes a source pad electrode, A semiconductor package in which the plate-shaped member is electrically connected to the source pad electrode. 【0470】 This application corresponds to Japanese Patent Application No. 2019-180861, filed with the Japan Patent Office on September 30, 2019, and the full disclosure of that application is incorporated herein by reference. Although embodiments of the present invention have been described in detail, these are merely examples used to illustrate the technical content of the present invention, and the present invention should not be construed as being limited to these examples, and the scope of the present invention is limited only by the appended claims. [Explanation of symbols] 【0471】 1 Semiconductor device 2 SiC chips (chips) 21 1st main surface electrode (electrode) 30 Inorganic insulating layer 31 Organic insulating layer 34. First opening 37. Second opening 38 Inner edge of the inorganic insulating layer 41 Ni plating layer (metal layer) 42 Outer plating layer 61 Semiconductor Equipment 101 Semiconductor Equipment 153 Gate main surface electrode (electrode) 155 Source main surface electrode (electrode) 166 First Gate Opening (First Opening) 167 First source opening (first opening) 171 Second Gate Opening (Second Opening) 172 Inner peripheral edge of the gate of the inorganic insulating layer 173 Second source opening (second opening) 174 Source inner periphery of inorganic insulating layer 183 First Ni plating layer (metal layer) 184 First outer plating layer 193 Second Ni plating layer (metal layer) 194 Second outer plating layer 201 Semiconductor Equipment 301 Semiconductor Package 302 Package Body 303 First Main Surface (First Surface) 304 Second Main Surface (Second Surface) 305A side 305B side 305C side 305D side 310 1st metal plate 311 1st heat dissipation section 312 1st terminal section 320 Second metal plate 321 2nd heat dissipation section 322 2nd terminal section 341 SBD chip (semiconductor device) 342 MISFET chips (semiconductor equipment) 351 First Metal Spacer 352 Second Metal Spacer T2 Thickness of the inorganic insulating layer T4 Ni plating layer thickness T5 Thickness of the outer plating layer W Width of the inner edge of the inorganic insulating layer Width of the inner peripheral edge of the gate of the WG inorganic insulating layer Width of the inner peripheral edge of the source of the WS inorganic insulating layer

Claims

[Claim 1] A chip with sides, An electrode formed on the aforementioned chip, An inorganic insulating layer covers the electrode and exposes the electrode through the first opening, An organic insulating layer covering the inorganic insulating layer, having a second opening with an opening end formed at a distance from the opening end of the first opening, and exposing the inner peripheral edge of the inorganic insulating layer in the region between the first opening and the second opening, The present invention includes a metal layer formed on the electrode, which covers the electrode within the first opening and covers the inner peripheral edge of the inorganic insulating layer within the second opening, The organic insulating layer has a second outer wall located inward from the first outer wall of the inorganic insulating layer. The semiconductor device is formed such that the second outer wall is located along the side surface and is spaced inward from the side surface. [Claim 2] The semiconductor device according to claim 1, wherein the first outer wall of the inorganic insulating layer is formed with a gap inward from the side surface. [Claim 3] The semiconductor device according to claim 1 or 2, wherein the metal layer is formed with a gap from the opening end of the second opening toward the inorganic insulating layer. [Claim 4] The semiconductor device according to any one of claims 1 to 3, further comprising an outer plating layer that covers the outer surface of the metal layer within the second opening. [Claim 5] The semiconductor device according to claim 4, wherein the outer plating layer has a thickness less than the thickness of the metal layer. [Claim 6] The semiconductor device according to any one of claims 1 to 5, wherein the metal layer includes a Ni plating layer. [Claim 7] The semiconductor device according to any one of claims 1 to 6, wherein the inner periphery of the inorganic insulating layer has a width exceeding the thickness of the inorganic insulating layer. [Claim 8] The semiconductor device according to any one of claims 1 to 7, wherein the second outer wall of the organic insulating layer is formed in a curved shape that is recessed toward the inorganic insulating layer. [Claim 9] The semiconductor device according to any one of claims 1 to 8, wherein the chip is made of a SiC chip. [Claim 10] The semiconductor device according to any one of claims 1 to 9, further comprising a transistor formed on the chip. [Claim 11] The semiconductor device according to claim 10, wherein the transistor includes a plurality of unit cells extending in a stripe shape. [Claim 12] The semiconductor device according to claim 11, wherein the transistor includes a plurality of trench gate structures extending in a stripe shape along the plurality of unit cells. [Claim 13] The aforementioned chip has a rectangular shape in plan view, The semiconductor device according to claim 12, wherein the plurality of trench gate structures extend along the short side of the chip. [Claim 14] The semiconductor device according to any one of claims 1 to 12, wherein the chip has a rectangular shape in plan view. [Claim 15] The chip has a second main surface opposite to the first main surface covered by the electrode, The second main surface further includes a back surface electrode, The semiconductor device according to any one of claims 1 to 14, wherein the back electrode includes a Ti layer. [Claim 16] The chip has a second main surface opposite to the first main surface covered by the electrode, The second main surface further includes a back surface electrode, The semiconductor device according to any one of claims 1 to 14, wherein the back electrode includes a Ni layer. [Claim 17] The resin package body and A plate-shaped member containing copper is placed inside the package body, The package body includes a semiconductor device according to any one of claims 1 to 16, The metal layer includes a source pad electrode. A semiconductor package in which the plate-shaped member is electrically connected to the source pad electrode.

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