Semiconductor device and method for manufacturing the same

Abstract

The semiconductor device (100) comprises a semiconductor body (10) having a top surface (11) and a bottom surface (19). A first main electrode (2) is disposed on the top surface, and a second main electrode (3) is disposed on the bottom surface. The semiconductor device comprises a gate electrode (3) and at least two trenches, namely, a first type trench (51) and a second type trench (52). The semiconductor body includes a drift region (14) disposed vertically between the top surface and the bottom surface, and at least two base regions (13a, 13b), each disposed vertically between the drift region and the top surface. The semiconductor body further includes an implantation region (12) adjacent to the first base region. The first main electrode is in electrical contact with the implantation region. A gate electrode extends into the first type trench. The second type trench is free of a gate electrode. The second type trench extends deeper into the semiconductor body than the first type trench.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device.

Background Art

[0002] There is a need for improved semiconductor devices, for example, semiconductor devices having improved static and / or dynamic behavior. Further, there is a demand for a method of manufacturing such semiconductor devices.

Summary of the Invention

Means for Solving the Problems

[0003] Embodiments of the present disclosure relate to a semiconductor device and a method of manufacturing a semiconductor device. First, the present semiconductor device will be described.

[0004] According to one embodiment, the semiconductor device comprises a semiconductor body extending vertically between a top surface and a bottom surface. A first main electrode is located on the top surface, and a second main electrode is located on the bottom surface. Furthermore, the semiconductor device comprises a gate electrode and at least two trenches, namely a first type trench and a second type trench, each extending from the top surface into the semiconductor body. The semiconductor body includes a drift region of a first conductivity type, arranged vertically between the top surface and the bottom surface, and at least two base regions, namely a first and a second base region, each base region being of a second conductivity type and arranged vertically between the drift region and the top surface. The semiconductor body further includes an injection region of a first conductivity type, spaced vertically apart from the drift region by the first base region and adjacent to the first base region. The first base region, the first type trench, the second base region, and the second type trench are arranged in this order in the first lateral direction. The first main electrode is in electrical contact with the injection region. The gate electrode extends into the first type of trench, where it is isolated from the semiconductor body by a gate insulating layer. The second type of trench does not have a gate electrode. The second type of trench extends deeper into the semiconductor body than the first type of trench.

[0005] Long-term performance stability of semiconductor devices such as IGBTs requires robustness against gate insulation layer degradation. Gate insulation layer degradation can be caused by dynamic avalanches during high-current turn-off switching events. Charge carriers generated by dynamic avalanches can have sufficient energy to be injected into the gate insulation layer, altering the gate capacitance and thus the switching characteristics of the semiconductor device (e.g., due to variations in switching speed and threshold voltage). Gate insulation layer degradation is a design challenge for semiconductor devices with trench structures, particularly due to the peak of avalanche occurrence near the gate insulation layer at the bottom of the trench.

[0006] Therefore, the technical challenge is to provide a semiconductor device that improves the trade-off between long-term stability (robustness against gate insulation layer degradation) and static loss.

[0007] This problem is solved, in particular, by making the second type of trench deeper than the first type of trench. These second type trenches have been found to efficiently protect the first type trench (which is an active trench) from hot carriers generated by dynamic avalanche, thereby improving the robustness against gate insulation layer degradation in the first type trench. This improved robustness against gate insulation layer degradation allows for an expansion of design space for structural elements that reduce static losses in semiconductor devices.

[0008] The semiconductor devices described herein may also be power semiconductor devices. For example, they may be configured to carry a current of at least 10A and / or to handle a voltage of at least 1000V or at least 3000V. The semiconductor device may also be a transistor device, in particular a gate-isolated transistor device, in particular an IGFET.

[0009] The semiconductor body may be based on silicon or silicon carbide. The thickness of the semiconductor body, measured vertically, is, for example, at least 100 μm, or at least 200 μm, and / or up to 500 μm. The top and bottom surfaces are the faces of the semiconductor body and define the semiconductor body vertically.

[0010] The first and / or second main electrodes may contain or consist of metal. Depending on the type of semiconductor device, the first electrode may be referred to here as the "emitter electrode" or "source electrode," and the second main electrode as the "collector electrode" or "drain electrode."

[0011] The gate electrode may contain metal and / or highly doped polysilicon. In particular, the gate electrode is an insulating gate electrode, i.e., electrically insulated from the semiconductor body. This may be achieved, for example, with the assistance of a gate insulating layer.

[0012] The trenches extend from the top surface of the semiconductor body into the semiconductor body and terminate within the semiconductor body, for example, in the drift region. The depth of each trench, measured in the vertical direction, may be at least 1 μm or at least 5 μm and / or up to 20 μm or up to 10 μm. Each trench may be elongated, and each may extend laterally, where the later direction is defined herein as the direction perpendicular to the vertical direction. In particular, the later direction is the direction parallel to the main extending plane of the semiconductor body. For example, the trenches may extend parallel to each other.

[0013] The first type of trench and the second type of trench may be spaced apart from each other in the first transverse direction. Each trench may extend in the second transverse direction perpendicular to the first transverse direction. The average distance between the first type of trench and the second type of trench is, for example, at least 100 nm or at least 500 nm and / or up to 2 μm. The distance between two trenches is defined herein, for example, as the pitch between trenches, i.e., the distance between the centers of the trenches. For example, in the transverse direction, no further trenches are located between the first type of trench and the second type of trench.

[0014] The first type of trench is filled with a conductive material, which is isolated from the semiconductor body by a gate insulating layer. The conductive material is spatially and electrically isolated from the semiconductor body by the gate insulating layer. The gate insulating layer may be an oxide, for example, SiO2. The thickness of the gate insulating layer may be at least 10 nm and / or up to 200 nm. For example, the thickness of the gate insulating layer may be between 50 nm and 150 nm.

[0015] In this specification, “electrically isolated” means, in particular, that there is no electrical contact between the two elements. Two electrically isolated elements are configured, for example, to be electrically biased or controlled independently. This means that they are configured to be at different potentials during the operation of the semiconductor device. Two electrically isolated elements may, in particular, be electrically insulated from each other, i.e., no current can flow between them.

[0016] The conductive material in the first type of trench may be a metal and / or highly doped polysilicon. The conductive material in the first type of trench is part of the gate electrode, i.e., electrically connected to the gate electrode. When two elements are electrically connected or in contact, this means that these two elements are not independently electrically biasable or controllable. Therefore, they are always at the same potential. The first type of trench is also referred to herein as an "active trench".

[0017] For example, the conductive material in the first type of trench reaches the semiconductor body to at least the same depth as the first base region and / or the second base region.

[0018] The second type of trench lacks a gate electrode; that is, the second type of trench is a trench without a gate electrode. In other words, the second type of trench is electrically isolated from the gate electrode.

[0019] The second type of trench may also be filled with a conductive material, which may be isolated from the semiconductor body by an insulating layer. However, this conductive material is electrically isolated from the gate electrode, i.e., not electrically connected to the gate electrode. The insulating layer may be the same as the gate insulating layer. Within the second type of trench, the conductive material may reach the semiconductor body to the same depth as the first base region and / or the second base region. The conductive material in the second type of trench may be a metal and / or highly doped polysilicon.

[0020] For example, the conductive material in the second type of trench is electrically connected to the first main electrode. In other words, the first main electrode may extend into the second type of trench.

[0021] Instead of being filled with conductive material, the second type of trench may not have any conductive material at all, and may be filled only with, for example, an electrically insulating material.

[0022] The second type of trench is also referred to herein as an "inert trench." The drift region of the semiconductor body is of the first conductivity type. The first conductivity type is, for example, n-type, meaning the drift region is n-doped. The second conductivity type is the opposite of the first conductivity type and may therefore be p-type. However, the reverse case, where the first conductivity type is p-type and the second conductivity type is n-type, may also be realized.

[0023] The drift region extends continuously across all base regions, for example. That is, in a top view, the drift region overlaps with both base regions.

[0024] The first type of trench is located in the first lateral direction between the first base region and the second base region. For example, the first type of trench is adjacent to the first base region on one side and / or adjacent to the second base region on the other side.

[0025] The second base region is disposed between the first type of trench and the second type of trench in the first lateral direction. The second base region may be adjacent to the second type of trench. The second base region may extend continuously, for example, without interruption, from the first type of trench to the second type of trench.

[0026] The structure including the first base region and the adjacent implantation structure, the first type of trench, the second base region, and the second type of trench may be repeated several times along the upper surface. The structure including at least a part (half) of the first base region together with the adjacent implantation region, the first type of trench, the second base region, and the second type of trench is part of a so-called "half cell" or "transistor half cell". The semiconductor device may include several such half cells arranged successively in the first lateral direction. Each two adjacent half cells may be mirror symmetric with respect to a mirror plane. The mirror plane extends, for example, perpendicular to the first longitudinal direction. The mirror plane may cross the first base region at the midpoint of their respective extensions in the first lateral direction.

[0027] The semiconductor body includes an implantation region of the first conductivity type. The implantation region is vertically spaced from the drift region by the first base region and is adjacent to the first base region. The implantation region reaches, for example, the upper surface. The implantation region may be embedded in the first base region. For example, the implantation region is adjacent to the first type of trench on the same side where the first base region is adjacent to the first type of trench. Each half cell may include exactly one such implantation region. The implantation region is also called a source region.

[0028] The injection region is in electrical contact with the first main electrode and, for example, is adjacent to the first main electrode. During operation of the semiconductor device in (static) transistor mode, charge carriers of the first type, for example electrons, are injected from the first main electrode into the injection region. The semiconductor device forms a path for charge carriers of the first type from the injection region towards the drift region by applying a predetermined potential to the gate electrode, such that the first base region adjacent to the first type of trench is depleted and the path is configured to extend vertically along the first type of trench.

[0029] The second base region may form a part of the upper surface, for example, the entire upper surface portion that is laterally positioned between the first type of trench and the second type of trench. For example, the semiconductor body is vertically arranged between the second base region and the upper surface and has no (injection) region of the first conductivity type adjacent to the second base region.

[0030] The depth of the second type of trench measured in the vertical direction may be at least 0.5 μm or at least 1 μm or at least 1.5 μm or at least 2 μm greater than the depth of the first type of trench. For example, both the first type of trench and the second type of trench extend deeper into the semiconductor body than the first and second base regions.

[0031] As described above, the semiconductor body may include several trenches of the first type and several trenches of the second type. Each trench of the second type may be deeper than each trench of the first type. In particular, all features disclosed in relation to one trench of the first type and one trench of the second type are also disclosed for all other (adjacent) trenches of the first type and trenches of the second type (pairs).

[0032] According to a further embodiment, the semiconductor device is an IGBT or an RC - IGBT, i.e., a reverse - conducting IGBT, or a MISFET, in particular a MOSFET.

[0033] According to further embodiments, the width of a second type of trench is greater than the width of a first type of trench. The trench width is defined herein as the average or maximum extension of the trench in the transverse direction perpendicular to the principal extension direction of the trench. In particular, the width may be the extension in the first transverse direction. For example, the width of a second type of trench is at least 100 nm, at least 300 nm, or at least 500 nm greater than the width of a first type of trench.

[0034] The manufacture of this type of trench with different depths and widths is particularly easy compared to the manufacture of trenches of the same depth, as the only necessary modification is a modified layout in the trench mask. This is because the trench depth is directly related to the trench width when etching the trench, at least for some etching processes.

[0035] According to a further embodiment, the minimum distance between a first type trench and a second type trench, measured in the first lateral direction, is up to three times, twice, or 1.5 times the width of the second type trench, or up to this width. By positioning the second type trench as close as possible to the first type trench, the protection of the first type trench by the second type trench can be further improved. The minimum distance is the minimum distance at which adjacent first type trenches and second type trenches come close together. For example, the minimum distance is up to 3 μm or up to 2 μm.

[0036] According to a further embodiment, the first main electrode extends into a second type of trench, where it is separated from the semiconductor body by an electrical insulating layer. That is, the second type of trench is filled with a conductive material electrically connected to the first main electrode. The electrical insulating layer may contain or consist of the same material as the gate insulating layer. For example, the electrical insulating layer in the second type of trench is formed in the same way as the gate insulating layer, particularly with respect to the material and / or thickness.

[0037] The first type of trench and the second type of trench can be set to different potentials during operation by having the first main electrode extend into the second type of trench. Alternatively, a further electrode, independently biasable / controllable from the gate electrode and the first main electrode, may extend into the second type of trench.

[0038] According to a further embodiment, the second base region includes at least one contact region, i.e., one or more contact regions. In the contact region, the second base region is in electrical contact with an electrode of a semiconductor device different from the gate electrode, for example, it is controllable / biasable independently of the gate electrode.

[0039] During operation, charge carriers can be extracted from the semiconductor body through the contact region. Therefore, the contact region is sometimes called an "extraction region." Such an extraction region can be advantageous during switching events, for example, during transistor mode turn-off, as it helps to rapidly reduce the plasma concentration within the semiconductor body. That is, the contact region constitutes a plasma control function. On the other hand, when the semiconductor device is operated in diode mode, the electrical contact between the electrode in the contact region and the semiconductor body provides a charge carrier path that reduces on-state losses in diode mode. Since the contact region is electrically in contact with an electrode different from the gate electrode, the charge carrier path is independent of the gate electrode potential. The location of the contact region in the second base region, i.e., spaced away from the first type of trench, further reduces the occurrence of avalanche in the region of the first type of trench, thus helping to protect the gate insulating layer in the first type of trench during switching events.

[0040] For example, the electrode to which the second base region is electrically connected in the contact region is located on the upper surface. The electrode may be the first main electrode or another electrode that can be controlled independently of the first main electrode.

[0041] The contact area belongs to the second base area and is therefore also referred to herein as the second contact area. The contact area may form part of the top surface. The second base area may be adjacent to the electrode over the entire area of ​​the contact area. In a top view of the top surface, the area of ​​the contact area is, in particular, smaller than the area of ​​the second base area. For example, in this top view, the area of ​​the contact area is 50% or less, 10% or less, 5% or less, or 1% or less of the area of ​​the second base area. For some contact areas, all features disclosed for one contact area are also disclosed for the other contact areas.

[0042] According to further embodiments, the second base region includes a plurality of contact regions. The second base region is in electrical contact with an electrode, for example, a first main electrode, in each of these contact regions. The contact regions may be spaced apart from each other in the lateral direction, for example, in the first and / or second lateral directions. All features disclosed in relation to one contact region of the second base region are also disclosed for all other contact regions of the second base region.

[0043] In a top view of the upper surface, the contact area within the second base area may be formed as a stripe, rectangle, or square.

[0044] For each pair of adjacent contact regions within the second base region, the two adjacent contact regions may be spaced apart from each other. Outside the contact regions, there is no direct electrical contact between the electrode and the second base region. In particular, outside the contact regions, the electrode is not adjacent to the second base region. For example, multiple contact regions of the second base region are arranged in a rectangular pattern when viewed from above. For example, when viewed from above, up to 50% and / or at least 10% of the area of ​​the second base region is formed by the contact regions.

[0045] According to a further embodiment, the distance between a first type trench and a second type trench, measured in a first transverse direction, changes as it moves along a second transverse direction, which is perpendicular to the first transverse direction. For example, this distance changes such that the maximum distance is at least 1.5 times or at least 2 times greater than the minimum distance. The maximum distance is the maximum distance that adjacent first type trenches and second type trenches are separated from each other.

[0046] According to a further embodiment, the contact areas within the second base area are spaced apart from each other in the second lateral direction. For example, the distance between adjacent contact areas in the second lateral direction is greater than the maximum distance between the first type of trench and the second type of trench, for example, at least twice or at least four times greater than this maximum distance.

[0047] According to further embodiments, the distance between the first type of trench and the second type of trench is greater when a contact area is located between them, and smaller when a contact area is not located between them. For example, the distance between the first type of trench and the second type of trench is greatest at the location where the contact area is located in the second base area. The location of the contact area is its position along its second lateral direction.

[0048] In a top view, each contact area within the second base area may be surrounded by a second type trench and a first type trench. For example, in this top view, each contact area is surrounded by a second type trench on three sides and by a first type trench on the remaining fourth side. For example, in a top view, the second type trench may have the shape of a rectangular function. The maximum distance between the first type trench and the second type trench is reached within each rectangle of the rectangular function. Within each rectangle, one contact area, for example, exactly one contact area, is located. Within each rectangle, the lateral distance of the second type trench to the contact area may be at most the width of the second type trench.

[0049] According to further embodiments, a second type of trench is positioned between two first type trenches in the first lateral direction. All features disclosed in relation to one first type trench are disclosed for the other first type trench. In particular, as described above, the structure of the first base region, the first type trench, the second base region, and the second type trench may be repeated several times as moving along the first lateral direction.

[0050] According to a further embodiment, two second-type trenches are arranged between two first-type trenches in a first lateral direction. All features disclosed in relation to one second-type trench are also disclosed for the other second-type trench. For example, no further trenches are arranged between two second-type trenches in a lateral direction.

[0051] According to further embodiments, the second type of trench is located between the second base region and the third base region in the first lateral direction. For example, each second type of trench of the semiconductor device may be located between the second base region and the third base region. The second type of trench may be adjacent to the third base region on the side opposite to the side adjacent to the second base region.

[0052] Similar to the first and second base regions, the third base region is of the second conductivity type. For example, the doping concentration in the third base region is the same as the doping concentration in the first and / or second base regions.

[0053] The third base region can extend continuously, for example without interruption, from the second type of trench to a further trench spaced apart from the second type of trench in the first lateral direction. The further trench may be another second type of trench.

[0054] The third base region may also form a portion of the upper surface, for example, the entire portion of the upper surface located laterally between two trenches that laterally define the third base region. The semiconductor body may be positioned perpendicularly between the third base region and the upper surface, and may not have a first conductivity type (injection) region adjacent to the third base region.

[0055] In a further embodiment, the third base region extends into the semiconductor body from the top surface to at least the same depth as the second type of trench. For example, the third base region extends deeper into the semiconductor body than the second type of trench. Such a design has been found to further reduce the avalanche strength near the first type of trench.

[0056] In a further embodiment, the third base region extends beneath the second type of trench toward the first type of trench. Thus, in a top view toward the top surface, the second type of trench and the third base region may overlap each other.

[0057] According to a further embodiment, the third base region is positioned between two second-type trenches in the first lateral direction. The third base region may be adjacent to both second-type trenches.

[0058] In a further embodiment, two second-type trenches flanking a third base region are connected to each other at their respective longitudinal ends, i.e., their ends in the second transverse direction, so that, in a top view to the top, the third base region is completely surrounded by a continuous trench. In other words, the second-type trenches flanking the third base region are formed by a single continuous trench. In a top view to the top, the continuous trench forms a frame, for example, a rectangular frame, around the third base region. This frame-type trench helps reduce hole leakage current during the ON state.

[0059] In a further embodiment, the third base region includes at least one contact region, i.e., one or more contact regions. In the contact region, the third base region is in electrical contact with an electrode of the semiconductor device that is different from the gate electrode. This electrode may be the same electrode that is in electrical contact with the second base region and in each (second) contact region. Thus, the electrode may be, in particular, the first principal electrode. The contact region of the third base region, also referred to herein as the third contact region, may form part of the top surface. The third contact region may have a smaller area than the area of ​​the third base region when viewed in a top view to the top surface. The same relative sizes disclosed in relation to the (second) contact region of the second base region may also apply here.

[0060] The contact region of the third base region provides further flexibility for optimizing charge carrier extraction, for example, during transistor mode turn-off and / or diode mode.

[0061] According to further embodiments, the first base region includes at least one contact region, i.e., one or more contact regions. In the contact region, the first base region is in electrical contact with an electrode of the semiconductor device that is different from the gate electrode. This electrode may be the same electrode that is in electrical contact with the second and / or third base regions in their respective contact regions. Thus, the electrode may, in particular, be the first main electrode.

[0062] According to a further embodiment, the drift region includes a first drift region and a second drift region arranged vertically in succession. The first and second drift regions may be adjacent to each other. Both the first and second drift regions are of a first conductivity type.

[0063] According to a further embodiment, the second drift region is positioned perpendicularly between the first drift region and the first base region. For example, the second drift region is adjacent to the first and / or second base region.

[0064] According to further embodiments, the second drift region has a higher doping concentration than the first drift region. For example, the average or maximum doping concentration in the second drift region is at least one order of magnitude or at least two orders of magnitude greater than the average or maximum doping concentration in the first drift region. The doping concentration may increase gradually / continuously from the first drift region to the second drift region. The second drift region is also referred to as an "enhancement region" or "enhancement layer." The enhancement layer helps to further reduce on-state losses.

[0065] The enhancement layer around the channel acts to stop the injection of type 2 charge carriers, such as holes, from the bottom to the first base region. As a result, more type 1 charge carriers are injected into the drift region from the top. Therefore, the higher the doping concentration of the enhancement layer, the lower the on-state loss. In IGBT designs, a blocking junction is formed between the first base region and the n-drift region. During blocking, the thickness and resistivity of the drift region (along with the buffer layer and the collector layer of type 2 conductivity at the bottom) are designed so that the depletion layer does not reach the collector layer and thereby the device does not fail. Therefore, it does not block if the enhancement layer doping concentration is too high. When using an enhancement layer, it is preferable that the doping concentration of this layer is low enough so that this layer is completely depleted during the off-state, i.e., so that there is a trade-off between blocking loss and on-state loss.

[0066] Next, a method for manufacturing a semiconductor device will be described. For example, the semiconductor device specified herein can be manufactured by this method. Therefore, all features disclosed in relation to this semiconductor device are also disclosed in relation to this method, and vice versa.

[0067] According to one embodiment, a method for manufacturing a semiconductor device includes the step of providing a semiconductor body having a top surface and a bottom surface. Then, at least two trenches, namely a first type of trench and a second type of trench, are formed in the semiconductor body, each of which trenches extends from the top surface into the semiconductor body. Furthermore, a first main electrode is formed on the top surface of the semiconductor body, and a second main electrode is formed on the bottom surface of the semiconductor body. A gate electrode is formed to extend into the first type of trench, where it is separated from the semiconductor body by a gate insulating layer. The second type of trench has no gate electrode. The semiconductor device is formed such that the semiconductor body includes a drift region of a first conductivity type perpendicularly positioned between the top surface and the bottom surface, and at least two base regions, namely a first and a second base region, each of a second conductivity type, each of which is perpendicularly positioned between the drift region and the top surface. The semiconductor body further includes an injection region of a first conductivity type, which is perpendicularly separated from the drift region by the first base region and adjacent to the first base region. The first base region, the first type of trench, the second base region, and the second type of trench are arranged in this order in the first lateral direction. The first main electrode is in electrical contact with the injection region. The trenches are formed such that the second type of trench extends deeper into the semiconductor body than the first type of trench.

[0068] The trench may be formed within the semiconductor body before the base region and injection region are formed. Alternatively, the base region may be formed, at least partially, before the trench is formed.

[0069] According to a further embodiment, the trenches are formed in a common etching step using a common mask. The mask includes holes in the region where the trenches are to be formed. The holes for the second type of trench have a greater width than the holes for the first type of trench.

[0070] The width of the hole defines the width of the trench. Since the etching depth increases with increasing width (especially in the case of anisotropic etching processes), the first type of trench and the second type of trench are automatically formed at different depths. Therefore, a common etching step can be applied to form the first type of trench and the second type of trench. For example, to achieve the automatic formation of trenches with different depths, etching processes such as the Bosch type process (C4F8 passivation step, O2 washing step, and SF6 isotropic etching step in a continuous pulse cycle), or other anisotropic dry etching processes such as a mixture of SF6 and C4F8 can be used.

[0071] The semiconductor device and the method for manufacturing the semiconductor device will be described below with reference to the drawings, based on embodiments. The accompanying drawings are included for further understanding. In the drawings, elements of the same structure and / or function may be referred to by the same reference numeral. It should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale. To the extent that elements or components correspond to each other in terms of their function in different drawings, their descriptions will not be repeated in each of the following drawings. For clarity, elements may not appear with their corresponding reference numerals in all drawings. [Brief explanation of the drawing]

[0072] [Figure 1] Different exemplary embodiments of the semiconductor device are shown in different figures. [Figure 2] Different exemplary embodiments of the semiconductor device are shown in different figures. [Figure 3] Different exemplary embodiments of the semiconductor device are shown in different figures. [Figure 4] Different exemplary embodiments of the semiconductor device are shown in different figures. [Figure 5] Different exemplary embodiments of the semiconductor device are shown in different figures. [Figure 6] Different exemplary embodiments of the semiconductor device are shown in different figures. [Figure 7] Different exemplary embodiments of the semiconductor device are shown in different figures. [Figure 8] Different exemplary embodiments of the semiconductor device are shown in different figures. [Figure 9] Different exemplary embodiments of the semiconductor device are shown in different figures. [Figure 10] Different exemplary embodiments of the semiconductor device are shown in different figures. [Figure 11] Different exemplary embodiments of the semiconductor device are shown in different figures. [Figure 12] Different exemplary embodiments of the semiconductor device are shown in different figures. [Figure 13] Different exemplary embodiments of the semiconductor device are shown in different figures. [Figure 14] This shows different locations in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 15] This shows different locations in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 16] This shows different locations in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 17] The simulation is shown. [Figure 18] The simulation is shown. [Figure 19] The simulation is shown. [Modes for carrying out the invention]

[0073] Figure 1 shows a cross-sectional view of a first exemplary embodiment of the semiconductor device 100. In this case, the semiconductor device 100 is an RC-IGBT. It includes a semiconductor body 10 having a top surface 11 and a bottom surface 19 that are opposite to each other in the vertical direction. The semiconductor body 10 is based on, for example, Si or SiC.

[0074] At the base surface 19, the semiconductor body 10 includes alternately arranged first-type regions 15 and second-type regions 16. Regions 15 and 16 are in electrical contact with the second main electrode 3, i.e., the collector electrode 3, at the base surface 19. The collector electrode 3 is made of, for example, metal.

[0075] The first type region 15 is a first conductivity type, which is n-type, and the second type region 16 is a second conductivity type, which is p-type. The drift region 14 is located between the top surface 11 and the bottom surface 19. The drift region 14 is of the first conductivity type, i.e., n-type. The drift region 14 is adjacent to the first type region 15 and the second type region 16.

[0076] Multiple trenches 51 and 52 extend from the top surface into the semiconductor body 10 and into the drift region 14. Trench 51 is a first type of trench, also referred to herein as an "active trench," and trench 52 is a second type of trench, also referred to herein as an "inactive trench" or "dummy trench."

[0077] The first type of trench 51 is filled with a conductive material that is electrically isolated from the semiconductor body 10 by an electrical insulating layer 40, referred to herein as the “gate insulating layer”. Therefore, there is no direct electrical contact between the semiconductor body 10 and the conductive material in the first type of trench 51. The gate insulating layer 40 is formed of an oxide such as SiO2. The conductive material in the first type of trench 51 may be highly doped polysilicon. The conductive material in the first type of trench 51 is part of the gate electrode 4 of the semiconductor device 100.

[0078] The second type of trench 52 is also filled with a conductive material, such as highly doped polysilicon, which is electrically isolated from the semiconductor body 10 by the same electrical insulating layer as the gate insulating layer 40. The conductive material in the second type of trench 52 is part of the first main electrode 2, i.e., the emitter electrode 2, located on the upper surface 12. The first base region 13a is in electrical contact adjacent to the emitter electrode 2 in the first contact region 6a, also called the "Rb prime region".

[0079] The semiconductor body 10 includes several base regions 13a, 13b, and 13c arranged perpendicularly between the drift region 14 and the top surface 11. The base regions 13a, 13b, and 13c are all of the second conductivity type, i.e., p-type, and are all adjacent to the drift region 14 and the top surface 11. The first base region 13a and the second base region 13b are shallower than the trenches 51 and 52 (they have little vertical extension). The third base region 13c is deeper than the trenches 51 and 52, i.e., it extends further into the semiconductor body 10.

[0080] As shown in Figure 1, the semiconductor device 100 is subdivided into several so-called half-cells. One such half-cell is shown in more detail in Figure 2. A half-cell is the structure between the vertical dashed lines in Figure 2. In Figure 1, several such half-cells are arranged successively in a first transverse direction running from left to right. Two adjacent half-cells are mirror images of each other in a plane extending perpendicular to the first transverse direction and passing through a third base region 13c (see the right vertical dashed line in Figure 2).

[0081] As can be seen from Figure 2, the half-cell includes a portion (half) of the first base region 13c, a first type trench 51, a second base region 13b, a second type trench 52, and a portion (half) of the third base region 13c, which are arranged in this order along the first lateral direction. The half-cell further includes a first conductivity type, i.e., n-type injection region 12 (source region 12) positioned perpendicularly between the first base region 13c and the top surface 11. The injection region 12 is adjacent to the first base region 13c and the first type trench 51. The injection region 12 is also adjacent to the emitter electrode 2 and is in electrical contact with it.

[0082] The operation of the semiconductor device may be as follows: In the so-called transistor mode, the emitter electrode 2 is set to ground and the collector electrode 3 is set to positive potential. The gate electrode 4 is set to positive potential such that the first base region 13a is depleted at the boundary of the first type of trench 51. In the first base region 13c, a conductive path is formed along the first type of trench 51. Electrons are then injected from the emitter electrode 2 into the injection region 12, travel along the conductive path, and reach the drift region 14. At the bottom surface 19, holes are injected from the collector electrode 3 through the second type of region 16, and the holes travel into the drift region 14, generating an electron-hole plasma.

[0083] When the transistor mode is switched off, the electron-hole plasma can generate an avalanche in the region of the first type trench 51. Figure 17 shows a simulation of the current I and voltage V as a function of time t during the turn-off from the transistor mode. Figure 18 shows the corresponding simulated maximum avalanche generation I_max as a function of time t. In fact, a very high intensity avalanche exists during the turn-off.

[0084] Such avalanches can adversely affect the gate insulating layer 40, negatively impacting the long-term performance stability of the semiconductor device 10. A second type of inert trench 52 and a third base region 13c that extends deeper into the semiconductor body than trenches 51 and 52 have been shown to help divert the avalanche away from the active trench 51.

[0085] This effect is further enhanced by the fact that the second type of trench 52 extends more deeply into the semiconductor body, that is, has a larger vertical extension than the first type of trench 51. For example, the depth of the second type of trench 52 is at least 0.5 μm greater than the depth of the first type of trench 51.

[0086] Figure 19 shows a simulation of impact ionization along the cross-section indicated by the vertical dashed line in Figure 2. The solid curves A1, A2, and A3 show impact ionization as a function of depth Y along the first type of trench 51, and the dashed curves B1, B2, and B3 show impact ionization as a function of depth Y along the second type of trench 52.

[0087] Curves A1 and B1 show the simulation results when the depths of the first type trench 51 and the second type trench 52 are equal. Curves A2 and B2 show the simulation results when the second type trench 52 is 1 μm deeper than the first type trench 51. Curves A3 and B3 show the simulation results when the second type trench 52 is 2 μm deeper than the first type trench 51.

[0088] As can be seen from the figure, when trenches 51 and 52 have the same depth, both trenches share the same level of collisional ionization. By making the second type of trench 52 deeper than the first type of trench 51, the stress on the gate insulating layer 40 in the first type of trench 51 is significantly reduced. The collisional ionization peak at the bottom of the first type of trench 51 decreases by more than an order of magnitude when the second type of trench 52 is 1 μm deeper than the first type of trench 51, and decreases by more than two orders of magnitude when the second type of trench 52 is 2 μm deeper than the first type of trench 51.

[0089] Figure 3 shows a further exemplary embodiment of the semiconductor device 100, which in this case is an IGBT. On the top surface 11, the semiconductor device 100 is the same as the semiconductor device in Figure 1. However, the bottom surface 19 is formed only by a second type of region 16 (collector layer 16), which is a second conductivity type.

[0090] Figure 4 shows one embodiment of a semiconductor device 100, which is a MISFET. Here again, the top surface 11 is the same as in Figures 1 and 3. However, the bottom surface 19 is formed only from an n-type semiconductor material.

[0091] In the exemplary embodiment of the semiconductor device 100 shown in Figure 5, the depth of the second type of trench 52 is greater than that of the first type of trench 51, and the width measured in the first lateral direction is also greater. Trenches having different depths and, at the same time, different widths can be manufactured particularly easily.

[0092] Another exemplary embodiment of the semiconductor device 100 is shown in Figure 6. In this case, the drift region 14 includes a first drift region 14a and a second drift region 14b. The second drift region 14b is located vertically between the first drift region 14a and the base regions 13a, 13b, 13c, and is adjacent to those base regions. Trench 51, 52 extend vertically beyond the second drift region 14b and terminate within the first drift region 14a. In the second drift region 14b, the doping concentration with the n-type dopant is, for example, at least 10 times or at least 100 times greater than the doping concentration in the first drift region 14a. Such a second drift region 14b is also called an “enhancement region” or “enhancement layer” and helps to improve on-state losses.

[0093] Figures 7 to 9 show further exemplary embodiments of the semiconductor device 100 in different diagrams. Here, each second base region 13b has a second contact region 6b in which the second base region 13b is electrically in contact with the first main electrode 2. During transistor mode turn-off, at least a portion of the plasma can be extracted through these contact regions 6b so that charge carriers are effectively diverted from the first type of trench 51. As a result, avalanche generation near the first type of trench 51 is further reduced.

[0094] Figure 9 shows the semiconductor device 100 of Figure 7 in a top view to the top surface 11. The upper horizontal dashed line indicates the cross-sectional plane of the cross-sectional view in Figure 7. The lower horizontal dashed line indicates the cross-sectional plane of the cross-sectional view in Figure 8.

[0095] As can be seen from Figure 9, each of the second type of trenches 52 follows a rectangular function when moving along the second lateral direction. The second lateral direction is from bottom to top in Figure 9. In each rectangle, the distance between the second type of trench 52 and the adjacent first type of trench 51, as measured in the first lateral direction, has a maximum value. Within each rectangle, there is a contact region 6b in which each second base region 13b is electrically in contact with the first main electrode 2. In regions where there is no contact region in the second base region 13b, the distance between the first type of trench 51 and the adjacent second type of trench 52 reaches a minimum value. This minimum value is smaller than, for example, the width of the second type of trench 52, for example, 200 nm or less.

[0096] Figures 10 to 12 show further exemplary embodiments of the semiconductor device 100 in the same figures described in relation to Figures 7 to 9. The third base region 13c also includes a contact region 6c in which the third base region 13c is electrically in contact with the first main electrode 2. These contact regions 6c may also help to divert the plasma from the first type of trench 51 during transistor mode turn-off.

[0097] Figure 13 shows a further exemplary embodiment of the semiconductor device 100, here only in a top view to the top surface 11 of the semiconductor body 10. As can be seen here, the second type of trenches 52 that sandwich the third base region 13c in the first lateral direction are actually connected at their respective longitudinal ends so that a continuous trench completely surrounds the first base region 13c.

[0098] Figure 14 shows a first position in an exemplary embodiment of a method for manufacturing a semiconductor device 100. In this position, a semiconductor body 10 is provided having a top surface 11 and a bottom surface 19. The bottom surface 19 is formed by alternatingly arranged first type regions 15 and second type regions 16. The top surface 11 is formed by a base region 13 of a second conductivity type. A drift region 14 is located between the bottom surface 19 and the base region 13, and the drift region 14 is of the first conductivity type.

[0099] Figure 15 shows the locations where trenches are formed in the semiconductor body 10 by etching the upper surface 11. The trenches are formed using a mask 200 that contains multiple holes in the region where the trenches are to be formed. The width of the holes in the second type of trench 52 is greater than the width of the holes in the first type of trench 51. As a result, the trenches are formed with different widths, but also with different depths.

[0100] Figure 16 shows the positions of the trenches 51 and 52 after they have been filled with conductive material. The conductive material in the trenches 51 and 52 is electrically isolated from the semiconductor body 10 by the electrically insulating material 40 placed within the trenches 51 and 52. Furthermore, the first base region 13a, the second base region 13b, and the third base region 13c are formed, for example, by ion implantation. The implanted region 12 is also formed in the semiconductor body 10, for example, by ion implantation.

[0101] The embodiments shown in Figures 1 to 16 above represent exemplary embodiments of improved semiconductor devices and improved methods for manufacturing semiconductor devices, and therefore do not constitute a complete list of all embodiments of improved semiconductor devices by improved methods. Actual semiconductor devices and methods may differ from the embodiments shown, for example, with respect to arrangement, elements, and the order of method steps. [Explanation of symbols]

[0102] Reference sign 2. First main electrode 3. Second main electrode 4 gate 5. Further electrodes 6a First contact area 6b Second contact area 6c Third contact area 10 Semiconductor main unit 11 Top side 12 Injection area 13 Base area 13a First base region 13b Second base region 13c Third base region 14. Drift Region 14a First drift region 14b Second drift region 15. The first type of domain 16. Second type of domain 19. Base 40 Electrical insulation layer / gate insulation layer 51. First type of trench 52. Second type of trench 100 Semiconductor Equipment 200 masks A1~A3 curve B1~B3 curve

Claims

1. Semiconductor device (100), - A semiconductor body (10) extending vertically between the top surface (11) and the bottom surface (19), - The first main electrode (2) on the upper surface (11) and the second main electrode (3) on the lower surface (19), -Gate (4), - comprising at least two trenches, namely a first type of trench (51) and a second type of trench (52), each trench extending from the upper surface (11) into the semiconductor body (10), - The semiconductor body (10) is - Between the upper surface (11) and the lower surface (19), a first conductivity type drift region (14) is formed vertically, - Including at least two base regions, namely a first base region (13a) and a second base region (13b), each base region being of a second conductivity type and arranged perpendicularly between the drift region (14) and the upper surface (11), the semiconductor body further comprises - The first base region (13a) is spaced perpendicularly away from the drift region (14), and includes the first conductive type injection region (12) adjacent to the first base region (13a), - The first base region (13a), the first type of trench (51), the second base region (13b), and the second type of trench (52) are arranged in this order in the first lateral direction. - The first main electrode (2) is in electrical contact with the injection region (12), - The gate electrode (4) extends into the first type of trench (51), where it is separated from the semiconductor body (10) by the gate insulating layer (40), - The second type of trench (52) lacks the gate electrode (4), - The second type of trench (52) extends deeper into the semiconductor body (10) than the first type of trench (51), - The second base region (13b) includes a plurality of contact regions (6b) spaced apart in the lateral direction, and the second base region (13b) is in electrical contact with the first main electrode (2) in each of these contact regions (6b). - The distance between the first type of trench (51) and the second type of trench (52), as measured in the first lateral direction, changes as it moves along the second lateral direction perpendicular to the first lateral direction. - The contact regions (6b) in the second base region (13b) are spaced apart from each other in the second lateral direction. - The distance between the first type of trench (51) and the second type of trench is greater where a contact area (6b) is located between them, and smaller where a contact area is not located between them, in a semiconductor device.

2. - The semiconductor device (100) according to claim 1, wherein the width of the second type of trench (52) is greater than the width of the first type of trench (51).

3. - The semiconductor device (100) according to claim 1 or 2, wherein the minimum distance between the first type of trench (51) and the second type of trench (52), as measured in the first lateral direction, is at most twice the width of the second type of trench (52).

4. - The semiconductor device (100) according to claim 1 or 2, wherein the first main electrode (2) extends into the second type of trench (52), where it is separated from the semiconductor body (10) by an electrical insulating layer (40).

5. - The semiconductor device (100) according to claim 1 or 2, wherein the second type of trench (52) is located between the two first type of trenches (51) in the first lateral direction.

6. - The second type of trench (52) is located between the second base region (13b) and the third base region (13c) in the first lateral direction, and the third base region (13c) is of the second conductivity type. - The semiconductor device (100) according to claim 5, wherein the third base region (13c) extends deeper into the semiconductor body (10) than the second type of trench (52).

7. - The third base region (13c) is located in the first lateral direction between the two second type trenches (52), - The third base region (13c) is adjacent to the two second type trenches (52), - The semiconductor device (100) according to claim 6, wherein the two second types of trenches (52) are connected to each other at their respective longitudinal ends, and the third base region (13c) is completely surrounded by a continuous trench in a top view to the top surface (11).

8. - The semiconductor device (100) according to claim 6, wherein the third base region (13c) includes at least one contact region (6c) in which the third base region (13c) is in electrical contact with the first main electrode (2).

9. - The drift region (14) includes a first drift region (14a) and a second drift region (14b) arranged successively in the vertical direction. - The second drift region (14b) is positioned perpendicularly between the first drift region (14a) and the first base region (13a). - The semiconductor device (100) according to claim 1 or 2, wherein the second drift region (14b) has a higher doping concentration than the first drift region (14a).

10. A method for manufacturing a semiconductor device (100), - To provide a semiconductor body (10) having an upper surface (11) and a lower surface (19), - The method includes forming at least two trenches, namely a first type of trench (51) and a second type of trench (52), each trench extending from the upper surface (11) into the semiconductor body (10), and the method further includes, - A first main electrode (2) is formed on the upper surface (11), and a second main electrode (3) is formed on the bottom surface (19), - comprising forming a gate electrode (4), wherein the gate electrode (4) extends into the first type of trench (51), therein it is separated from the semiconductor body (10) by a gate insulating layer (40), - The second type of trench (52) lacks the gate electrode (4), - The semiconductor device (100) is such that the semiconductor body (10) is - Between the upper surface (11) and the lower surface (19), a first conductivity type drift region (14) is formed vertically, - Formed to include at least two base regions, namely a first base region (13a) and a second base region (13b), each base region being of a second conductivity type and arranged perpendicularly between the drift region (14) and the upper surface (11), the semiconductor device further comprises the semiconductor body, - The first base region (13a) is spaced perpendicularly from the drift region (14) and is formed to include the injection region (12) of the first conductive type, which is adjacent to the first base region (13a). - The first base region (13a), the first type of trench (51), the second base region (13b), and the second type of trench (52) are arranged in this order in the first lateral direction. - The first main electrode (2) is in electrical contact with the injection region (12), - The trenches (51, 52) are formed such that the second type of trench (52) extends deeper into the semiconductor body (10) than the first type of trench (51). - The second base region (13b) includes a plurality of contact regions (6b) spaced apart in the lateral direction, and the second base region (13b) is in electrical contact with the first main electrode (2) in each of these contact regions (6b). - The distance between the first type of trench (51) and the second type of trench (52), as measured in the first lateral direction, changes as it moves along the second lateral direction perpendicular to the first lateral direction. - The contact regions (6b) in the second base region (13b) are spaced apart from each other in the second lateral direction. - The distance between the first type of trench (51) and the second type of trench is greater where a contact area (6b) is located between them, and smaller where a contact area is not located between them, in this manner.

11. - The trenches (51, 52) are formed by a common etching process using a common mask (200), - The mask (200) includes holes in the region where the trenches (51, 52) are to be formed. The method according to claim 10, wherein the hole for the second type of trench (52) has a greater width than the hole for the first type of trench (51).

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