Silicon carbide device and method for manufacturing the same
The silicon carbide device design addresses breakdown voltage and on-resistance issues by employing multiple gate trenches and a thicker insulating layer to distribute electric fields, improving reliability and reducing parasitic resistance.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- SUZHOU ORIENTAL SEMICONDUCTOR CO LTD
- Filing Date
- 2024-06-14
- Publication Date
- 2026-06-19
Smart Images
Figure 0007876247000001 
Figure 0007876247000002 
Figure 0007876247000003
Abstract
Description
Technical Field
[0001] This application belongs to the technical field of silicon carbide devices, and relates to, for example, silicon carbide devices and their manufacturing methods. This application claims the priority of a Chinese patent application with an application number of 202310715907.5, filed with the China National Intellectual Property Administration on June 16, 2023, and all the contents of the above application are incorporated herein by reference.
Background Art
[0002] As one of the representatives of the third-generation wide-bandgap semiconductor materials, silicon carbide materials have characteristics such as a large bandgap, a high critical breakdown electric field, a high thermal conductivity, and a high electron saturation drift velocity, and are expected to have a wide range of applications in the fields of high-power, high-temperature, and high-frequency power electronics. The mobility of planar silicon carbide devices is low, and the on-resistance of silicon carbide devices increases due to the resistance of parasitic junction field-effect transistors (JFETs), resulting in a large chip area. Trench-type silicon carbide devices eliminate the JFET resistance parasitic in planar silicon carbide devices, reduce the cell size, and significantly improve the current density. Therefore, trench-type silicon carbide devices have gradually replaced planar silicon carbide devices and become the mainstream. Silicon carbide devices usually use silicon dioxide as the gate dielectric layer material. However, since the dielectric constant of silicon carbide is about 2.5 times that of silicon dioxide, when the silicon carbide device is in the off state, the gate dielectric layer receives about 2.5 times the drift layer electric field. In trench-type silicon carbide devices, the electric field distribution at the bottom corner of the gate trench is concentrated, and the gate dielectric layer at the bottom corner of the gate trench is easily broken before the avalanche breakdown of the silicon carbide device occurs, which affects the breakdown voltage of the silicon carbide device and the reliability and stability of the device.
Summary of the Invention
Problems to be Solved by the Invention
[0003] This application provides a silicon carbide device and a method for manufacturing the same that improve the breakdown voltage performance of the silicon carbide device and reduce the on-resistance of the silicon carbide device. [Means for solving the problem]
[0004] The embodiments of this application are as follows: n-type silicon carbide substrate and An n-type silicon carbide layer formed on the aforementioned n-type silicon carbide substrate, Multiple gate trenches formed within the n-type silicon carbide layer, A p-shaped body region is formed on each side of each gate trench, An n-type source region and a current channel region are formed within each p-type body region, Each gate trench comprises two gate electrodes, each located on one of the two side walls of the gate trench and extending over the corresponding horizontal channel region, Each side of the p-type body region includes a first p-type body region and a second p-type body region located between the first p-type body region and an adjacent gate trench, wherein the depth of the second p-type body region is less than the depth of the first p-type body region, and the depth of the gate trench is less than the depth of the first p-type body region and greater than the depth of the second p-type body region. The current channel region includes a horizontal channel region and a vertical channel region. The gate electrode is insulated from the n-type silicon carbide layer via a gate electrode insulating layer between the gate electrode and the n-type silicon carbide layer, and the gate electrode is provided to control the on / off state of the current channel region by the gate electrode voltage. We provide silicon carbide devices.
[0005] Preferably, the thickness of the gate electrode insulating layer at the bottom of the gate trench is greater than the thickness of the gate electrode insulating layer at the side wall of the gate trench.
[0006] Preferably, the n-type source region is located within a first p-type body region in the p-type body region in which it resides, and the horizontal channel region is located within a second p-type body region in the p-type body region in which it resides.
[0007] Preferably, the n-type source region is located within a first p-type body region in the p-type body region in which it resides, and the horizontal channel region is located within a second p-type body region in the p-type body region in which it resides, and extends into the first p-type body region in the p-type body region in which it resides.
[0008] Preferably, the n-type source region is located within a first p-type body region in the p-type body region in which it is located, and extends into a second p-type body region in the p-type body region in which it is located, and the horizontal channel region is located within a second p-type body region in the p-type body region in which it is located.
[0009] Preferably, the silicon carbide device further includes p-type body contact regions located within each of the first p-type body regions.
[0010] Preferably, the silicon carbide device further includes n-type doped regions located within the n-type silicon carbide layer and below each gate trench, where each n-type doped region overlaps with the gap between two gate electrodes in their respective gate trenches.
[0011] The embodiments of this application are as follows: Forming an n-type silicon carbide layer on an n-type silicon carbide substrate, Forming a first insulating layer on the aforementioned n-type silicon carbide layer, Etching the first insulating layer to form a mask pattern, The first insulating layer is used as a mask to perform vertical p-type ion implantation, thereby forming a plurality of first p-type body regions within the n-type silicon carbide layer. Using the first insulating layer as a mask, p-type ion implantation is performed inclined toward one side of each first p-type body region to form a second p-type body region located within the n-type silicon carbide layer toward one side of each first p-type body region. Using the first insulating layer as a mask, p-type ion implantation is performed inclined toward the other side of each first p-type body region to form a second p-type body region located on the other side of each first p-type body region within the n-type silicon carbide layer, and the plurality of first p-type body regions and the plurality of second p-type body regions form a plurality of p-type body regions of a silicon carbide device. The first insulating layer is etched away, and n-type ion implantation is performed to form n-type source regions within each p-type body region. Etching the n-type silicon carbide layer to form multiple gate trenches within the n-type silicon carbide layer, A gate electrode insulating layer is formed on the bottom and side wall surfaces of each gate trench and on the surface of the n-type silicon carbide layer. This includes forming a first conductive layer on the surface of the gate electrode insulating layer so as to form two gate electrodes in each of the gate trenches, and etching the first conductive layer. The two gate electrodes are located on the two side walls of each gate trench and extend over the corresponding horizontal channel region on each side. Further, the present invention provides a method for manufacturing silicon carbide devices.
[0012] Preferably, the method for manufacturing a silicon carbide device further includes implanting n-type ions into the n-type silicon carbide layer through the gap between two gate electrodes in each gate trench to form an n-type doped region located below each gate trench within the n-type silicon carbide layer.
[0013] Preferably, the method for manufacturing a silicon carbide device further includes performing p-type ion implantation to form a p-type body contact region within each p-type body region before forming an n-type source region within each p-type body region. [Brief explanation of the drawing]
[0014] Hereinafter, the drawings necessary for explaining the embodiments will be briefly described. In the drawings, for the sake of convenience of explanation, the thicknesses of the layers and regions are enlarged, and the sizes shown do not represent actual dimensions. The drawings are schematic diagrams of idealized embodiments of the present application, and the embodiments shown in the present application are not limited to the specific shapes of the regions shown in the drawings, and should include the obtained shapes such as manufacturing variations. For example, curves obtained by etching usually have the characteristics of being curved or rounded, but in the embodiments of the present application, they are all represented by rectangles. The representations in the drawings are schematic, but this does not limit the scope of the present application. [Figure 1] It is a schematic cross-sectional structure diagram of a silicon carbide device provided by an embodiment of the present application. [Figure 2] It is a schematic cross-sectional structure diagram of an n-type silicon carbide layer formed in the manufacturing method of a silicon carbide device according to an embodiment of the present application. [Figure 3] It is a schematic cross-sectional structure diagram of a first p-type body region formed in the manufacturing method of a silicon carbide device according to an embodiment of the present application. [Figure 4] It is a schematic cross-sectional structure diagram of a second p-type body region on one side of the first p-type body region formed in the manufacturing method of a silicon carbide device according to an embodiment of the present application. [Figure 5] It is a schematic cross-sectional structure diagram of a second p-type body region located on the other side of the first p-type body region formed in the manufacturing method of a silicon carbide device according to an embodiment of the present application. [Figure 6] It is a schematic cross-sectional structure diagram of a p-type body contact region formed in the manufacturing method of a silicon carbide device according to an embodiment of the present application. [Figure 7] It is a schematic cross-sectional structure diagram of the first p-type body region and the second p-type body region formed in the manufacturing method of a silicon carbide device according to an embodiment of the present application. [Figure 8] It is a schematic cross-sectional structure diagram of an n-type source region formed in the manufacturing method of a silicon carbide device according to an embodiment of the present application. [Figure 9] It is a schematic cross-sectional view of a gate trench formed in the method for manufacturing a silicon carbide device according to an embodiment of the present application. [Figure 10] It is a schematic cross-sectional view of a gate electrode insulating layer and a gate electrode formed in the method for manufacturing a silicon carbide device according to an embodiment of the present application. [Figure 11] It is a schematic cross-sectional view of an n-type doped region formed in the method for manufacturing a silicon carbide device according to an embodiment of the present application. [Figure 12] It is a flowchart of the method for manufacturing a silicon carbide device according to an embodiment of the present application.
Embodiments for Carrying Out the Invention
[0015] FIG. 1 is a schematic cross-sectional view of a silicon carbide device provided by an embodiment of the present application. As shown in FIG. 1, the silicon carbide device includes an n-type silicon carbide substrate 21, an n-type silicon carbide layer 22 located on the n-type silicon carbide substrate 21, and several gate trenches 31 located in the n-type silicon carbide layer 22. For the convenience of illustration, only two gate trenches 31 are exemplarily shown in the embodiment of the present application.
[0016] P-type body regions 23 located on both sides of the gate trench 31 and within the n-type silicon carbide layer 22 include a first p-type body region 23a and a second p-type body region 23b located between the first p-type body region 23a and the gate trench 31. The depth of the second p-type body region 23b is smaller than the depth of the first p-type body region 23a, the depth of the gate trench 31 is smaller than the depth of the first p-type body region 23a, and is larger than the depth of the second p-type body region 23b.
[0017] The n-type source region 25 and the current channel region 10 are located within the p-type body region 23, and the current channel region 10 includes a horizontal channel region 10a and a vertical channel region 10b, the vertical channel region 10b is located within the second p-type body region 23b. Preferably, the n-type source region 25 is located within the first p-type body region 23a and the horizontal channel region 10a is located within the second p-type body region 23b, and extends into the first p-type body region 23a, and preferably, the n-type source region 25 is located within the first p-type body region 23a and extends into the second p-type body region 23b, and the horizontal channel region 10a is located within the second p-type body region 23b. In the embodiment of the present application, the n-type source region 25 is located within the first p-type body region 23a, and the horizontal channel region 10a is located within the second p-type body region 23b and extends into the first p-type body region 23a.
[0018] The p-type body contact region 24 located within the first p-type body region 23a can reduce the contact resistance when the p-type body region 23 comes into contact with the external electrode.
[0019] Two gate electrodes 27 are located within a gate trench 31, each situated on one of the two side walls of the gate trench 31, and extending over the corresponding horizontal channel region 10a on each side. The silicon carbide device includes a horizontal channel region 10a and a vertical channel region 10b corresponding to each gate electrode 27, and the gate electrodes 27 are insulated from the n-type silicon carbide layer 22 via a gate electrode insulating layer 26, the material of which is typically silicon oxide. Preferably, the thickness of the gate electrode insulating layer 26 at the bottom of the gate trench 31 is greater than the thickness of the gate electrode insulating layer 26 at the side walls of the gate trench 31, which can improve the breakdown voltage of the silicon carbide device.
[0020] The gate electrode 27 controls the on / off state of the current channel region 10 located within the p-type body region 23 by the gate electrode voltage. The current channel region is an inversion layer formed within the body region when the semiconductor device is turned on.
[0021] In the embodiment of the present invention, the silicon carbide device can also reduce parasitic JFET resistance by providing an n-type doped region located below the gate trench within the n-type silicon carbide layer. In the embodiment of the present invention, the current channel region of the silicon carbide device includes a horizontal channel region at the top and a vertical channel region on the side wall, thereby overcoming the problem of low mobility in planar silicon carbide devices. Furthermore, by employing a shallow gate trench structure, the embodiment of the present invention not only mitigates the parasitic JFET effect but also reduces on-resistance. At the same time, because the gate trench is shallow, the electric field in the oxide layer at the bottom of the gate trench is reduced, making it less susceptible to damage and improving the reliability and stability of the silicon carbide device.
[0022] Figures 2 to 11 are schematic diagrams of cross-sectional structures formed in the steps of the method for manufacturing a silicon carbide device according to an embodiment of the present application. The method for manufacturing a silicon carbide device according to an embodiment of the present application includes the following steps.
[0023] In step 1, as shown in Figure 2, an n-type silicon carbide layer 22 is formed on the provided n-type silicon carbide substrate 21, and a first insulating layer 30 is formed on the n-type silicon carbide layer 22, the material of which is usually silicon oxide or a silicon oxide and silicon nitride laminate. After defining the position of the first p-type body region 23a by a photolithography process, the first insulating layer 30 is etched to expose the n-type silicon carbide layer 22.
[0024] In step 2, as shown in Figure 3, vertical p-type ion implantation is performed using the first insulating layer 30 as a mask to form a first p-type body region 23a within the n-type silicon carbide layer 22.
[0025] In step 3, as shown in Figure 4, p-type ion implantation is performed with the first insulating layer 30 as a mask, tilting toward one side of each first p-type body region, thereby forming a second p-type body region 23b located on one side of the first p-type body region 23a within the n-type silicon carbide layer 22.
[0026] In step 4, as shown in Figure 5, p-type ion implantation is performed with the first insulating layer 30 as a mask, tilting toward the other side of each first p-type body region, to form a second p-type body region 23b located on the other side of the first p-type body region 23a within the n-type silicon carbide layer 22. The first p-type body region 23a and the second p-type body region 23b are combined to form the p-type body region of the silicon carbide device.
[0027] In step 5, as shown in Figure 6, after etching away the first insulating layer 30, the position of the p-type body contact region 24 is defined by a photolithography process, and then p-type ion implantation is performed to form the p-type body contact region 24 within the p-type body region 23.
[0028] In the embodiments of this application, the structural regions of the silicon carbide devices are all shown as rectangular. However, in the actual manufacturing process, the edges of the structural regions of the silicon carbide devices are usually curved or rounded. For example, the stepped shape between the first p-type body region 23a and the second p-type body region 23b in the embodiments of this application usually becomes arc-shaped after the annealing process in the actual manufacturing process. That is, as shown in Figure 7, the area between the first p-type body region 23a and the second p-type body region 23b is actually arc-shaped 40, not stepped. However, for convenience of representation, it is shown as stepped in the embodiments of this application. If the space between the first p-type body region 23a and the second p-type body region 23b is arc-shaped, then the depth of the second p-type body region 23b being smaller than the depth of the first p-type body region 23a can be understood as the depth of the second p-type body region 23b on the side closer to the gate trench 31 being smaller than the depth of the first p-type body region 23a. Alternatively, the minimum depth of the second p-type body region 23b can be understood as being smaller than the depth of the first p-type body region 23a.
[0029] In step 6, as shown in Figure 8, after defining the position of the n-type source region 25 by a photolithography process, n-type ion implantation is performed to form the n-type source region 25 within the p-type body region 23. The positions of the n-type source region 25 formed within one p-type body region 23 are on both sides of the p-type body contact region 24.
[0030] In step 7, as shown in Figure 9, after defining the positions of the gate trenches 31 by a photolithography process, the n-type silicon carbide layer 22 is etched to form multiple gate trenches 31 within the n-type silicon carbide layer 22. However, in this embodiment, only two gate trenches 31 are shown as an example.
[0031] In step 8, as shown in Figure 10, a gate electrode insulating layer 26 is formed on the surface of the gate trench 31 and the surface of the n-type silicon carbide layer 22. Then, a first conductive layer is formed on the surface of the gate electrode insulating layer 26 to form two gate electrodes 27 located within the gate trench 31, and the formed first conductive layer is etched so that the two gate electrodes 27 are located on the two side walls of the gate trench 31, respectively, and extend over the horizontal channel region 10a on their respective sides.
[0032] In step 9, as shown in Figure 11, n-type ions are implanted into the n-type silicon carbide layer 22 through the gap between the two gate electrodes 27 in the same gate trench 31, forming an n-type doped region 28 located below the gate trench within the n-type silicon carbide layer 22. This n-type doped region can reduce the parasitic JFET resistance.
[0033] In step 10, a passivation layer is formed on the surface of the formed structure to form a silicon carbide device, the formed passivation layer is etched to form contact holes, and then a metal layer is formed. This step is not shown.
[0034] As shown in Figure 12, the method for manufacturing a silicon carbide device according to the embodiment of the present application is as follows: S1, which forms an n-type silicon carbide layer on an n-type silicon carbide substrate, S2 forms a first insulating layer on an n-type silicon carbide layer, S3 involves etching the first insulating layer to form a mask pattern, S4 is formed by performing vertical p-type ion implantation using the first insulating layer as a mask, thereby forming multiple first p-type body regions within the n-type silicon carbide layer. S5 is performed by using the first insulating layer as a mask to perform p-type ion implantation that is tilted toward one side of each first p-type body region, thereby forming a second p-type body region located on one side of each first p-type body region within the n-type silicon carbide layer. S6 is performed to form a second p-type body region located on the other side of each first p-type body region within the n-type silicon carbide layer, with the first insulating layer acting as a mask and the p-type ion implantation tilted toward the other side of each first p-type body region, and the multiple first p-type body regions and the multiple second p-type body regions form multiple p-type body regions of the silicon carbide device. S7 involves etching away the first insulating layer, performing n-type ion implantation, and forming n-type source regions within each p-type body region. S8 involves etching the n-type silicon carbide layer to form multiple gate trenches within the n-type silicon carbide layer. S9 forms a gate electrode insulating layer on the bottom and side wall surfaces of each gate trench and on the surface of the n-type silicon carbide layer, A first conductive layer is formed on the surface of the gate electrode insulating layer so as to form two gate electrodes in each gate trench, the first conductive layer is etched, and the two gate electrodes are located on the two side walls of each gate trench and extend over the corresponding horizontal channel region S10, Includes.
Claims
1. n-type silicon carbide substrate and An n-type silicon carbide layer formed on the n-type silicon carbide substrate, Multiple gate trenches formed within the n-type silicon carbide layer, A p-shaped body region is formed on both sides of each gate trench, An n-type source region and a current channel region are formed within each p-type body region, Each gate trench comprises two gate electrodes, each located on one of the two side walls of the gate trench and extending over the corresponding horizontal channel region, Each side of the p-type body region includes a first p-type body region and a second p-type body region located between the first p-type body region and an adjacent gate trench, wherein the depth of the second p-type body region is less than the depth of the first p-type body region, and the depth of the gate trench is less than the depth of the first p-type body region and greater than the depth of the second p-type body region. The current channel region includes a horizontal channel region and a vertical channel region. The gate electrode is insulated from the n-type silicon carbide layer via a gate electrode insulating layer between the gate electrode and the n-type silicon carbide layer, and the gate electrode is provided to control the on / off state of the current channel region by the gate electrode voltage. The n-type source region is located within a first p-type body region in the p-type body region in which it is located, and extends into a second p-type body region in the p-type body region in which it is located, and the horizontal channel region is located within a second p-type body region in the p-type body region in which it is located. Silicon carbide devices.
2. The thickness of the gate electrode insulating layer at the bottom of the gate trench is greater than the thickness of the gate electrode insulating layer at the side wall of the gate trench. The silicon carbide device according to claim 1.
3. Further including p-type body contact regions located within each of the first p-type body regions, The silicon carbide device according to claim 1.
4. The n-type silicon carbide layer further includes n-type doped regions located below each of the gate trenches, each n-type doped region overlapping with the gap between two gate electrodes in its corresponding gate trench. The silicon carbide device according to claim 1.
5. Forming an n-type silicon carbide layer on an n-type silicon carbide substrate, Forming a first insulating layer on the n-type silicon carbide layer, Etching the first insulating layer to form a mask pattern, Using the first insulating layer as a mask, vertical p-type ion implantation is performed to form a plurality of first p-type body regions within the n-type silicon carbide layer. Using the first insulating layer as a mask, p-type ion implantation is performed inclined toward one side of each first p-type body region to form a second p-type body region located within the n-type silicon carbide layer toward one side of each first p-type body region. Using the first insulating layer as a mask, p-type ion implantation is performed inclined toward the other side of each first p-type body region to form a second p-type body region located on the other side of each first p-type body region within the n-type silicon carbide layer, and the plurality of first p-type body regions and the plurality of second p-type body regions form a plurality of p-type body regions of a silicon carbide device. The first insulating layer is etched away, and n-type ion implantation is performed to form n-type source regions within each p-type body region. Etching the n-type silicon carbide layer to form multiple gate trenches within the n-type silicon carbide layer, A gate electrode insulating layer is formed on the bottom and side wall surfaces of each gate trench and on the surface of the n-type silicon carbide layer. This includes forming a first conductive layer on the surface of the gate electrode insulating layer so as to form two gate electrodes in each of the gate trenches, and etching the first conductive layer. The two gate electrodes are located on the two side walls of each gate trench and extend over the corresponding horizontal channel region on each side. A method for manufacturing silicon carbide devices.
6. The further step includes implanting n-type ions into the n-type silicon carbide layer through the gap between two gate electrodes in each of the gate trenches, thereby forming an n-type doped region located below each of the gate trenches within the n-type silicon carbide layer. A method for producing a silicon carbide device according to claim 5.
7. The process further includes performing p-type ion implantation to form p-type body contact regions within each p-type body region before forming n-type source regions within each p-type body region. A method for producing a silicon carbide device according to claim 5.