Electronic circuit

Abstract

To provide an electronic circuit which allows a changed FPGA to be used without changing firmware.SOLUTION: An electronic circuit includes: a processor; a first FPGA (Field-Programmable Gate Array); a first generation circuit; and a second generation circuit. The first FPGA executes configuration with a first bit stream before the processor is activated. The first generation circuit outputs a first reset signal to the processor for resetting the processor on the basis of a first completion signal indicating that the configuration has completed. The second generation circuit outputs a second completion signal indicating that the configuration has completed on the basis of a control signal output from the processor.SELECTED DRAWING: Figure 1

Description

【Technical Field】 【0001】 Embodiments of the present invention relate to electronic circuits. 【Background Art】 【0002】 Conventionally, when a design change is made to change an FPGA (Field-Programmable Gate Array) mounted on an electronic circuit to a different FPGA, the size of bitstream data to be loaded into the FPGA and the time required for loading change. Therefore, it is necessary to change the firmware that controls the loading of bitstream data to the FPGA. 【0003】 However, changing the firmware requires a lot of development man-hours. 【Summary of the Invention】 【Problems to be Solved by the Invention】 【0004】 The problem to be solved by the present invention is to provide an electronic circuit that enables the use of a changed FPGA without changing the firmware. 【Means for Solving the Problems】 【0005】 The electronic circuit of the embodiment includes a processor, a first FPGA (Field-Programmable Gate Array), a first generation circuit, and a second generation circuit. The first FPGA performs configuration with first bitstream data before the processor is activated. The first generation circuit outputs a first reset signal for resetting the processor to the processor based on a first completion signal indicating that the configuration has been completed. The second generation circuit Reset by the first reset signal output from the processor Configuration that instructs the execution of the configuration. signal If the first specified period has elapsed since the input was made and outputs a second completion signal indicating that the configuration has been completed to the processor. 【Brief Description of the Drawings】 【0006】 [Figure 1] Figure 1 is a block diagram showing an example of an electronic circuit according to this embodiment. [Figure 2] Figure 2 is a flowchart showing an example of the startup process performed by the electronic circuit according to this embodiment. [Modes for carrying out the invention] 【0007】 The embodiments of the electronic circuit will be described in detail below with reference to the attached drawings. Note that the embodiments described below are just one example of an electronic circuit and do not limit its configuration or specifications. 【0008】 Figure 1 is a block diagram showing an example of an electronic circuit 1 according to this embodiment. The electronic circuit 1 comprises a processor 10, a first FPGA (Field-Programmable Gate Array) 11, a first storage unit 12, a second storage unit 13, a reset signal generation circuit 14, and a dummy signal generation circuit 15. The electronic circuit 1 originally had a second FPGA (not shown), but due to a design change, the first FPGA 11 is used instead of the second FPGA. 【0009】 The processor 10 is a processing circuit that controls the electronic circuit 1. For example, the processor 10 is a processing circuit such as a CPU (Central Processing Unit). Note that the processor 10 is not limited to a CPU; it may be any other processing circuit. 【0010】 The processor 10 executes the processing procedures indicated in the firmware 132. Then, by operating according to the firmware 132, the processor 10 starts up the electronic circuit 1. 【0011】 More specifically, when the processor 10 has finished resetting, it outputs a configuration signal to the dummy signal generation circuit 15 that instructs the execution of the configuration using the second bitstream data 131. The configuration signal is an example of a control signal. 【0012】 The first FPGA11 is an integrated circuit that constitutes logic specified by HDL (Hardware Description Language), etc. Furthermore, the first FPGA11 is a different type of FPGA from the second FPGA before the design change. In other words, the first FPGA11 is an FPGA that has been modified due to the design change. 【0013】 Furthermore, the first FPGA 11 performs configuration using the first bitstream data 121 before the processor 10 starts up. More specifically, the first FPGA 11 is connected to the first memory unit 12 via SPI (Serial Peripheral Interface). The first FPGA 11 is set to master SPI mode when a fixed value is input to a specific input terminal. That is, the first FPGA 11 is set to a mode that reads the first bitstream data 121 stored in the first memory unit 12. Then, the first FPGA 11 reads the first bitstream data 121 stored in the first memory unit 12. 【0014】 The first FPGA 11 performs a configuration that loads the first bitstream data 121 read from the first memory unit 12. Then, when the configuration is complete, the first FPGA 11 outputs a completion signal to the reset signal generation circuit 14. 【0015】 The first storage unit 12 is implemented using a storage medium such as flash ROM (Read Only Memory). The first storage unit 12 stores the first bitstream data 121. 【0016】 The first bitstream data 121 is data loaded into the first FPGA 11. In other words, the first bitstream data 121 is data in which logic is represented by HDL or the like. 【0017】 The second storage unit 13 is implemented using a storage medium such as flash ROM. The second storage unit 13 stores the firmware 132 and the second bitstream data 131. 【0018】 Firmware 132 is software for controlling electronic circuit 1. Here, firmware 132 includes a program that controls the startup of the second FPGA. However, modifying firmware 132 to apply it to the first FPGA 11 would require a lot of development effort. Therefore, electronic circuit 1 enables the use of the first FPGA 11 through hardware without modifying firmware 132. 【0019】 The second bitstream data 131 is the bitstream data created for the second FPGA before the first FPGA 11 was modified due to a design change. In other words, the second bitstream data 131 is data in which logic is represented by HDL, etc. 【0020】 The reset signal generation circuit 14 is a circuit that generates a reset signal to reset the processor 10. Based on a completion signal indicating that the configuration is complete, the reset signal generation circuit 14 outputs a reset signal to the processor 10 to reset the processor 10. The completion signal is an example of a first completion signal. The reset signal generation circuit 14 is an example of a first generation circuit. The reset signal is an example of a first reset signal. 【0021】 The dummy signal generation circuit 15 generates a dummy reset signal and a dummy completion signal. In the case of the second FPGA, the processor 10 performed the configuration using the second bitstream data 131 stored in the second memory unit 13. When the configuration was complete, the processor 10 received a completion signal input from the second FPGA. Also, when the second FPGA was reset, the processor 10 received a reset signal input from the second FPGA. 【0022】 However, the first FPGA 11 starts up before the processor 10. Then, the processor 10 is reset after the configuration of the first FPGA 11 is completed. Since the timing at which the reset signal and the completion signal are generated has changed with the change in the first FPGA 11, the processor 10 no longer receives these signals. Therefore, the dummy signal generation circuit 15 generates a dummy reset signal and a dummy completion signal, which are dummy signals. Then, the dummy signal generation circuit 15 outputs these signals to the processor 10. 【0023】 More specifically, the dummy signal generation circuit 15 receives an input of a configuration signal that instructs the execution of the configuration from the processor 10. Based on the configuration signal output from the processor 10, the dummy signal generation circuit 15 outputs a dummy completion signal indicating that the configuration has been completed to the processor 10. The dummy completion signal is an example of a second completion signal. The dummy signal generation circuit 15 is an example of a second generation circuit. Also, the dummy completion signal is a dummy signal. That is, the dummy completion signal is a signal that disguises the completion of the configuration. 【0024】 The dummy signal generation circuit 15 outputs the dummy completion signal to the processor 10 when the first specified period has elapsed since the configuration signal was input. The first specified period is, for example, the period taken for the configuration in the second FPGA. 【0025】 The dummy signal generation circuit 15 outputs a dummy reset signal indicating that the first FPGA 11 has been reset to the processor 10 when the second specified period has elapsed since the dummy completion signal was output. And the dummy reset signal is a dummy signal. That is, the dummy reset signal is a signal that disguises the reset of the first FPGA 11. Also, the dummy reset signal is an example of a second reset signal. The second specified period is, for example, the period taken from the completion of the configuration to the reset in the second FPGA. 【0026】 Next, the startup process executed by the electronic circuit 1 will be described. FIG. 2 is a flowchart showing an example of the startup process executed by the electronic circuit 1 according to the present embodiment. 【0027】 The first FPGA 11 executes a configuration to load the first bitstream data 121 read from the first storage unit 12 (step S1). 【0028】 The first FPGA 11 determines whether the configuration has been completed (step S2). If the configuration has not been completed (step S2; No), the first FPGA 11 waits. 【0029】 When the configuration is completed (step S2; Yes), the first FPGA 11 outputs a completion signal indicating that the configuration has been completed to the reset signal generation circuit 14 (step S3). 【0030】 The reset signal generation circuit 14 outputs a reset signal for resetting the processor 10 to the processor 10 (step S4). 【0031】 The processor 10 is reset when the reset signal is input (step S5). Further, the processor 10 outputs a configuration signal for instructing the execution of the configuration to the dummy signal generation circuit 15 (step S6). 【0032】 The dummy signal generation circuit 15 determines whether a first specified period has elapsed since the configuration signal was input (step S7). If the first specified period has not elapsed (step S7; No), the dummy signal generation circuit 15 waits. 【0033】 When the first specified period has elapsed (step S7; Yes), the dummy signal generation circuit 15 outputs a dummy completion signal to the processor 10 (step S8). 【0034】 The dummy signal generation circuit 15 determines whether a second specified period has elapsed since outputting the dummy completion signal (step S9). If the second specified period has not elapsed (step S9; No), the dummy signal generation circuit 15 remains in standby mode. 【0035】 If the second specified period has elapsed (step S9; Yes), the dummy signal generation circuit 15 outputs a dummy reset signal to the processor 10 (step S10). 【0036】 As a result, electronic circuit 1 terminates its startup process. 【0037】 As described above, the electronic circuit 1 according to this embodiment comprises a processor 10, a modified first FPGA 11 modified by a design change, a reset signal generation circuit 14, and a dummy signal generation circuit 15. The first FPGA 11 reads the first bitstream data 121 before the processor 10 starts up. The reset signal generation circuit 14 outputs a reset signal to the processor 10 to reset the processor 10 when the configuration of the first FPGA 11 is complete. The dummy signal generation circuit 15 then outputs a dummy completion signal to the processor 10 that simulates the completion of the configuration of the first FPGA 11. 【0038】 Thus, due to the design change, the second FPGA was replaced with the first FPGA 11, and the first FPGA 11 performs configuration before the processor 10 starts up. Therefore, the processor 10 cannot accept the input of a completion signal indicating that the configuration of the first FPGA 11 is complete, but it does accept the input of a dummy completion signal from the dummy signal generation circuit 15. 【0039】 This allows electronic circuit 1 to simulate the same processing procedure as when the second FPGA was in use before being changed to the first FPGA 11. In other words, electronic circuit 1 simulates the same input / output relationship for processor 10. And because the input / output relationship is the same, processor 10 can execute processing according to the processing procedure shown in firmware 132. Therefore, electronic circuit 1 can enable the use of the modified first FPGA 11 without changing firmware 132. 【0040】 While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. 【0041】 The programs executed in each of the above embodiments and modified devices shall be provided pre-installed in the storage medium (ROM or storage unit) provided in each device, but are not limited to this. For example, the programs may be configured to be provided as installable or executable files recorded on a computer-readable recording medium such as a CD-ROM, flexible disk (FD), CD-R, or DVD (Digital Versatile Disk). Furthermore, the storage medium is not limited to a medium independent of the computer or embedded system, but also includes storage media that store or temporarily store programs downloaded from a LAN, the Internet, etc. 【0042】 Furthermore, the programs executed by each of the above embodiments and modified devices may be stored on a computer connected to a network such as the Internet and provided by being downloaded via the network, or they may be provided or distributed via a network such as the Internet. [Explanation of Symbols] 【0043】 1 Electronic circuit 10 processors 11. 1st FPGA 12 1st memory section 13 2nd memory section 14 Reset signal generation circuit 15. Dummy signal generation circuit 121 First bitstream data 131 Second bitstream data 132 Firmware [Prior art documents] [Patent Documents] 【0044】 [Patent Document 1] Patent No. 3660219

Claims

[Claim 1] Processor and A first FPGA (Field-Programmable Gate Array) that performs configuration using first bitstream data before the aforementioned processor starts up, A first generation circuit outputs a first reset signal to the processor to reset the processor based on a first completion signal indicating that the configuration has been completed, A second generation circuit outputs a second completion signal to the processor indicating that the configuration has been completed when a configuration signal instructing the execution of the configuration, output from the processor which has been reset by the first reset signal, is input and a first predetermined period has elapsed. An electronic circuit equipped with the following features. [Claim 2] The first FPGA is set to a mode for reading the first bitstream data stored in the first storage unit. The electronic circuit according to claim 1. [Claim 3] It further comprises a second storage unit for storing second bitstream data, The first FPGA performs the configuration which loads the first bitstream data read from the first storage unit. The electronic circuit according to claim 2. [Claim 4] The processor outputs the configuration signal to the second generation circuit, which instructs the execution of the configuration using the second bitstream data. The electronic circuit according to claim 3. [Claim 5] The second generation circuit outputs a second reset signal to the processor indicating that the first FPGA has been reset when a second specified period has elapsed since outputting the second completion signal. The electronic circuit according to claim 4.