Floating metal on the back increases capacitance.

Abstract

A semiconductor structure having one or more backside metal layers including a plurality of portions of a floating metal layer separated by a dielectric material from one or more power and ground lines in the backside metal layer, wherein a height of each of the plurality of portions of the floating metal layer in each of the one or more backside metal layers and a distance between adjacent portions of the plurality of portions of the floating metal layer in each of the one or more backside metal layers are correlated to a respective capacitance of the one or more backside metal layers.

Description

Technical Field

[0001] The present invention generally relates to the field of semiconductor device manufacturing, and more particularly to the formation of backside floating metal to increase the capacitance of backside power distribution.

Background Art

[0002] According to Moore's law, the number of transistors in a semiconductor chip doubles approximately every two years, and further miniaturization of transistors and shortening of connections between transistors are being advanced. One of the factors driving the complexity of semiconductor chips and the high functionality of computing systems is the increasing use of artificial intelligence based on deep neural networks, which requires more device circuits and higher processing speeds. In the design of semiconductor chips, more circuits are continuously packed into the semiconductor chips. As a result, the line width in the semiconductor chips and the spacing between adjacent device elements continue to shrink to support the increasing functional requirements of computer systems. As transistors and interconnect wiring shrink, the resistance of transistors and interconnect wiring in the semiconductor chip increases, and they consume more power.

[0003] In addition, advances in semiconductor chip process technology and digital system architecture are increasing the operating frequencies of integrated circuits. Higher operating frequencies generally result in an undesirable increase in power consumption in semiconductor chips. Power consumption is typically a significant issue for semiconductor chips, especially large, complex, high-speed processors and microprocessors. As operating frequencies increase and more device circuits with faster processing speeds are required, the power delivery network within a semiconductor chip needs to supply more power without significantly impacting the device circuits' ability to provide the desired electrical performance and the necessary interconnect wiring. Due to the increased power consumption at higher operating frequencies and the additional semiconductor devices within a semiconductor chip, supplying more power is becoming increasingly difficult.

[0004] Typically, semiconductor devices such as transistors are formed on the front metal layer of a semiconductor chip and connected by interconnect layers and power structures formed on the front metal layer above the transistors. In conventional semiconductor chip designs, the power supply network is formed by conductors and vias on the front metal layer and connected to the VDD / VSS terminals of the semiconductor chip to supply power to individual devices and transistors on the front side of the semiconductor chip. Conventional power rails in conventional power supply networks are usually located with memory devices or on the interconnect layer above transistors in the core logic area of ​​the semiconductor chip, and these power rails are connected to the power and ground terminals of the transistors. Conventional power rails on the front metal interconnect layer of a semiconductor chip utilize a considerably large semiconductor wiring area, thereby limiting semiconductor wiring.

[0005] In some semiconductor chips, embedded power rails may be formed within portions of the semiconductor substrate. Typically, embedded power rails are formed on a single metal layer within the semiconductor substrate. Embedded power rails are generally limited to a single metal layer. In other more recent semiconductor structures, power planes are formed on the back surface of the semiconductor substrate, and the power planes are coupled to metal lines on the front surface of the semiconductor chip using a series of deep vias that penetrate the semiconductor substrate. Each power plane is continuous across the back surface of the semiconductor substrate and covers the back surface of the semiconductor substrate. The layers of the back surface power planes are separated by dielectric material. High-k dielectric materials may be used to increase capacitance, but if each back surface power plane encloses a region of the semiconductor substrate, using back surface power planes provides minimal opportunity to adjust the electrical or thermal performance of each back surface metal layer of the back surface power planes. [Overview of the project]

[0006] Embodiments of the present invention disclose a semiconductor structure having one or more back metal layers that supply power to one or more front metal layers of the semiconductor structure. Embodiments of the present invention provide one or more back metal layers comprising one or more portions of a floating metal layer separated from power and ground lines by a dielectric material. Embodiments of the present invention provide portions of a floating metal layer that are located between the power and ground lines and are not directly connected to the back ground line. Even without sufficient ground connection, portions of the floating metal layer provide increased capacitance to the back metal layer of the semiconductor structure.

[0007] Embodiments of the present invention fabricate a semiconductor structure having a backside metal layer forming a power distribution network on a semiconductor substrate. By moving the power distribution network from the front side to the back side of the semiconductor substrate, embodiments of the present invention provide additional area on the frontside metal layer in the semiconductor chip for arranging more frontside interconnect wiring or semiconductor devices, or both. Alternatively, embodiments of the present invention that move the power distribution network or a portion of the power distribution network from the front side to the back side of the semiconductor chip provide the ability to reduce the size of the semiconductor chip. Embodiments of the present invention that move the power distribution network or a portion of the power distribution network from the front side to the back side of the semiconductor chip can combine the ability to reduce the size of the semiconductor chip with the ability to increase the available area of ​​the frontside metal layer for adding semiconductor devices or interconnect wiring.

[0008] Embodiments of the present invention disclose a semiconductor structure in which the height of each of the multiple portions of the floating metal layer in each of the back metal layers having a floating metal layer, and the distance between adjacent portions of the floating metal layer in each back metal layer having a floating metal layer, correlate with the capacitance of each portion of the back metal layer having a floating metal layer. Embodiments of the present invention provide, at least partially, the ability to control the magnitude of capacitance and thermal conductivity provided by the back metal layer by controlling the amount of metal, i.e., the density of the portions of the floating metal layer.

[0009] Embodiments of the present invention disclose a semiconductor structure in which a portion of a floating metal layer contacts a semiconductor wafer. Embodiments of the present invention also provide a semiconductor structure in which a portion of a floating metal layer resides on a dielectric material that separates the power and ground lines from the portion of the floating metal layer, with power and ground lines contacting the semiconductor wafer. In each semiconductor structure, embodiments of the present invention have the ability to provide desired capacitance and desired thermal properties for each back metal layer. Embodiments of the present invention give the ability to at least partially determine the capacitance and thermal properties of each back metal layer by controlling one or more of the height of the portion of the floating metal layer, the dielectric constant of the dielectric material, and the pitch of the power and ground lines.

[0010] Embodiments of the present invention disclose a method for forming multiple portions of a floating metal layer on one or more backside metal layers of a semiconductor wafer, the method utilizing a damascene backside wiring process that includes selectively etching a portion of the backside of the semiconductor wafer and depositing a dielectric material on the backside of the semiconductor wafer. The method includes depositing a first metal layer on the dielectric material and removing the excess portion of the first metal layer on the dielectric material by a first chemical mechanical polish. In addition, the method includes depositing a second metal layer on the backside of the semiconductor wafer, the dielectric material and the exposed surface of the first metal layer. The method includes removing the excess portion of the second metal layer on the upper surface of the first metal layer by a second chemical mechanical polish and depositing an interlayer insulating material on the second metal layer, the dielectric material and the exposed surface of the first metal layer. By using this method to control the etching depth of the semiconductor wafer and the spacing between each removed portion of the semiconductor wafer, the capacitance provided by the residual portion of the second metal layer that becomes a floating metal layer can be controlled, at least partially. Embodiments of the present invention include an optional step of recessing the second metal layer before depositing the interlayer insulating material. Embodiments of the present invention utilizing the optional step of recessing the second metal provide a method for further adjusting the magnitude of the capacitance supplied to the power lines on the back surface by the portion of the floating metal layer formed by the residual portion of the second metal layer.

[0011] Embodiments of the present invention also disclose a method for forming multiple portions of a floating metal layer on one or more backside metal layers of a semiconductor wafer using a subtractive wiring process. This method includes depositing a first metal layer on the backside of a semiconductor wafer and selectively etching the first metal layer to form one or more of a plurality of power and ground lines on the backside of the semiconductor wafer. The method includes depositing a dielectric material on the exposed surface of the first metal layer and on the backside of the thinned semiconductor wafer. The method includes depositing a second metal layer on the dielectric material and then removing the excess portion of the second metal layer on the dielectric material. Furthermore, the method includes depositing a layer of interlayer insulating material on the exposed surface of the dielectric material and the second metal layer. The method includes an optional step of recessing the residual portion of the second metal before depositing the interlayer insulating material to adjust the capacitance magnitude and thermal properties provided by the residual portion of the second metal that forms the floating metal layer.

[0012] The above and other aspects, features, and advantages of various embodiments of the present invention will become even more apparent from the following description made in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0013] [Figure 1] This is a cross-sectional view of a semiconductor structure having a back-side power supply structure and a back-side floating metal that increases capacitance, according to an embodiment of the present invention. [Figure 2] This is a cross-sectional view of a semiconductor structure having a part of a wafer substrate having a metal layer and a device region, according to an embodiment of the present invention. [Figure 3] This is a cross-sectional view of a semiconductor structure after subtractive etching of a portion of the metal layer according to an embodiment of the present invention. [Figure 4] This is a cross-sectional view of a semiconductor structure after a dielectric material has been deposited on a wafer substrate and the residual portion of a metal layer, according to an embodiment of the present invention. [Figure 5]This is a cross-sectional view of a semiconductor structure after depositing another metal layer on a dielectric material, according to an embodiment of the present invention. [Figure 6] This is a cross-sectional view of a semiconductor structure after chemical mechanical polishing (CMP) according to an embodiment of the present invention. [Figure 7] This is a cross-sectional view of a semiconductor structure after a metal layer has been recessed and an interlayer insulating material has been deposited on the semiconductor structure, according to an embodiment of the present invention. [Figure 8] This is a cross-sectional view of a semiconductor structure having a front metal layer and a first back metal layer that form a floating metal that increases the power distribution structure and capacitance, according to an embodiment of the present invention. [Figure 9] This is a cross-sectional view of a semiconductor structure after wafer thinning of a wafer substrate according to an embodiment of the present invention. [Figure 10] This is a cross-sectional view of a semiconductor structure after etching a wafer substrate according to an embodiment of the present invention. [Figure 11] This is a cross-sectional view of a semiconductor structure after a dielectric material has been deposited on a wafer substrate according to an embodiment of the present invention. [Figure 12] This is a cross-sectional view of a semiconductor structure according to an embodiment of the present invention, after depositing a first metal material and performing CMP to remove the excess portion of the first metal material from the upper surface of the wafer substrate. [Figure 13] This is a cross-sectional view of a semiconductor structure obtained by etching a portion of a wafer substrate other than the residual dielectric material, according to an embodiment of the present invention. [Figure 14] This is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention, in which a wafer substrate, a dielectric material, and a second metal material are deposited on the exposed portion of a first metal material, and CMP is performed. [Figure 15] This is a cross-sectional view of a semiconductor structure after a second metal material has been recessed according to an embodiment of the present invention. [Figure 16] This is a cross-sectional view of a semiconductor structure after depositing a layer of ILD material according to an embodiment of the present invention. [Figure 17]This flowchart shows the steps of a damascene wiring process for forming one or more backside metal layers on a wafer according to an embodiment of the present invention. [Modes for carrying out the invention]

[0014] Embodiments of the present invention are based on the recognition that embedded power rails generally provide a single metal layer for power distribution to a semiconductor substrate, i.e., a wafer. Embodiments of the present invention are based on the recognition that embedded power rails in a semiconductor substrate provide a limited amount of wiring for a power supply network, supplying only a portion of the power required by many semiconductor chips. Embodiments of the present invention are based on the recognition that advanced semiconductor device designs allow more circuits to be incorporated into semiconductor chips. To realize more circuits and devices on a semiconductor chip, feature sizes such as line width and spacing between device elements are reduced. As devices and interconnect lines are reduced, the resistance of devices and interconnect lines in a semiconductor chip increases, allowing them to use more power. In addition, embodiments of the present invention are based on the recognition that advances in semiconductor process technology and digital system architecture have enabled high-operating-frequency integrated circuits that require more power. Embodiments of the present invention are based on the recognition that a semiconductor structure that can supply more power to a semiconductor chip without affecting electrical performance is desirable.

[0015] Embodiments of the present invention are based on the recognition that by moving the power supply network to the back surface of the wafer and connecting it to the front-side metal layer using through-silicon vias (TSVs), the wiring demand in the front-side wiring layer is reduced. By using a plurality of back-side metal layers for the back-side power supply network, more power and ground lines and more power planes are provided for power distribution compared to conventional embedded power rails. Embodiments of the present invention are based on the recognition that a new semiconductor structure forming a back-side power supply network within a plurality of back-side metal layers is desirable. Embodiments of the present invention are based on the recognition that by generating a back-side power distribution network, a semiconductor chip with a smaller area can be provided.

[0016] Embodiments of the present invention are based on the recognition that in order to supply power from the back surface of a semiconductor chip to front-side semiconductor devices, a decoupling capacitor on the back surface of the semiconductor chip is required to stabilize the flow of current on the back surface of the semiconductor chip. Embodiments of the present invention are based on the recognition that the ability to provide an increased capacitance is desirable to stabilize the flow of current to the back-side power line. Further, embodiments of the present invention are based on the recognition that the decoupling capacitance in the back-side metal layer of the power supply network reduces power supply noise.

[0017] Embodiments of the present invention provide a semiconductor structure and a method of forming a semiconductor structure that form a portion of a floating metal layer between power and ground lines for a power supply network in one or more backside metal layers of a semiconductor chip. Embodiments of the present invention provide multiple backside metal layers having floating metal between power and ground lines, thereby increasing the decoupling capacitance and capacitance density for backside power supply. Embodiments of the present invention provide a semiconductor structure having portions of backside floating metal in one or more backside metal layers, thereby increasing the decoupling capacitance for current stability of a backside power supply network that supplies power to semiconductor devices on the front side of a wafer. The floating metal does not contact the power and ground lines on the backside of the wafer, but embodiments of the present invention provide a portion of a floating metal layer that increases capacitance without an obvious ground connection.

[0018] Embodiments of the present invention provide any number of backside metal layers, where each backside metal layer is composed of one or more of the power planes, one or more portions of the power planes, or multiple portions of a floating metal layer separated from dielectric material by some power and ground lines constituting a backside power distribution network. By generating a power distribution network in the backside metal layer of the semiconductor chip, the front side metal layer of the semiconductor chip for additional wiring and circuits can be freed, or the size of the semiconductor chip can be reduced, or both can be achieved.

[0019] Embodiments of the present invention provide a portion of a floating metal layer that is between power and ground lines and is separated from the power and ground lines by a high-k dielectric material to increase the capacitance density of the backside power supply network. Embodiments of the present invention provide using a high-k dielectric constant material on the backside of the wafer to increase the backside decoupling capacitance and using a low-k dielectric material on the front side metal layer to reduce the parasitic capacitance between signal lines on the front side of the wafer.

[0020] Embodiments of the present invention provide a power distribution network using a portion of a floating metal layer and several power and ground lines in the back metal layer of one or more semiconductor chips. The portion of the floating metal layer and the power and ground lines are formed in a pre-empted, or unused, portion of the back surface of the wafer. In embodiments of the present invention, a portion of the floating metal layer is provided that is the same height as the adjacent power and ground lines. In other embodiments of the present invention, a portion of the floating metal is provided that is different in height from the adjacent power and ground lines. In embodiments of the present invention, the height of the portion of the floating metal layer is adjusted to give a desired capacitance. In addition, in embodiments of the present invention, the amount of floating metal can be controlled to achieve desired thermal properties for each back metal layer having the floating metal.

[0021] Embodiments of the present invention provide a method for controlling, at least partially, the capacitance of a back-side power supply structure using the density of floating metal, in which case the density of floating metal is determined by the height of the floating metal adjacent to the power and ground lines and the distance between adjacent portions of the floating metal layer. In embodiments of the present invention, the distance between adjacent portions of the floating metal layer can be adjusted by changing the pitch of adjacent power lines or ground lines or both. The density of portions of the floating metal layer affects the capacitance density of the back-side metal power supply network. Embodiments of the present invention provide a method for controlling or adjusting the capacitance density of each back-side metal layer in a back-side power supply network by controlling the height of portions of the floating metal layer and the pitch or distance between portions of the floating metal layer.

[0022] Embodiments of the present invention adjust the capacitance of the back metal layer at least partially by selecting a dielectric material between the floating metal portion and the power and ground lines. The dielectric constant of the dielectric material between the floating metal portion and the power line or the ground line or both at least partially determines the capacitance, i.e., decoupling capacitance, provided by the floating metal adjacent to the dielectric material in contact with the power and ground lines of the back metal layer. Embodiments of the present invention provide a dielectric material with a high k dielectric constant to isolate the floating metal portion from the power and ground lines. Using a dielectric material with a high k dielectric constant between the floating metal and the power and ground lines further increases the capacitance provided by embodiments of the present invention.

[0023] Embodiments of the present invention provide a method and structure for controlling, at least partially, the capacitance, power distribution, and thermal conductivity of a backside metal layer by the number of backside metal layers utilizing floating metal. In addition, embodiments of the present invention can increase the backside metal density to improve the dissipation of thermal energy generated by frontside semiconductor devices that become hot spots in a semiconductor chip.

[0024] Embodiments of the present invention provide a plurality of back metal layers incorporating power and ground lines separated from floating metal by a portion of a layer of high-k dielectric material. While the description of embodiments of the present invention focuses on forming floating metal on a first back metal layer on a wafer substrate having pre-formed front devices and wiring, as is known to those skilled in the art, floating metal can be formed on more than one number of back metal layers on a wafer, together with one or more power planes or portions of power planes in other back metal layers, by some process modifications. According to embodiments of the present invention, portions of the floating metal layer can be formed on a third or fourth metal layer on the back surface of the wafer.

[0025] Embodiments of the present invention provide several methods for forming a semiconductor structure having floating metal separated from the power and ground lines by a dielectric material, and also between the power and ground lines. Embodiments of the present invention provide both subtractive and damascene wiring processes for forming the floating metal.

[0026] Embodiments of the present invention provide a subtractive wiring process for forming floating metal, which includes depositing a metal layer on the upper surface of an inverted wafer. The inverted wafer is a thinned wafer, and the upper surface of the inverted wafer is the lower surface of the back of the wafer after device formation and backside grinding of the wafer.

[0027] In embodiments of the present invention, a metal material is provided that can be subjected to a semiconductor subtractive etching process, such as reactive ion etching. The metal layer is patterned and selectively etched to form power and ground lines in the first back metal layer. A dielectric material is deposited on top of the power and ground lines and the exposed surface on the back of the wafer. By selecting the dielectric material, capacitance can be improved. A second metal layer is deposited on top of the dielectric material. The second metal layer may be the same metal as the first metal layer or a different metal. In various embodiments, the metal of the second metal layer may be etched by a subtractive etching process. Excess portions of the second metal layer above the high-k dielectric material are removed by chemical mechanical polishing (CMP).

[0028] In embodiments of the present invention, an optional step of recessing a metal layer is performed. In the optional recessing step, a second metal layer is recessed using a subtractive etching process. The amount of recession of the second metal layer controls the amount of floating metal between the power and ground lines. Recessing the second metal material provides one method to at least partially control the capacitance provided by the floating metal and the metal density of the floating metal, which affects the thermal properties of the floating metal in the back metal layer.

[0029] After the second metal layer is deposited, or after the second metal layer is optionally recessed, a layer of interlayer insulating material is deposited on the semiconductor structure. The interlayer insulating material covers the dielectric material and the exposed portion of the floating metal. After the interlayer insulating material has been deposited, forming the floating metal, power and ground lines, another backside metal layer may be deposited on the interlayer insulating material, forming another backside power structure, such as part of the power plane or another floating metal layer with power and ground lines. One or more vias may be formed in the interlayer insulating material to connect the power and ground lines of the first backside metal layer to one or more metal layers on the front side of the semiconductor wafer. Embodiments of the present invention provide a method for forming portions of floating metal layers on second, third, fourth, fifth, or further upper backside metal layers using a subtractive wiring process. The floating metal layer portions and power and ground lines formed on the second and even higher metal layers may require larger sizes and spacing, similar to semiconductor lines and features already formed on the metal layers above the back-end-of-the-line (BEOL) interconnection layers on the upper side of the semiconductor wafer. In various embodiments, through-silicon vias connecting the back-side metal layer to the front-side metal layer are formed before the back-side metal layer is formed.

[0030] In embodiments of the present invention, a damascene wiring process is performed to form a power supply network on one or more backside metal layers on a wafer substrate. The damascene wiring process for the backside metal layers includes patterning and etching the upper surface of the backside of the wafer, where the inverted backside of the wafer is represented as the upper surface for the patterning and etching processes. By etching the wafer, recesses or trenches are formed on the backside of the wafer. The pitch of the trenches is determined by the patterning before etching, and the depth of the trenches is determined by the etching process (controlled by etching process parameters such as dose and etching time, for example). The pitch and depth of the trenches are correlated with the capacitance and thermal properties of each backside metal layer. The method includes depositing a layer of dielectric material, such as a high-k dielectric material, on a semiconductor structure to cover the exposed surface of the backside of the wafer. A layer of first metal is deposited on the dielectric material, and excess portions of the first metal above the upper surface of the dielectric material are removed by CMP. After CMP, the first metal remains in the formed trenches surrounded by the dielectric material. In embodiments of the present invention, the power and ground lines in the completed semiconductor chip are formed from a first metal above the upper surface of the dielectric material.

[0031] In embodiments of the present invention, the next step of the method is performed to form floating metal using a damascene wiring process. The next step includes removing wafer material surrounding the sides of the dielectric material using a wet process combined with a dry etching process. Once the combined wet etching and dry etching process is complete, at least the bottom of the dielectric material is in contact with the wafer. A portion of the first metal remains inside the dielectric material.

[0032] Embodiments of the present invention include depositing a second metal on the upper surface of a semiconductor structure. The second metal covers the wafer, dielectric material, and exposed portions of the first metal. CMP removes the excess second metal above the top of the dielectric material. In some embodiments, the dielectric material is the CMP stop. In one embodiment, portions of the dielectric material and the first metal are removed. The remaining portions of the second metal on the wafer, surrounded by the sides of the dielectric material, become floating metal in the finished semiconductor chip.

[0033] Embodiments of the present invention include an optional step of recessing a second metal. The amount of second metal removed is controlled. The amount of second metal removed controls the height of the remaining floating metal. By controlling the height of the floating metal during the recess etching process, the capacitance provided by the floating metal can be adjusted or controlled. With respect to subtractive wiring processes, as described above, the amount of second metal remaining after the optional recess of the second metal determines the density of the floating metal for removing thermal energy and providing capacitance.

[0034] Embodiments of the present invention provide a method for forming portions of floating metal layers on one or more backside metal layers on the back surface of a wafer using either a damascene or subtractive wiring process. This method allows for control of the size, shape, and distance between portions of the floating metal layer, at least partially enclosed by a dielectric material, as a method for controlling the capacitance of a backside power supply network. Providing a backside power supply network with floating metal layer portions also provides additional wiring possibilities on the frontside metal layer of a semiconductor chip (for example, freeing up semiconductor real estate on the frontside wafer metal layer for wiring previously required for the power supply network).

[0035] Detailed embodiments of the claimed structure and method are disclosed herein. The method steps described below do not constitute a complete process flow for manufacturing integrated circuits, such as semiconductor devices. These embodiments may be carried out in conjunction with integrated circuit manufacturing techniques currently used in the art and include only those commonly practiced process steps necessary for understanding the embodiments described. The figures represent cross-sectional portions of the semiconductor structure after manufacturing and are not drawn to exact proportions, but are drawn to illustrate the features of the embodiments described. Specific structural and functional details disclosed herein should not be construed as limiting, but merely as representative grounds for teaching those skilled in the art to employ the methods and structures of this disclosure in various ways. In this specification, well-known features and technical details may be omitted to avoid unnecessarily obscuring the embodiments presented.

[0036] References in this specification to “one embodiment,” “other embodiment,” “another embodiment,” and “an embodiment” indicate that the embodiments described may include certain features, structures, or characteristics, but not all embodiments necessarily include such features, structures, or characteristics. Furthermore, such expressions do not necessarily refer to the same embodiment. Moreover, if certain features, structures, or characteristics are described in relation to an embodiment, it is understood that any influence on such features, structures, or characteristics in relation to other embodiments, whether explicitly stated or not, is within the knowledge of those skilled in the art.

[0037] In the following description, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” and “bottom,” and their derivatives, refer to the structures and methods disclosed as oriented in the drawings. The terms “overlying,” “atop,” “over,” “on,” “positioned on,” or “positioned atop” mean that the first element is located on the second element, and intervening elements such as interface structures may be present between the first and second elements. The term “direct contact” means that the first and second elements are connected at the interface of the two elements without an intermediate conductive layer, insulating layer, or semiconductor layer.

[0038] To avoid obscuring the presentation of embodiments of the present invention, some processing steps, materials, or operations known in the art may be combined in the following detailed description for the purpose of presentation and explanation, and in some cases, they may not be described in detail. In addition, in order to be concise and to continue to focus on the distinctive features of the elements of the present invention, previously described materials, processes, and structures may not be repeated in subsequent figures. In other cases, known processing steps or operations may not be described. It should be understood that the following description focuses rather on the distinctive features or elements of various embodiments of the present invention.

[0039] Figure 1 shows a cross-sectional view of a semiconductor structure 100 having a back-side wafer structure 19 for a back-side power supply structure, comprising power and ground lines 12 and a floating metal 14 for increasing capacitance, according to an embodiment of the present invention. As shown, Figure 1 includes signal line 1 of the M1 metal layer, signal line 2 of the M2 metal layer, signal line 3 of the M3 metal layer, via 4 connecting a portion of signal line 1 to signal line 2, and via 5 connecting one of signal lines 2 to one of signal lines 3, with signal lines 1, 2 and 3 along vias 4 and 5 each representing a portion of the BEOL interconnect layer 18 in the ILD 6 above the device region 11 on the wafer substrate 10. Figure 1 also shows a back-side wafer structure 19 having two back-side metal layers, including a first metal layer on the back side of the wafer substrate 10 comprising a floating metal 14 separated from the power and ground lines 12 by a dielectric material 13, and a second metal layer on the back side of the wafer substrate 10 having a power plane 22 in the ILD 26. As shown, the power plane 22 of the second back metal layer is connected to the power and ground line 12 of the first back metal layer by vias 24. In other examples, the power plane 22 may be part of the power plane or another layer of the power and ground line (e.g., the power and ground line 12 in the second back metal layer). The semiconductor structure 100 may be formed using a damascene wiring process, as will be described in detail with respect to Figures 9 to 17.

[0040] The power and ground lines 12, floating metal 14, and power plane 22 on the back surface of the wafer substrate 10 may, but are not limited to, copper, ruthenium, cobalt, tungsten, or other metal or metal alloy materials suitable for use as semiconductor wires. The power and ground lines 12 may, but are not limited to, alternating adjacent power and ground lines. In some examples, adjacent power and ground lines 12 may be two adjacent power lines surrounded by multiple ground lines. In some cases, the power and ground lines 12 may be power rails. The specific allocation of power and ground lines may be determined by the semiconductor chip design. The spacing, or pitch, between the power and ground lines 12 may determine the length of each floating metal 14. The spacing between the power and ground lines 12 and the height of the floating metal 14 correlate with the capacitance of the first back surface metal layer on the wafer substrate 10. The method for forming the semiconductor substructure 100 allows for adjustment or modification of the height of the floating metal 14 and the pitch between the power and ground lines 12, thereby achieving desired electrical performance in the finished semiconductor chip. By changing either the height of the floating metal 14 or the pitch of the power and ground lines 12, or both, both the capacitance and thermal properties of each back metal layer can be increased or decreased. In addition, even if the floating metal 14 is not connected to the power and ground lines 12, the capacitance of each back metal layer can be increased using floating metal layers such as the floating metal 14 shown on the first back metal layer on the wafer substrate 10.

[0041] Although Figure 1 shows only two back metal layers, embodiments of the present invention are not limited to two back metal layers. In other embodiments, there may be five or six back metal layers, each of which is separated by an ILD material and connected by one or more vias (similar to via 24, for example). One or more of the multiple back metal layers may include several portions of floating metal similar to floating metal 14, separated from power and ground lines (similar to power and ground lines 12, for example) by a dielectric material 13. For example, power and ground lines similar to power and ground lines 12 may be formed in a third back metal layer (not shown in Figure 1) together with several portions of the floating metal layer. The floating metal may be separated from the power and ground lines in the third back metal layer by the dielectric material 13 or another similar high-k dielectric material.

[0042] The power and ground lines of the third back metal layer may be formed by the same or similar process, but may be larger in size than the power and ground lines 12 of the first back metal layer, or have a larger pitch between the power and ground lines of the third metal layer, or both. As is known to those skilled in the art, due to limitations of the semiconductor manufacturing process, the size of the power and ground lines 12 and the floating metal 14 and the spacing between them may increase in subsequent back metal layers (for example, in the fifth back metal layer, the power and ground lines 12 may become larger, as may the spacing between them).

[0043] As shown in Figure 1, the floating metal 14 is formed between the power and ground lines 12 in the first back metal layer. In Figure 1, the floating metal 14 is isolated from the power and ground lines 12 by a dielectric material 13. In various embodiments, using a high-k dielectric material for the dielectric material 13 between the floating metal 14 and the power and ground lines 12 increases the capacitance of the power supply network. By forming the floating metal 14 between the power and ground lines 12 in the back metal layer on the wafer substrate 10, previously unused portions of the back surface of the wafer substrate 10 are utilized.

[0044] Figure 1 also shows a wafer substrate 10 and a device region 11. The wafer substrate 10 may be thinned after the BEOL process using a known back-side wafer grinding process. The wafer substrate 10 may be a thinned wafer or a portion of a thinned wafer thinned using a known back-side wafer grinding process. The device region 11 may be formed before the BEOL process and includes one or more active semiconductor devices and associated semiconductor structures. The device region 11 and the BEOL interconnection layer 18 are formed prior to the formation of the floating metal 14 on the back surface of the wafer substrate 10.

[0045] As shown in Figure 1, the floating metal 14 and the power and ground lines 12 are formed using a damascene back-side wiring process. Using the damascene back-side wiring process results in power and ground lines 12 with a smaller bottom contact area with the wafer substrate 10 and a larger bottom surface for the power and ground lines 12 (for example, the bottom surface of the power and ground lines 12 is on the side away from the surface of the wafer substrate 10). For example, the power and ground lines 12 may have a trapezoidal shape where the smaller portion of the trapezoid contacts the wafer substrate 10. In other examples, the power and ground lines 12 may have a rounded cone shape with a large bottom surface. As shown in Figure 1, the bottom surface of the power and ground lines 12 on the back surface of the wafer substrate 10 and the bottom surface of the floating metal 14 are at the same height. The power and ground lines 12 and the floating metal 14 constitute a first back-side metal layer on the wafer substrate 10. The BEOL interconnect layer 18 includes wiring, vias, and contacts (not shown) above the device region 11. The BEOL interconnect layer 18 includes signal lines and vias for conducting current, but does not include power and ground structures such as power lines or power planes for distributing the power typically required to the BEOL interconnect layer 18. In various embodiments, structures such as power planes, grounds, and power lines are located in the back metal layer 18 together with the floating metal 14. In this way, the semiconductor occupied area in the BEOL interconnect layer 18 is not used for power and ground structures. In embodiments of the present invention, the BEOL interconnect layer 18 provides more available semiconductor area in each metal layer for wiring. Even with the use of embedded power rails, it is not possible to provide as much available semiconductor occupied area in the BEOL interconnect layer 18 for wiring as in embodiments of the present invention that utilize multiple back metal layers for power and ground structures with improved, i.e., increased capacitance due to the presence of floating metal between the back power and ground lines. Although not shown in Figure 1, in various embodiments, known through-silicon vias (TSVs) connect a backside power structure, such as a power and ground line 12 or a power plane 22 or both, to one or more of the BEOL interconnect layers 18, such as a recessed power rail or a frontside power network.

[0046] Figure 1 is an extended view of Figure 16, including a second back metal layer that forms a power plane 22. In various embodiments, the second back metal layer is connected by one or more vias 24 to one of the power and ground lines 12 present in the first back metal layer. Figure 16 shows a first back metal layer having a metal 140 that becomes part of a floating metal (e.g., a floating metal 14 shown in Figure 1) and a metal material 120 that becomes a power and ground line (e.g., a power and ground line 12 shown in Figure 1). Both the semiconductor structure 100 in Figure 1 and the semiconductor structure 1600 in Figure 16 are formed using a damascene wiring process in various embodiments. Figure 1 is similar to or essentially the same as Figure 16, with the exception that Figure 1 shows an additional second back metal layer having a power plane 22 and vias 24 within the ILD 26, the vias 24 connecting the power and ground line 12 to the power plane 22.

[0047] As mentioned above, in other examples, a third back metal layer may be located below the power plane 22 in Figure 1. The third back metal layer (not shown) connects to the power plane 22 of the second back metal layer using one or more additional vias in the ILD 26. The third back metal layer may include a portion of a floating metal layer separated by a dielectric material, similar to the first back metal layer in Figure 1, and power and ground lines. As is known to those skilled in the art, conventional semiconductor manufacturing processes can be completed on the semiconductor structure 100 (e.g., wafer dicing) to produce a semiconductor chip.

[0048] Figure 2 shows a cross-sectional view of a semiconductor structure 200 having a portion of a wafer substrate 10 having metal 20 and a device region 11, according to an embodiment of the present invention. Figures 2 to 8 show embodiments of a subtractive wiring process for forming a portion of a floating metal layer in a power supply network. As shown, Figure 2 includes a device region 11 and a metal layer 20 on the wafer substrate 10. The layer of metal 20 is on one side of the wafer substrate 10, and the device region 11 is on the other side of the wafer substrate 10. In Figure 2, the wafer substrate 10 is drawn with its front side down, so that the device region 11 is beneath the wafer substrate 10. Not shown in Figure 2 are the BEOL metal layers such as M1, M2, and M3 of the BEOL interconnection layer 18 shown in Figure 1.

[0049] In Figures 2-7 and 9-16, the device side of the wafer substrate is facing downwards (i.e., during backside processing of the wafer substrate 10, the device region 11 is on the underside of the inverted wafer substrate 10), so the terms "upper side" or "top surface" can correspond to the back surface of the inverted wafer substrate. Thus, the exposed surface or exposed top surface of the wafer substrate 10, normally called the back surface of the wafer substrate, can be processed to form the backside power supply structure.

[0050] Metal 20 is deposited on the back surface of the wafer substrate 10. In various embodiments, metal 20 is a first back surface metal layer deposited on the back surface of the wafer substrate 10. As shown in Figure 2, the wafer substrate 10 is inverted so that the front side of the wafer substrate 10 with the device region 11 is facing downwards and the back surface of the wafer substrate 10 is facing upwards.

[0051] In various embodiments, a layer of metal 20 is deposited on the exposed surface of the wafer substrate 10. Metal 20 can be deposited using known semiconductor deposition methods such as chemical vapor deposition (CVD), plasma vapor deposition (PVD), or atomic layer deposition (ALD), but is not limited to these. Metal 20 can be any metallic material used in semiconductor manufacturing that can be subtractively etched to form power and ground lines on the back surface. For example, metal 20 may consist of cobalt, ruthenium, tungsten, or molybdenum, but is not limited to these metals. The thickness of the deposited metal 20 may vary depending on the application of the semiconductor chip and the semiconductor devices in the device region 11.

[0052] For example, if the cell height of the semiconductor device in the device region 11 above the metal 20 is approximately 200 nm, the thickness of the metal 20 may be in the range of 100 to 200 nm. However, the metal 20 may also have other different thicknesses. In various embodiments, the thickness of the metal 20 depends, at least in part, on the pitch of the device in the device region 11. Although not shown in Figure 2, if additional back metal layers, such as a second or third back metal layer, are deposited as described above, the thickness of each additional back metal layer may increase, and the size of the power and ground lines formed, and the associated floating metal features between the power and ground lines, may increase.

[0053] Figure 3 shows a cross-sectional view of a semiconductor structure 300 after subtractive etching of a portion of the metal 20 according to an embodiment of the present invention. As shown, Figure 3 includes the elements of Figure 2 after a portion of the metal 20 has been removed to initiate the formation of a power distribution structure (e.g., ground and power lines and planes on the back surface). The remaining portions of metal 20 after the selective etching process become the power and ground lines on the back surface of the wafer substrate 10. The pitch between the remaining portions of metal 20 at least partially determines the length of the portions of the floating metal layer to be deposited, as will be discussed later with respect to Figure 5. In some embodiments, the height of the remaining metal 20 determines the height of the portions of the floating metal layer formed by metal 40, as will be shown later in Figure 6.

[0054] Conventional photolithography and wafer etching processes can remove portions of the metal 20. For example, the top surface of the metal 20 can be patterned to remove selected portions of the metal 20 using a dry etching process such as reactive ion etching (RIE). RIE is an anisotropic etching process in which the wafer substrate 10 can be used as an etch stop. As shown, Figure 3 includes two portions of metal 20 remaining on the wafer substrate 10 after etching. In other examples, several portions of metal 20 may be formed with the same or different spacing, i.e., pitch, between the residual metal 20.

[0055] The desired height, shape, and pitch between the residual portions of metal 20 may vary depending on several factors, such as the pitch and height of the device cells above the metal 20 in the device region 11, or the desired metal density of the power and ground features formed by the residual portions of metal 20. Different sizes or shapes of residual metal 20 can be given using different patterns in photolithography and different process parameters during RIE etching. The size, shape, and pitch of the power and ground features formed by the residual metal 20 after etching can be controlled or adjusted to achieve specific electrical performance of the finished semiconductor chip. For example, the height and width of the power lines can be adjusted to minimize resistance and improve chip performance. Furthermore, the spacing, i.e., pitch, between adjacent portions of metal 20 affects the capacitance provided by the floating metal fabricated in a later processing step. As shown in Figure 3, in various embodiments, after etching, the bottom of the power and ground line 12 is larger than the top of the power and ground line 12 (for example, the power and ground line 12 may have a trapezoidal, modified, or rounded conical cross-section).

[0056] Figure 4 shows a cross-sectional view of a semiconductor structure 400 after deposition of dielectric material 30 on the exposed portion of the wafer substrate 10 and the residual portion of the metal 20 according to an embodiment of the present invention. As shown, Figure 4 includes a device region 11, a wafer substrate 10, metal 20, and dielectric material 30. The dielectric material 30 can be any dielectric material. In various embodiments, the dielectric material 30 is a high-k dielectric material. For example, the dielectric material 30 may be, but is not limited to, hafnium oxide material (e.g., HfO2), zirconium oxide material (e.g., ZrO2), aluminum nitride material (e.g., AlN), silicon oxide (e.g., SiO2), or aluminum oxide material (e.g., Al2O3).

[0057] The thickness of the dielectric material 30 may be in the range of 7 nm to 500 nm, but is not limited to this range. The dielectric material 30 may be deposited using one of the following methods: plasma-enhanced CVD (PECVD), PVD, CVD, or ALD, but may also be deposited using other semiconductor manufacturing deposition processes. In one embodiment, a spin-on dielectric material or spin-on glass (SOG) is deposited on the wafer substrate 10. The dielectric material 30 separates the metal 20, which forms the power and ground lines, from the floating metal formed in a later process step. By selecting a high-k dielectric material for the dielectric material 30, such as hafnium oxide, an increased capacitance can be obtained in the finished semiconductor chip (e.g., shown in Figure 8).

[0058] Figure 5 shows a cross-sectional view of a semiconductor structure 500 after depositing metal 40 on a dielectric material 30 according to an embodiment of the present invention. As shown, Figure 5 includes the elements of Figure 4 and metal 40. Metal 40 can be deposited by PVD, CVD, ALD, or other suitable metal deposition process. Metal 40 may be composed of different or the same metal material as metal 20. Metal 40 may be composed of, but is not limited to, cobalt, ruthenium, molybdenum, or tungsten. As shown in Figure 5, the deposition of metal 40 may cover the dielectric material 30 and extend above the upper surface of the dielectric material 30. The combination of metal 20 and metal 40 constitutes the first back metal layer of the finished semiconductor chip.

[0059] In one embodiment, the deposition of metal 40 covers the bottom of the dielectric material 30 (for example, extending to 50% or 70% of the side surface of the dielectric material 30). If the metal 40 is deposited to a desired depth below the top surface of the dielectric material 30, the CMP described with respect to Figure 6 may be omitted. In other words, instead of depositing metal 40 and then performing CMP and wet etching recesses, as will be discussed later with respect to Figure 6, controlled deposition of metal 40 to a desired height may be used.

[0060] As shown in Figure 5, in various embodiments, the bottom of the metal 40 that is in contact with the dielectric material 30 and close to the wafer substrate 10 is smaller than the top of the metal 40 that is not close to the wafer substrate 10. For example, the metal 40 that becomes a floating metal may have a trapezoidal shape, with the smaller portion of the trapezoid being close to the wafer substrate 10 and above the dielectric material 30.

[0061] Figure 6 shows a cross-sectional view of the semiconductor structure 600 after CMP according to an embodiment of the present invention. CMP removes excess metal 40 above the dielectric material 30, using the upper surface of the dielectric material 30 as a CMP stop. After CMP, the upper surface of the semiconductor structure 600 is flat, and the upper surface of the metal 40 is at the same height as the upper surface of the dielectric material 30 above the remaining portion of metal 20. As shown, the height of the metal 40 can be determined by the height of the power and ground lines formed by the metal 20 and the thickness of the dielectric material 30.

[0062] Figure 7 shows a cross-sectional view of a semiconductor structure 700 according to an embodiment of the present invention, after recessing the metal 40 and depositing ILD 60 on the exposed upper surface of the dielectric material 30 and the remaining portion of the metal 40. Recessing the metal 40 is an optional step and may be performed or not performed, at least in part, depending on the desired electrical performance characteristics of the semiconductor chip, or the limitations and yield in the semiconductor device manufacturing process, or both. As shown, Figure 7 includes the elements of Figure 6, except that the height of the metal 40 is lower. The height of the metal 40 between the dielectric material 30 on the metal 20 may be the same as the upper surface of the dielectric material 30 if the optional recess of the metal 40 is not performed, and the height of the metal 40 may be lower than the height of the metal 20. For example, the height of the remaining metal 40 may be varied depending on the desired metal density of the metal 40 that will become the floating metal of the finished semiconductor chip. For example, the magnitude of the capacitance may be controlled at least in part by the amount of metal 40 remaining after recessing. By increasing the amount of residual metal 40 that becomes floating metal, the capacitance and capacitance density of the backside power supply network can be increased. In addition, by controlling the amount of residual metal 40 after recessing, the desired thermal conductivity of the backside metal layer of the finished semiconductor chip can be provided.

[0063] RIE may be used to recess the metal 40. The depth of the recess or the amount of metal 40 removed can be varied and adjusted by the desired metal density in the first back metal layer (for example, adjusted to suit optimal electrical and thermal chip performance). For example, the recess of metal 40 can expose about half the height, i.e., the sidewall, of the dielectric material 30 on the metal 20. The semiconductor structure 700 may be formed using a subtractive process on the wafer substrate 10, metal 20, and metal 40.

[0064] Figure 8 shows a cross-sectional view of a semiconductor structure 800 according to an embodiment, comprising a BEOL interconnect layer 98 and a first back metal layer 99 which forms a power distribution structure having part of three floating metal portions consisting of metal 20 and capacitance-increasing metal 40. Figure 8 includes a device region 11 and the BEOL interconnect layer 98 above the wafer substrate 10, and a back metal layer 99 with metal 20 and metal 40 below the wafer substrate 10. As shown, Figure 8 includes an ILD 60, a dielectric material 30 in contact with the periphery of metal 20 and part of the wafer substrate 10, metal 40 above the ILD 60 surrounded by the dielectric material 30, the device region 11 above the wafer substrate 10, signal lines 91, 92 and 93, and vias 94 and 95 in the ILD 16 of the BEOL interconnect layer 98. Figure 8 shows a semiconductor structure 800 formed using a subtractive wiring process.

[0065] The metal 20 and metal 40 of the back metal layer 99 are formed by a subtractive process. Each portion of metal 20 is either a power line or a ground line. As mentioned above, the arrangement of power and ground lines in the back metal layer 99 can be determined by the semiconductor chip design. For example, the leftmost metal 20 may be a power line adjacent to a metal 20 that is a ground line.

[0066] As is known to those skilled in the art, although only lines 91, 92, 93 and vias 4, 5 are shown as the BEOL interconnect layer 98, the BEOL interconnect layer 98 may also include other lines, vias, and contacts above line 93 of the M3 of the BEOL interconnect layer 98, as well as additional metal layers (e.g., M4, M5, M10, etc.). Not shown in Figure 8, in various embodiments, the TSV connects the power and ground lines 20 to one or more of the BEOL interconnect layers 98 or to an embedded power rail (not shown). As is known to those skilled in the art, not shown in Figure 8, one or more additional back metal layers deposited, patterned, and etched to form more floating metal layers and portions of power lines may be present in Figure 8, along with vias connecting the metal layers and layers of ILD 60 separating the metal layers.

[0067] Figure 9 shows a cross-sectional view of a semiconductor structure 900 having a wafer substrate 101 according to an embodiment of the present invention. As shown, Figure 9 includes the wafer substrate 101 after back-ground milling and the device region 11 on the front side, i.e., the device side, of the wafer substrate 101. The device region 11 is essentially the same as the device region 11 in Figure 1. Although not shown in Figure 9, a BEOL metal layer exists above the device region 11 on the front side of the wafer substrate 10. The BEOL metal layer is shown as the BEOL interconnection layer 98 in Figure 1. In various embodiments, the wafer substrate is a thinned wafer substrate 101. The wafer substrate 101 may be similar to or essentially the same as the wafer substrate 10 shown in Figure 1.

[0068] Figure 10 shows a cross-sectional view of a semiconductor structure 1000 after etching a wafer substrate 101 according to an embodiment of the present invention. Figures 10 to 16 show a method for forming a floating metal layer on the back surface of the wafer substrate 101 using a damascene wiring process.

[0069] Using known semiconductor wafer etching processes such as photolithography and RIE or ion beam etching (IBE), portions of the wafer substrate 101 are selectively removed to form back-side power structures (e.g., lines and planes). The amount or portion of the wafer substrate 101 removed can at least partially determine the size and shape of the power and ground lines formed in the first back-side metal layer in a later process step. In addition, the spacing of the removed portions of the wafer substrate 101 can determine the pitch of the power and ground lines formed in a later process step. The size, spacing, and shape of the removed portions of the wafer substrate 101 can be controlled to result in desired capacitance and thermal performance characteristics of the first back-side metal layer of the finished semiconductor chip. In other words, the amount of wafer substrate 101 removed by RIE can control at least some of the electrical and thermal performance characteristics of the first back-side metal layer when the semiconductor chip processing is complete.

[0070] Figure 11 shows a cross-sectional view of a semiconductor structure 1100 after a dielectric material 130 has been deposited on a wafer substrate 101 according to an embodiment of the present invention. As shown, Figure 11 includes a device region 11 below the wafer substrate 101 and the dielectric material 130. The dielectric material 130 can be deposited on the upper surface of the wafer substrate 101 and inside recesses or trenches formed by etching the wafer substrate 101, for example, using one of PECVD, PVD, CVD, or ALD. In one embodiment, a spin-on dielectric material or spin-on glass (SOG) is deposited on the wafer substrate 101. The dielectric material 130 conformally coats the surface of the wafer substrate 101.

[0071] The dielectric material 130 can be any dielectric material used in semiconductor manufacturing. In various embodiments, the dielectric material 130 is a high-k dielectric material selected to improve the capacitance of the finished power supply network. For example, the dielectric material 130 may be, but is not limited to, one of the following: hafnium oxide, zinc oxide, aluminum nitride, or aluminum oxide. The thickness of the dielectric material 130 can be controlled and vary depending on the desired electrical requirements, i.e., capacitance, of the finished semiconductor chip (e.g., from 7 nm to 500 nm). As mentioned above, using a high-k dielectric material instead of a low-k dielectric material for the dielectric material 130 between the floating metal and the power and ground lines can result in a larger capacitance compared to using a low-k dielectric material in the same semiconductor chip design.

[0072] Figure 12 shows a cross-sectional view of a semiconductor structure 1200 after depositing a metal material 120 according to an embodiment of the present invention and performing CMP to remove excess dielectric material 130 and excess metal material 120 from the unetched upper surface of the wafer substrate 101. As shown, Figure 12 includes the elements of Figure 11 and the metal material 120. The metal material 120 may be a metal with copper added, similar to the metal material used for metal 20 in Figure 2. Copper is not used in Figure 2 of the previous embodiment because it is difficult to use subtractive etching processes on copper in semiconductor manufacturing. Therefore, the metal material 120 may be, but is not limited to, copper, cobalt, ruthenium, tungsten, molybdenum, or similar metals or metal alloys used in semiconductor power supply structures. The metal material 120 may be, but is not limited to, known semiconductor metal deposition processes such as PVD, CVD, and ALD. The metal material 120 is deposited on the dielectric material 130, filling recesses in the wafer substrate 101 and extending above the surface of the dielectric material 130.

[0073] After the deposition of the metal material 120, CMP (Chemical Polishing) may be performed to remove any excess dielectric material 130 and metal material 120 that is located higher up on the wafer substrate 101, i.e., above the unetched top surface. In various embodiments, CMP uses the unetched top surface of the wafer substrate 101 as a CMP stop. In this case, the top surfaces of the wafer substrate 101, the dielectric material 130, and the metal material 120 are all at the same height (for example, the top surface of the semiconductor structure 900 is flat). As previously stated, the wafer substrate 101 is a wafer that has been turned over for processing, and is shown so that what is typically known as the back layer of the wafer substrate 101 (e.g., the metal material 120 and dielectric material 130) is on the top surface of the wafer substrate 101. In other words, the top surface of the wafer substrate 101 when it is not turned over becomes the bottom surface of the wafer substrate 101.

[0074] In some embodiments, the CMP removes a portion of the unetched upper surface of the wafer substrate 101. In this embodiment, the CMP at least partially determines the height of the floating metal (i.e., metal 140) portion of the semiconductor structure 1400, which will later be shown in Figure 14.

[0075] Figure 13 shows a cross-sectional view of the semiconductor structure 1300 after etching the portion of the wafer substrate 101 other than the portion below the residual dielectric material 130, according to an embodiment of the present invention. As shown, Figure 13 includes the elements of Figure 12, except that the amount of wafer substrate 101 is reduced. For example, using a combination of dry etching and wet etching such as RIE, the exposed upper portion of the wafer substrate 101 can be removed to a height equal to or just above the bottom surface of the dielectric material 130. RIE etching may leave portions of the wafer substrate 101 around recessed areas, i.e., lower portions of the dielectric material 130, which can be removed by a wet etching process. Once the etching process is complete, almost all of the side surfaces, i.e., the outside of the dielectric material 130, may be exposed. As shown in Figure 13, the wafer substrate 101 remains below the bottom of the dielectric material 130. In the embodiment, a small portion of the upper surface of the wafer substrate 101 is above the bottom of the dielectric material 130.

[0076] Figure 14 shows a cross-sectional view of a semiconductor structure 1400 after depositing metal 140 on an exposed portion of a wafer substrate 101 and performing CMP, according to another embodiment of the present invention. As shown, Figure 14 includes the elements of Figure 13 and metal 140. In various embodiments, metal 140 fills cavities between adjacent sides of dielectric material 130 and extends over the upper surface of residual metal material 120. Metal 140 may be, but is not limited to, cobalt, ruthenium, molybdenum, or tungsten. Metal 140 may be, but is not limited to, these metals or alloys of these metals. Metal 140 may be deposited on the exposed surfaces of the wafer substrate 101, dielectric material 130, and metal material 120 using known deposition processes such as CVD, PVD, or ALD. The combination of metal material 120 and metal 140 constitutes a first backside metal layer.

[0077] After depositing metal 140, CMP may be performed to remove excess metal 140. CMP may leave a flat surface of the semiconductor structure 1400 where the top surfaces of the exposed portions of metal 140, metal material 120, and dielectric material 130 are at the same height. In various embodiments, CMP stops at the top surface of metal material 120. In embodiments, the top of metal material 120 and the top portion where dielectric material 130 and metal 140 are related are removed. In one embodiment, depositing metal 140 fills a portion of the trenches, i.e., the region between adjacent sides of dielectric material 130 (for example, only the bottom 50% of the sides of dielectric material 130 are covered by metal 140). In this case, CMP is not performed, and optional recesses of metal 140 are not required.

[0078] The metal 140 remaining around the sides of the dielectric material 130 and above the exposed surface of the wafer substrate 101 can form a floating metal in contact with the dielectric material 130 and between the power and ground lines formed by the residual portion of the metal material 120. The portion of the floating metal layer created by the metal 140 increases the capacitance of the backside power structure. Increasing the size or density of the residual portion of metal 140 that forms the floating metal increases the capacitance. The metal 140 that becomes the floating metal provides a decoupling capacitance that stabilizes the flow of current. As mentioned above, it is desirable to increase the capacitance of the backside power supply network. Furthermore, by creating the portion of metal 140, the backside metal density is increased, which can assist in the dissipation of thermal energy generated by the semiconductor device in the device region 11 of the semiconductor chip.

[0079] As explained in Figures 9 to 14, etching the wafer substrate 101 using a damascene wiring process, depositing dielectric material 130, depositing metal material 120 to form power and ground lines, and depositing metal 140 to form floating metal portions allows for control or adjustment of the capacitance of the final semiconductor chip, at least partially, by controlling the shape and material used to form the floating metal portions formed from metal 140 between the power and ground lines of metal material 120. Even without sufficient grounding connections, increased capacitance can be provided by metal 140 (e.g., floating metal). In addition, the amount and density of metal 140 remaining after CMP can be controlled to provide the desired thermal conductivity to the remaining back metal.

[0080] Figure 15 shows a cross-sectional view of the semiconductor structure 1500 after recessing the metal 140 according to an embodiment of the present invention. As shown, Figure 15 includes the elements of Figure 14, except that the amount of metal 140 is reduced. The step of recessing the metal 140 is optional. The recessing of the metal 140 may be performed to obtain a desired metal density in the first back metal layer in order to achieve desired capacitance and thermal conductivity from the first back metal layer in the finished semiconductor chip. In various embodiments, the chip designer achieves a desired balance between capacitance and metal density for both electrical and thermal chip requirements by controlling the residual portion of metal 140 (i.e., floating metal).

[0081] The recess of metal 140 after CMP may be performed using one or more known wet etching processes. The specific wet etching process may be selected depending on the metal material of metal 140. The depth of the recess of metal 140 may be varied by controlling known wet parameters such as etching time, chemical reaction, and temperature. The recess of metal 140 may be small (e.g., about 10% of the height of metal 140) or large (e.g., 60% of the height of metal 140), but is not limited to these amounts. As mentioned above, the capacitance and thermal conductivity provided by the residual portion of metal 140 may be controlled or regulated by the amount of recess that determines the height of metal 140 in contact with the dielectric material 130 between power and ground structures or lines formed by the metal material 120.

[0082] Figure 16 shows a cross-sectional view of the semiconductor structure 1600 after depositing the ILD 160 according to an embodiment of the present invention. As shown, Figure 16 includes the elements of Figure 15 and the ILD 160. The ILD 160 is deposited on the semiconductor structure 1600 to cover the exposed surfaces of the metal 140, dielectric material 130, and metal material 120. The ILD 160 can be any known interlayer insulating material used in semiconductor manufacturing. For example, the ILD 160 may be SiO2. In Figure 16, the portion of the metal 140 in contact with the wafer substrate 101 is larger than the portion of the metal 140 in contact with the ILD 160. In various embodiments, the metal 140 forms a floating metal separated from the power and ground lines of the metal material 120 by the dielectric material 130.

[0083] As is known to those skilled in the art, a second backside metal layer can be deposited on top of the ILD 160. When etching of the wafer substrate 10 is performed as etching of the ILD 160, the process steps described with respect to Figures 9 to 16 are repeated, and a second metal layer (not shown) on the ILD 160 may be personalized to form another layer of power and ground lines on the metal material 120 surrounded by a layer of dielectric material 130. Another layer of metal 140 forms floating metal between the dielectric material 130 on the power and ground lines of the metal material 120. Vias (not shown) can connect the power and ground lines 120 of the first backside metal layer to the power and ground lines 120 (not shown) of the second backside metal layer. In some cases, the second metal layer may be a power plane, such as the power plane 22 shown in Figure 1. Referring to Figures 9 to 16, any number of back metal layers can be formed in one or more layers of floating metal (e.g., metal 140) separated from power and ground lines (e.g., metal material 120) by dielectric material 130.

[0084] Figure 17 is a flowchart showing the steps of a damascene wiring process for forming one or more backside metal layers on a wafer according to an embodiment of the present invention. The wafer is turned over for the following damascene processing steps, so that when not turned over (for example, when the frontside devices of the wafer are facing up), the top surface of the turned wafer becomes the bottom surface of the wafer. The formed backside power distribution network supplies power to one or more frontside metal layers on the wafer using one or more TSVs. The TSVs connect one or more power and ground lines, or a backside power plane, or both, to one or more of the frontside embedded power rails or BEOL interconnect layers on the front side of the wafer.

[0085] In step 1702, the method includes selectively etching a portion of the back surface of the wafer. As previously detailed with reference to Figure 10, the back surface of the wafer is patterned and etched using a known semiconductor wafer etching process.

[0086] In step 1704, the method includes depositing a dielectric material. In various embodiments, a high-k dielectric material is deposited on a wafer, as detailed previously with reference to Figure 11.

[0087] In step 1705, the method includes depositing a first metal layer on the dielectric material, as described in detail with respect to Figure 12. The deposited first metal layer fills recesses or trenches formed during the selective etching of the wafer in step 1702 and covers the dielectric material.

[0088] In step 1706, the method includes performing CMP to remove excess first metal layer above the unetched portion of the wafer and dielectric material above the unetched portion of the wafer. The portion of the first metal material layer remaining after CMP forms power and ground lines above the dielectric material on the wafer.

[0089] In some embodiments, the height of the unetched portion remaining after CMP at least partially determines the height of the floating metal formed in a later step (i.e., step 1712). CMP is described in detail with reference to Figure 12.

[0090] In step 1708, the method includes selectively removing portions of the wafer that are not in contact with the dielectric material. Exposed portions of the wafer that are not in direct contact with the dielectric material may be removed using a known combination of a dry etching process (e.g., RIE) and one or more wet etching processes. As detailed previously with reference to Figure 13, the exposed portions of the wafer are selectively removed until the top surface of the exposed wafer etched by the combination of etching processes is at approximately the same height as the lowest bottom surface of the dielectric material (i.e., the bottom surface of the dielectric material deposited in the wafer trench formed in step 1702).

[0091] In step 1710, the method includes depositing a floating metal layer on a semiconductor structure. As previously detailed with reference to Figure 14, a layer of floating metal (i.e., metal 140) is deposited on the exposed surface of the wafer, residual dielectric material, and residual portion of the first metal layer.

[0092] In step 1712, the method includes performing CMP to remove excess floating metal. The floating metal is removed above the portion of the first metal layer and one or more portions of floating metal directly above one or more portions of the wafer other than those beneath the dielectric material, as detailed previously with reference to Figure 14. The remaining portions of floating metal (e.g., the height, length, and spacing of each remaining portion) at least partially determine the capacitance of the first backside metal layer on the wafer.

[0093] In step 1714, the method includes an optional step of recessing the remaining portion of the floating metal, as previously detailed with reference to Figure 15.

[0094] In step 1716, the method includes depositing a layer of ILD on a semiconductor structure (e.g., on floating metal, dielectric material, and exposed portions of the first metal layer), as previously detailed with reference to Figure 16. In various embodiments, vias may be formed in the ILD, and one or more additional metal layers may be formed. As is known to those skilled in the art, additional metal layers may be deposited and processed using the above process steps with some modifications to form floating metal portions on a second, third, or fourth metal layer on the wafer. These additional metal layers also become part of the back-side power distribution network on the wafer.

[0095] While the present invention has been shown and described with reference to certain exemplary embodiments, it will be understood by those skilled in the art that various modifications can be made to those embodiments in form and detail without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.

[0096] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive or limitful to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the embodiments described. The terms used herein have been selected to best describe the principles of one or more embodiments, their practical applications or technical improvements to the art found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure, One or more power and ground lines, A plurality of floating metal portions are arranged between the one or more power supply and ground lines and separated from the one or more power supply and ground lines by a dielectric material. A semiconductor structure comprising a first backside metal layer on a semiconductor wafer containing a

2. The semiconductor structure according to claim 1, wherein the capacitance of the first back metal layer is controlled by controlling the height of each of the plurality of floating metal portions in the first back metal layer.

3. The semiconductor structure according to claim 1, wherein the capacitance of the first back metal layer is controlled by controlling the distance between adjacent portions of the plurality of floating metal portions in the first back metal layer.

4. The semiconductor structure according to claim 1, wherein the capacitance density of the first back metal layer is correlated with one or more of the heights of the plurality of floating metal portions and the distances between adjacent portions of the plurality of floating metal layers.

5. The semiconductor structure according to claim 1, wherein the density of the plurality of floating metal portions in the first back metal layer affects the thermal conductivity of the first back metal layer.

6. The semiconductor structure according to claim 1, wherein the first back metal layer supplies power to at least one front metal layer of the semiconductor wafer.

7. The semiconductor structure according to claim 1, wherein the dielectric material is a high-k dielectric material.

8. The semiconductor structure according to claim 7, wherein the capacitance of the first back metal layer is correlated with that of the dielectric material.

9. The semiconductor structure according to claim 1, wherein the height of the plurality of floating metal portions is lower than the height of the one or more power supply and ground lines.

10. The semiconductor structure according to any one of claims 1 to 9, further comprising a second backside metal layer on the semiconductor wafer, which includes a power plane connected to one or more power supply and ground lines.

11. The semiconductor structure according to any one of claims 1 to 9, further comprising one or more power and ground lines, the plurality of floating metal portions, and a layer of interlayer insulating material covering the exposed surface of the dielectric material.

12. A method for forming multiple portions of a floating metal layer on one or more back metal layers of a semiconductor wafer, wherein the method is: Selective etching of the back surface of a semiconductor wafer to form a residual portion, The dielectric material is deposited conformally on the back surface of the semiconductor wafer, A first metal layer is deposited on the dielectric material, The excess portion of the first metal layer on the dielectric material is removed by first chemical mechanical polishing, Selectively removing one or more portions of the residual portion on the surface of the back surface of the semiconductor wafer that is not covered by the dielectric material, A second metal layer is deposited on the back surface of the semiconductor wafer, the dielectric material, and the exposed surface of the first metal layer. The excess portion of the second metal layer on the upper surface of the first metal layer is removed by a second chemical mechanical polishing, The method involves depositing an interlayer insulating material on the exposed surfaces of the second metal layer, the dielectric material, and the first metal layer. A method that includes this.

13. The method according to claim 12, further comprising selectively etching one or more portions of the second metal layer to recess the upper surface of one or more portions of the second metal layer below the upper surface of the first metal layer.

14. A method for forming multiple portions of a floating metal layer on one or more back metal layers of a semiconductor wafer, wherein the method is: Depositing a first metal layer on the back surface of the semiconductor wafer, Selective etching of the first metal layer, Depositing a dielectric material on the first metal layer and the exposed surface of the back surface of the semiconductor wafer, A second metal layer is deposited on the dielectric material, Removing the excess portion of the second metal layer on the dielectric material, The interlayer insulating material is deposited on the exposed surfaces of the dielectric material and the second metal layer. A method that includes this.

15. The method according to claim 14, further comprising removing the excess portion of the second metal layer on the dielectric material to recess the second metal layer and form a plurality of portions of the second metal layer for a floating metal layer.

16. Etching one or more vias into the interlayer insulating material, A third metal layer is deposited on the interlayer insulating material and in one or more vias. Selective etching of the third metal layer, The second layer of the dielectric material is deposited on the exposed surface of the interlayer insulating material and the third metal layer. A fourth metal layer is deposited on the second layer of the dielectric material, Removing the excess portion of the fourth metal layer on the second layer of the dielectric material, Depositing the second layer of the interlayer insulating material The method according to claim 14, including the method described in claim 14.

17. The method according to any one of claims 12 to 16, wherein the first metal layer forms a plurality of lines for one or more power and ground lines, and the second metal layer forms the floating metal layer.

18. A semiconductor structure having multiple portions of a floating metal layer on the back surface of a semiconductor wafer and one or more semiconductor devices on the front surface of the semiconductor wafer, wherein the semiconductor structure is Multiple portions of the floating metal layer on the back surface of the semiconductor wafer, A dielectric material on the back surface portion of the semiconductor wafer adjacent to the plurality of portions of the floating metal layer, and on the side surface portion of the plurality of portions of the floating metal layer, A plurality of power and ground lines located inside the dielectric material, wherein the upper surfaces of the plurality of power and ground lines, the dielectric material, and the plurality of parts of the floating metal layer are at the same height. The plurality of power and ground lines, the dielectric material, and the interlayer insulating material covering the upper surface of each of the plurality of portions of the floating metal layer, A silicon through-via in the semiconductor wafer brings one of the plurality of portions of the floating metal layer in the first back metal layer on the semiconductor wafer into contact with the front metal layer of the semiconductor wafer. A semiconductor structure comprising the following features.

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