Photoelectric conversion devices and equipment

Abstract

To provide a technique advantageous for improving redundancy of a photoelectric conversion device.SOLUTION: A photoelectric conversion device comprises: first and second signal lines for reading signals from a pixel array; first to fourth reading circuits; and a switching circuit that switches connection between the first and second signal lines and the first to fourth reading circuits. The first reading circuit can output signals based on signals supplied to the first reading circuit and the second reading circuit. The third reading circuit can output signals based on signals supplied to the third reading circuit and the fourth reading circuit. The switching circuit can switch settings between first settings for connecting the first signal line to the first reading circuit and connecting the second signal line to the second reading circuit, and second settings for connecting the first signal line to the third reading circuit and connecting the second signal line to the fourth reading circuit.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device and equipment.

Background Art

[0002] Photoelectric conversion devices are used in image input devices such as digital cameras. Patent Document 1 shows that by configuring a plurality of analog circuits arranged in a column processing unit in a redundant configuration, defects in the analog circuits can be remedied and the yield resulting from the defects can be improved.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the case of performing arithmetic processing such as addition and subtraction on analog signals read between a plurality of analog circuits in an analog circuit, Patent Document 1 shows switching the connection from a defective analog circuit to a normal analog circuit, but does not consider the switching of analog circuits when supplying analog signals read by a plurality of analog circuits to one analog circuit for arithmetic processing.

[0005] An object of the present invention is to provide a technique advantageous for improving the redundancy of a photoelectric conversion device.

Means for Solving the Problems

[0006] In view of the above problems, a photoelectric conversion device according to an embodiment of the present invention comprises: a pixel array having a plurality of pixels arranged to constitute a plurality of rows and a plurality of columns; a plurality of signal lines for reading signals from the pixel array; a plurality of read circuits arranged in a number greater than the plurality of signal lines; and a switching circuit for switching the connections between the plurality of signal lines and the plurality of read circuits, wherein the plurality of read circuits are a first read circuit, a second read circuit, a third read circuit 、 4th readout circuit , the 7th readout circuit and the 8th readout circuit The first readout circuit is configured to output a signal based on the signals supplied to the first readout circuit and the second readout circuit, respectively. The seventh readout circuit is positioned between the first readout circuit and the second readout circuit, and the signals supplied to the seventh readout circuit are not configured to be supplied to the first readout circuit. The third readout circuit is configured to output a signal based on the signals supplied to the third readout circuit and the fourth readout circuit, respectively, and the plurality of signal lines are the first signal line 、 Second signal line and the 5th signal line The switching circuit includes the first signal line and connects it to the first readout circuit. ,before Connect the second signal line to the second readout circuit. Furthermore, the fifth signal line is connected to the seventh readout circuit. The first setting is to connect the first signal line to the third readout circuit. ,before Connect the second signal line to the fourth readout circuit. Furthermore, the fifth signal line is connected to the eighth readout circuit. It is characterized by being configured to allow switching between a second setting and a third setting. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a technology that is advantageous for improving the redundancy of photoelectric conversion devices. [Brief explanation of the drawing]

[0008] [Figure 1] A diagram showing an example configuration of the photoelectric conversion device of this embodiment. [Figure 2] Figure 1 illustrates the default settings of the photoelectric converter. [Figure 3] Figure 1 shows an example of the configuration of the switching circuit of the photoelectric converter. [Figure 4] This diagram illustrates the calculation process between the readout circuits of the photoelectric converter shown in Figure 1. [Figure 5]Figure 1 shows an example of a redundant configuration for a photoelectric converter. [Figure 6] Figure 1 shows an example of a redundant configuration for a photoelectric converter. [Figure 7] Figure 1 shows a modified example of the photoelectric conversion device. [Figure 8] Figure 1 shows a modified example of the photoelectric conversion device. [Figure 9] Figure 1 shows a modified example of the photoelectric conversion device. [Figure 10] This figure shows an example of the configuration of a device incorporating the photoelectric converter shown in Figure 1. [Modes for carrying out the invention]

[0009] The embodiments will be described in detail below with reference to the attached drawings. Note that the following embodiments do not limit the invention as defined in the claims. While the embodiments describe multiple features, not all of these features are essential to the invention, and the features may be combined in any way. Furthermore, in the attached drawings, identical or similar configurations are given the same reference numerals, and redundant descriptions are omitted.

[0010] A photoelectric converter according to an embodiment of the present disclosure will be described with reference to Figures 1 to 9. Figure 1 is a diagram showing an example configuration of the photoelectric converter 100 of this embodiment. The photoelectric converter 100 includes a pixel array 101, a plurality of signal lines 301, a plurality of readout circuits 401, and a switching circuit 106. The photoelectric converter 100 also includes a vertical scanning circuit 102, a counter circuit 105, a horizontal scanning circuit 107, and a digital processing circuit 108.

[0011] The pixel array 101 includes a plurality of pixels 111 each including a photoelectric conversion element and outputting an analog signal so as to constitute a plurality of rows and a plurality of columns. In the configuration shown in FIG. 1, for simplicity of explanation, the pixels 111 are arranged in a 10-row × 16-column manner in the pixel array 101. However, in reality, a larger number of pixels 111 can be arranged in the pixel array 101. Further, in the configuration shown in FIG. 1, the pixels 111 arranged in odd-numbered columns and the pixels 111 arranged in even-numbered columns will be described as having sensitivities to lights of different colors. For example, it will be described that the pixels 111 arranged in odd-numbered columns include pixels 111 each having a color filter that transmits red light, and the pixels 111 arranged in even-numbered columns include pixels 111 each having a color filter that transmits blue light.

[0012] The vertical scanning circuit 102 selects the pixels 111 that output signals. More specifically, the vertical scanning circuit 102 selects the rows of the pixels 111 that output signals, and an analog signal is output from the pixels 111 of the selected row to the signal line 301.

[0013] A plurality of signal lines 301 are arranged to read signals from the pixel array 101. In the configuration shown in FIG. 1, the signal lines 301 are shared by the pixels 111 arranged in the column direction, and since the number of pixel columns is 16 columns, 16 signal lines 301 are arranged in the horizontal direction. Although not shown in FIG. 1, a constant current circuit for obtaining an output signal from the pixels 111 may be arranged on the signal lines 301. Further, a circuit for turning off the constant current circuit at a predetermined timing may be arranged on the signal lines 301 in order to reduce the power consumption of the photoelectric conversion device 100. Also, a circuit for clipping the lower limit level and the upper limit level of the voltage of the analog signal supplied to the signal lines 301 may be arranged on the signal lines 301 for the purpose of limiting the input range to the subsequent readout circuit 401. Hereinafter, when indicating a specific signal line among the plurality of signal lines 301, a suffix is added after the reference number like the signal line 301 "a", and when any one is acceptable, it is simply indicated as the signal line "301". The same applies to other components.

[0014] The readout circuit 401 is a circuit that processes the signals (analog signals) output from the pixel 111 to the signal line 301 within a column. Also, in the present embodiment, the readout circuit 401 is provided with a circuit for performing arithmetic processing on signals supplied from different columns of pixels 111. Although details will be described later, for example, the readout circuit 401f is configured to be able to output a signal based on the signal supplied to the readout circuit 401f, or the signals respectively supplied to the readout circuit 401f and the readout circuit 401h. In FIG. 1, such a combination like the readout circuit 401f and the readout circuit 401 is shown as a "pair". The readout circuit 401 includes, for example, an AD converter and a memory, and converts the analog signal supplied from the pixel 111 into a digital signal.

[0015] In the configuration shown in FIG. 1, 16 signal lines 301 are arranged, while 20 readout circuits 401 are arranged. That is, a larger number of readout circuits 401 are arranged than the number of signal lines 301. For example, among the readout circuits 401, the readout circuits 401a to 401d are arranged as redundant circuits for remedying defects when defects occur in some of the readout circuits 401. FIG. 1 shows the connection relationship between the signal lines 301 and the readout circuits 401 when a defect occurs in the readout circuit 401k and the readout circuits 401a to 401d set as redundant circuits are used.

[0016] As mentioned above, Figure 1 shows the following pairs: read circuit 401e and read circuit 401g, read circuit 401f and read circuit 401h, read circuit 401i and read circuit 401k, read circuit 401j and read circuit 401l, read circuit 401m and read circuit 401o, read circuit 401n and read circuit 401p, read circuit 401q and read circuit 401s, and read circuit 401r and read circuit 401t. Furthermore, the redundant read circuits 401a to 401d are paired as follows: read circuit 401a and read circuit 401c, and read circuit 401b and read circuit 401d. Hereafter, pairs of read circuits 401 between odd-numbered rows, such as read circuit 401e and read circuit 401g, may be referred to as odd-numbered row pairs, and pairs of read circuits 401 between even-numbered rows, such as read circuit 401f and read circuit 401h, may be referred to as even-numbered row pairs. The reason why read circuits 401 that receive signals from even-numbered pixels 111 are placed between odd-numbered row pairs is that, as mentioned above, pixels 111 sensitive to different colored light are included between odd-numbered and even-numbered rows. In other words, this is to prevent each read circuit 401 from performing calculations within the circuit based on multiple signals supplied from pixels 111 sensitive to different colored light and outputting a signal corresponding to the calculation result.

[0017] Here, the arithmetic operations performed within the circuit include addition and subtraction of analog signal voltages. For example, the read circuit 401f performs addition and subtraction operations based on the analog signals supplied to the read circuit 401f and the analog signals supplied to the read circuit 401h. The details of the configuration of the read circuit 401 will be described later, but in this embodiment, the read circuit 401 has a configuration that adds analog signals by capacitive coupling at the input position of the read circuit 401. The read circuit 401 also includes an AD converter and temporarily holds the digital data after digital conversion in the memory within the read circuit 401. The transfer timing of the digital data held in the memory within the read circuit 401 is controlled by the horizontal scanning circuit 107. The digital data held in the read circuit 401 of each column is sequentially transferred to the subsequent digital processing circuit 108. From the digital processing circuit 108 onward, additional processing and data compression may be performed on the transferred digital data.

[0018] Next, we will explain a method for improving the yield of the photoelectric converter 100 by improving redundancy through the recovery of faulty circuits in the readout circuit 401, which includes analog circuits. In some cases, the readout circuit 401 may have locally lower characteristics compared to other surrounding readout circuits 401 due to manufacturing variations in the transistors and capacitances contained within the circuit. In addition, there may be readout circuits 401 that exhibit obvious defects at the functional level due to open or short circuits in the wiring pattern caused by foreign matter contamination. Furthermore, even if the characteristics of the readout circuit 401 are within the expected range of variation, in some readout circuits 401 arranged in a row, the driving force of the transistor, which has a significant impact on the analog characteristics, may be weaker (or stronger) compared to adjacent readout circuits 401. In such cases, thin scratches visible in the obtained image may appear. If the scratches are noticeable enough during image testing, the photoelectric converter 100 cannot be considered a good product, and this will be a factor in reducing the yield.

[0019] Therefore, in this embodiment, the photoelectric converter 100 switches the connection relationship between the signal line 301 and the readout circuit 401 by the switching circuit 106 when a certain readout circuit 401 has a performance degradation and a defect such as a wire scratch is detected due to the readout circuit 401. At that time, both the readout circuit 401 with the performance degradation and the readout circuit 401 paired with the readout circuit 401 with the performance degradation are simultaneously not used, and a readout circuit 401 arranged as a redundant circuit is used.

[0020] The main point of this embodiment will be explained using Figures 1 and 2. Figure 2 shows the default configuration in which the read circuits 401a to 401d, which are set as redundant circuits, are not used. On the other hand, Figure 1 shows the redundant configuration using the read circuits 401a to 401d, which are set as redundant circuits. In Figures 1 and 2, it is assumed that among the read circuits 401a to 401t, read circuit 401k is determined not to satisfy the predetermined characteristics. In the default configuration shown in Figure 2, among the read circuits 401a to 401t, the four leftmost columns of read circuits 401a to 401d are set as redundant circuits and are not used, with none of the signal lines 301 connected to them. The arrangement of the read circuits 401 set as redundant circuits is not limited to the examples shown in Figures 1 and 2, and they can be placed in any appropriate location.

[0021] The switching circuit 106 is positioned between multiple signal lines 301 and multiple read circuits 401, and switches the connections between the multiple signal lines 301 and the multiple read circuits 401. In Figures 1 and 2, the solid lines drawn above the switching circuit 106 visually represent which of the 20 read circuits 401a to 401t the 16 signal lines are connected to. For example, in Figure 2, the signal line 301 is not connected to read circuits 401a to 401d, indicating that the four leftmost read circuits 401a to 401d (redundant circuits) are not in use. If a test is performed with the default settings shown in Figure 2 and it is confirmed that there are no problems with the characteristics of the 16 read circuits 401 being used, the photoelectric converter 100 is considered a good product and has no problems whatsoever. On the other hand, if it is determined that there is a readout circuit 401 exhibiting reduced performance in the default settings, for example, if there is a problem with the readout circuit 401 in Figure 2, the switching circuit 106 is controlled to switch to the redundant setting shown in Figure 1 and use the photoelectric converter 100. This makes it possible to improve the performance of the photoelectric converter 100.

[0022] To explain in more detail, in Figures 1 and 2, the signals supplied from signal line 301a and signal line 301c of signal line 301 are subject to arithmetic processing within the readout circuit 401. Therefore, in the default setting shown in Figure 2, the switching circuit 106 connects signal line 301a to readout circuit 401i and signal line 301 to readout circuit 401k. Here, if the test reveals line defects (luminance differences visible due to the output difference with surrounding rows) in the pixel row using readout circuit 401k, it can be said that the characteristics of readout circuit 401k are inferior to those of surrounding readout circuits 401.

[0023] Therefore, the switching circuit 106 is controlled using an external input register or the like, and the switching circuit 106 switches from the default setting to a redundant setting to compensate for the failure of the read circuit 401k as shown in Figure 1. By controlling the switching circuit 106, the connection relationship between the signal line 301 and the read circuit 401 is switched, and compensation by the redundant circuit is realized. The switching circuit 106 connects the signal line 301a to the read circuit 401e and the signal line 301c to the read circuit 401g. The switching circuit 106 controls the connection destination of the signal line 301 to sequentially shift the read circuit 401 to which the signal line 301 is connected, by not using not only the read circuit 401k with degraded characteristics but also the read circuit 401i which is paired with the read circuit 401k. As a result, the signal line 301 is connected to the read circuits 401a to 401d, which are arranged as redundant circuits in the leftmost four columns of the read circuit 401, thereby compensating for the four unused read circuits 401i to 401l. If a test is performed again with the redundant configuration shown in Figure 1 and it is confirmed that there are no problems with the image, it is possible to produce a good quality photoelectric converter 100 assuming the use of the redundant configuration.

[0024] Furthermore, as shown in Figure 2, in the default setting, the switching circuit 106 connects signal line 301b to read circuit 401j and signal line 301d to read circuit 401l. Here, read circuit 401j is positioned between the degraded read circuit 401k and the read circuit 401i that is paired with read circuit 401k. Here, as in the redundant setting shown in Figure 1, not only pairs containing a faulty read circuit 401, but also pairs containing a read circuit 401 sandwiched between pairs containing a faulty read circuit 401 may be left unused in the redundant setting. For this reason, the switching circuit 106 connects signal line 301b to read circuit 401f and signal line 301d to read circuit 401h. As shown in Figure 1, if four rows of read circuits 401i to 401l are left unused, the switching circuit 106 only needs to be configured to shift the connection destination between the signal line 301 and the read circuit 401 in units of four rows. Therefore, the control pulse for switching the connection destination between the signal line 301 and the read circuit 401 can be made common, and the size of circuits such as the switching circuit 106 can be reduced, which is an advantage. In addition, depending on the layout of the read circuits 401, the wiring pattern connecting the read circuits 401 that make up a pair including the read circuit 401 with degraded characteristics can avoid the risk of coupling with and affecting the analog signal of the read circuit 401 sandwiched between the pair including the read circuit 401 with degraded characteristics.

[0025] In the redundancy setting, the connection relationships of read circuits 401e to 401h, which are located on the side of read circuits 401a to 401d that are arranged as redundant circuits, are sequentially shifted compared to the pair containing the faulty read circuit 401k and the pair containing read circuit 401j sandwiched between the pairs containing read circuit 401k. On the other hand, the connection relationships between read circuits 401m to 401t, which are located on the opposite side of read circuits 401a to 401d compared to the pair containing the faulty read circuit 401k and the pair containing read circuit 401j sandwiched between the pairs containing read circuit 401k, and signal line 301 do not change from the default setting. It can also be said that the degraded read circuit 401k is located between read circuit 401j sandwiched between the pairs containing read circuit 401k and read circuits 401m to 401t.

[0026] Figure 3 illustrates an example of the circuit configuration of the switching circuit 106 for realizing the default and redundant settings described above. A pair of read circuits 401 that perform calculations within the circuit based on signals supplied from multiple signal lines are set together, and the connection relationship between the signal line 301 and the read circuit 401 can be controlled in units of four columns. Switching between the default and redundant settings can be controlled using an external input register. Upon receiving the value of the external input register, a decoder (not shown) in the switching circuit 106 generates control pulses in units of four columns, enabling different connections in units of four columns. With the switching circuit 106 having such a circuit configuration, if a performance degradation is observed in a certain read circuit 401, the four columns of read circuits 401 in the combination described above, including the read circuit 401 with the performance degradation, are made unused. Then, the four columns of read circuits 401 including the read circuit 401 with the performance degradation are skipped, and the connection relationship between the signal line 301 and the read circuit 401 is switched. Figure 3 shows the switching circuit 106 corresponding to the read circuits 401e to 401l. Although the switching circuits 106 corresponding to the other read circuits 401 are not described, they have a similar control configuration grouped in units of four columns.

[0027] First, in the default settings, control signals SIG-11, SIG-12, and SIG-13 are set to Lo level, and their inverse signals, control signals SIG-11B, SIG-12B, and SIG-13B, are set to Hi level. This causes switches 30 and 33 to be OFF (not conducting), and switches 31 and 34 to be ON (conducting). At the same time, control signals SIG-21, SIG-22, and SIG-23 are set to Lo level, and their inverse signals, control signals SIG-21B, SIG-22B, and SIG-23B, are set to Hi level. This causes switches 32 and 35 to be OFF. Here, in Figure 3 and Figure 4 described later, signals with a "B" appended after the reference number of the control signal indicate the inverse signal of the control signal without the appended number, and the explanation of the inverse signal state will be omitted in the following explanation.

[0028] Next, in the case of a performance degradation in the readout circuit 401k, the redundancy setting is configured by setting the control signals SIG-11 and SIG-12 to a high level, which turns on switches 30 and 33 and off switches 31 and 34. This allows the connection of the readout circuit 401 to the signal line 301 to be shifted four columns to the left.

[0029] In other words, in the default settings, the switching circuit 106 connects signal line 301a to read circuit 401i, signal line 301b to read circuit 401j, signal line 301c to read circuit 401k, and signal line 301d to read circuit 401l. Furthermore, the switching circuit 106 connects signal line 301e to read circuit 401e, signal line 301f to read circuit 401f, signal line 301g to read circuit 401g, and signal line 301d to read circuit 401h. Although not shown in Figure 3, signal line 301 is not connected to read circuits 401a to 401d, which are arranged as redundant circuits.

[0030] On the other hand, in the redundant configuration, the connection point of signal line 301 is shifted four columns to the left, and the switching circuit 106 connects signal line 301a to read circuit 401e, signal line 301b to read circuit 401f, signal line 301c to read circuit 401g, and signal line 301d to read circuit 401h. In addition, although not shown in Figure 3 (shown in Figure 1), signal lines 301e to 301h are connected to read circuits 401a to 401d, which are arranged as redundant circuits four columns to the left.

[0031] Furthermore, in the configuration shown in Figure 3, the switch 35 is turned ON by setting the control signal SIG-22 to a Hi level during the redundancy setting. As a result, the input signal levels to the read circuits 401i to 401l, which are not connected to signal line 301 and are therefore unused in the redundancy setting, are fixed to the GND level. The inputs of the read circuits 401 that are not connected to any of the signal lines 301 among the multiple read circuits 401 are connected to a fixed potential, not limited to the GND level. This suppresses the generation of through-currents and other issues that may occur due to the input being in a floating state. In addition, when the input level is fixed, it may be possible to operate the unused read circuits 401 without affecting the characteristics of the photoelectric converter 100. Here, operating the unused read circuits 401 means that, in this embodiment, the unused read circuits 401 perform AD conversion even for GND level inputs. By saving power only to the four unused read circuits 401, uneven current flow in the power lines may occur, potentially affecting nearby read circuits 401. This risk can be avoided by keeping the unused read circuits 401 operational in the redundant configuration. Similarly, in the default configuration, the inputs of read circuits 401a to 401d, which are arranged as redundant circuits, may be connected to a fixed potential. Likewise, in the default configuration, read circuits 401a to 401d may be operational.

[0032] Figure 4 is a circuit diagram showing an example configuration of the readout circuit 401. While Figure 4 shows readout circuits 401i to 401l as examples, other readout circuits 401 may have similar configurations. Furthermore, the signal input from the pixels 111 to the readout circuit 401 is shown as input lines IN1 to IN4 connecting the switching circuit 106 and the readout circuit 401.

[0033] The readout circuits 401i to 401l shown in Figure 4 are configured to output digital signals based on the analog signals supplied to each readout circuit 401. The mode in which each readout circuit 401 performs AD conversion of the signals supplied to each readout circuit 401 may be referred to as the normal mode below. On the other hand, the readout circuit 401i is configured to output digital signals based not only on the analog signals supplied to the readout circuit 401i, but also on the analog signals supplied to the readout circuit 401i and its paired readout circuit 401k. Similarly, the readout circuit 401j is configured to output digital signals based not only on the analog signals supplied to the readout circuit 401j, but also on the analog signals supplied to the readout circuit 401j and its paired readout circuit 401l. The mode in which the readout circuit 401 performs AD conversion of the signals supplied to its readout circuit 401 and its paired readout circuit 401 may be referred to as the decimation mode below. The photoelectric converter 100 (readout circuit 401) of this embodiment can be operated by switching settings between normal mode and decimation mode.

[0034] In normal mode, while the resulting image quality is high, the amount of image data is large. Therefore, in order to reduce the amount of image data, there is a need for a specification that allows switching to a mode in which the number of readout circuits that perform AD conversion is reduced, for example, by half (decimation mode). In order to maintain good image quality even in decimation mode, the readout circuit 401 reads out the signal from all rows without decimation from the pixels 111. On the other hand, Figure 4 shows an example configuration in which the readout circuits 401i and 401j perform summation processing of the analog voltage signal supplied from the pixels 111.

[0035] The read circuit 401 also includes an AD converter and memory MEM. The AD converter is, for example, a slope-type AD converter that uses a ramp wave output from a comparator COMP, a counter circuit 105, and a ramp waveform generation circuit (not shown). The AD converter compares the ramp wave with the input voltage level using the comparator COMP, counts the clock supplied by the counter circuit 105 which is synchronized with the ramp wave, and writes the count value of the time when the input voltage level crosses the ramp wave to memory MEM. The AD converter may also be a successive approximation type or a delta-sigma type AD converter.

[0036] In this embodiment, the signals supplied to read circuits 401i and 401k, respectively, and the signals supplied to read circuits 401j and 401l, respectively, are capable of being added together. Two pairs of read circuits 401 make up two sets of four columns, and the same circuit configuration is repeated for the other read circuits 401. Therefore, Figure 4 shows the four columns of read circuits 401, from 401i to 401l.

[0037] The readout circuit 401 is equipped with two types of input capacitors: input capacitor C11 and input capacitor C21. In normal mode, setting the control signal SIG-3 to a low level turns on switches 41, 42, 43, and 44, and turns off switches 45 and 46. As a result, in each readout circuit 401, the signal supplied via the input line IN is input to both input capacitor C11 and input capacitor C21. In other words, a signal input from one signal line 301 is supplied to the corresponding readout circuit 401 in that row, resulting in a closed process within that row.

[0038] On the other hand, in decimation mode, setting the control signal SIG-3 to a high level turns off switches 41, 42, 43, and 44, and turns on switches 45 and 46. As a result, the signal supplied via input line IN1 is input to the input capacitor C11 of the readout circuit 401i, and the signal supplied via input line IN3 is input to the input capacitor C21 of the readout circuit 401i. Similarly, the signal supplied via input line IN2 is input to the input capacitor C11 of the readout circuit 401j, and the signal supplied via input line IN4 is input to the input capacitor C21 of the readout circuit 401j. Consequently, the negative input of comparator COMP1 of the readout circuit 401i shows a signal that is a combination of the signals supplied via input lines IN1 and IN3, respectively. Similarly, the negative input of comparator COMP2 of the readout circuit 401j shows a signal that is a combination of the signals supplied via input lines IN2 and IN4, respectively. As a result, addition is performed in the read circuits 401i and 401j.

[0039] In this embodiment, the analog signal level appearing on the negative input side of comparator COMP is compared with a ramp wave supplied as a reference voltage to the positive input side of comparator COMP. When the signal levels on the positive and negative input sides of comparator COMP reverse, comparator COMP outputs an inverted signal, and the counter value of the time when the inverted signal was output is written to memory MEM. As a result, the analog signal supplied from pixel 111 is converted into a digital signal.

[0040] Furthermore, by changing the capacitance ratio between input capacitance C11 and input capacitance C21, it is possible to weight the signals supplied to the two readout circuits 401 in decimation mode. In other words, in the configuration shown in Figure 4, weighted addition processing is possible in readout circuits 401i and 401j. For example, if the capacitance ratio between input capacitance C11 and input capacitance C21 is set to 2:1, then in readout circuit 401i, calculation processing can be achieved such that the signal supplied via signal line IN1 has twice as much influence on the output value after AD conversion as the signal supplied via input line IN3. When performing weighted addition, switching the connection destination of the readout circuits 401 as a set makes it easier to switch between them, as input line IN1:input line IN3=2:1, maintaining a relationship where the input line IN corresponding to the left column always has a weight of "2". Therefore, switching the connection between the signal line 301 and the read circuit 401 for each pair of read circuits 401, as in the normal and redundant settings described above, may simplify the circuit design compared to switching without considering the pairs of read circuits 401.

[0041] Furthermore, in the configuration shown in Figure 4, comparators COMP3 and COMP4 of the read circuits 401k and 401l are not used in decimation mode, but comparators COMP3 and COMP4 may be used. For example, comparator COMP3 is supplied with a signal that combines the signal supplied via input line IN1 and the signal supplied via input line IN3, similar to comparator COMP1. Similarly, comparator COMP4 is supplied with a signal that combines the signal supplied via input line IN2 and the signal supplied via input line IN4, similar to comparator COMP2. In this case, a ramp waveform input with a different slope from the ramp waveform supplied to comparators COMP1 and COMP2 of the read circuits 401i and 401j is supplied to the positive input side of comparators COMP3 and COMP4. This allows simultaneous AD conversion with different AD conversion gains to be performed between read circuits 401i and 401j and read circuits 401k and 401l. Furthermore, for example, different arithmetic processing may be performed in the read circuits 401i, 401j and the read circuits 401k, 401l. For example, the comparator COMP3 of the read circuit 401k may be supplied with a signal obtained by subtracting the signal supplied via input line IN3 from the signal supplied via input line IN1. Similarly, the comparator COMP4 of the read circuit 401l may be supplied with a signal obtained by subtracting the signal supplied via input line IN4 from the signal supplied via input line IN2. It is also possible to apply this to each circuit and perform addition and subtraction A / D operations simultaneously. The read circuits 401i, 401j and 401k, 401l can be used to obtain digital data based on the added analog signal and digital data based on the subtracted analog signal.

[0042] As described above, when performing calculations using a signal supplied to another readout circuit 401, instead of only disabling the readout circuit 401 with degraded characteristics, the paired readout circuit 401 is also disabling, and the system switches to a redundant circuit. In some cases, as described above, if the characteristics of one of the paired readout circuits 401 are degraded, even if only the degraded readout circuit 401 is isolated using a switch, the effect may not be completely isolated in the case of analog circuits. If the readout circuit 401 with no degraded characteristics among the paired readout circuits 401 is used instead of being disabling, for example, in a redundant configuration, the connection destination of the connection line NET1 shown in Figure 4 is switched to a readout circuit 401 in another column using a switch, for example. However, the control pulse of the switch used to switch the connection destination to a readout circuit 401 in another column changes between a Hi level and a Lo level. Due to the coupling between the switch control pulse and the analog signal in the readout circuit 401, this change in the control pulse may affect the accuracy of the AD conversion. Furthermore, the more complex the calculation processing performed by the readout circuit 401, the more complex the control becomes in keeping one of the pair of readout circuits 401 in use and switching the other. Therefore, when transferring signals supplied between readout circuits 401 and performing calculation processing, the pair of readout circuits 401 that includes the defective readout circuit 401 with degraded characteristics is not used, and the connection destination of the signal line 301 is switched collectively. By having such a configuration, the complexity of circuit design is reduced, and a photoelectric converter 100 with excellent redundancy is realized.

[0043] In the above-described embodiment, the readout circuit 401 is arranged in a single block with one in the column direction and multiple in the row direction. However, it is not limited to this. For example, multiple readout circuits 401 may also be arranged in the column direction. In the above description, it was explained that each signal line 301 is arranged to correspond to each column of multiple pixels 111. However, for example, multiple signal lines 301 may be arranged in predetermined numbers to correspond to each column of multiple pixels 111, and signals may be read simultaneously from pixels 111 arranged in multiple rows to achieve high speed. In such a case, multiple readout circuits 401 may be arranged in both the column and row directions.

[0044] Figures 5(a) to 5(c) illustrate variations in the redundancy settings of the readout circuit 401. In the configurations shown in Figures 5(a) to 5(c), for example, a readout circuit 401 is shown arranged in a 2x20 grid to simultaneously read signals from 2x16 pixels 111. Also, as in Figure 1, pairs of readout circuits 401 related to arithmetic processing are shown. In Figures 5(a) to 5(c), readout circuits 401 filled with dots are those that are not connected to the signal line 301 and are therefore unused, and do not necessarily represent the locations of readout circuits 401 that are arranged as redundant circuits. Readout circuits 401 with diagonal lines indicate locations of readout circuits 401 that have degraded characteristics and are therefore unused.

[0045] Figure 5(a) shows an example of the default settings. The leftmost 2 rows x 4 columns of read circuits 401 are unused and assigned to redundant circuits. If no performance degradation is observed in any of the read circuits 401, there is no problem in using the photoelectric converter 100 with the default settings. Figure 5(b) shows an example of the usage pattern of read circuits 401 in the redundant settings. As described above, four read circuits 401 are unused: a pair of read circuits 401 that includes a read circuit 401 that shows performance degradation, and a pair of read circuits 401 that includes a read circuit 401 that is sandwiched between the pairs of read circuits 401 that include a read circuit 401 with performance degradation. In this case, the read circuit 401 that is located in the same row as the read circuit 401 with performance degradation and is arranged as a redundant circuit is used. An example of the switching circuit 106 that switches the connection between the signal line 301 and the read circuits 401 from the default settings to the redundant settings is as described above. Figure 5(c) shows an example of a usage pattern for the read circuit 401 in a redundant configuration, different from the usage pattern shown in Figure 5(b). In this configuration, the unused read circuits 401 in the usage pattern shown in Figure 5(b) are extended in the column direction, with all read circuits 401 from the 9th to the 12th column from the left being unused, and the redundant circuits located in the 1st to 4th columns being used.

[0046] Figures 6(a) and 6(b) illustrate variations in the redundancy setting of the read circuit 401, similar to Figures 5(a) to 5(c). In each of the embodiments described above, an example was described in which redundant circuits are arranged horizontally and the connection between the signal line 301 and the read circuit 401 is switched in the column direction by the switching circuit 106. However, it is also possible to have a configuration with redundant circuits in the vertical direction. However, when redundant circuits are arranged vertically compared to horizontally, the column layout becomes longer vertically, so this is effective only when there is sufficient space in the layout size. Even when redundant circuits are arranged vertically, as described above, instead of only disabling the read circuit 401 with degraded characteristics, both read circuits 401 in the pair of read circuits 401 related to arithmetic processing are disabling, and the setting is switched to use the read circuit 401 arranged as a redundant circuit. When redundant circuits are arranged vertically rather than horizontally, if pairs of readout circuits 401 are not simultaneously deactivated and switched, the distance between the readout circuits 401 that transfer the signal becomes longer, making it easier for noise to be superimposed on the signal. Therefore, as described above, pairs of readout circuits 401 with degraded characteristics are deactivated as a set and switched to the redundant circuit.

[0047] Figure 6(a) shows an example of the default settings. In Figure 6(a), the readout circuits 401 located in the bottom row are unused and allocated to the redundant circuit. If no performance degradation is observed in any of the readout circuits 401, there is no problem in using the photoelectric converter 100 with the default settings. Figure 6(b) shows an example of the usage pattern of the readout circuits 401 in the redundant setting. Four readout circuits 401 are unused: a pair of readout circuits 401 that includes a readout circuit 401 that shows performance degradation, and a pair of readout circuits 401 that includes a readout circuit 401 sandwiched between the pairs of readout circuits 401 that include a readout circuit 401 with performance degradation. In addition, a readout circuit 401 located in the same row as the unused readout circuits 401 is used as a redundant circuit. An example of the switching circuit 106 that switches the connection between the signal line 301 and the readout circuits 401 from the default setting to the redundant setting is as described above.

[0048] Thus, even when signals are transferred and calculations are performed between readout circuits 401, including analog circuits, a photoelectric converter 100 can be realized that achieves both high image quality and improved redundancy through the recovery of faulty circuits.

[0049] Figure 7 shows a modified example of the photoelectric converter 100 described above. In the configuration shown in Figure 7, the switching circuits 106 are arranged separately for odd-numbered and even-numbered rows of pixels 111. Switching circuit 106a corresponds to the pixels 111 arranged in the odd-numbered rows, and switching circuit 106b corresponds to the pixels 111 arranged in the even-numbered rows. Switching circuits 106a and 106b each switch the connection relationship between the signal line 301 and the readout circuit 401 using separate external input registers. The other configurations may be the same as in the embodiment described above, so their explanation will be omitted here as appropriate.

[0050] In the configuration shown in Figure 7, 18 readout circuits 401 are arranged horizontally for 16 signal lines 301. Additionally, the leftmost two columns of readout circuits 401a and 401b are configured as redundant circuits. Furthermore, in the configuration shown in Figure 7, the connection between the signal lines 301 corresponding to the odd-numbered pixels 111 of the pixel array 101 and the readout circuits 401 is controlled by switching circuit 106a. The connection between the signal lines 301 corresponding to the even-numbered pixels 111 of the pixel array 101 and the readout circuits 401 is controlled by switching circuit 106b. As mentioned above, if the pixels 111 in the odd-numbered rows and the pixels 111 in the even-numbered rows are sensitive to different colors of light, it is conceivable that it is infrequent to process signals corresponding to different colors of light. Therefore, the configuration shown in Figure 7 separates the switching circuits 106 corresponding to the odd-numbered and even-numbered rows of the pixel array 101, allowing for individual control. Furthermore, although not explicitly shown in Figure 7, the read circuits 401a and 401b, which are provided as redundant circuits, are configured to be shared between odd-numbered and even-numbered rows. In other words, both the switching circuit 106a and the switching circuit 106b are configured to allow the connection destination of the signal line 301 to be connected to the read circuit 401a and the read circuit 401b, respectively.

[0051] In Figure 7, the readout circuit 401i, indicated by the diagonal lines, exhibits a performance degradation. In the default setting of the switching circuit 106a, the signal line 301c connected to the readout circuit 401i is in an odd-numbered column. Therefore, the switching circuit 106a switches to a redundant setting, and an example is shown where readout circuits 401a and 401b, which are arranged as redundant circuits in the leftmost two columns, are used. The switching circuit 106b is left in its default setting, assuming that the performance degradation of the readout circuit 401 is not a problem. The solid lines drawn on the switching circuit 106a in Figure 7 visually represent the connection between the signal line 301 corresponding to the odd-numbered pixel 111 and the readout circuit 401. The dotted lines drawn on the switching circuit 106a indicate that the signal line 301 corresponding to the even-numbered pixel 111 is not controlled by the switching circuit 106a, and the connection does not switch. Similarly, the solid lines drawn on the switching circuit 106b visually represent the connection between the signal line 301 corresponding to the even-numbered pixels 111 and the readout circuit 401. The dotted lines drawn on the switching circuit 106b indicate that the signal line 301 corresponding to the odd-numbered pixels 111 is not controlled by the switching circuit 106b, and therefore the connection does not switch. The connection between the signal line 301 and the readout circuit 401 in the default setting is not shown, and may be similar to the configuration in Figure 2, where two of the readout circuits 401a to 401d in the leftmost four columns are removed.

[0052] The redundancy setting shown in Figure 7 will be described in more detail. If a performance degradation is observed in the readout circuit 401i, in the default setting, the switching circuit 106a connects the signal line 301a to the readout circuit 401i. In this configuration, the switching circuit 106a, which can shift the connection destination of the signal line 301 corresponding to the odd-numbered pixels 111, is controlled using an external input register. The readout circuit 401i with degraded performance and the readout circuit 401g paired with the readout circuit 401i are not used, and the readout circuits 401a and 401b, which are arranged as redundant circuits in the leftmost two columns, are used. By configuring the readout circuits 401a and 401b, which are arranged as redundant circuits, to be shareable between the switching circuit 106a and the switching circuit 106b, the number of readout circuits 401 arranged as redundant circuits can be reduced. As a result, the circuit size can be reduced compared to the embodiment shown in Figure 1, resulting in advantages such as a more favorable layout area. Furthermore, while the configuration shown in Figure 7 illustrates an example where a readout circuit 401, which is provided as a redundant circuit between switching circuit 106a and switching circuit 106b, is shared, the configuration is not limited to this. Instead of sharing a readout circuit 401 provided as a redundant circuit between switching circuit 106a and switching circuit 106b, for example, four rows of readout circuits 401 may be provided as redundant circuits. In the configuration shown in Figure 7, it is important that the connection relationship between the signal lines 301 corresponding to pixels 111 arranged in odd-numbered rows and the readout circuit 401, and the connection relationship between the signal lines 301 corresponding to pixels 111 arranged in even-numbered rows and the readout circuit 401 can be controlled independently. Even in such a configuration, it is possible to realize a photoelectric converter 100 that achieves both high image quality and improved redundancy through the recovery of faulty circuits, even when signals are transferred and calculations are performed between readout circuits 401 including analog circuits.

[0053] Figure 8 shows a modified example of the photoelectric converter 100 described above. In the configuration shown in Figure 8, the multiple signal lines 301, switching circuit 106, and multiple readout circuits 401 constitute one group, and the photoelectric converter 100 comprises multiple groups. More specifically, the photoelectric converter 100 comprises a first group comprising multiple signal lines 301, switching circuit 106a, and multiple readout circuits 401, and a second group comprising multiple signal lines 311, switching circuit 106b, and multiple readout circuits 411. In this case, a pixel array 101 is arranged between block 104a of the multiple readout circuits 401 belonging to the first group and block 104b of the multiple readout circuits 411 belonging to the second group. In addition, counter circuits 105a, 105b, horizontal scanning circuits 107a, 107b, and digital processing circuits 108a, 108b are arranged according to these groups. The configuration shown in Figure 8 has two groups, but the photoelectric converter 100 may have three or more groups. Other configurations may be the same as those shown in Figure 1 above, so the following explanation will focus on different configurations, and explanations of configurations that may be the same will be omitted as appropriate.

[0054] In the configuration shown in Figure 8, each group of read circuits 401 and 411 is equipped with redundant circuits, and redundancy can be set for each group by switching circuits 106a and 106b. In a group including signal lines 301, switching circuit 106a, and read circuits 401, 16 columns of signal lines 301 are provided. In addition, 20 read circuits 401 are provided, and the leftmost four columns of read circuits 401a to 401b are set as redundant circuits. In the example shown in Figure 8, there is a performance degradation in read circuit 401k, and the switching circuit 106a is controlled using an external input register or the like, and the setting is changed from the default setting to a redundant setting, which shows a connection in which the read circuits 401a to 401d, which are provided as redundant circuits, are used. Although not shown in Figure 8, in the default setting, the switching circuit 106a connects signal line 301a to read circuit 401i, signal line 301b to read circuit 401j, signal line 301c to read circuit 401k, and signal line 301d to read circuit 401l. On the other hand, in the redundant setting, the read circuit 401k with degraded performance and the read circuit 401i paired with read circuit 401k are not used. Also, as mentioned above, the pair containing read circuit 401j (read circuits 401j, 401l) sandwiched between pairs containing the faulty read circuit 401k is not used. The switching circuit 106a connects signal line 301a to read circuit 401e, signal line 301b to read circuit 401f, signal line 301c to read circuit 401g, and signal line 301d to read circuit 401h. Accordingly, the signal line 301 located to the left of signal line 301a in Figure 8 is connected to read circuits 401a to 401d, which are arranged as redundant circuits.

[0055] Furthermore, in a group including signal line 311, switching circuit 106b, and read circuit 411, 16 columns of signal line 311 are provided. In addition, 20 read circuits 411 are provided, with the leftmost four columns of read circuits 411a to 411b set as redundant circuits. In the example shown in Figure 8, in addition to the read circuit 401k mentioned above, there is also a performance degradation in read circuit 411e, and the connection is shown in which the switching circuit 106b is controlled and the setting is changed from the default setting to a redundant setting, thereby using the read circuits 411a to 411d which are set as redundant circuits. Although not shown in Figure 8, in the default setting, the switching circuit 106b connects signal line 311a to read circuit 411e, signal line 311b to read circuit 411f, signal line 311c to read circuit 411g, and signal line 311d to read circuit 411h. On the other hand, in the redundant configuration, the read circuit 411e with degraded performance and the read circuit 411g paired with read circuit 411e are not used. Also, as mentioned above, the pair containing read circuit 411f (read circuits 411f, 411h) which is sandwiched between pairs containing the faulty read circuit 411e is not used. The switching circuit 106b connects signal line 311a to read circuit 411a, signal line 311b to read circuit 411b, signal line 311c to read circuit 411c, and signal line 311d to read circuit 411d. In other words, in the default configuration, signal lines 311a to 311d are connected to read circuits 411a to 411b, which are configured as redundant circuits and are not connected to any of the signal lines 311.

[0056] As shown in Figure 8, when the readout circuits 401 and 411 are arranged separately on the lower and upper sides of the pixel array 101, redundant circuits are provided for each readout circuit 401 and 411, and the switching circuits 106a and 106b corresponding to each readout circuit 401 and 411 are controlled independently. As shown in Figure 8, when the readout circuits 401 and 411 are arranged on either side of the pixel array 101, the readout circuits 401 and 411 are physically separated from each other. Therefore, it is difficult to share redundant circuits between the readout circuits 401 and 411, and redundant circuits are provided for each readout circuit 401 and 411. In addition, by independently controlling the switching circuits 106a and 106b, the number of readout circuits 401 that can be salvaged increases, which can improve the yield of the photoelectric converter 100. Even in the configuration shown in Figure 8, when reading circuits 401 and 411, which include analog circuits, transfer signals between reading circuits 401 and between reading circuits 411 to perform calculations, it is possible to realize a photoelectric converter 100 that achieves both high image quality and improved redundancy through the recovery of faulty circuits.

[0057] Figure 9 shows a modified example of the photoelectric converter 100 described above. In the configuration shown in Figure 9, similar to the configuration shown in Figure 9, the photoelectric converter 100 includes a first group comprising multiple signal lines 301, a switching circuit 106a, and multiple readout circuits 401, and a second group comprising multiple signal lines 311, a switching circuit 106b, and multiple readout circuits 411. On the other hand, unlike the configuration shown in Figure 9, the block 104a of the multiple readout circuits 401 belonging to the first group and the block 104b of the multiple readout circuits 411 belonging to the second group are arranged in a row direction that intersects with the column direction in which the multiple signal lines 301 and 311 extend. Also, the counter circuit 105 is shared by both groups. Although the configuration shown in Figure 9 shows a configuration comprising two groups, the photoelectric converter 100 may have three or more groups. Other configurations may be the same as those shown in Figures 1 and 8 above; therefore, the following explanation will focus on the different configurations, and explanations of configurations that may be the same will be omitted as appropriate.

[0058] Figure 9 shows an example where 111 pixels are arranged in a 10x32 grid. Corresponding to the 32 columns of pixels, 32 signal lines 301 and 311 are provided. Additionally, 40 read circuits 401 and 411 are provided. Of the 40 read circuits 401 and 411, the 20 shown on the left side of Figure 9 belong to the first group of read circuits 401, and the 20 on the right side belong to the second group of read circuits 411. Of the read circuits 401 belonging to the first group, the leftmost four columns of read circuits 401a to 401d are provided as redundant circuits, and of the read circuits 411 belonging to the second group, the leftmost four columns of read circuits 411a to 411b are provided as redundant circuits. The switching circuit 106a switches the connection relationship between the signal lines 301 and the read circuits 401 corresponding to the 16 pixel columns on the left. The switching circuit 106b switches the connection relationship between the signal line 311 corresponding to the rightmost 16 columns of pixels and the readout circuit 411. The switching circuits 106a and 106b can each be controlled independently using external input registers or the like. Similar to the configuration shown in Figure 8, if the use of redundant circuits can be controlled individually in the first group and the second group, the number of readout circuits 401 and 411 that can be salvaged will increase, and the yield can be improved.

[0059] Digital data held in the memory MEM of the read circuit 401 belonging to the first group is read sequentially with timing control by the horizontal scanning circuit 107a. Similarly, digital data held in the memory MEM of the read circuit 411 belonging to the second group is read sequentially with timing control by the horizontal scanning circuit 107b. By arranging the horizontal scanning circuits 107a and 107b according to the group, digital data can be read independently by each. Therefore, the digital data read time can be shortened compared to the case where a single horizontal scanning circuit 107 is used to read signals from the read circuits 401 and 411. Here, when multiple horizontal scanning circuits 107 are arranged, redundant circuits may be provided for each region of the read circuits 401 and 411 scanned by each horizontal scanning circuit 107. In other words, the horizontal scanning circuits 107 may be arranged corresponding to the respective groups to which the read circuits 401 and 411 belong. For example, consider a case where no redundant circuit is set in the readout circuit 411 belonging to the second group, and the readout circuits 401a to 401d, which are the leftmost four columns of the readout circuit 401 belonging to the first group, are shared by both groups as redundant circuits. In this case, with the default settings, the digital data of the left 16 columns of pixels is transferred to the digital processing circuit 108a by the horizontal scanning circuit 107a. On the other hand, if there is a performance degradation in one of the readout circuits 411 belonging to the second group and the redundant setting described above is implemented, the digital data of the left 20 columns of pixels will be transferred to the digital processing circuit 108a by the horizontal scanning circuit 107a. Therefore, if data is not exchanged between the digital processing circuit 108a and the digital processing circuit 108b after the digital data is transferred, there is a possibility that the intended digital processing may not be possible. For this reason, it is desirable to configure the circuits so that the data of the left 16 pixel columns is always scanned by the horizontal scanning circuit 107a, and the data of the right 16 pixel columns is always scanned by the horizontal scanning circuit 107b.

[0060] Figure 9 shows an example where performance degradation was observed in two read circuits 401 and 411, read circuits 401k and 411e, and shows the connection state with redundancy settings applied. Although not shown in Figure 9, in the default setting, the switching circuit 106a connects signal line 301a to read circuit 401i, signal line 301b to read circuit 401j, signal line 301c to read circuit 401k, and signal line 301d to read circuit 401l. Also in the default setting, the switching circuit 106b connects signal line 311a to read circuit 411e, signal line 311b to read circuit 411f, signal line 311c to read circuit 411g, and signal line 311d to read circuit 411h.

[0061] On the other hand, in the redundant configuration, the read circuit 401k with degraded performance and the read circuit 401i paired with read circuit 401k are not used. Also, as mentioned above, the pair containing read circuit 401j (read circuits 401j, 401l) sandwiched between pairs containing the faulty read circuit 401k is not used. The switching circuit 106a connects signal line 301a to read circuit 401e, signal line 301b to read circuit 401f, signal line 301c to read circuit 401g, and signal line 301d to read circuit 401h. Accordingly, the signal lines 301 located to the left of signal line 301a in Figure 8 are connected to the read circuits 401a to 401d, which are configured as redundant circuits. Furthermore, in the redundant configuration, the read circuit 411e, which has degraded performance, and the read circuit 411g, which is paired with read circuit 411e, are not used. Also, as mentioned above, the pair containing read circuit 411f (read circuits 411f, 411h), which is sandwiched between pairs containing the faulty read circuit 411e, is not used. The switching circuit 106b connects signal line 311a to read circuit 411a, signal line 311b to read circuit 411b, signal line 311c to read circuit 411c, and signal line 311d to read circuit 411d. In other words, in the default configuration, signal lines 311a to 311d are connected to read circuits 411a to 411b, which are configured as redundant circuits and are not connected to any of the signal lines 311.

[0062] Even in the configuration shown in Figure 9, when signals are transferred and calculations are performed between read circuits 401 and 411, which include analog circuits, a photoelectric converter 100 can be realized that achieves both high image quality and improved redundancy through the recovery of faulty circuits. As a result, the yield of the photoelectric converter 100 can be improved.

[0063] Here, an application example of the photoelectric converter 100 of this embodiment will be described using Figure 10. Figure 10 is a schematic diagram of equipment 9191 equipped with the photoelectric converter 100. The photoelectric converter 100 is housed in a package 920, as shown in Figure 10. The package 920 may include a base on which the photoelectric converter 100 is fixed, and a lid made of glass or the like that faces the photoelectric converter 100. The package 920 may further include bonding members such as bonding wires or bumps that connect terminals provided on the base to pads provided on the photoelectric converter 100.

[0064] The device 9191 may include at least one of the following: an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 is, for example, a lens, a shutter, or a mirror. The control device 950 controls the photoelectric converter 100. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0065] The processing unit 960 processes the signal output from the photoelectric converter 100. The processing unit 960 is a semiconductor device such as a CPU or ASIC that constitutes an AFE (analog front end) or DFE (digital front end). The display device 970 is an EL display device or liquid crystal display device that displays the information (image) obtained from the photoelectric converter 100. The storage device 980 is a magnetic device or semiconductor device that stores the information (image) obtained from the photoelectric converter 100. The storage device 980 is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or a hard disk drive.

[0066] The mechanical device 990 has movable parts or propulsion parts such as motors or engines. The device 9191 displays the signals output from the photoelectric converter 100 on the display device 970 or transmits them to the outside using a communication device (not shown) provided in the device 9191. For this purpose, the device 9191 may further include a storage device 980 and a processing device 960, separate from the memory circuits and arithmetic circuits of the photoelectric converter 100. The mechanical device 990 may be controlled based on the signals output from the photoelectric converter 100.

[0067] Furthermore, the device 9191 is suitable for electronic devices such as information terminals with shooting capabilities (e.g., smartphones and wearable devices) and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). In a camera, the mechanical device 990 can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in a camera can move the photoelectric converter 100 for vibration damping.

[0068] Furthermore, the device 9191 can also be applied to on-board cameras mounted on transportation equipment such as vehicles, ships, airplanes, and industrial robots. The mechanical device 990 in transportation equipment can be used as a mobile device. As transportation equipment, the device 9191 is suitable for transporting the photoelectric converter 100 or for assisting and / or automating driving (operation) through its imaging function. The processing device 960 for assisting and / or automating driving (operation) can perform processing to operate the mechanical device 990 as a mobile device based on the information obtained from the photoelectric converter 100. The device 9191 incorporating the photoelectric converter 100 can be applied not only to transportation equipment but also to a wide range of equipment that utilizes object recognition, such as intelligent transportation systems (ITS). Alternatively, the device 9191 may be medical equipment such as endoscopes, measuring instruments such as distance sensors, analytical instruments such as electron microscopes, or office equipment such as photocopiers.

[0069] The disclosures herein include the following photoelectric conversion devices and equipment.

[0070] (Item 1) A pixel array comprising multiple pixels arranged to constitute multiple rows and multiple columns, Multiple signal lines for reading signals from the aforementioned pixel array, Multiple read circuits arranged in a number greater than the aforementioned multiple signal lines, A photoelectric converter comprising a switching circuit that switches the connection between the plurality of signal lines and the plurality of readout circuits, The plurality of read circuits include a first read circuit, a second read circuit, a third read circuit, and a fourth read circuit, wherein the first read circuit is configured to output a signal based on the signals supplied to the first read circuit and the second read circuit, respectively, and the third read circuit is configured to output a signal based on the signals supplied to the third read circuit and the fourth read circuit, respectively. The aforementioned plurality of signal lines include a first signal line and a second signal line, The photoelectric converter is characterized in that the switching circuit is configured to switch between a first setting in which the first signal line is connected to the first readout circuit and the second signal line is connected to the second readout circuit, and a second setting in which the first signal line is connected to the third readout circuit and the second signal line is connected to the fourth readout circuit.

[0071] (Item 2) The photoelectric converter according to item 1, characterized in that the switching circuit switches the setting from the first setting to the second setting when the first reading circuit does not satisfy predetermined characteristics.

[0072] (Item 3) The photoelectric converter according to item 1 or 2, characterized in that, in the first setting, none of the signal lines among the plurality of signal lines are connected to the third readout circuit and the fourth readout circuit.

[0073] (Item 4) The plurality of read circuits further include a fifth read circuit and a sixth read circuit, and the fifth read circuit is configured to output a signal based on the signals supplied to the fifth read circuit and the sixth read circuit, respectively. The aforementioned plurality of signal lines further include a third signal line and a fourth signal line, The switching circuit is, In the first setting, the third signal line is connected to the third readout circuit, and the fourth signal line is connected to the fourth readout circuit. The photoelectric converter according to item 1 or 2, characterized in that, in the second setting, the third signal line is connected to the fifth readout circuit and the fourth signal line is connected to the sixth readout circuit.

[0074] (Item 5) The plurality of read circuits further include a seventh read circuit and an eighth read circuit, the seventh read circuit being arranged between the first read circuit and the second read circuit. The aforementioned plurality of signal lines further include a fifth signal line, The photoelectric converter according to any one of items 1 to 4, characterized in that the switching circuit connects the fifth signal line to the seventh readout circuit in the first setting and connects the fifth signal line to the eighth readout circuit in the second setting.

[0075] (Item 6) The photoelectric converter according to item 5, characterized in that, in the first setting, none of the signal lines among the plurality of signal lines are connected to the eighth readout circuit.

[0076] (Item 7) The plurality of read circuits further include a ninth read circuit, The aforementioned plurality of signal lines further include a sixth signal line, The photoelectric converter according to item 5, characterized in that the switching circuit connects the sixth signal line to the eighth readout circuit in the first setting and connects the sixth signal line to the ninth readout circuit in the second setting.

[0077] (Item 8) The plurality of read circuits further include a seventh read circuit, an eighth read circuit, a tenth read circuit, and an eleventh read circuit, wherein the seventh read circuit is positioned between the first read circuit and the second read circuit and is configured to output a signal based on signals supplied to the seventh read circuit and the tenth read circuit, respectively, and the eighth read circuit is configured to output a signal based on signals supplied to the eighth read circuit and the eleventh read circuit, respectively. The aforementioned plurality of signal lines further include a fifth signal line and a seventh signal line, The switching circuit is, In the first setting, the fifth signal line is connected to the seventh readout circuit, and the seventh signal line is connected to the tenth readout circuit. A photoelectric converter according to any one of items 1 to 4, characterized in that, in the second setting, the fifth signal line is connected to the eighth readout circuit and the seventh signal line is connected to the eleventh readout circuit.

[0078] (Item 9) The plurality of read circuits further include a 12th read circuit, The aforementioned plurality of signal lines further include an eighth signal line, The second read circuit is arranged between the first read circuit and the third read circuit, the third read circuit is arranged between the second read circuit and the fourth read circuit, and the first read circuit is arranged between the twelfth read circuit and the second read circuit. The photoelectric converter according to any one of items 1 to 8, characterized in that the switching circuit connects the 8th signal line to the 12th readout circuit in the first setting and the second setting.

[0079] (Item 10) The photoelectric converter according to any one of items 1 to 9, characterized in that each signal line is arranged to correspond to each row of the plurality of pixels.

[0080] (Item 11) The photoelectric conversion device according to any one of items 1 to 9, characterized in that the plurality of signal lines are arranged in predetermined numbers to correspond to each row of the plurality of pixels.

[0081] (Item 12) The plurality of signal lines, the switching circuit, and the plurality of read circuits constitute a single group. The photoelectric conversion device according to any one of items 1 to 11, characterized in that the photoelectric conversion device comprises a plurality of groups including a first group and a second group.

[0082] (Item 13) The photoelectric conversion device according to item 12, characterized in that the pixel array is arranged between the block of the plurality of read circuits belonging to the first group and the block of the plurality of read circuits belonging to the second group.

[0083] (Item 14) The photoelectric converter according to item 12, characterized in that the blocks of the plurality of read circuits belonging to the first group and the blocks of the plurality of read circuits belonging to the second group are arranged in a row direction that intersects with the column direction in which the plurality of signal lines extend.

[0084] (Item 15) The photoelectric converter according to any one of items 1 to 14, characterized in that the input of a readout circuit that is not connected to any of the signal lines among the plurality of readout circuits is connected to a fixed potential.

[0085] (Item 16) The photoelectric converter according to any one of items 1 to 15, characterized in that the first readout circuit outputs the signal based on the signals supplied to the first readout circuit and the second readout circuit, respectively, by performing at least one of addition and subtraction processing based on the signal supplied to the first readout circuit and the signal supplied to the second readout circuit.

[0086] (Item 17) The photoelectric converter according to item 16, characterized in that the third readout circuit outputs the signal based on the signals supplied to the third readout circuit and the fourth readout circuit, respectively, by performing at least one of addition and subtraction operations based on the signal supplied to the third readout circuit and the signal supplied to the fourth readout circuit.

[0087] (Item 18) The photoelectric conversion device according to item 16 or 17, characterized in that the first readout circuit weights the signals supplied to the first readout circuit and the signals supplied to the second readout circuit.

[0088] (Item 19) The photoelectric converter according to any one of items 1 to 18, characterized in that the first readout circuit can switch between an operation to output a signal supplied to the first readout circuit and an operation to output a signal based on signals supplied to the first readout circuit and the second readout circuit, respectively.

[0089] (Item 20) The photoelectric converter according to any one of items 1 to 19, characterized in that the third readout circuit can switch between an operation to output a signal supplied to the third readout circuit and an operation to output a signal based on signals supplied to the third readout circuit and the fourth readout circuit, respectively.

[0090] (Item 21) A photoelectric converter described in any one of items 1 through 20, A processing device that processes the signal output from the aforementioned photoelectric converter, A device characterized by being equipped with the following features.

[0091] The invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, claims are attached to disclose the scope of the invention. [Explanation of Symbols]

[0092] 100: Photoelectric converter, 101: Pixel array, 106: Switching circuit, 111: Pixel, 301, 311: Signal line, 401, 411: Readout circuit

Claims

1. A pixel array comprising multiple pixels arranged to constitute multiple rows and multiple columns, Multiple signal lines for reading signals from the aforementioned pixel array, Multiple read circuits arranged in a number greater than the aforementioned multiple signal lines, A photoelectric converter comprising a switching circuit that switches the connection between the plurality of signal lines and the plurality of readout circuits, The plurality of read circuits include a first read circuit, a second read circuit, a third read circuit, a fourth read circuit, a seventh read circuit, and an eighth read circuit, wherein the first read circuit is configured to output a signal based on signals supplied to the first read circuit and the second read circuit, respectively, and the third read circuit is configured to output a signal based on signals supplied to the third read circuit and the fourth read circuit, respectively. The seventh read circuit is located between the first read circuit and the second read circuit, and the signals supplied to the seventh read circuit are not configured to be supplied to the first read circuit. The aforementioned plurality of signal lines include a first signal line, a second signal line, and a fifth signal line. The photoelectric converter is characterized in that the switching circuit is configured to switch between a first setting in which the first signal line is connected to the first readout circuit, the second signal line is connected to the second readout circuit, and the fifth signal line is connected to the seventh readout circuit, and a second setting in which the first signal line is connected to the third readout circuit, the second signal line is connected to the fourth readout circuit, and the fifth signal line is connected to the eighth readout circuit.

2. The photoelectric converter according to claim 1, characterized in that the switching circuit switches the setting from the first setting to the second setting when the first reading circuit does not satisfy predetermined characteristics.

3. The photoelectric converter according to claim 1, characterized in that, in the first setting, none of the signal lines among the plurality of signal lines are connected to the third readout circuit and the fourth readout circuit.

4. The plurality of read circuits further include a fifth read circuit and a sixth read circuit, the fifth read circuit being configured to output a signal based on the signals supplied to the fifth read circuit and the sixth read circuit, respectively. The aforementioned plurality of signal lines further include a third signal line and a fourth signal line, The switching circuit is, In the first setting, the third signal line is connected to the third readout circuit, and the fourth signal line is connected to the fourth readout circuit. The photoelectric converter according to claim 1, characterized in that, in the second setting, the third signal line is connected to the fifth readout circuit and the fourth signal line is connected to the sixth readout circuit.

5. The photoelectric converter according to claim 1, characterized in that, in the first setting, none of the signal lines among the plurality of signal lines are connected to the eighth readout circuit.

6. The plurality of read circuits further include a ninth read circuit, The aforementioned plurality of signal lines further include a sixth signal line, The photoelectric converter according to claim 1, characterized in that the switching circuit connects the sixth signal line to the eighth readout circuit in the first setting and connects the sixth signal line to the ninth readout circuit in the second setting.

7. The plurality of read circuits further include a tenth read circuit and an eleventh read circuit, the seventh read circuit is configured to output a signal based on signals supplied to the seventh read circuit and the tenth read circuit, respectively, and the eighth read circuit is configured to output a signal based on signals supplied to the eighth read circuit and the eleventh read circuit, respectively. The aforementioned plurality of signal lines further include a seventh signal line, The switching circuit is, In the first setting, the seventh signal line is connected to the tenth readout circuit, The photoelectric converter according to claim 1, characterized in that, in the second setting, the seventh signal line is connected to the eleventh readout circuit.

8. The plurality of read circuits further include a 12th read circuit, The aforementioned plurality of signal lines further include an eighth signal line, The second read circuit is arranged between the first read circuit and the third read circuit, the third read circuit is arranged between the second read circuit and the fourth read circuit, and the first read circuit is arranged between the twelfth read circuit and the second read circuit. The photoelectric converter according to claim 1, characterized in that the switching circuit connects the eighth signal line to the twelfth readout circuit in the first setting and the second setting.

9. The photoelectric conversion device according to claim 1, characterized in that each signal line is arranged to correspond to each row of the plurality of pixels.

10. The photoelectric conversion device according to claim 1, characterized in that the plurality of signal lines are arranged in predetermined numbers to correspond to each row of the plurality of pixels.

11. The plurality of signal lines, the switching circuit, and the plurality of read circuits constitute a single group. The photoelectric conversion device according to claim 1, characterized in that the photoelectric conversion device comprises a plurality of groups including a first group and a second group.

12. The photoelectric converter according to claim 11, characterized in that the pixel array is arranged between the block of the plurality of read circuits belonging to the first group and the block of the plurality of read circuits belonging to the second group.

13. The photoelectric conversion device according to claim 11, characterized in that the blocks of the plurality of read circuits belonging to the first group and the blocks of the plurality of read circuits belonging to the second group are arranged in a row direction that intersects with the column direction in which the plurality of signal lines extend.

14. The photoelectric converter according to claim 1, characterized in that the input of a readout circuit that is not connected to any of the signal lines among the plurality of readout circuits is connected to a fixed potential.

15. The photoelectric converter according to claim 1, characterized in that the first readout circuit outputs a signal based on the signals supplied to the first readout circuit and the second readout circuit, respectively, by performing at least one of an addition process and a subtraction process based on the signals supplied to the first readout circuit and the signals supplied to the second readout circuit.

16. The photoelectric converter according to claim 15, characterized in that the third readout circuit outputs the signal based on the signals supplied to the third readout circuit and the fourth readout circuit, respectively, by performing at least one of addition and subtraction processing based on the signal supplied to the third readout circuit and the signal supplied to the fourth readout circuit.

17. The photoelectric conversion device according to claim 15, characterized in that the first readout circuit weights the signals supplied to the first readout circuit and the signals supplied to the second readout circuit.

18. The photoelectric converter according to claim 1, characterized in that the first readout circuit can switch between an operation to output a signal supplied to the first readout circuit and an operation to output a signal based on signals supplied to the first readout circuit and the second readout circuit, respectively.

19. The photoelectric converter according to claim 1, characterized in that the third readout circuit can switch between an operation to output a signal supplied to the third readout circuit and an operation to output a signal based on the signals supplied to the third readout circuit and the fourth readout circuit, respectively.

20. The photoelectric converter according to claim 18, characterized in that the third readout circuit can switch between an operation to output a signal supplied to the third readout circuit and an operation to output a signal based on signals supplied to the third readout circuit and the fourth readout circuit, respectively.

21. The photoelectric conversion device according to claim 1, characterized in that the first readout circuit and the seventh readout circuit are supplied with signals from pixels among the plurality of pixels that are sensitive to light of different colors from each other.

22. A photoelectric conversion device according to any one of claims 1 to 21, A processing device that processes the signal output from the aforementioned photoelectric converter, A device characterized by being equipped with the following features.

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