Semiconductor device and method for manufacturing a semiconductor device

Abstract

The present disclosure relates to a semiconductor device. The semiconductor device comprises a semiconductor substrate, a channel layer provided above the semiconductor substrate and formed from a first nitride semiconductor, a barrier layer provided above the channel layer and formed from a second nitride semiconductor having a band gap larger than the band gap of the first nitride semiconductor, a metal film formed selectively above the barrier layer, a composite layer provided in contact with the metal film and having at least a conductive material and an insulating material, and an insulating film formed in a region above the barrier layer where the metal film or the composite layer is not formed.

Description

【Technical Field】 【0001】 The present disclosure relates to a semiconductor device, and more particularly to a heterojunction field-effect semiconductor device composed of a semiconductor containing a nitride. 【Background Art】 【0002】 As an example of a conventional heterojunction field-effect semiconductor device composed of a semiconductor containing a nitride (nitride semiconductor), for example, a heterojunction field-effect transistor disclosed in Patent Document 1 can be cited. The heterojunction field-effect transistor has an AlGaN / GaN heterojunction having a GaN (gallium nitride) channel layer and an AlGaN (aluminum gallium nitride) barrier layer. 【0003】 An ohmic electrode composed of a metal film such as Ti (titanium), Al (aluminum), Mo (molybdenum), or a metal multilayer film or alloy film containing these is provided on the barrier layer, and constitutes the drain electrode and source electrode of the transistor. 【0004】 These ohmic electrodes are covered with an insulating film composed of SiN (silicon nitride) or SiO2 (silicon oxide), and the insulating film is opened to form a contact hole so that a part of the upper surface is exposed, and is connected to a wiring for connection to the outside. 【0005】 Generally, an ohmic electrode is formed by depositing a metal film (including a metal multilayer film and an alloy film) on a semiconductor layer, then performing heat treatment, and then depositing a SiN film so as to cover the heat-treated metal film. 【Prior Art Documents】 【Patent Documents】 【0006】 【Patent Document 1】 Japanese Patent Application Laid-Open No. 2014-179389 【Summary of the Invention】 【Problems to be Solved by the Invention】 【0007】 In ohmic electrodes such as source electrodes, drain electrodes, and cathode electrodes used in semiconductor devices such as transistors and diodes formed on a semiconductor layer containing an AlGaN / GaN heterojunction, it is desirable that the resistance be as low as possible to improve the performance of the semiconductor device. 【0008】 To reduce resistance, ohmic electrodes are typically constructed by depositing a metal film on a semiconductor layer and then heat-treating it at temperatures exceeding 600°C to alloy it with the semiconductor layer. Subsequently, a protective surface film, such as SiN, is formed to protect the surface of the semiconductor layer, simultaneously covering the metal film. However, if this high-temperature heat treatment is performed with the metal film exposed, a portion of the metal film may evaporate into areas other than those forming the electrode, reattach, and remain between the semiconductor layer and the protective film, potentially negatively impacting the properties of the semiconductor device. 【0009】 On the other hand, in order to prevent the evaporation and re-adhesion of the metal, a capping film made of SiN or other material with low reactivity to the metal film is sometimes deposited over the metal film, followed by high-temperature heat treatment, and then the capping film is removed. However, this method adds an extra step of depositing and then removing the capping film, which can complicate the manufacturing process and increase manufacturing costs. 【0010】 This disclosure is made to solve the above-mentioned problems and aims to provide a semiconductor device that does not degrade the characteristics of the semiconductor device and suppresses the complexity of the manufacturing process. [Means for solving the problem] 【0011】 The semiconductor device according to this disclosure comprises a semiconductor substrate, a channel layer made of a first nitride semiconductor provided on the semiconductor substrate, a barrier layer made of a second nitride semiconductor provided on the channel layer and having a band gap larger than the band gap of the first nitride semiconductor, a metal film selectively formed above the barrier layer, a composite layer provided in contact with the metal film and having at least a conductive material and an insulating material, and an insulating film formed in a region on the barrier layer where the metal film and the composite layer are not formed, wherein the sheet resistance due to the two-dimensional electron gas generated at the interface between the channel layer and the barrier layer in the region of the barrier layer in contact with the insulating film is 1 kΩ / sq or less. The composite layer is provided so as to cover a portion of the upper surface of the metal film opposite to the barrier layer, the side surface of the metal film, and the lower surface of the metal film opposite to the upper surface, and the wiring layer is provided so as to be in contact with the area of ​​the upper surface of the metal film where the composite layer is not provided. ru. [Effects of the Invention] 【0012】 The semiconductor device described herein makes it possible to obtain a semiconductor device that does not degrade the characteristics of the semiconductor device and suppresses the complexity of the manufacturing process. [Brief explanation of the drawing] 【0013】 [Figure 1] This is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 1 of this disclosure. [Figure 2] This figure schematically shows the current flow in the semiconductor device of Embodiment 1 according to the present disclosure. [Figure 3] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1 of this disclosure. [Figure 4] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1 of this disclosure. [Figure 5] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1 of this disclosure. [Figure 6] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1 of this disclosure. [Figure 7] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1 of this disclosure. [Figure 8]It is a cross-sectional view showing the configuration of the semiconductor device of Embodiment 2 according to the present disclosure. [Figure 9] It is a cross-sectional view showing the manufacturing method of the semiconductor device of Embodiment 2 according to the present disclosure. [Figure 10] It is a cross-sectional view showing the configuration of the semiconductor device of Embodiment 3 according to the present disclosure. [Figure 11] It is a cross-sectional view showing the manufacturing method of the semiconductor device of Embodiment 3 according to the present disclosure. [Figure 12] It is a cross-sectional view showing the manufacturing method of the semiconductor device of Embodiment 3 according to the present disclosure. [Figure 13] It is a cross-sectional view showing the manufacturing method of the semiconductor device of Embodiment 3 according to the present disclosure. [Figure 14] It is a cross-sectional view showing the manufacturing method of the semiconductor device of Embodiment 3 according to the present disclosure. [Figure 15] It is a cross-sectional view showing the manufacturing method of the semiconductor device of Embodiment 3 according to the present disclosure. [Figure 16] It is a cross-sectional view showing the manufacturing method of the semiconductor device of Embodiment 3 according to the present disclosure. [Figure 17] It is a cross-sectional view showing the configuration of the semiconductor device of Embodiment 4 according to the present disclosure. [Figure 18] It is a cross-sectional view showing the manufacturing method of the semiconductor device of Embodiment 4 according to the present disclosure. [Figure 19] It is a cross-sectional view showing the configuration of the semiconductor device of Embodiment 5 according to the present disclosure. [Figure 20] It is a cross-sectional view showing the manufacturing method of the semiconductor device of Embodiment 5 according to the present disclosure. [Figure 21] It is a cross-sectional view showing the manufacturing method of the semiconductor device of Embodiment 5 according to the present disclosure. [Figure 22] It is a cross-sectional view showing the manufacturing method of the semiconductor device of Embodiment 5 according to the present disclosure. [Figure 23] It is a cross-sectional view showing the manufacturing method of the semiconductor device of Embodiment 5 according to the present disclosure. [Figure 24] It is a cross-sectional view showing the manufacturing method of the semiconductor device of Embodiment 5 according to the present disclosure. [Figure 25]This is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 5 of the present disclosure. [Figure 26] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 5 of the present disclosure. [Figure 27] This is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 6 of this disclosure. [Figure 28] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 6 of the present disclosure. [Figure 29] This is a cross-sectional view showing the semiconductor device of Embodiment 7 according to this disclosure in a state in which the metal film and insulating film have not been formed. [Figure 30] This is a schematic cross-sectional view showing the 2DEG induced at the AlGaN / GaN interface of the semiconductor device according to Embodiment 7 of this disclosure. [Figure 31] This is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 9 of this disclosure. [Figure 32] This is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 10 of this disclosure. [Figure 33] This is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 11 of this disclosure. [Figure 34] This is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 12 of this disclosure. [Modes for carrying out the invention] 【0014】 <Embodiment 1> <Device configuration> Figure 1 is a cross-sectional view showing the configuration of the semiconductor device 100 according to Embodiment 1 of the present disclosure. For convenience, Figure 1 shows only the main electrode portion, which is part of a heterojunction field-effect transistor, for example. 【0015】 As shown in Figure 1, the semiconductor device 100 has a semiconductor substrate 1 made of, for example, silicon carbide (SiC), on which a channel layer 3 made of GaN (first nitride semiconductor) is stacked via a buffer layer 2 made of AlN (aluminum nitride). A barrier layer 4 made of AlGaN (second nitride semiconductor) is formed on the channel layer 3, forming a heterojunction with the channel layer 3. By using such nitride semiconductors, a practical heterojunction field-effect transistor can be obtained. Note that the AlGaN constituting the barrier layer 4 has a larger band gap than the GaN constituting the channel layer 3. 【0016】 A metal film 5, which constitutes the drain electrode and source electrode, is selectively provided on the barrier layer 4, and a portion of the side and top surfaces of the metal film 5 is covered with a composite layer 8 of metal and an insulator. An insulating film 6, such as SiO2 or SiN, is provided in the areas of the barrier layer 4 other than the areas where the composite layer 8 and the metal film 5 are formed. 【0017】 The composite layer 8 on the upper surface of the metal film 5 is provided with contact holes CH such that a portion of the upper surface of the metal film 5 is exposed, and a wiring layer 7 is provided so as to be in contact with the metal film 5 through the contact holes CH. 【0018】 The composite layer 8 is, for example, a silicide layer formed by the reaction of the metal film 5 with SiO2, or a silicide layer formed by the reaction of the metal film 5 with SiN, and has a conductive portion with lower resistance than the metal film 5. The composite layer 8 is not limited to a silicide layer; for example, any layer that is conductive, formed by combining a conductive material and an insulating material through heat treatment at 600°C or higher, can be used. 【0019】 Figure 2 schematically shows the current flowing from the wiring layer 7 to the channel layer 3. As shown in Figure 2, the current flowing from the wiring layer 7 to the channel layer 3 passes through two paths: current path C1, which flows from the wiring layer 7 to the channel layer 3 via the metal film 5, and current path C2, which flows from the wiring layer 7 to the channel layer 3 via the composite layer 8. This reduces the contact resistance. 【0020】 As an example of contact resistance, if the insulating film 6 is made of SiO2 and the Al composition and thickness of the AlGaN barrier layer 4 are 26% and 15 nm respectively, the contact resistance will be 0.6 Ω mm to 0.7 Ω mm. From the above values, it can be predicted that reducing the Al composition and thickness of the barrier layer 4 will increase the contact resistance. 【0021】 Such a structure in which a metal film 5 is covered with a composite layer 8 can be obtained by forming the metal film 5 on a barrier layer 4, depositing an insulating film 6 to cover the barrier layer 4 and the metal film 5, and then performing heat treatment at a high temperature of, for example, 600°C or higher. This causes the metal film 5 to alloy with the barrier layer 4 to form an ohmic electrode, and the metal film 5 and the insulating film 6 to react to form a silicide layer. In this case, the insulating film 6 on the barrier layer 4 functions as a protective film that protects the semiconductor layer below the barrier layer 4, and prevents evaporation of the metal during high-temperature heat treatment and re-adhesion to the barrier layer 4 without adding any new processes. 【0022】 <Manufacturing method> Next, the manufacturing method of the semiconductor device 100 will be explained using Figures 3 to 7, which sequentially show the manufacturing process. In Figures 3 to 7, components identical to those of the semiconductor device 100 shown in Figure 1 are denoted by the same reference numerals, and redundant explanations are omitted. 【0023】 First, in the process shown in Figure 3, a buffer layer 2 composed of AlN, a channel layer 3 composed of GaN, and a barrier layer 4 composed of AlGaN are grown in that order on a SiC semiconductor substrate 1 using an epitaxial growth method such as MOCVD (metal organic chemical vapor deposition) or MBE (molecular beam epitaxy). Next, a metal film 5 is formed in the desired region using a vapor deposition and lift-off method. The metal film 5 can be a single layer film of Ti, Al, Ni (nickel), Au (gold), Mo, etc., or a multilayer film of these materials. 【0024】 Next, in the process shown in Figure 4, an insulating film 6 is deposited on the barrier layer 4 so as to cover the metal film 5, for example by plasma CVD. For example, SiO2 or SiN can be formed as the insulating film 6. Note that the method for forming the insulating film 6 is not limited to plasma CVD; thermal CVD and sputtering methods can also be used. 【0025】 Next, in the process shown in Figure 5, heat treatment is performed at a temperature of 500°C to 900°C, more preferably 800°C to 850°C, using a method such as RTA (Rapid Thermal Annealing), to react the portion where the metal film 5 and the insulating film 6 are in contact, forming a silicide layer to create a composite layer 8. The metal film 5 is then covered with the composite layer 8, and the metal film 5 is alloyed with the barrier layer 4 to form an ohmic electrode. 【0026】 Next, in the process shown in Figure 6, for example, using a resist material as a mask, the composite layer 8 in the region where the wiring layer 7 is to be formed is removed using a dry etching method, and a contact hole CH is formed on the bottom surface where the upper surface of the metal film 5 is exposed. 【0027】 Next, in the process shown in Figure 7, a resist mask RM is formed on the composite layer 8 and insulating film 6, with openings OP in the areas where the wiring layer 7 is to be formed. Then, a single layer film of Ti, Al, Ni, Au, etc., or a multilayer film thereof, is formed on the resist mask RM and within the openings OP by deposition, and the wiring layer 7 is formed by removing the resist mask RM using the lift-off method, thereby obtaining the semiconductor device 100 shown in Figure 1. 【0028】 <Embodiment 2> <Device configuration> Figure 8 is a cross-sectional view showing the configuration of the semiconductor device 200 according to Embodiment 2 of this disclosure. In Figure 8, components identical to those of the semiconductor device 100 described using Figure 1 are denoted by the same reference numerals, and redundant explanations are omitted. 【0029】 As shown in Figure 8, the semiconductor device 200 has a metal film 5 covered by a composite layer 8, and an insulating film 6 such as SiO2 or SiN is provided in the area on the barrier layer 4 other than the area where the composite layer 8 and the metal film 5 are formed. 【0030】 A wiring layer 7 is selectively provided on the upper surface of the composite layer 8. The composite layer 8 is, for example, a silicide layer formed by the reaction of a metal film 5 and SiO2, or a silicide layer formed by the reaction of a metal film 5 and SiN, and has a conductive portion with lower resistance than the metal film 5. As a result, the current flowing to the channel layer 3 through the wiring layer 7 passes through two paths: a current path from the wiring layer 7 to the channel layer 3 via the composite layer 8 and the metal film 5, and a current path from the wiring layer 7 to the channel layer 3 via the composite layer 8, thereby reducing contact resistance. 【0031】 The insulating film 6 on the barrier layer 4, provided to obtain a structure in which such a metal film 5 is covered by a composite layer 8, functions as a protective film that protects the semiconductor layer below the barrier layer 4 during heat treatment, and can prevent the evaporation of the metal and its re-adhesion to the barrier layer 4 during high-temperature heat treatment without adding any new processes. 【0032】 Furthermore, since the wiring layer 7 is provided in contact with the upper surface of the composite layer 8, there is no need to provide contact holes in the composite layer 8, thus simplifying the manufacturing process. 【0033】 <Manufacturing method> Next, the manufacturing method of the semiconductor device 200 will be explained using Figure 9, which shows the manufacturing process. Up to the steps shown in Figure 9, the process is the same as that shown in Figures 3 to 5, which were used to explain the manufacturing method of the semiconductor device 100 in Embodiment 1. The metal film 5 and the insulating film 6 are reacted using the RTA method or the like to form a silicide layer to form a composite layer 8, the metal film 5 is covered with the composite layer 8, and the metal film 5 is alloyed with the barrier layer 4 to form an ohmic electrode. 【0034】 Subsequently, in the process shown in Figure 9, a resist mask RM is formed on the composite layer 8 and insulating film 6, with openings OP in the areas where the wiring layer 7 is to be formed. Then, a single layer film of Ti, Al, Ni, Au, etc., or a multilayer film thereof is formed on the resist mask RM and within the openings OP by vapor deposition, and the wiring layer 7 is formed by removing the resist mask RM using the lift-off method, thereby obtaining the semiconductor device 200 shown in Figure 8. 【0035】 <Embodiment 3> <Device configuration> Figure 10 is a cross-sectional view showing the configuration of the semiconductor device 300 according to Embodiment 3 of the present disclosure. In Figure 10, components identical to those of the semiconductor device 100 described using Figure 1 are denoted by the same reference numerals, and redundant explanations are omitted. 【0036】 As shown in Figure 10, the semiconductor device 300 has a composite layer 8 covering the top and sides of the metal film 5, and a composite layer 8 is also provided between the bottom surface of the metal film 5 and the barrier layer 4. An insulating film 6, such as SiO2 or SiN, is provided in the area on the barrier layer 4 other than the area where the composite layer 8 and the metal film 5 are formed. 【0037】 The composite layer 8 on the upper surface of the metal film 5 is provided with contact holes CH such that a portion of the upper surface of the metal film 5 is exposed, and a wiring layer 7 is provided so as to be in contact with the metal film 5 through the contact holes CH. 【0038】 The composite layer 8 is, for example, a silicide layer formed by the reaction of the metal film 5 with SiO2, or a silicide layer formed by the reaction of the metal film 5 with SiN, and has a conductive portion with lower resistance than the metal film 5. Therefore, the current flowing from the wiring layer 7 to the channel layer 3 passes through two paths: a current path from the wiring layer 7 through the metal film 5 and the lower composite layer 8 to the channel layer 3, and a current path from the wiring layer 7 through the composite layer 8 to the channel layer 3, resulting in a reduction in contact resistance. Furthermore, the lower composite layer 8 and the barrier layer 4 are in contact, allowing for a further reduction in contact resistance compared to the semiconductor device 100 of Embodiment 1. 【0039】 Furthermore, the insulating film 6 on the barrier layer 4, which is provided to obtain a structure in which such a metal film 5 is covered with a composite layer 8, functions as a protective film that protects the semiconductor layer below the barrier layer 4 during heat treatment, and can prevent the evaporation of the metal and its re-adhesion to the barrier layer 4 during high-temperature heat treatment without adding any new processes. 【0040】 <Manufacturing method> Next, the manufacturing method for the semiconductor device 300 will be explained using Figures 11 to 16, which show the manufacturing process in order. 【0041】 First, in the process shown in Figure 11, a buffer layer 2 made of AlN, a channel layer 3 made of GaN, and a barrier layer 4 made of AlGaN are grown in that order on a SiC semiconductor substrate 1 using an epitaxial growth method such as MOCVD or MBE. Next, an insulating film 61 (first insulating film) is deposited on the barrier layer 4, for example, by plasma CVD. For the insulating film 61, for example, SiO2 or SiN can be formed. 【0042】 Next, in the process shown in Figure 12, a metal film 5 is formed on a desired region on the insulating film 61 using vapor deposition and lift-off methods. The metal film 5 can be a single layer film of Ti, Al, Ni, Au, Mo, etc., or a multilayer film of these materials. 【0043】 Next, in the process shown in Figure 13, an insulating film 62 (second insulating film) is deposited, for example, by plasma CVD, so as to cover the metal film 5 and insulating film 61. The insulating film 62 can be made of the same SiO2 or SiN as the insulating film 61. Note that the method for forming insulating films 61 and 62 is not limited to plasma CVD; thermal CVD and sputtering methods can also be used. 【0044】 Next, in the process shown in Figure 14, heat treatment is performed at a temperature of 500°C to 900°C using methods such as RTA to react the parts in contact with the metal film 5 and the insulating film 6 to form a silicide layer, which is then used to form a composite layer 8. The entire metal film 5 is covered with the composite layer 8, and the metal film 5, composite layer 8, and barrier layer 4 are alloyed with each other to form an ohmic electrode. Note that in Figure 14, insulating films 61 and 62 are shown together as an insulating film 6. 【0045】 Next, in the process shown in Figure 15, for example, using a resist material as a mask, the composite layer 8 in the region where the wiring layer 7 is to be formed is removed using a dry etching method, and a contact hole CH is formed on the bottom surface where the upper surface of the metal film 5 is exposed. 【0046】 Next, in the process shown in Figure 16, a resist mask RM is formed on the composite layer 8 and insulating film 6, with openings OP in the areas where the wiring layer 7 is to be formed. Then, a single layer film of Ti, Al, Ni, Au, etc., or a multilayer film thereof, is formed on the resist mask RM and within the openings OP by deposition, and the wiring layer 7 is formed by removing the resist mask RM using the lift-off method, thereby obtaining the semiconductor device 300 shown in Figure 10. 【0047】 <Embodiment 4> <Device configuration> Figure 17 is a cross-sectional view showing the configuration of the semiconductor device 400 according to Embodiment 4 of the present disclosure. In Figure 17, components identical to those of the semiconductor device 100 described using Figure 1 are denoted by the same reference numerals, and redundant explanations are omitted. 【0048】 As shown in Figure 17, the semiconductor device 400 has a composite layer 8 covering the top and sides of the metal film 5, and a composite layer 8 is also provided between the bottom surface of the metal film 5 and the barrier layer 4. An insulating film 6, such as SiO2 or SiN, is provided in the area on the barrier layer 4 other than the area where the composite layer 8 and the metal film 5 are formed. 【0049】 A wiring layer 7 is selectively provided on the upper surface of the composite layer 8. The composite layer 8 is, for example, a silicide layer formed by the reaction of a metal film 5 and SiO2, or a silicide layer formed by the reaction of a metal film 5 and SiN, and has a conductive portion with lower resistance than the metal film 5. As a result, the current flowing to the channel layer 3 through the wiring layer 7 passes through two paths: a current path from the wiring layer 7 through the upper composite layer 8, the metal film 5, and the lower composite layer 8 to the channel layer 3, and a current path from the wiring layer 7 through the composite layer 8 to the channel layer 3, resulting in a reduction in contact resistance. 【0050】 Furthermore, the insulating film 6 on the barrier layer 4, which is provided to obtain a structure in which such a metal film 5 is covered with a composite layer 8, functions as a protective film that protects the semiconductor layer below the barrier layer 4 during heat treatment, and can prevent the evaporation of the metal and its re-adhesion to the barrier layer 4 during high-temperature heat treatment without adding any new processes. 【0051】 Furthermore, since the wiring layer 7 is provided in contact with the upper surface of the composite layer 8, there is no need to provide contact holes in the composite layer 8, thus simplifying the manufacturing process. 【0052】 <Manufacturing method> Next, the manufacturing method of the semiconductor device 400 will be explained using Figure 18, which shows the manufacturing process. The steps up to the process shown in Figure 18 are the same as those shown in Figures 11 to 14 used to explain the manufacturing method of the semiconductor device 300 in Embodiment 3. The metal film 5 and the insulating film 6 are reacted at the point of contact using the RTA method or the like to form a silicide layer to form a composite layer 8, the entire metal film 5 is covered with the composite layer 8, and the metal film 5, composite layer 8 and barrier layer 4 are alloyed with each other to form an ohmic electrode. 【0053】 Subsequently, in the process shown in Figure 18, a resist mask RM is formed on the composite layer 8 and insulating film 6, with openings OP in the areas where the wiring layer 7 is to be formed. Then, a single layer film of Ti, Al, Ni, Au, etc., or a multilayer film thereof, is formed on the resist mask RM and within the openings OP by vapor deposition, and the wiring layer 7 is formed by removing the resist mask RM using the lift-off method, thereby obtaining the semiconductor device 400 shown in Figure 17. 【0054】 <Embodiment 5> <Device configuration> Figure 19 is a cross-sectional view showing the configuration of the semiconductor device 500 according to Embodiment 5 of the present disclosure. In Figure 19, components identical to those of the semiconductor device 100 described using Figure 1 are denoted by the same reference numerals, and redundant explanations are omitted. 【0055】 As shown in Figure 19, the semiconductor device 500 has a composite layer 8 covering the top and sides of the metal film 5, and a composite layer 8 is also provided between a part of the bottom surface of the metal film 5 and the barrier layer 4. An insulating film 6 such as SiO2 or SiN is provided in the area on the barrier layer 4 other than the area where the composite layer 8 and the metal film 5 are formed. 【0056】 The composite layer 8 on the upper surface of the metal film 5 is provided with contact holes CH such that a portion of the upper surface of the metal film 5 is exposed, and a wiring layer 7 is provided so as to be in contact with the metal film 5 through the contact holes CH. 【0057】 The composite layer 8 is, for example, a silicide layer formed by the reaction of the metal film 5 with SiO2, or a silicide layer formed by the reaction of the metal film 5 with SiN, and has a conductive portion with lower resistance than the metal film 5. Therefore, the current flowing from the wiring layer 7 to the channel layer 3 passes through two paths: a current path from the wiring layer 7 to the channel layer 3 via the metal film 5, and a current path from the wiring layer 7 to the channel layer 3 via the composite layer 8, resulting in a reduction in contact resistance. Furthermore, the metal film 5 and the barrier layer 4 are in contact, and by heat treatment at a high temperature of, for example, 600°C or higher to form the composite layer 8, the metal film 5 alloys with the barrier layer 4 to form an ohmic electrode, further reducing contact resistance. 【0058】 Furthermore, in this case, the insulating film 6 on the barrier layer 4 functions as a protective film that protects the semiconductor layers below the barrier layer 4, preventing the evaporation of metal during high-temperature heat treatment and its re-adhesion to the barrier layer 4 without adding any new processes. 【0059】 <Manufacturing method> Next, the manufacturing method of the semiconductor device 500 will be explained using Figures 20 to 26, which show the manufacturing process in order. 【0060】 First, in the process shown in Figure 20, a buffer layer 2 made of AlN, a channel layer 3 made of GaN, and a barrier layer 4 made of AlGaN are grown in that order on a SiC semiconductor substrate 1 using an epitaxial growth method such as MOCVD or MBE. Next, an insulating film 61 is deposited on the barrier layer 4, for example, by plasma CVD. For the insulating film 61, for example, SiO2 or SiN can be formed. 【0061】 Next, in the process shown in Figure 21, for example, using a resist material as a mask, the insulating film 61 in the region where the metal film 5 is to be formed is removed using a dry etching method, and a contact hole CH1 is formed on the bottom surface where the upper surface of the barrier layer 4 is exposed. 【0062】 Next, in the process shown in Figure 22, a metal film 5 is formed on a desired region of the insulating film 61, including the contact hole CH1, using vapor deposition and lift-off methods. The metal film 5 can be a single layer film of Ti, Al, Ni, Au, Mo, etc., or a multilayer film of these materials. 【0063】 Next, in the process shown in Figure 23, an insulating film 62 is deposited, for example, by plasma CVD, so as to cover the metal film 5 and the insulating film 61. The insulating film 62 can be made of the same SiO2 or SiN as the insulating film 61. Note that the method for forming the insulating films 61 and 62 is not limited to plasma CVD; thermal CVD and sputtering methods can also be used. 【0064】 Next, in the process shown in Figure 24, heat treatment is performed at a temperature of 500°C to 900°C using methods such as RTA to react the parts in contact with the metal film 5 and the insulating film 6 to form a silicide layer, which is then used to form a composite layer 8. The metal film 5 is then covered with the composite layer 8, and the metal film 5, composite layer 8, and barrier layer 4 are alloyed with each other to form an ohmic electrode. At this time, a composite layer 8 is also formed between a part of the lower surface of the metal film 5 and the barrier layer 4. Note that in Figure 24, insulating films 61 and 62 are shown together as an insulating film 6. 【0065】 Next, in the process shown in Figure 25, for example, using a resist material as a mask, the composite layer 8 in the region where the wiring layer 7 is to be formed is removed using a dry etching method, and a contact hole CH is formed on the bottom surface where the upper surface of the metal film 5 is exposed. 【0066】 Next, in the process shown in Figure 26, a resist mask RM is formed on the composite layer 8 and insulating film 6, with openings OP in the areas where the wiring layer 7 is to be formed. Then, a single layer film of Ti, Al, Ni, Au, etc., or a multilayer film thereof is formed on the resist mask RM and within the openings OP by vapor deposition, and the wiring layer 7 is formed by removing the resist mask RM using the lift-off method, thereby obtaining the semiconductor device 500 shown in Figure 19. 【0067】 <Embodiment 6> <Device configuration> Figure 27 is a cross-sectional view showing the configuration of the semiconductor device 600 according to Embodiment 6 of the present disclosure. In Figure 27, components identical to those of the semiconductor device 100 described using Figure 1 are denoted by the same reference numerals, and redundant explanations are omitted. 【0068】 As shown in Figure 27, the semiconductor device 600 has a composite layer 8 covering the top and sides of the metal film 5, and a composite layer 8 is also provided between a part of the bottom surface of the metal film 5 and the barrier layer 4. An insulating film 6 such as SiO2 or SiN is provided in the area on the barrier layer 4 other than the area where the composite layer 8 and the metal film 5 are formed. 【0069】 A wiring layer 7 is selectively provided on the upper surface of the composite layer 8. The composite layer 8 is, for example, a silicide layer formed by the reaction of a metal film 5 and SiO2, or a silicide layer formed by the reaction of a metal film 5 and SiN, and has a conductive portion with lower resistance than the metal film 5. As a result, the current flowing to the channel layer 3 through the wiring layer 7 passes through two paths: a current path from the wiring layer 7 through the upper composite layer 8 and metal film 5 to the channel layer 3, and a current path from the wiring layer 7 through the composite layer 8 to the channel layer 3, resulting in a reduction in contact resistance. 【0070】 Furthermore, since the wiring layer 7 is provided in contact with the upper surface of the composite layer 8, there is no need to provide contact holes in the composite layer 8, thus simplifying the manufacturing process. 【0071】 <Manufacturing method> Next, the manufacturing method of the semiconductor device 600 will be explained using Figure 28, which shows the manufacturing process. The process up to the steps shown in Figure 28 is the same as the steps in Figures 20 to 24 used to explain the manufacturing method of the semiconductor device 500 in Embodiment 5. The metal film 5 and the insulating film 6 are reacted using the RTA method or the like to form a silicide layer to form a composite layer 8, and the metal film 5 is covered with the composite layer 8. At the same time, the metal film 5, the composite layer 8 and the barrier layer 4 are alloyed with each other to form an ohmic electrode. In this process, a composite layer 8 is also formed between a part of the lower surface of the metal film 5 and the barrier layer 4. 【0072】 Subsequently, in the process shown in Figure 28, a resist mask RM is formed on the composite layer 8 and insulating film 6, with openings OP in the areas where the wiring layer 7 is to be formed. Then, a single layer film of Ti, Al, Ni, Au, etc., or a multilayer film thereof, is formed on the resist mask RM and within the openings OP by vapor deposition, and the wiring layer 7 is formed by removing the resist mask RM using the lift-off method, thereby obtaining the semiconductor device 600 shown in Figure 27. 【0073】 <Embodiment 7> <Device configuration> The configuration of the semiconductor device 700 in Embodiment 7 of this disclosure is the same as the configuration of the semiconductor device 100 in Embodiment 1 shown in Figure 1, except that the sheet resistance is controlled by a two-dimensional electron gas generated at the interface between the barrier layer 4 and the channel layer 3. The semiconductor device 700 will be described with reference to Figure 1, and with reference to Figures 29 and 30. 【0074】 As shown in Figure 1, the semiconductor device 700 has an AlGaN / GaN heterojunction, with a barrier layer 4 made of AlGaN forming a heterojunction with the channel layer 3, which is made of GaN. 【0075】 In an ohmic electrode formed on a semiconductor layer having an AlGaN / GaN heterojunction, the Al composition and thickness of the AlGaN layer are designed such that, in the state where the metal film 5 and insulating film 6 are not formed, i.e., the state shown in Figure 29, the sheet resistance due to the two-dimensional electron gas (2DEG) generated at the interface between the barrier layer 4 and the channel layer 3 (AlGaN / GaN interface) is sufficiently high, i.e., at least 10 kΩ / sq or more. 【0076】 For example, if the Al composition and thickness of the AlGaN barrier layer 4 are set to 15% and 7nm, or 20% and 5nm, or 100% and 1nm, the sheet resistance will be 10kΩ / sq or more. 【0077】 Furthermore, the sheet resistance of the barrier layer 4 in the state where only the barrier layer 4 is formed on the channel layer 3 described above is defined as the intrinsic sheet resistance of the barrier layer 4. 【0078】 On the barrier layer 4, which is composed of the AlGaN layer designed in this way, an insulating film 6, for example, SiO2, is deposited, and by heat treatment at a temperature of 500°C to 900°C, 1 × 10⁻¹⁶ layers are deposited at the AlGaN / GaN interface. 12 cm -2 2DEG can be induced at the above concentrations. This state is schematically shown in Figure 30. 【0079】 Figure 30 shows that 2DEG9 is induced at the interface between the channel layer 3 and the barrier layer 4, and 2DEG reduces the sheet resistance to, for example, 1 kΩ / sq or less. 【0080】 In semiconductor devices such as transistors and diodes composed of nitride semiconductors that use the 2DEG thus induced as a carrier, high-temperature heat treatment is required for the purpose of inducing 2DEG and for the purpose of forming low-resistance ohmic electrodes as described in Embodiments 1 to 6. However, it is not necessary to perform each of these separately, and the process can be simplified by performing them simultaneously. 【0081】 In other words, the process can be simplified by simultaneously performing the formation of the composite layer 8 for the low-resistance ohmic electrode described in Embodiments 1 to 6 and the high-temperature heat treatment for inducing 2DEG. 【0082】 This means that the ohmic electrode structure in this disclosure is more effective when the sheet resistance due to 2DEG generated at the AlGaN / GaN interface is sufficiently high, i.e., at least 10 kΩ / sq, when the metal film 5 and insulating film 6 are not formed. 【0083】 <Embodiment 8> <Device configuration> The configuration of the semiconductor device of Embodiment 8 according to this disclosure is the same as the configuration of the semiconductor device 100 of Embodiment 1 shown in Figure 1, except that the composite layer 8 contains elements that constitute the insulating film 6, and also contains one or more metal elements that are included in the barrier layer 4 and the metal film 5. The semiconductor device of this embodiment will be described with reference to Figure 1. 【0084】 The metallic elements included in the composite layer 8 can be one or more of Ga, Al, and Au. By adopting this configuration, the composite layer 8 contains materials that constitute the semiconductor device, particularly nitride semiconductor devices, and no unwanted impurities are mixed into the composite layer 8, resulting in a semiconductor device with stable electrical properties. 【0085】 Here, the barrier layer 4 can be made of AlGaN and the metal film 5 can be made of Al or Au, and at least one of the metal elements Al and Ga contained in the barrier layer 4 can be incorporated into the composite layer 8. Alternatively, at least one of the metal elements Al and Au contained in the metal film 5 can be incorporated into the composite layer 8. 【0086】 In other words, by ensuring that the composite layer 8 contains one or more of the metal elements Al, Ga, and Au found in the barrier layer 4 and the metal film 5, it is possible to suppress the inclusion of unwanted impurities in the composite layer 8. 【0087】 If the composite layer 8 contains gallium, it can contain 2 atomic percent (at%) or more; if the composite layer 8 contains aluminum, it can contain 10 atomic percent (at%) or more; and if the composite layer 8 contains gold, it can contain 5 atomic percent (at%) or more. By adopting such a configuration, the composite layer 8 can be formed from materials constituting semiconductor devices, particularly nitride semiconductor devices, thereby suppressing the complexity of the manufacturing process. 【0088】 In Embodiment 8, the composite layer 8 in the semiconductor device 100 of Embodiment 1 shown in Figure 1 was used as an example for explanation. However, the composite layer 8 of each of the semiconductor devices 200 to 700 in Embodiments 2 to 7 can also be configured to include one or more metal elements contained in the barrier layer 4 and the metal film 5. 【0089】 <Embodiment 9> <Device configuration> Figure 31 is a cross-sectional view showing the configuration of the semiconductor device 800 according to Embodiment 9 of the present disclosure. In Figure 31, components identical to those of the semiconductor device 100 described using Figure 1 are denoted by the same reference numerals, and redundant explanations are omitted. 【0090】 As shown in Figure 31, the semiconductor device 800 has, in addition to the configuration of the semiconductor device 100 shown in Figure 1, an insulating film 6, a composite layer 8, and an insulating film 10 that partially covers the wiring layer 7. When the semiconductor device 800 is a transistor, the insulating film 10 functions as a gate insulating film of the gate electrode, which is provided in a part not shown. Also, if a separate gate insulating film is provided, it functions as a protective film of the gate electrode. The insulating film 10 can be made of Al2O3, SiO2, or SiN, similar to the insulating film 6. 【0091】 Thus, even in a configuration in which an insulating film 10 is further provided on an ohmic electrode formed on a semiconductor layer having an AlGaN / GaN heterojunction, the presence of the composite layer 8 reduces contact resistance, and by using the insulating film 10 as a protective film for the gate insulating film or gate electrode, abnormalities such as deterioration, alteration, or peeling of the gate insulating film or gate electrode can be suppressed, enabling the realization of various semiconductor devices. 【0092】 Although Figure 31 shows a configuration in which an insulating film 10 is provided on the semiconductor device 100, it is also possible to provide the insulating film 10 in any of the configurations of the semiconductor devices 200 to 700 in Embodiments 2 to 7. 【0093】 <Embodiment 10> <Device configuration> Figure 32 is a cross-sectional view showing the configuration of the semiconductor device 900 according to Embodiment 10 of the present disclosure. In Figure 32, components identical to those of the semiconductor device 100 described using Figure 1 are denoted by the same reference numerals, and redundant explanations are omitted. 【0094】 As shown in Figure 32, the semiconductor device 900 is configured such that the wiring layer 7 engages not only with the inside of the contact holes CH provided in the composite layer 8, but also with a portion of the upper part of the composite layer 8. With this configuration, the contact holes CH are completely covered by the wiring layer 7, preventing gaps from forming between the contact holes CH and the wiring layer 7. This suppresses abnormalities such as peeling of the composite layer 8 or deterioration of the metal film 5 inside the contact holes CH. 【0095】 <Embodiment 11> <Device configuration> Figure 33 is a cross-sectional view showing the configuration of the semiconductor device 1000 according to Embodiment 11 of the present disclosure. In Figure 33, components identical to those of the semiconductor device 100 described using Figure 1 are denoted by the same reference numerals, and redundant explanations are omitted. 【0096】 As shown in Figure 33, the semiconductor device 1000 has a buffer layer 2 in which multiple layers of AlN layer 21 and AlGaN layer 22 are formed in alternating layers. Adopting this configuration has the effect of suppressing the degradation of crystal quality due to the difference in lattice constants between the semiconductor substrate 1 and the channel layer 3 made of GaN. 【0097】 <Embodiment 12> <Device configuration> Figure 34 is a cross-sectional view showing the configuration of the semiconductor device 1100 according to Embodiment 12 of this disclosure. In Figure 34, components identical to those of the semiconductor device 100 described using Figure 1 are denoted by the same reference numerals, and redundant explanations are omitted. 【0098】 As shown in Figure 34, the semiconductor device 1100 has a configuration in which a back barrier layer 11 made of AlGaN is formed on the buffer layer 2. By providing a back barrier layer 11 made of AlGaN, which has a larger band gap than the GaN of the channel layer 3, drain leakage current can be suppressed. 【0099】 <Variation> In the semiconductor devices 100 to 1100 of embodiments 1 to 12 described above, the semiconductor substrate 1 is composed of SiC, the buffer layer 2 of AlN, the channel layer 3 of GaN, and the barrier layer 4 of AlGaN, but the invention is not limited to these. 【0100】 In other words, the semiconductor substrate 1 can be made of Si, sapphire, AlN, and GaN. If a different SiC or Si material is used for the semiconductor substrate 1 than the channel layer 3, a buffer layer 2 is required. However, if GaN, AlGaN, or InAlGaN, which are the same material as the channel layer 3, is used for the semiconductor substrate 1, a buffer layer 2 is not necessarily required. 【0101】 Therefore, if a channel layer 3 and a barrier layer 4 are formed as semiconductor layers on the semiconductor substrate 1, the effects of each embodiment of this disclosure can be obtained. 【0102】 The buffer layer can be made of GaN and AlGaN, and the channel layer 3 can be made of AlGaN and InAlGaN. The barrier layer 4 can be made of GaN, AlN, InAlGaN, and InAlN. 【0103】 Furthermore, insulating films 6 and 10 are not limited to SiO2 or SiN, but can also be alumina (Al2O3), HfO x It can be composed of SiON, AlON, and HfON. 【0104】 Furthermore, while nitride semiconductor layers can be undoped (without impurities), they can also contain impurities such as Si, Mg (magnesium), Fe (iron), C (carbon), and Ge (germanium) in amounts that do not interfere with transistor operation. 【0105】 Although this disclosure has been described in detail, the above description is illustrative in all respects and does not limit this disclosure. It is understood that countless variations not illustrated may be conceivable without falling outside the scope of this disclosure. 【0106】 Furthermore, within the scope of this disclosure, it is possible to freely combine each embodiment, or to modify or omit each embodiment as appropriate.

Claims

[Claim 1] Semiconductor substrate and A channel layer made of a first nitride semiconductor provided on the semiconductor substrate, A barrier layer provided on the channel layer and composed of a second nitride semiconductor having a band gap larger than the band gap of the first nitride semiconductor, A metal film selectively formed on the barrier layer, A composite layer provided in contact with the aforementioned metal film, having at least a conductive material and an insulating material, The barrier layer comprises an insulating film formed in a region where the metal film and the composite layer are not formed, The sheet resistance due to the two-dimensional electron gas generated at the interface between the channel layer and the barrier layer in the region of the barrier layer that is in contact with the insulating film is 1 kΩ / sq or less. The aforementioned composite layer is It is provided so as to cover a part of the upper surface of the metal film on the side opposite to the barrier layer, the side of the metal film, and the lower surface of the metal film on the side opposite to the upper surface. A semiconductor device in which a wiring layer is provided so as to be in contact with the region on the upper surface of the metal film where the composite layer is not provided. [Claim 2] A semiconductor substrate and A channel layer made of a first nitride semiconductor provided on the semiconductor substrate, A barrier layer provided on the channel layer and composed of a second nitride semiconductor having a band gap larger than the band gap of the first nitride semiconductor, A metal film selectively formed on the barrier layer, A composite layer provided in contact with the aforementioned metal film, having at least a conductive material and an insulating material, The barrier layer comprises an insulating film formed in a region where the metal film and the composite layer are not formed, The sheet resistance due to the two-dimensional electron gas generated at the interface between the channel layer and the barrier layer in the region of the barrier layer that is in contact with the insulating film is 1 kΩ / sq or less. The aforementioned composite layer is The barrier layer is provided so as to cover the upper surface of the metal film on the opposite side, the side surface of the metal film, and the lower surface of the metal film on the opposite side of the upper surface. A semiconductor device in which a wiring layer is provided so as to be in contact with the composite layer on the upper surface of the metal film. [Claim 3] A semiconductor substrate and A channel layer made of a first nitride semiconductor provided on the semiconductor substrate, A barrier layer provided on the channel layer and composed of a second nitride semiconductor having a band gap larger than the band gap of the first nitride semiconductor, A metal film selectively formed on the barrier layer, A composite layer provided in contact with the aforementioned metal film, having at least a conductive material and an insulating material, The barrier layer comprises an insulating film formed in a region where the metal film and the composite layer are not formed, The sheet resistance due to the two-dimensional electron gas generated at the interface between the channel layer and the barrier layer in the region of the barrier layer that is in contact with the insulating film is 1 kΩ / sq or less. The aforementioned composite layer is It is provided so as to cover a part of the upper surface of the metal film on the side opposite to the barrier layer, the side of the metal film, and a part of the lower surface of the metal film on the side opposite to the upper surface. A semiconductor device in which a wiring layer is provided so as to be in contact with the region on the upper surface of the metal film where the composite layer is not provided. [Claim 4] A semiconductor substrate and A channel layer made of a first nitride semiconductor provided on the semiconductor substrate, A barrier layer provided on the channel layer and composed of a second nitride semiconductor having a band gap larger than the band gap of the first nitride semiconductor, A metal film selectively formed on the barrier layer, A composite layer provided in contact with the aforementioned metal film, having at least a conductive material and an insulating material, The barrier layer comprises an insulating film formed in a region where the metal film and the composite layer are not formed, The sheet resistance due to the two-dimensional electron gas generated at the interface between the channel layer and the barrier layer in the region of the barrier layer that is in contact with the insulating film is 1 kΩ / sq or less. The aforementioned composite layer is The upper surface of the metal film opposite to the barrier layer, the side surface of the metal film, and the upper surface It is provided so as to cover a part of the lower surface of the metal film on the opposite side, A semiconductor device in which a wiring layer is provided so as to be in contact with the composite layer on the upper surface of the metal film. [Claim 5] The semiconductor device according to any one of claims 1 to 4, wherein the composite layer is a silicide layer of the metal film. [Claim 6] The channel layer is made of gallium nitride. The semiconductor device according to any one of claims 1 to 4, wherein the barrier layer is composed of aluminum gallium nitride. [Claim 7] The aforementioned composite layer is A semiconductor device according to any one of claims 1 to 4, comprising one or more metal elements contained in the barrier layer and the metal film, together with the elements constituting the insulating film. [Claim 8] The aforementioned metallic element is The semiconductor device according to claim 7, comprising one or more of gallium, aluminum, and gold. [Claim 9] If the aforementioned metal element is gallium, then gallium is present in a quantity of 2 atomic percent or more. If the aforementioned metal element is aluminum, then aluminum must be present in a quantity of 10 atomic percent or more. The semiconductor device according to claim 8, wherein if the aforementioned metal element is gold, it contains 5 atomic percent or more of gold. [Claim 10] A semiconductor substrate and A channel layer made of a first nitride semiconductor provided on the semiconductor substrate, A barrier layer provided on the channel layer and composed of a second nitride semiconductor having a band gap larger than the band gap of the first nitride semiconductor, A metal film selectively formed on the barrier layer, A composite layer provided in contact with the aforementioned metal film, having at least a conductive material and an insulating material, The barrier layer comprises an insulating film formed in a region where the metal film and the composite layer are not formed, A method for manufacturing a semiconductor device, wherein the sheet resistance due to the two-dimensional electron gas generated at the interface between the channel layer and the barrier layer in the region of the barrier layer in contact with the insulating film is 1 kΩ / sq or less, A step of forming the channel layer on the semiconductor substrate, A step of forming the barrier layer on the channel layer, A step of selectively forming the metal film on the barrier layer, A step of forming the insulating film so as to cover the metal film, A method for manufacturing a semiconductor device, comprising the steps of forming the insulating film, then performing heat treatment at a temperature of 500°C to 900°C to react the portion where the metal film and the insulating film are in contact to form the composite layer. [Claim 11] A semiconductor substrate and A channel layer made of a first nitride semiconductor provided on the semiconductor substrate, A barrier layer provided on the channel layer and composed of a second nitride semiconductor having a band gap larger than the band gap of the first nitride semiconductor, A metal film selectively formed on the barrier layer, A composite layer provided in contact with the aforementioned metal film, having at least a conductive material and an insulating material, The barrier layer comprises an insulating film formed in a region where the metal film and the composite layer are not formed, A method for manufacturing a semiconductor device, wherein the sheet resistance due to the two-dimensional electron gas generated at the interface between the channel layer and the barrier layer in the region of the barrier layer in contact with the insulating film is 1 kΩ / sq or less, A step of forming the channel layer on the semiconductor substrate, A step of forming the barrier layer on the channel layer, A step of forming a first insulating film on the barrier layer, A step of selectively forming the metal film on the first insulating film, A step of forming a second insulating film so as to cover the metal film, A method for manufacturing a semiconductor device, comprising the steps of: forming the second insulating film, then performing heat treatment at a temperature of 500°C to 900°C to react the portion where the metal film and the first and second insulating films are in contact to form the composite layer. [Claim 12] A semiconductor substrate and A channel layer made of a first nitride semiconductor provided on the semiconductor substrate, A barrier layer provided on the channel layer and composed of a second nitride semiconductor having a band gap larger than the band gap of the first nitride semiconductor, A metal film selectively formed on the barrier layer, A composite layer provided in contact with the aforementioned metal film, having at least a conductive material and an insulating material, The barrier layer comprises an insulating film formed in a region where the metal film and the composite layer are not formed, A method for manufacturing a semiconductor device, wherein the sheet resistance due to the two-dimensional electron gas generated at the interface between the channel layer and the barrier layer in the region of the barrier layer in contact with the insulating film is 1 kΩ / sq or less, A step of forming the channel layer on the semiconductor substrate, A step of forming the barrier layer on the channel layer, A step of forming a first insulating film on the barrier layer, A step of partially removing the first insulating film to form a contact hole reaching the barrier layer, A step of selectively forming the metal film on the first insulating film including the contact hole, A step of forming a second insulating film so as to cover the metal film, A method for manufacturing a semiconductor device, comprising the steps of: forming the second insulating film, then performing heat treatment at a temperature of 500°C to 900°C to react the portion where the metal film and the first and second insulating films are in contact to form the composite layer.