Semiconductor equipment

Abstract

To provide a transistor having high electron field-effect mobility; or provide a transistor having stable electrical characteristics; or provide a transistor having less current in an OFF state (non-conductive state); or provide a semiconductor device having the above-described transistor.SOLUTION: A semiconductor device comprises: a first electrode formed on a substrate; a first insulation layer formed adjacent to a lateral face of the first electrode; and a second insulation layer which covers the first insulation layer and is formed adjacent to at least part of a surface of the first electrode. The surface of the first electrode is formed by a conductive material where an impurity element is less likely to penetrate; and the second insulation layer is formed by an insulating material where an impurity element is less likely to penetrate. The semiconductor device further comprises an oxide semiconductor layer formed on the first electrode via third insulation layer.SELECTED DRAWING: Figure 1

Description

【Technical Field】 【0001】 The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, a manufacture, or a composition of matter. Further, one aspect of the present invention relates to a semiconductor device, a display device, a light-emitting device, a lighting device, a power storage device, a memory device, a processor, their driving methods, or their manufacturing methods. In particular, one aspect of the present invention relates to a semiconductor device, a display device, or a light-emitting device including an oxide semiconductor. 【0002】 Note that, in this specification and the like, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. A display device, a light-emitting device, a lighting device, an electro-optical device, a semiconductor circuit, and an electronic device may have a semiconductor device. 【Background Art】 【0003】 Silicon used for the semiconductor of a transistor is properly selected between amorphous silicon and polycrystalline silicon depending on the application. For example, when applied to a transistor constituting a large-sized display device, it is preferable to use amorphous silicon for which a formation technique on a large-area substrate has been established. On the other hand, when applied to a transistor constituting a high-functional display device in which a drive circuit is integrally formed, it is preferable to use polycrystalline silicon capable of manufacturing a transistor having a high field-effect mobility. Polycrystalline silicon is formed by performing heat treatment at a high temperature or laser light treatment on amorphous silicon. treatment on amorphous silicon. A method of forming polycrystalline silicon by performing heat treatment at a high temperature or laser light treatment on amorphous silicon is known. treatment on amorphous silicon is known. 【0004】 In recent years, oxide semiconductors have been attracting attention. For example, having indium, gallium, and zinc A transistor using an amorphous oxide semiconductor has been disclosed (see Patent Document 1). 【0005】 Oxide semiconductors can be formed using methods such as sputtering, making them suitable for large-scale display devices. It can be used in the channel formation region of a transistor. Furthermore, using an oxide semiconductor... Because the transistor has high field-effect mobility, it is a high-performance device with an integrated drive circuit. A display device can be realized. In addition, part of the production equipment for transistors using amorphous silicon Because it can be modified and reused, it also has the advantage of reducing capital investment. 【0006】 By the way, transistors using oxide semiconductors exhibit extremely high leakage current in the non-conductive state. It is known that the leakage is small. For example, the low leakage of transistors using oxide semiconductors. Low-power CPUs that utilize these characteristics have been disclosed (see Patent Document 2). [Prior art documents] [Patent Documents] 【0007】 [Patent Document 1] Japanese Patent Publication No. 2006-165528 [Patent Document 2] Japanese Patent Publication No. 2012-257187 [Overview of the Initiative] [Problems that the invention aims to solve] 【0008】 One of the objectives is to provide a transistor with high field-effect mobility. One of the objectives is to provide a transistor with stable thermal characteristics. Alternatively, when off (non-conductive) One of the objectives is to provide a transistor with low current (through-current). Alternatively, power consumption One of the challenges is to provide transistors with fewer defects. Alternatively, a reliable transistor. One of the objectives is to provide a transistor. Alternatively, to provide a novel transistor. This will be one of the issues to address. 【0009】 Alternatively, one of the objectives is to provide a semiconductor device with a small footprint. Alternatively, integration density One of the challenges is to provide a semiconductor device with high performance. Alternatively, a semiconductor device with good reliability. One of the objectives is to provide a novel semiconductor device. Let's assume that. 【0010】 Furthermore, the description of these problems does not preclude the existence of other problems. The approach does not need to solve all of these problems. This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings It is possible to extract other issues from the descriptions in the surfaces, claims, etc. [Means for solving the problem] 【0011】 One aspect of the present invention comprises a first electrode, a first insulating layer, a second insulating layer, and a third insulating layer. The material has an oxide semiconductor layer and a second insulating layer, the first insulating layer being adjacent to the side surface of the first electrode and the second insulating layer It covers the first insulating layer and is in contact with at least a portion of the surface of the first electrode, and the first electrode It is superimposed on the oxide semiconductor layer via a third insulating layer, and the second insulating layer is permeable to impurity elements. It is an insulating material that is difficult to penetrate, and the surface of the first electrode is a conductive material that is difficult for impurity elements to permeate. This semiconductor device is characterized by the following: 【0012】 Alternatively, one aspect of the present invention comprises a first gate electrode, a second gate electrode, and a first gate insulator A marginal layer, a second gate insulating layer, an oxide semiconductor layer, a source electrode, a drain electrode, and The oxide semiconductor layer has an insulating layer and a second insulating layer, and the oxide semiconductor layer has a first gate insulating layer and a second Sandwiched between two gate insulating layers, the first gate insulating layer, the oxide semiconductor layer, and the second gate insulating layer The marginal layer is sandwiched between the first gate electrode and the second gate electrode, and the source electrode and drain electrode are located within it. The first insulating layer is in contact with the oxide semiconductor layer, and the second insulating layer is adjacent to the side surface of the second gate electrode. The insulating layer covers the first insulating layer and is in contact with at least a portion of the surface of the second gate electrode. The second insulating layer is an insulating material that is resistant to the permeation of impurity elements, and the surface of the second gate electrode The semiconductor device is characterized by having a conductive material that is resistant to the penetration of impurity elements. 【0013】 The second insulating layer consists of aluminum oxide, aluminum nitride, aluminum oxide nitride, and aluminum nitride. Aluminum oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide Formed using lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. ru. 【0014】 The surface of the first electrode and the surface of the second gate electrode are made of indium tin oxide (hereinafter referred to as "IT Also called "O". ), indigenous compounds containing silicon, phosphorus, boron, nitrogen, and / or carbon. Indium gallium containing tin oxide, silicon, phosphorus, boron, nitrogen, and / or carbon It is formed using conductive materials such as zinc oxide, tantalum nitride, or ruthenium. [Effects of the Invention] 【0015】 It is possible to provide semiconductor devices with a small footprint, or semiconductor devices with a high degree of integration. It can provide a reliable semiconductor device. Alternatively, a novel semiconductor device can be provided. 【0016】 Furthermore, the description of these effects does not preclude the existence of other effects. The embodiment does not need to have all of these effects. Other effects are described in the specification. This will become clear from the descriptions in the drawings and claims, and the specification, drawings, and claims will be clear from the description, drawings, and claims. It is possible to extract other effects from any of these descriptions. [Brief explanation of the drawing] 【0017】 [Figure 1] A diagram illustrating an example of a transistor and a capacitive element according to one aspect of the present invention. [Figure 2] A diagram illustrating an example of the manufacturing process for a transistor according to one aspect of the present invention. [Figure 3] A diagram illustrating an example of the manufacturing process for a transistor according to one aspect of the present invention. [Figure 4] A diagram illustrating an example of the manufacturing process for a transistor according to one aspect of the present invention. [Figure 5] A diagram illustrating an example of the manufacturing process for a transistor according to one aspect of the present invention. [Figure 6] A diagram illustrating the energy band structure. [Figure 7] High-resolution TEM image with Cs correction in cross-section of CAAC-OS, and schematic cross-sectional diagram of CAAC-OS. [Figure 8] High-resolution TEM image with Cs correction in the plane of CAAC-OS. [Figure 9] A diagram illustrating the XRD structural analysis of CAAC-OS and single-crystal oxide semiconductors. [Figure 10] A figure showing the electron diffraction pattern of CAAC-OS. [Figure 11] A diagram showing the changes in the crystalline structure of In-Ga-Zn oxide due to electron irradiation. [Figure 12]A schematic diagram illustrating the film deposition models for CAAC-OS and nc-OS. [Figure 13] A diagram illustrating InGaZnO4 crystals and pellets. [Figure 14] A schematic diagram illustrating the film deposition model of CAAC-OS. [Figure 15] Cross-sectional TEM images and local Fourier transform images of oxide semiconductors. [Figure 16] A diagram illustrating the nanobeam electron diffraction pattern of an oxide semiconductor film, and a diagram illustrating an example of a transmission electron diffraction measurement device. [Figure 17] A diagram illustrating an example of structural analysis by transmission electron diffraction measurement, and a planar TEM image. [Figure 18] A cross-sectional view and circuit diagram illustrating an example of a semiconductor device. [Figure 19] Circuit diagram showing an example of a semiconductor device according to one aspect of the present invention. [Figure 20] A block diagram illustrating an example of a semiconductor device. [Figure 21] A circuit diagram illustrating an example of a memory device. [Figure 22] A block diagram of an RF tag according to one aspect of the present invention. [Figure 23] A diagram illustrating an example of the use of an RF tag according to one aspect of the present invention. [Figure 24] A block diagram and circuit diagram illustrating one form of a semiconductor device. [Figure 25] A diagram illustrating the display module. [Figure 26] A diagram illustrating an electronic device according to one aspect of the present invention. [Figure 27] A diagram illustrating the cross-sectional structure and analysis results of the sample used in Example 1. [Figure 28] A diagram illustrating the cross-sectional structure and analysis results of the sample used in Example 2. [Figure 29] A diagram illustrating an example of the manufacturing process for a transistor according to one aspect of the present invention. [Figure 30] A diagram illustrating an example of a transistor and a capacitive element according to one aspect of the present invention. [Modes for carrying out the invention] 【0018】 Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Without departing from the spirit and scope of the present invention, its form and details may be modified in various ways. It will be easily understood by those skilled in the art to obtain this. Therefore, the present invention is as shown in the embodiments below. The description is not to be interpreted as being limited to the stated content. The same reference numeral is used in common across different drawings for parts that are identical or have similar functions. I will omit the explanation of that repetition. 【0019】 Furthermore, the position, size, and scope of each component shown in the drawings, etc., are intended to facilitate understanding of the invention. Therefore, it may not represent the actual location, size, or range. For this reason, disclosure is required. The invention is not necessarily limited to the location, size, scope, etc. disclosed in the drawings, etc. For example. In the actual manufacturing process, the resist mask may be unintentionally damaged by processes such as etching. While this may result in a reduction in value, it is sometimes omitted for the sake of easier understanding. 【0020】 Furthermore, especially in the top view (also called the "plan view"), in order to make the drawing easier to understand, In some cases, the description of certain components may be omitted. 【0021】 Furthermore, in this specification, the terms "electrode" and "wiring" do not limit the functionality of these components. It is not fixed. For example, "electrode" can be used as part of "wiring". The reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes" and "wiring". This also includes cases where the "lines" are formed as a single unit. 【0022】 In this specification, the terms "above" and "below" refer to the relative positions of the constituent elements, specifically whether they are directly above or below. It is not limited to being below and in direct contact. For example, "electrode on insulating layer A" If the expression is "B", then it is not necessary for electrode B to be formed in direct contact with insulating layer A. Cases containing other components between marginal layer A and electrode B are not excluded. 【0023】 Furthermore, the source and drain functions may differ when using transistors with different polarities, or when rotating In circuit operation, the direction of the current changes, and depending on the operating conditions, they can be swapped. Therefore, it is difficult to determine which is the source and which is the drain. In this specification, the terms source and drain may be used interchangeably. Let's assume that. 【0024】 Furthermore, in this specification, "electrically connected" means "having some kind of electrical effect." This includes cases where the connection is made via ". Here, "something that has some electrical effect" The term "connection" is not particularly limited as long as it enables the exchange of electrical signals between connected objects. Therefore, even when expressed as "electrically connected," in actual circuits, In some cases, there is no logical connection point, and the wiring simply extends without any apparent purpose. 【0025】 Furthermore, in this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. This refers to the state in which something is positioned. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "abbreviated "Parallel" refers to a state where two straight lines are positioned at an angle between -30° and 30°. Furthermore, "perpendicular" and "orthogonal" refer to two lines positioned at an angle of 80° to 100°. This refers to a state in which it is in a certain position. Therefore, it also includes cases where the angle is between 85° and 95°. "Straight" refers to a state in which two straight lines are positioned at an angle between 60° and 120°. 【0026】 In this specification, if a crystal is trigonal or rhombohedral, it will be represented as a hexagonal crystal system. . 【0027】 Furthermore, in this specification, when an etching process is performed after a photolithography process, Unless otherwise specified, the resist mask formed in the photolithography process is It shall be removed after the finishing process is complete. 【0028】 Furthermore, voltage is defined by a certain potential and a reference potential (for example, ground potential or source potential). It often refers to the potential difference between (voltage and electric potential). Therefore, it is possible to rephrase voltage as electric potential. ru. 【0029】 Furthermore, even when the term "semiconductor" is used, if, for example, its conductivity is sufficiently low, it can be referred to as an "insulator." They may have the following characteristics. Also, the boundary between "semiconductors" and "insulators" is ambiguous, and strictly speaking... In some cases, it may be impossible to distinguish between them. Therefore, the term "semiconductor" as used in this specification is used interchangeably with "insulator". In some cases, it can be rephrased. Similarly, the term "insulator" as used herein may be interpreted as "semiconductor." In some cases, this can be rephrased as "...". 【0030】 Furthermore, even when the term "semiconductor" is used, if, for example, its conductivity is sufficiently high, it can be referred to as a "conductor." They may have certain characteristics. Also, the boundary between "semiconductors" and "conductors" is ambiguous, and strictly speaking... In some cases, it may be impossible to distinguish between them. Therefore, the term "semiconductor" as used in this specification is used interchangeably with "conductor". In some cases, it can be rephrased. Similarly, the term "conductor" as used herein means "semiconductor." In some cases, this can be rephrased as "...". 【0031】 Furthermore, semiconductor impurities refer to components other than the main components that make up the semiconductor, for example, concentration. Elements present in less than 0.1 atomic percent are considered impurities. The presence of impurities can, for example, affect semiconductors. The body's DOS (Density of State) increases, and the rate of carrier migration increases. This can result in a decrease in quality or a decrease in crystallinity. In that case, impurities that change the properties of the semiconductor include, for example, Group 1 elements and Group 2 elements. These include elements, Group 14 elements, Group 15 elements, and transition metals other than the main component, and in particular, for example, water Element (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. There are such cases. In the case of oxide semiconductors, for example, the inclusion of impurities such as hydrogen can form oxygen vacancies. This can sometimes happen. Also, if the semiconductor is a silicon film, impurities can alter the properties of the semiconductor. In terms of substances, for example, Group 1 elements (excluding oxygen and hydrogen), Group 2 elements, Group 13 elements, and Group 15 elements. There are group elements, etc. 【0032】 In this specification, ordinal numbers such as "the first," "the second," etc., are used to avoid confusion of constituent elements. It is added for the purpose of indicating the order or sequence of processes or stacking order, or any other kind of order or ranking. No. Furthermore, even if a term is not given an ordinal number in this specification, the constituent elements may be mixed. To avoid ambiguity, ordinal numbers may be used in the claims. 【0033】 Note that "channel length" refers to, for example, the length of the semiconductor (or transistor) in the top view of a transistor. When the transistor is ON, the part of the semiconductor through which current flows and the gate electrode overlap. In the region where a region or channel is formed, the source (source region or source electrode) This refers to the distance between the drain (drain region or drain electrode). In a transistor, the channel length is not necessarily the same across all regions. That is, The channel length of a single transistor may not be fixed to a single value. Therefore, The detailed explanation states that the channel length is any one value, the maximum value, in the region where the channel is formed. , or the minimum value or the average value. 【0034】 Furthermore, "channel width" refers to, for example, the half-length of a semiconductor (or transistor) when it is turned on. A region or channel is formed where the part of the conductor through which current flows overlaps with the gate electrode. This refers to the length of the portion where the source and drain face each other in the region. In a transistor, the channel width is not necessarily the same across all regions. In other words, the channel width of a single transistor may not be fixed to a single value. In this specification, the channel width is any one value in the region where the channel is formed. This represents the maximum value, minimum value, or average value. 【0035】 Furthermore, depending on the transistor structure, the channel may actually be formed in the region where the channel is formed. The channel width (hereinafter referred to as the effective channel width) and the top view of the transistor are shown. The channel width (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In transistors with a three-dimensional structure, the effective channel width is shown in the top view of the transistor. The apparent channel width shown in [the relevant section] becomes larger, and its effect can no longer be ignored. In some cases, such as in transistors with a fine and three-dimensional structure, the upper surface of the semiconductor may be The ratio of channel regions formed on the side surface of the semiconductor to the ratio of channel regions formed In some cases, the apparent channel width shown in the top view may become larger. However, the effective channel width actually formed is larger. 【0036】 By the way, in transistors with a three-dimensional structure, the effective channel width is measured Estimation can be difficult in some cases. For example, estimating the effective channel width from the design value. In order to do this, it is necessary to assume that the shape of the semiconductor is known. If this information is not precisely known, it is difficult to accurately measure the effective channel width. 【0037】 Therefore, in this specification, in the top view of a transistor, the semiconductor and the gate electrode overlap. The apparent channel is the length of the portion in the region where the source and drain face each other. Channel width is defined as "Surrounded Channel Width (SCW)". It is sometimes referred to as "channel width." Also, in this specification, when simply referred to as channel width, This may refer to the enclosed channel width or the apparent channel width. Or, this detail In some documents, when simply referred to as "channel width," it may refer to the effective channel width. Oh, channel length, channel width, effective channel width, apparent channel width, enclosure channel Channel width and other parameters can be determined by acquiring cross-sectional TEM images and analyzing those images. The value can be determined. 【0038】 Furthermore, the field-effect mobility of the transistor and the current value per channel width are calculated to determine this. In some cases, the calculation may be performed using the enclosure channel width. In such a case, the value may be different from that obtained when calculating using the effective channel width. 【0039】 (Embodiment 1) In this embodiment, a configuration example of the transistor 100 according to one aspect of the present invention will be described with reference to the drawings. 【0040】 <A: Configuration Example of Transistor and Capacitor Element> FIG. 1(A) is a top view of the transistor 100 and the capacitor element 130. FIG. 1(B) is a cross-sectional view of the portion indicated by the dashed line A1 - A2 in FIG. 1(A). FIG. 1(C) is a cross-sectional view of the portion indicated by the dashed line B1 - B2 in FIG. 1(A). 【0041】 The transistor 100 shown in FIG. 1 is formed on the substrate 101. The transistor 100 includes an electrode 102, an insulating layer 106, an insulating layer 107, an oxide semiconductor layer 108, an electrode 109, an electrode 119, an insulating layer 110, an electrode 111, and an insulating layer 112. Also, in FIGS. 1(A) and 1(B), the electrodes 103 and 104 are also shown. 【0042】 More specifically, the electrodes 102, 103, and 104 are formed on the substrate 101, and an insulating layer 105 is formed between these electrodes. The electrode 102 has a structure in which an electrode 102b is laminated on an electrode 102a. The electrode 103 has a structure in which an electrode 103b is laminated on an electrode 103a. The electrode 104 has a structure in which an electrode 104b is laminated on an electrode 104a. The insulating layer 106 is formed on the insulating layer 105 in contact with a part of the electrode 102b, a part of the electrode 103b, and a part of the electrode 104b. 【0043】 Furthermore, the insulating layer 107 is located on a portion of electrode 102b, a portion of electrode 103b, and electrode 104b. It is formed on the insulating layer 106, in contact with a portion of it. The insulating layer 107 has a protrusion, and on the protrusion An oxide semiconductor layer 108a and an oxide semiconductor layer 108b are formed thereon. Also, electrode 10 9 and electrode 119 are formed in contact with the oxide semiconductor layer 108b. Electrode 119 is The electrode 104 is electrically connected to the insulating layer 107 through an opening formed in the insulating layer 107. 【0044】 Furthermore, the oxide semiconductor layer 108c is connected to the oxide semiconductor layer 108b, electrode 109, and electrode 1 It is formed in contact with 19. In Figure 1, oxide semiconductor layer 108a, oxide semiconductor layer 10 8b and oxide semiconductor layer 108c are shown as oxide semiconductor layer 108. 【0045】 Furthermore, an insulating layer 110 is formed on the oxide semiconductor layer 108c, and an electrode 11 is placed on the insulating layer 110. 1 is formed. Also, an insulating layer 112 covers electrodes 109, 119, and 111. It is formed. 【0046】 Electrode 111 can function as a gate electrode. Insulating layer 110 is a gate insulating layer. It can function as either a source electrode or a drain electrode. It can function as either a source electrode or a drain electrode. It can be done. Electrode 102 can function as a back gate electrode. The transistor 100 is a transistor that uses an oxide semiconductor in the semiconductor layer where the channel is formed. Therefore, transistor 100 can be considered a type of top-gate transistor. ru. 【0047】 Here, let me explain back gate electrodes. Generally, back gate electrodes are made of a conductive layer. The gate electrode and back gate electrode are arranged to sandwich the channel formation region of the semiconductor layer. It is placed there. Therefore, the back gate electrode can be made to function in the same way as the gate electrode. The potential of the back gate electrode may be the same potential as the gate electrode, or it may be the GND potential or any other potential. It may also be expressed as an electric potential. Furthermore, the electric potential of the buck gate electrode can be changed independently of the gate electrode. By doing this, the threshold voltage of the transistor can be changed. 【0048】 Both electrodes 111 and 102 of transistor 100 are gate electrodes. It can function. Therefore, both insulating layer 110 and insulating layer 107 are gate insulating. It can function as a marginal layer. Therefore, either electrode 111 or electrode 102 When one is simply called the "gate electrode," the other is called the "back gate electrode." Also, electrode 1 Either electrode 11 or electrode 102 is called the "first gate electrode," and the other is called the "second gate electrode." It is sometimes referred to as a "gate electrode." Also, when electrode 102 is used as a "gate electrode" Transistor 100 can be considered a type of bottom-gate transistor. 【0049】 By providing electrodes 111 and 102 with the oxide semiconductor layer 108 in between, further, By setting electrode 111 and electrode 102 to the same potential, carriers in the oxide semiconductor layer 108 Because the region in which A flows becomes larger in the film thickness direction, the amount of carrier movement increases. As a result, the on-current of transistor 100 increases, and the field-effect mobility also increases. . 【0050】 Therefore, transistor 100 has a large on-current relative to its occupied area. It is a transistor. In other words, the area occupied by transistor 100 is relative to the required on-current. It can be made smaller. According to one aspect of the present invention, the area occupied by the transistor can be reduced. Therefore, according to one aspect of the present invention, a semiconductor device with a high degree of integration can be realized. It is possible. 【0051】 Furthermore, since the gate electrode and back gate electrode are formed of conductive layers, outside the transistor... Function to prevent the generated electric field from acting on the semiconductor layer in which the channel is formed (especially static electricity) It has an electrostatic shielding function against [the effects of electrostatic discharge]. 【0052】 Furthermore, electrodes 111 and 102 each have the function of shielding against external electric fields. Therefore, the charge of charged particles and other elements provided on the substrate 101 side and the electrode 111 side is transferred to the oxide semiconductor layer It does not affect 10⁸. As a result, stress testing (e.g., applying a negative charge to the gate) is not possible. The deterioration of the GBT (Gate Bias-Temperature) stress test was suppressed. This also suppresses fluctuations in the on-current rise voltage at different drain voltages. This can be achieved. Note that this effect occurs when electrodes 111 and 102 are at the same potential or different potentials. This occurs in the case of electric potential. 【0053】 Note that the BT stress test is a type of accelerated stress test, and it tests the transient effects that occur due to long-term use. Changes in the characteristics of the sta (i.e., changes over time) can be evaluated in a short time. In particular, BT The amount of variation in the transistor's threshold voltage before and after stress testing is used to investigate reliability. This is an important indicator. The smaller the fluctuation in threshold voltage before and after the BT stress test, the better. It can be said that it is a highly reliable transistor. 【0054】 Furthermore, it has electrodes 111 and 102, and electrodes 111 and 102 are at the same potential. This reduces the fluctuation in threshold voltage before and after the BT stress test. Therefore, variations in the electrical characteristics of multiple transistors are also reduced at the same time. 【0055】 Furthermore, transistor 100, which has a back gate electrode, applies a positive charge to the gate. The threshold voltage fluctuates only slightly before and after the GBT stress test. 【0056】 Furthermore, when light is incident from the back gate electrode side, the back gate electrode has light-shielding properties. By forming it with a conductive film, it prevents light from entering the semiconductor layer from the back gate electrode side. This prevents photodegradation of the semiconductor layer and shifts the threshold voltage of the transistor. This prevents deterioration of electrical properties, such as those mentioned above. 【0057】 Next, let me explain "threshold voltage". Here, electrode 111 is the gate electrode and It is used as follows. When a voltage is applied to electrode 111, an electric field of a strength corresponding to the voltage is generated in the insulating layer 1 The oxide semiconductor layer 108 is applied via 10, and carriers are generated in the oxide semiconductor layer 108. Then, a channel is formed. Once the channel is formed, electrode 109 and electrode 119 become electrically connected. It is connected and becomes conductive (on). A channel is formed in the oxide semiconductor layer 108. The voltage at electrode 111 when it begins to heat up is called the "threshold voltage." 【0058】 For example, if transistor 100 is an n-channel type transistor, and electrode 109 is the source electrode When electrode 119 is used as the drain electrode, when the potential of electrode 109 is set to 0V, When a voltage greater than the threshold voltage is applied to electrode 111, the oxide semiconductor layer 10 Carriers are supplied to 8, and a channel is formed. Generally speaking, channels in semiconductor layers The region where the channel is formed is called the "channel formation region." At this time, a positive voltage is applied to electrode 119. When applied, carriers flow from electrode 109 to electrode 119. In other words, Current flows from electrode 119 to electrode 109. Note that this occurs when the transistor is ON. The current flowing between the source and drain electrodes of a transistor is called the "on-current." The current that flows between the source and drain electrodes when the device is in the "off" state is called the "off current." 【0059】 Insulating layer 106 and insulating layer 112 contain impurities such as hydrogen, water, alkali metals, and alkaline earth metals. Alternatively, it is preferable to form it using an insulating material that is impermeable to oxygen. By using this method to form insulating layers 106 and 112, the oxide semiconductor layer 10 can be accessed from the outside. The diffusion of impurities into 8 can be suppressed. Also, the acid contained in the oxide semiconductor layer 108 This can suppress the diffusion of the element to the outside. 【0060】 Furthermore, it is preferable not to provide an insulating layer 106 on at least a portion of the electrode 102. By not providing an insulating layer 106 on at least a portion of the electrode 102, the electrode 102 and the oxide semiconductor are separated. The distance of the body layer 108 can be shortened by the thickness of the insulating layer 106. Therefore, electrode 102 This can increase the electric field strength exerted on the oxide semiconductor layer 108. Therefore, the electrode 102 This can enhance its function as a gate electrode or back gate electrode. 【0061】 Furthermore, the capacitive element 130 has an insulating layer 107 as a dielectric between the electrode 103 and the electrode 109. It is formed by sandwiching. In this embodiment, the insulating layer 106 on the electrode 103 is removed. However, without removing the insulating layer 106 on the electrode 103, the product of insulating layer 106 and insulating layer 107 The layer may be used as a dielectric. 【0062】 Furthermore, it is preferable to bring the insulating layer 106 and the insulating layer 112 into contact on the outside of the transistor 100. i. In Figure 1(B), there are regions at both ends of Figure 1(B) where insulating layer 106 and insulating layer 112 are in contact. This configuration allows impurities to enter the oxide semiconductor layer 108 from the outside. Furthermore, the effect of suppressing diffusion can be further enhanced. Also, the oxide semiconductor layer 108 contains This can further enhance the effect of suppressing the diffusion of oxygen to the outside. One aspect of the present invention According to the manufacturer, it is possible to provide highly reliable semiconductor devices. 【0063】 [A-1: Circuit board 101] There are no major restrictions on the material used for the substrate 101, but it must at least be able to withstand subsequent heat treatment. It is necessary to have a certain degree of heat resistance. For example, barium borosilicate glass or aluminum Glass substrates such as borosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, etc. You can use it. 【0064】 Furthermore, the substrate 101 can be a single-crystal semiconductor substrate made of silicon or silicon carbide, or a polycrystalline semiconductor substrate. A semiconductor substrate, a compound semiconductor substrate made of silicon germanium, etc. may be used. Furthermore, SOI substrates and semiconductor substrates on which semiconductors such as strained transistors and FIN type transistors are placed. It is also possible to use devices equipped with elements, or high electron mobility transistors. HEMT: High Electron Mobility Transistor) Applicable materials: gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride Indium phosphate, silicon germanium, etc. may also be used. By using this, it is possible to create a transistor suitable for high-speed operation. Furthermore, the substrate 101 is not merely a support substrate, but also has other devices such as transistors formed on it. A substrate may also be used. In this case, the gate electrode and source electrode of transistor 100, and At least one of the drain electrodes may be electrically connected to the other devices mentioned above. . 【0065】 A flexible substrate may be used as the substrate 101. When using this method, transistors, capacitive elements, etc., may be directly fabricated on the flexible substrate. Transistors, capacitive elements, etc., are fabricated on other substrates, and then peeled off and transferred to a flexible substrate. This may be done. In addition, in order to peel and transfer the fabricated substrate to the flexible substrate, the fabricated substrate and the trans It is advisable to provide a delamination layer between the zista and capacitive elements. 【0066】 [A-2: Electrode 102a, Electrode 103a, and Electrode 104a] The conductive material for forming electrodes 102a, 103a, and 104a is Aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum , tungsten, hafnium (Hf), vanadium (V), niobium (Nb), manganese, A metallic element selected from magnesium, zirconium, beryllium, etc., the aforementioned metallic elements You can use alloys as components, or alloys that combine the aforementioned metal elements. Furthermore, polycrystalline silicon containing impurity elements such as phosphorus has high electrical conductivity. A semiconductor, such as nickel silicide, may also be used. The method for forming the conductive layer is particularly special. Not limited to, various formation methods such as vapor deposition, CVD, sputtering, and spin coating. The law can be used. 【0067】 Generally speaking, CVD methods utilize plasma CVD (Plasma CVD: Plasma CVD). Enhanced CVD (ma) method, thermal CVD (TCVD) which utilizes heat. It can be further classified into methods such as CVD (Metal Vapor Deposition). :Metal CVD) method, metal organic CVD (MOCVD) method It can be classified into methods such as CVD (Chemical Vapor Deposition). 【0068】 Furthermore, generally speaking, vapor deposition methods include resistance heating deposition, electron beam deposition, and MBE (Molecular Beam Evaporation). Beam Epitaxy) method, PLD (Pulsed Laser Deposit) ion) method, IAD:Ion beam Assisted Deposit (tion) method, ALD (ALD: Atomic Layer Deposition) method They can be classified into categories such as these. 【0069】 Plasma CVD is a method that can produce high-quality films at relatively low temperatures. When a film deposition method that does not use plasma during film formation is used, damage to the surface to be formed is less likely to occur. Furthermore, a film with fewer defects can be obtained. 【0070】 Furthermore, electrodes 102a, 103a, and 104a are coated with indium tin oxide and oxide. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, Titanium oxide containing indium oxide, titanium oxide containing indium tin oxide, indium Conductive materials containing oxygen, such as zinc oxide and silicon-added indium tin oxide, nitride Conductive materials containing nitrogen, such as titanium and tantalum nitride, can also be applied. It is also possible to create a laminated structure by combining a material containing a metallic element with a conductive material containing oxygen. Yes, it is possible. Also, the product of combining the aforementioned metal element-containing material with a nitrogen-containing conductive material. It can also be made into a layered structure. Furthermore, the aforementioned materials containing metallic elements and conductive materials containing oxygen... It can also be a laminated structure combining conductive materials containing nitrogen. 【0071】 Electrodes 102a, 103a, and 104a may have a single-layer structure or a stacked structure of two or more layers. It may also be constructed as follows: For example, a single-layer structure of an aluminum layer containing silicon, or an aluminum layer on top of an aluminum layer. A two-layer structure in which a titanium layer is laminated on top of a titanium nitride layer, a two-layer structure in which a titanium layer is laminated on top of a titanium nitride layer, A two-layer structure in which a tungsten layer is stacked on top of a tungsten layer, and a tungsten layer is stacked on top of a tantalum nitride layer. A two-layer structure, consisting of a titanium layer and an aluminum layer laminated on top of that titanium layer, and further on top of that There are also three-layer structures that form a titanium layer on top of aluminum. Layers of elements selected from tungsten, molybdenum, chromium, neodymium, and scandium, Alternatively, multiple alloy layers or nitride layers may be used. 【0072】 The thickness of electrodes 102a, 103a, and 104a is between 10 nm and 500 nm. Preferably, the wavelength should be between 50 nm and 300 nm. 【0073】 [A-3: Electrode 102b, electrode 103b, and electrode 104b] Electrodes 102b, 103b, and 104b are used for hydrogen, water, alkali metals, and alkalis. It is preferable to form the material using a conductive material that is impermeable to impurities such as earth metals and oxygen. Examples of such conductive materials include indium tin oxide, silicon, phosphorus, boron, and nitrogen. , and / or indium tin oxide containing carbon, silicon, phosphorus, boron, nitrogen, and Examples of conductive oxide materials include indium gallium zinc oxide containing carbon. It is possible to do so. Furthermore, conductive materials such as tantalum nitride and ruthenium can be cited. Furthermore, electrodes 102b, 103b, and 104b may have a single-layer structure or two or more layers. A laminated structure may also be used. 【0074】 The thickness of electrodes 102b, 103b, and 104b is between 10 nm and 500 nm. Preferably, the wavelength should be between 50 nm and 300 nm. 【0075】 Furthermore, without providing electrodes 102a, 103a, and 104a, electrodes 102 and electrodes Electrode 103 and electrode 104 are used with only electrodes 102b, 103b, and 104b. It may be structured as is. 【0076】 [A-4: Insulating layer 105] The insulating layer 105 consists of aluminum nitride, aluminum oxide, aluminum nitride oxide, and nitrogen oxide. Aluminum oxide, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, Silicon oxide nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide Materials selected from um, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. It can be formed as a single layer or in layers. Also, oxide materials, nitride materials, and nitrogen oxides. A mixture of multiple materials, including ionized materials and nitride oxide materials, may also be used. 【0077】 In this specification, nitride oxides refer to compounds in which the nitrogen content is greater than the oxygen content. Furthermore, oxidized nitrides are compounds in which the oxygen content is higher than the nitrogen content. The content can be measured, for example, by the Rutherford backscattering method (RBS). Measurements can be taken using methods such as kscattering (spectrometry). . 【0078】 If the insulating layer 105 is made up of multiple layers, for example, the first layer is a silicon nitride layer, and the second layer The eyes may be made of a silicon oxide layer. In this case, the silicon oxide layer may also be a silicon oxide nitride layer. That's fine. Also, the silicon nitride layer can be a silicon nitride oxide layer. 【0079】 The thickness of the insulating layer 105 is 10 nm or more and 500 nm or less, preferably 50 nm or more and 300 nm or less. It should be less than or equal to m. 【0080】 [A-5: Insulating layer 106] The insulating layer 106 is permeable to impurities such as hydrogen, water, alkali metals, alkaline earth metals, and oxygen. It is preferable to form it using an insulating material that is resistant to acid. Aluminum oxide, aluminum nitride, aluminum oxide nitride, aluminum oxide nitride, acid Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, Examples of insulating oxide materials include neodymium oxide, hafnium oxide, and tantalum oxide. Cut. 【0081】 The thickness of the insulating layer 106 is 10 nm or more and 500 nm or less, preferably 50 nm or more and 300 nm or less. It should be less than or equal to m. 【0082】 〔A-6: Insulating layer 107〕 The insulating layer 107 can be formed by the same materials and methods as the insulating layer 105. Also, in order to prevent an increase in the hydrogen concentration in the oxide semiconductor, it is preferable to reduce the hydrogen concentration of the insulating layer 107. Specifically, the hydrogen concentration of the insulating layer 107 is 2×10 3 , 【0083】 , 3 , , 3 , 3 , , , , , 1 , , 17 , 18 , 18 , , atoms / cm 3 or less, preferably 5×10 19 atoms / cm 3 or less, more preferably 1×10 19 atoms / cm 3 or less, even more preferably 5×10 18 atoms / cm 3 or less. Also, in order to prevent an increase in the nitrogen concentration in the oxide semiconductor, it is preferable to reduce the nitrogen concentration of the insulating layer 107. Specifically, the nitrogen concentration of the insulating layer 107 is 5×10 in SIM 19 S less than atoms / cm 3 , preferably 5×10 18 atoms / cm 3 or less, more preferably 1×10 18 atoms / cm 3 or less, even more preferably 5×10 17 atoms / cm 3 or less. 【0083】 Also, the insulating layer 107 is preferably formed using an insulating layer containing more oxygen than oxygen satisfying the stoichiometric composition. The insulating layer containing more oxygen than oxygen satisfying the stoichiometric composition has a part of oxygen desorbed by heating. The insulating layer containing more oxygen than oxygen satisfying the stoichiometric composition has an oxygen desorption amount, in terms of oxygen atoms, of 1.0×10 in TDS analysis 1 8 atoms / cm 3 Preferably 3.0 × 10 20 atoms / cm 3 That's all. This is an insulating layer. Note that the surface temperature of the film during the above TDS analysis was 100°C or higher. A temperature of 0°C or lower, or a range of 100°C to 500°C, is preferred. 【0084】 The thickness of the insulating layer 106 is 10 nm or more and 500 nm or less, preferably 50 nm or more and 300 nm or less. It should be less than or equal to m. 【0085】 [A-7: Oxide semiconductor layer 108] The oxide semiconductor layer 108 consists of oxide semiconductor layer 108a, oxide semiconductor layer 108b, and oxide semiconductor layer 108a. It has a structure in which conductive layers 108c are stacked. 【0086】 The oxide semiconductor layer 108a, oxide semiconductor layer 108b, and oxide semiconductor layer 108c are Formed from a material containing either indium or gallium, or both. Typically, I n-Ga oxide (oxide containing In and Ga), In-Zn oxide (oxide containing In and Zn) There are also In-M-Zn oxides (oxides containing In, element M, and Zn). 【0087】 Element M is preferably aluminum, gallium, yttrium, or tin. Other elements to which element M can be applied include boron, silicon, titanium, iron, and nickel. Germanium, yttrium, zirconium, molybdenum, lanthanum, cerium, neo Examples include gym, hafnium, tantalum, and tungsten. However, as for element M, as mentioned above... In some cases, it is acceptable to combine multiple elements. Element M, for example, has a bonding energy with oxygen. It is an element with high ghee. Element M is, for example, a mechanism that increases the energy gap of oxides. It is an element that possesses properties. The oxide semiconductor layer 108 is an oxide semiconductor containing element M. This is preferable. Furthermore, it is preferable that the oxide semiconductor contains zinc. When the oxide contains zinc, for example... For example, it makes it easier to crystallize oxides. 【0088】 However, oxide semiconductors are not limited to oxides containing indium. For example, zinc tin oxide or gallium tin oxide would also be acceptable. 【0089】 The oxide semiconductor layer 108 is formed by sputtering, CVD (Chemical Vapor Deposition method (MOCVD (Metal Organic Chemica) l Vapor Deposition) method, ALD (Atomic Layer Deposition) method, Position CVD, thermal CVD, or PECVD (Plasma-Enhanced CVD) This includes, but is not limited to, the Chemical Vapor Deposition (CVA) method. i) MBE (Molecular Beam Epitaxy) or PLD (Pu It is preferable to use the (L-type Laser Deposition) method for film deposition. In particular, MO When using CVD, ALD, or thermal CVD methods, plasma is not used, thus producing oxide semiconductors. This design minimizes damage to layer 108 and keeps the leakage current of the transistor in the off state low. This is preferable because it allows for this. 【0090】 For example, as the oxide semiconductor layer 108, InGaZnO is produced by thermal CVD. X (X>0) Forms a film When forming a film, trimethylindium, trimethylgallium, and dimethylzinc are used. The chemical formula for trimethylindium is In(CH3)3. The chemical formula for gallium is Ga(CH3)3. The chemical formula for dimethylzinc is Zn. It is (CH3)2. Furthermore, it is not limited to these combinations, and trimethylgallium can be substituted. Triethylgallium (chemical formula Ga(C2H5)3) can also be used, and dimethyl sulfate Diethylzinc (chemical formula Zn(C2H5)2) can also be used as a substitute for lead. 【0091】 For example, as the oxide semiconductor layer 108, InGaZnO is produced by the ALD method. X (X>0) Forms a film When forming a film, an InO2 layer is created by sequentially introducing In(CH3)3 gas and O3 gas repeatedly. After forming, Ga(CH3)3 gas and O3 gas are simultaneously introduced to form a GaO layer. Furthermore, Zn(CH3)2 and O3 gas are introduced simultaneously to form a ZnO layer. The order of these layers is not limited to this example. Also, by mixing these gases, an InGaO2 layer or In By forming mixed compound layers such as a ZnO2 layer, a GaInO layer, a ZnInO layer, and a GaZnO layer This is also good. Furthermore, instead of O3 gas, use H2O gas that has been bubbled with an inert gas such as Ar. It is also acceptable to use O3 gas, but it is preferable to use O3 gas that does not contain H. In(CH3)3 gas Instead, use In(C2H5)3 gas or tris(acetylacetonato)indium That's also good. Incidentally, tris(acetylacetonato)indium is also called In(acac)3. Also, instead of Ga(CH3)3 gas, Ga(C2H5)3 gas or Tris(acetyl) Gallium acetonato may be used. Note that tris(acetylacetonato)gallium is... It is also called Ga(acac)3. Furthermore, instead of In(CH3)3 gas, In(C2H5 )3 gas may be used. Alternatively, Zn(CH3)2 gas or zinc acetate may be used. It is not limited to these gas species. 【0092】 When depositing an oxide semiconductor layer 108 by sputtering, in order to reduce the number of particles, It is preferable to use a target containing indium. Furthermore, oxides with a high atomic ratio of element M are also preferable. When a target is used, the target's conductivity may decrease. (Contains indium) When using a target, the conductivity of the target can be increased, and DC discharge, AC discharge This makes it easier to handle large-area substrates. Therefore, the productivity of semiconductor devices It can improve. 【0093】 When depositing an oxide semiconductor layer 108 by sputtering, the atomic ratio of the target is I n:M:Zn is 3:1:1, 3:1:2, 3:1:4, 1:1:0.5, 1:1:1, 1 You can use :1:2, 1:4:4, and so on. 【0094】 When depositing an oxide semiconductor layer 108 by sputtering, the atomic ratio of the target is not determined. A film with an atomic ratio that is different from that of the target may be formed. In particular, zinc may have an atomic ratio that is different from that of the target. The atomic ratio of the film may become smaller. Specifically, the number of zinc atoms contained in the target. The ratio may be between 40 atomic% and approximately 90 atomic%. 【0095】 The oxide semiconductor layer 108a and the oxide semiconductor layer 108c constitute the oxide semiconductor layer 108b. It is preferable that the material be formed from a material containing one or more of the same metallic elements. It is desirable. When such materials are used, the oxide semiconductor layer 108a and the oxide semiconductor layer 10 Interface with 8b, and interface with oxide semiconductor layer 108c and oxide semiconductor layer 108b This makes it less likely for interface states to form. Therefore, carrier scattering and capture at the interface are reduced. This makes it less likely for this to occur, and it becomes possible to improve the field-effect mobility of the transistor. This makes it possible to reduce variations in the threshold voltage of the transistor. Therefore, good electrical performance can be achieved. This makes it possible to realize semiconductor devices with specific characteristics. 【0096】 The thickness of oxide semiconductor layer 108a and oxide semiconductor layer 108c is 3 nm to 100 nm. The following is preferably 3 nm to 50 nm. Also, the thickness of the oxide semiconductor layer 108b The wavelength is 3 nm to 200 nm, preferably 3 nm to 100 nm, and more preferably The size should be between 3nm and 50nm. 【0097】 Furthermore, the oxide semiconductor layer 108b is In-M-Zn oxide, and the oxide semiconductor layer 108a And when the oxide semiconductor layer 108c is also an In-M-Zn oxide, the oxide semiconductor layer 10 8a and the oxide semiconductor layer 108c are arranged in In:M:Zn=x1:y1:z1 [atomic ratio]. If the oxide semiconductor layer 108b is In:M:Zn=x2:y2:z2 [atomic ratio], then y Oxide semiconductor layer 108a, oxide semiconductor layer 108 where 1 / x1 is greater than y2 / x2 c and oxide semiconductor layer 108b are selected. Preferably, y1 / x1 is greater than y2 / x2. The oxide semiconductor layer 108a, oxide semiconductor layer 108c, and are larger by more than 1.5 times. Select the oxide semiconductor layer 108b. More preferably, y1 / x1 is greater than y2 / x2. The oxide semiconductor layer 108a, oxide semiconductor layer 108c, and oxide semiconductor layer become more than twice as large. Select the conductor layer 108b. More preferably, y1 / x1 is at least three times greater than y2 / x2 Select the oxide semiconductor layer 108a, the oxide semiconductor layer 108c, and the oxide semiconductor layer 108 b. At this time, in the oxide semiconductor layer 108b, it is preferable that when y1 is greater than or equal to x1, stable electrical characteristics can be imparted to the transistor. However, when y1 is more than three times x1, the field-effect mobility of the transistor decreases. Therefore, it is preferable that y1 is less than three times x1. By configuring the oxide semiconductor layer 108a and the oxide semiconductor layer 108c as described above, the oxide semiconductor layer 108a and the oxide semiconductor layer 108c can be made into layers in which oxygen deficiency is less likely to occur than in the oxide semiconductor layer 108b. Preferably, y1 is greater than or equal to x1, as this can impart stable electrical characteristics to the transistor. However, when y1 exceeds three times x1, the field-effect mobility of the transistor decreases. Therefore, it is preferable that y1 is less than three times x1. When y1 is more than three times x1, the field-effect mobility of the transistor decreases. Therefore, it is preferable that y1 is less than three times x1. By configuring the oxide semiconductor layer 108a and the oxide semiconductor layer 108c as described above, the oxide semiconductor layer 108a and the oxide semiconductor layer 108c can be made into layers in which oxygen deficiency is less likely to occur than in the oxide semiconductor layer 108b. By making the oxide semiconductor layer 108a and the oxide semiconductor layer 108c have the above configuration, the oxide semiconductor layer 108a and the oxide semiconductor layer 108c can be made into layers in which oxygen deficiency is less likely to occur than the oxide semiconductor layer 108b. In addition, when the oxide semiconductor layer 108a and the oxide semiconductor layer 108c are In-M-Zn oxides, and the sum of In and M is 100 atomic%, the atomic ratio of In to M is preferably less than 50 atomic% for In and 50 atomic% or more for M, and more preferably less than 25 atomic% for In and 75 atomic% or more for M. Also, when the oxide semiconductor layer 108b is an In-M-Zn oxide, and the sum of In and M is 100 atomic%, the atomic ratio of In to M is preferably 25 atomic% or more for In and less than 75 atomic% for M, and more preferably 34 atomic% or more for In and less than 66 atomic% for M. 【0098】 For example, as the oxide semiconductor layer 108a containing In or Ga and the oxide semiconductor layer 108c containing In or Ga, In:Ga:Zn = 1:3:2, 1:3:4, 1:3:6, When the sum of In and M is 100 atomic%, the atomic ratio of In to M is preferably less than 50 atomic% for In and 50 atomic% or more for M, and more preferably less than 25 atomic% for In and 75 atomic% or more for M. Preferably, In is less than 50 atomic% and M is 50 atomic% or more, and more preferably In is less than 25 atomic% and M is 75 atomic% or more. Further, when the oxide semiconductor layer 108b is an In-M-Zn oxide, and the sum of In and M is 100 atomic% %, the atomic ratio of In to M is preferably 25 atomic% or more for In and less than 75 atomic% for M, and more preferably 34 atomic% or more for In and less than 66 atomic% for M. Preferably, In is 25 atomic% or more and M is less than 75 atomic%, and more preferably In is 34 atomic% or more and M is less than 66 atomic%. For example, as the oxide semiconductor layer 108a containing In or Ga and the oxide semiconductor layer 108c containing In or Ga, In:Ga:Zn = 1:3:2, 1:3:4, 1:3:6, For example, as the oxide semiconductor layer 108a containing In or Ga and the oxide semiconductor layer 108c containing In or Ga, In:Ga:Zn = 1:3:2, 1:3:4, 1:3:6, 【0099】 For example, the oxide semiconductor layer 108a containing In or Ga, and the oxide semiconductor layer 108c containing In or Ga In:Ga:Zn = 1:3:2, 1:3:4, 1:3:6, In-Ga formed using a target with an atomic ratio of 1:6:4, 1:9:6, or the like -Zn oxide, or an In-Ga oxide formed using a target with an atomic ratio of In:Ga = 1:9, 7:93, or the like can be used. Also, regarding the oxide semiconductor layer 108b For example, an In-Ga-Zn oxide formed using a target with an atomic ratio of In:Ga:Zn = 1:1:1 or 3:1:2 can be used. Note that the atomic ratios of the oxide semiconductor layer 108a, the oxide semiconductor layer 108b, and the oxide semiconductor layer 108c each include fluctuations of plus or minus 20% of the above atomic ratios as an error. 【0100】 In order to impart stable electrical characteristics to the transistor using the oxide semiconductor layer 108, it is particularly preferable to reduce impurities and oxygen deficiencies in the oxide semiconductor layer 108 to achieve high purity intrinsicity, and make the oxide semiconductor layer 108 an oxide semiconductor layer that can be regarded as intrinsic or substantially intrinsic. Also, it is preferable that at least the channel formation region in the oxide semiconductor layer 108 is a semiconductor layer that can be regarded as intrinsic or substantially intrinsic. 【0101】 Note that an oxide semiconductor layer that can be regarded as substantially intrinsic refers to an oxide semiconductor layer in which the carrier density is less than 1×10 / cm 17 , less than 1×10 3 / cm 15 , or less than 1×10 3 / cm 13 3 【0102】 Here, regarding the function and effect of the oxide semiconductor layer 108 composed of the stack of the oxide semiconductor layer 108a, the oxide semiconductor layer 108b, and the oxide semiconductor layer 108c, refer to FIG. 6 ​​​​​​​​This will be explained using the energy band structure diagram shown. Figure 6 shows the C1-C2 section of Figure 1(C). The dashed lines indicate the energy band structure of the region shown. Figure 6 shows a transistor. This shows the energy band structure of 100 channel-forming regions. 【0103】 In Figure 6, Ec382, Ec383a, Ec383b, Ec383c, and Ec386 are... These are insulating layer 107, oxide semiconductor layer 108a, oxide semiconductor layer 108b, oxide semiconductor This shows the energy at the lower end of the conduction band in layer 108c and insulating layer 110. 【0104】 Here, the difference between the energy of the vacuum level and the energy of the lower end of the conduction band (also called "electron affinity") is true The difference between the energy of the empty level and the energy of the upper end of the valence band (also called the ionization potential) This is the value after subtracting the energy gap. Note that the energy gap is measured using a spectroscopic ellipsometer. Measurement can be performed using the HORIBA JOBIN YVON UT-300. The energy difference between the vacant level and the upper end of the valence band is determined by ultraviolet photoelectron spectroscopy (UPS). iolet Photoelectron Spectroscopy (PHI Corporation) It can be measured using VersaProbe. 【0105】 Furthermore, In-G was formed using a target with an atomic ratio of In:Ga:Zn=1:3:2. The energy gap of α-Zn oxide is approximately 3.5 eV, and the electron affinity is approximately 4.5 eV. Furthermore, In- formed using a target with an atomic ratio of In:Ga:Zn=1:3:4 The energy gap of Ga-Zn oxide is approximately 3.4 eV, and the electron affinity is approximately 4.5 eV. Furthermore, In formed using a target with an atomic ratio of In:Ga:Zn=1:3:6 The energy gap of the -Ga-Zn oxide is about 3.3 eV, and the electron affinity is about 4.5 eV There is. Also, using a target with an atomic ratio of In:Ga:Zn = 1:6:2, the I The energy gap of the n-Ga-Zn oxide is about 3.9 eV, and the electron affinity is about 4.3 eV is. Also, using a target with an atomic ratio of In:Ga:Zn = 1:6:8, the The energy gap of the In-Ga-Zn oxide is about 3.5 eV, and the electron affinity is about 4.4e V. Also, using a target with an atomic ratio of In:Ga:Zn = 1:6:10 to form The energy gap of the In-Ga-Zn oxide thus formed is about 3.5 eV, and the electron affinity is about 4. 5 eV. Also, using a target with an atomic ratio of In:Ga:Zn = 1:1:1 to form The energy gap of the In-Ga-Zn oxide thus formed is about 3.2 eV, and the electron affinity is about 4 .7 eV. Also, using a target with an atomic ratio of In:Ga:Zn = 3:1:2 to The energy gap of the In-Ga-Zn oxide thus formed is about 2.8 eV, and the electron affinity is about 5.0 eV. 【0106】 Since the insulating layer 107 and the insulating layer 110 are insulators, Ec382 and Ec386 are closer to the vacuum level (have a smaller electron affinity) than Ec38 3a, Ec383b, and Ec383c. . 【0107】 Also, Ec383a is closer to the vacuum level than Ec383b. Specifically, Ec383a is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0 .15 eV or more, and preferably closer to the vacuum level by 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less than Ec383b. 【0108】 Furthermore, Ec383c is closer to the vacuum level than Ec383b. Specifically, Ec383c This is 0.05eV or more, 0.07eV or more, 0.1eV or more, or 0 eV higher than Ec383b. 0.15eV or greater, and 2eV or less, 1eV or less, 0.5eV or less, or 0.4eV or less (true) It is preferable to be close to the empty level. 【0109】 Furthermore, near the interface between the oxide semiconductor layer 108a and the oxide semiconductor layer 108b, and the oxide Near the interface between the semiconductor layer 108b and the oxide semiconductor layer 108c, a mixed region is formed. Therefore, the energy at the lower end of the conduction band changes continuously. That is, at these interfaces, the levels are They either don't exist or are almost nonexistent. 【0110】 Therefore, in the laminated structure having the energy band structure, electrons are in the oxide semiconductor layer 1 The movement will mainly occur in 08b. Therefore, the oxide semiconductor layer 108a and the insulating layer 10 The energy level was present at the interface with 7, or at the interface between the oxide semiconductor layer 108c and the insulating layer 110. Even so, this level has almost no effect on electron movement. Also, oxide semiconductor layer 108a The interface between the oxide semiconductor layer 108b and the oxide semiconductor layer 108c and the oxide semiconductor layer 1 Because there are no or very few energy levels at the interface with 08b, electron movement occurs in that region. It does not inhibit either. Therefore, the transistor 10 having the above oxide semiconductor stacked structure A value of 0 allows for high field-effect mobility. 【0111】 Furthermore, as shown in Figure 6, the interface between the oxide semiconductor layer 108a and the insulating layer 107, and the oxide Near the interface between the semiconductor layer 108c and the insulating layer 110, trap levels are present due to impurities and defects. Although 390 may be formed, oxide semiconductor layer 108a and oxide semiconductor layer 108c This allows the oxide semiconductor layer 108b to be kept away from the trap level. ru. 【0112】 In particular, the transistor 100 illustrated in this embodiment has an oxide in the channel width direction. The top and side surfaces of the semiconductor layer 108b are in contact with the oxide semiconductor layer 108c, and the oxide semiconductor layer 108 The lower surface of b is formed in contact with the oxide semiconductor layer 108a (see Figure 1(C)). Thus, the oxide semiconductor layer 108b is made of oxide semiconductor layer 108a and oxide semiconductor layer 108c By using a covering configuration, the influence of the above-mentioned trap levels can be further reduced. 【0113】 However, in the case where the energy difference between Ec383a or Ec383c and Ec383b is small In addition, electrons in the oxide semiconductor layer 108b exceed the energy difference and reach the trap level. There is a trap level where electrons are trapped, creating a negative fixed charge at the interface of the insulating layer. As a result, the transistor's threshold voltage shifts in the positive direction. 【0114】 Therefore, the energy difference between Ec383a and Ec383c and Ec383b is... If each is set to 0.1 eV or higher, preferably 0.15 eV or higher, the threshold voltage of the transistor Because the pressure fluctuations are reduced and the electrical characteristics of the transistor can be improved, It seems so. 【0115】 Furthermore, the band gaps of the oxide semiconductor layer 108a and the oxide semiconductor layer 108c are acid It is preferable that the band gap is wider than that of the synthetic semiconductor layer 108b. 【0116】 [About oxide semiconductors] The following section provides a detailed description of oxide semiconductors applicable to the oxide semiconductor layer 108. 【0117】 Applicable to oxide semiconductor layer 108a, oxide semiconductor layer 108b, and oxide semiconductor layer 108c. Oxide semiconductors are oxides containing indium. Oxides, for example, contain indium. This increases carrier mobility (electron mobility). 【0118】 However, oxide semiconductors are not limited to oxides containing indium. For example, zinc tin oxide or gallium tin oxide would also be acceptable. 【0119】 Furthermore, oxide semiconductors use oxides with a large energy gap. The energy gap is, for example, between 2.5 eV and 4.2 eV, preferably 2.8 eV or more. The voltage should be 3.8 eV or less, and more preferably 3 eV to 3.5 eV. 【0120】 The following section explains the effects of impurities in oxide semiconductors. To stabilize its electrical properties, the impurity concentration in the oxide semiconductor is reduced, and the carrier density is low. It is effective to improve the degree of oxidation and increase the purity. The carrier density of oxide semiconductors is 1 × 10 17 pieces / cm 3 Less than 1 × 10 15 pieces / cm 3 Less than, or 1 × 10⁻⁶ 13 pieces / cm 3 It shall be less than. In order to reduce the impurity concentration in oxide semiconductors, the impurity concentration in adjacent films shall be reduced. It is preferable to reduce the degree as well. 【0121】 For example, silicon in oxide semiconductors can act as a carrier trap or carrier source. Therefore, silicon between the oxide semiconductor and the insulating layer 107 and insulating layer 110 The ion concentration is measured by secondary ion mass spectrometry (SIMS). In spectrometry, 1 × 10 19 atoms / cm 3 Less than, preferably is 5 x 10 18 atoms / cm 3 Less than 2 × 10 18 ate / c m 3 Less than. 【0122】 The structure of oxide semiconductors will be described below. 【0123】 Oxide semiconductors can be further divided into, for example, non-single-crystal oxide semiconductors and single-crystal oxide semiconductors. Alternatively, oxide semiconductors can be divided into, for example, crystalline oxide semiconductors and amorphous oxide semiconductors. Non-single-crystal oxide semiconductors are CAAC-OS (C Axis Aligned C). rystalline Oxide Semiconductor), polycrystalline oxide semiconductor These include solid oxide semiconductors, microcrystalline oxide semiconductors, and amorphous oxide semiconductors. Furthermore, crystalline oxide semiconductors... These include single-crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and microcrystalline oxide semiconductors. It has a body, etc. 【0124】 《CAAC-OS》 First, let me explain CAAC-OS. 【0125】 CAAC-OS is an oxide semiconductor having multiple c-axis oriented crystalline portions (also called pellets). It is a type of conductor. 【0126】 Transmission Electron Microscope (TEM) A composite analysis image of the bright-field image and diffraction pattern of CAAC-OS (high-angle scope) is obtained. By observing a high-resolution TEM image (also known as a high-resolution TEM image), multiple pellets can be identified. On the other hand, high-resolution TEM images also clearly show the boundaries between pellets, i.e., grain boundaries. Also called a boundary. ) It is not possible to confirm this. Therefore, CAAC-OS is not This means that a decrease in electron mobility due to grain boundaries is less likely to occur. 【0127】 For example, as shown in Figure 7(A), the cross-section of CAAC-OS is viewed from a direction approximately parallel to the sample surface. High-resolution TEM images are observed. Here, spherical aberration correction is performed. Observe the TEM image using the (ration Corrector) function. Note that spherical aberration In the following, high-resolution TEM images obtained using correction functions will be specifically referred to as Cs-corrected high-resolution TEM images. Furthermore, the acquisition of Cs-corrected high-resolution TEM images can be performed using, for example, an atomic-resolution TEM manufactured by JEOL Ltd. This can be done using an electron analyzer microscope such as the JEM-ARM200F. 【0128】 Figure 7(B) shows a magnified Cs-corrected high-resolution TEM image of region (1) in Figure 7(A). (B) confirms that in the pellet, metal atoms are arranged in layers. Each atomic layer is a concave surface (also called the surface to be formed) or upper surface that forms the CAAC-OS film. The shape reflects a convexity and is arranged parallel to the surface or top surface of the CAAC-OS. 【0129】 In Figure 7(B), CAAC-OS has a characteristic atomic arrangement. Figure 7(C) shows the characteristic The typical atomic arrangement is shown with auxiliary lines. From Figures 7(B) and 7(C), Peret The size of each pellet is approximately 1 nm to 3 nm, and the tilt of the pellets It can be seen that the size of the resulting gap is about 0.8 nm. Therefore, the pellet is made of na They can also be called nanocrystals (nc: nanocrystal). 【0130】 Here, from the Cs-corrected high-resolution TEM image, the CAAC-OS pellets 5 on substrate 5120 are shown. A schematic representation of the arrangement of 100 would be a structure resembling stacked bricks or blocks. (See Figure 7(D).) A tilt occurs between the pellets as observed in Figure 7(C). The area in question corresponds to region 5161 shown in Figure 7(D). 【0131】 Furthermore, as shown in Figure 8(A), for example, from a direction approximately perpendicular to the sample surface, the CAAC-OS Observe the planar Cs-corrected high-resolution TEM image. Regions (1) and (2) in Figure 8(A) Cs-corrected high-resolution TEM images with the region (3) enlarged are shown in Figure 8(B) and Figure 8(C), respectively. And shown in Figure 8(D). From Figures 8(B), 8(C), and 8(D), the pellets are It can be confirmed that metal atoms are arranged in a triangular, square, or hexagonal shape. However, However, no regularity is observed in the arrangement of metal atoms between different pellets. 【0132】 For example, X-ray diffraction (XRD:X) is performed on CAAC-OS having an InGaZnO4 crystal. - Ray Diffraction) apparatus used with out-of-plane method When the diffraction analysis is performed, a peak appears near 31° in the diffraction angle (2θ), as shown in Figure 9(A). In some cases, this peak may be attributed to the (009) plane of the InGaZnO4 crystal. Furthermore, the CAAC-OS crystals have c-axis orientation, and the c-axis is approximately perpendicular to the surface being formed or the upper surface. It can be confirmed that it is facing forward. 【0133】 Furthermore, the out-of-plane method for CAAC-OS containing InGaZnO4 crystals Structural analysis revealed that in addition to a peak near 2θ = 31°, a peak also appeared near 2θ = 36°. In some cases, this may occur. Peaks near 36° 2θ indicate c-axis orientation in a portion of CAAC-OS. This indicates that it contains crystals that do not have [the specified characteristic]. CAAC-OS has a 2θ of approximately 31°. It is preferable that the curve is shown and that 2θ does not show a peak near 36°. 【0134】 On the other hand, for CAAC-OS, X-rays are incident from a direction approximately perpendicular to the c-axis in an in-plan configuration. Structural analysis using the e method reveals a peak near 2θ = 56°. This peak corresponds to In It is attributed to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is 56 The sample is fixed in the vicinity of °, and the analysis is performed while rotating the sample around the normal vector of the sample surface as the axis (φ axis). Even after performing a φ scan, no clear peak appears, as shown in Figure 9(B). For a single-crystal oxide semiconductor of InGaZnO4, if 2θ is fixed to around 56°, the φ gap When this occurs, the peaks are attributed to the crystal plane equivalent to the (110) plane, as shown in Figure 9(C). Six of these are observed. Therefore, from structural analysis using XRD, CAAC-OS is a-axis. Furthermore, it can be confirmed that the orientation of the b-axis is irregular. 【0135】 Next, for the CAAC-OS In-Ga-Zn oxide, a direction parallel to the sample surface is applied. Diffraction pattern when an electron beam with a lobe diameter of 300 nm is incident (limited field transmission electron diffraction) Also called a pattern.) is shown in Figure 10(A). From Figure 10(A), for example, InGaZn Spots originating from the (009) plane of the O4 crystal are observed. Therefore, electron diffraction However, the pellets contained in CAAC-OS have c-axis orientation, and the c-axis is aligned with the surface to be formed or It can be seen that it is oriented in a direction approximately perpendicular to the upper surface. On the other hand, for the same sample, perpendicular to the sample surface Figure 10(B) shows the diffraction pattern when an electron beam with a probe diameter of 300 nm is incident from that direction. As shown in Figure 10(B), a ring-shaped diffraction pattern can be observed. Therefore, electron Diffraction also shows that the a-axis and b-axis of the pellets contained in CAAC-OS do not have orientation. It can be seen that the first ring in Figure 10(B) is a crystal of InGaZnO4. This is thought to be caused by the (010) plane and the (100) plane, etc. Also, in Figure 10(B) The second ring is thought to be caused by the (110) plane, etc. 【0136】 Thus, the c-axis of each pellet (nanocrystal) is approximately perpendicular to the surface being formed or the upper surface. Because it is facing in a certain direction, CAAC-OS is CANC (C-Axis Aligned It can also be called an oxide semiconductor containing nanocrystals. 【0137】 CAAC-OS is an oxide semiconductor with a low impurity concentration. The impurities are hydrogen, carbon, silica. These are elements other than the main components of oxide semiconductors, such as transition metals. In particular, silicon. The element that has a stronger bonding force with oxygen than the metal elements that make up oxide semiconductors is the element that makes up the oxide semiconductor. By removing oxygen, the atomic arrangement of oxide semiconductors is disrupted, leading to a decrease in crystallinity. Furthermore, heavy metals such as iron and nickel, argon, and carbon dioxide have atomic radii (or molecular weight). Because of its large radius, when it is contained within an oxide semiconductor, it disrupts the atomic arrangement of the oxide semiconductor. This is a factor that reduces crystallinity. Furthermore, impurities contained in oxide semiconductors are carrier transistors. It can be a source of splatter or carrier activity. 【0138】 Furthermore, CAAC-OS is an oxide semiconductor with a low defect level density. For example, oxide semiconductors Oxygen deficiency throughout the body can act as a carrier trap, or by capturing hydrogen, it can lead to the development of carriers. A can be a source of contamination. 【0139】 Furthermore, transistors using CAAC-OS exhibit electrical properties that change with visible light and ultraviolet light irradiation. The fluctuations are small. 【0140】 Microcrystalline oxide semiconductor Next, we will explain microcrystalline oxide semiconductors. 【0141】 Microcrystalline oxide semiconductors are regions where crystalline parts can be observed in high-resolution TEM images. It has regions where a clear crystalline structure cannot be identified. It is contained in microcrystalline oxide semiconductors. The crystalline portion is between 1 nm and 100 nm in size, or between 1 nm and 10 nm in size. This is often the case. In particular, microcrystals between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor having nanocrystals is called nc-OS (nanocrystalline It is called Oxide Semiconductor. Also, nc-OS is, for example, high In high-resolution TEM images, grain boundaries may not be clearly visible. Note that nanocrystals are C It may have the same origin as the pellets in AAC-OS. Therefore, n The crystalline portion of c-OS is sometimes referred to as a pellet. 【0142】 nc-OS is used in minute regions (for example, regions between 1 nm and 10 nm, especially between 1 nm and 3 nm). The atomic arrangement has periodicity in the region of less than nm. In addition, nc-OS has different pellets. No regularity in crystal orientation is observed between the layers. Therefore, no orientation is observed throughout the entire film. Therefore, depending on the analysis method, nc-OS may be indistinguishable from amorphous oxide semiconductors. For example, an XRD device that uses X-rays with a larger diameter than pellets compared to nc-OS. When structural analysis is performed using this method, the out-of-plane method shows that the crystal planes are visible. No peak is detected. Also, nc-OS has a larger probe diameter than the pellet (for example) When electron diffraction (also called limited-field electron diffraction) is performed using an electron beam of 50 nm or more, A diffraction pattern resembling a halo pattern is observed. On the other hand, for nc-OS, pellet A probe diameter that is close in size to or smaller than the pellet (for example, between 1 nm and 30 nm) When electron diffraction using an electron beam (hereinafter also called nanobeam electron diffraction) is performed, the spot is It is observed. Also, when nanobeam electron diffraction is performed on nc-OS, it forms a circular pattern ( In some cases, areas of high brightness (in a ring-like pattern) may be observed. Also, with respect to nc-OS, nanobeam When electron diffraction is performed, multiple spots may be observed within a ring-shaped region. 【0143】 Thus, since the crystal orientation of each pellet (nanocrystal) does not have any regularity, nc-OS has NANC (Non-Aligned nanocrystals) It can also be called an oxide semiconductor. 【0144】 nc-OS is an oxide semiconductor with higher orderliness than amorphous oxide semiconductors. Therefore, nc-OS has a lower defect level density than amorphous oxide semiconductors. However, nc-OS There is no regularity in crystal orientation between different pellets. Therefore, nc-OS is CA Compared to AC-OS, the defect level density is higher. 【0145】 Amorphous oxide semiconductors Next, we will explain amorphous oxide semiconductors. 【0146】 Amorphous oxide semiconductors are oxides in which the atomic arrangement in the film is irregular and which do not have crystalline regions. It is a semiconductor. One example is an oxide semiconductor that has an amorphous state, such as quartz. 【0147】 In amorphous oxide semiconductors, the crystalline structure cannot be observed in high-resolution TEM images. 【0148】 When structural analysis of amorphous oxide semiconductors is performed using an XRD device, out-of-pl Analysis using the ANE method does not detect any peaks indicating crystal planes. Furthermore, amorphous oxide semiconductors... When electron diffraction is performed on a material, a halo pattern is observed. Furthermore, amorphous oxide semiconductors... In contrast, when nanobeam electron diffraction is performed, no spots are observed, but a halo pattern is observed. It can be done. 【0149】 Various views have been expressed regarding amorphous structures. For example, some argue that the atomic arrangement has absolutely no order. A structure that does not have a completely amorphous structure It is sometimes called the cture. Also, up to the nearest neighbor distance or the second nearest neighbor distance. A structure that possesses order but lacks long-range order is sometimes called an amorphous structure. According to the most rigorous definition, an amorphous oxide semiconductor is defined as an oxide semiconductor that has even a slight order in its atomic arrangement. It cannot be called a crystalline oxide semiconductor. Furthermore, it is an oxide with long-range order. A semiconductor cannot be called an amorphous oxide semiconductor. Therefore, since it has crystalline parts, For example, CAAC-OS and nc-OS are amorphous oxide semiconductors or completely amorphous acids It cannot be called a monstrous semiconductor. 【0150】 Furthermore, oxide semiconductors have a structure that exhibits physical properties between nc-OS and amorphous oxide semiconductors. In some cases, oxide semiconductors having such a structure are called amorphous-like oxide semiconductors. (a-like OS:amorphous-like Oxide Semiconductor It is called a uctor. 【0151】 a-like OS exhibits porosity (also called voids) in high-resolution TEM images. In some cases, the crystalline region can be clearly identified in high-resolution TEM images. It has a region where the crystalline part cannot be identified, and a region where the crystalline part cannot be identified. 【0152】 The following section explains the differences in the effects of electron irradiation depending on the structure of the oxide semiconductor. 【0153】 a-like OS (Sample A), nc-OS (Sample B), and CAAC-OS (Sample C) Prepare the following. All samples are In-Ga-Zn oxide. 【0154】 First, high-resolution cross-sectional TEM images are obtained for each sample. It can be seen that all of them have crystalline parts. 【0155】 Furthermore, the size of the crystalline portion of each sample is measured. Figure 11 shows the crystalline portion of each sample (from 22 locations). This is an example of investigating the change in the average size of 45 locations. Figure 11 shows a-like OS. This shows that the crystalline portion grows larger in proportion to the cumulative amount of electron irradiation. Specifically, Figure As shown in (1) in 11, the size is approximately 1.2 nm in the initial stages of TEM observation. The crystalline region (also called the initial nucleus) was irradiated with a cumulative dose of 4.2 × 10⁻¹⁴.8 e - / nm 2 smell It can be seen that it has grown to a size of about 2.6 nm. On the other hand, nc-OS and C AAC-OS has a cumulative electron dose of 4.2 × 10⁻¹⁴ from the start of electron irradiation. 8 e - / nm 2 to Within the range up to this point, no change in the size of the crystal region is observed regardless of the cumulative electron irradiation dose. I understand. Specifically, as shown in (2) in Figure 11, nc-OS is used for TEM observation. Regardless of the time elapsed, the size of the crystalline portion is approximately 1.4 nm. Also, CAAC- As shown in (3) in Figure 11, the OS is determined by the size of the crystal portion, regardless of the progress of TEM observation. It can be seen that the size is approximately 2.1 nm. 【0156】 Thus, a-like OS can be detected by minute electron irradiation, such as that required for observation by TEM. Crystallization may occur, and growth of the crystalline portion may be observed. On the other hand, with high-quality nc-OS, With CAAC-OS, crystallization by minute electron irradiation, such as that observed by TEM, is almost impossible. I realize that it won't be seen. 【0157】 Furthermore, the size of the crystal portion of a-like OS and nc-OS was measured using high-resolution TEM. This can be done using an image. For example, the crystal of InGaZnO4 has a layered structure, In -There are two Ga-Zn-O layers between the O layers. The unit cell of the InGaZnO4 crystal is, It has three In-O layers and six Ga-Zn-O layers, for a total of nine layers arranged in layers along the c-axis. It has an overlapping structure. Therefore, the spacing between these adjacent layers is the grid of the (009) plane. It is approximately the same as the interplanar spacing (also called the d-value), and its value was determined to be 0.29 nm from crystal structure analysis. Therefore, focusing on the grid lines in high-resolution TEM images, the spacing between grid lines is 0 In areas between 0.28nm and 0.30nm, each lattice fringe is InGaZ This corresponds to the ab-plane of the nO4 crystal. 【0158】 Furthermore, oxide semiconductors can have different densities depending on their structure. For example, a certain oxide semiconductor If the composition is known, then by comparing it with the density of a single crystal with the same composition, the The structure of oxide semiconductors can be estimated. For example, for the density of a single crystal, a-lik The density of e OS is between 78.6% and 92.3%. Also, for example, the density of a single crystal In contrast, the density of nc-OS and CAAC-OS is between 92.3% and less than 100%. Furthermore, oxide semiconductors with a density of less than 78% of the density of a single crystal cannot be formed into a film. I am in a physical condition. 【0159】 The above will be explained using a concrete example. For example, In:Ga:Zn=1:1:1[atom In an oxide semiconductor satisfying the numerical ratio, a single crystal InGaZnO4 having a rhombohedral crystal structure The density is 6.357 g / cm³. 3 Therefore, for example, In:Ga:Zn=1:1:1[ In an oxide semiconductor satisfying the [atomic ratio], the density of a-like OS is 5.0 g / cm³. 3 More than 5.9g / cm 3 It becomes less than. Also, for example, In:Ga:Zn=1:1:1[original In an oxide semiconductor satisfying the [number of particles ratio], the density of nc-OS and the density of CAAC-OS It is 5.9 g / cm³ 3 More than 6.3g / cm 3 It will be less than. 【0160】 Note that single crystals with the same composition may not exist. In that case, crystals with different compositions in arbitrary proportions may be found. By combining single crystals, it is possible to calculate the density corresponding to a single crystal with a desired composition. Yes, it is possible. The density of a single crystal of the desired composition depends on the ratio of single crystals with different compositions combined. The density can be calculated using a weighted average. However, the density should be calculated using as few types of single crystals as possible. It is preferable to calculate by combining the two factors. 【0161】 Oxide semiconductors include, for example, amorphous oxide semiconductors, a-like OS, and microcrystalline oxide semiconductors. The film may be a multilayer film containing two or more materials, including a monocrystalline semiconductor and CAAC-OS. 【0162】 Oxide semiconductors with low impurity concentrations and low defect level density (few oxygen vacancies) are carriers The density can be reduced. Therefore, such oxide semiconductors can be made into high-purity intrinsic or These are essentially called high-purity intrinsic oxide semiconductors. CAAC-OS and nc-OS are a- It has lower impurity concentrations and lower defect level densities than like OS and amorphous oxide semiconductors. In other words, it tends to become a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Therefore Transistors using CAAC-OS or nc-OS have a negative threshold voltage. It rarely exhibits the electrical properties (also called normally-on). Furthermore, it is highly pure and intrinsic. In essence, high-purity intrinsic oxide semiconductors have few carrier traps. Therefore, CAA Transistors using C-OS or ncOS exhibit less variation in electrical characteristics and are highly reliable. This results in a high transistor. Furthermore, the charge trapped in the carrier trap of the oxide semiconductor is It can take a long time to release, sometimes behaving as if it were a fixed charge. Therefore, transistors using oxide semiconductors with high impurity concentrations and high defect level densities are electric. The weather characteristics may become unstable. 【0163】 <Film deposition model> The following describes an example of a film deposition model for CAAC-OS and nc-OS. 【0164】 Figure 12(A) shows the deposition process of CAAC-OS by sputtering. This is a schematic diagram of the interior. 【0165】 Target 5130 is bonded to the backing plate. Multiple magnets are placed in positions facing the target 5130. A magnetic field is generated by the magnet. The magnetic field from the magnet is used to increase the film deposition rate. The sputtering method is also known as magnetron sputtering. 【0166】 Target 5130 has a polycrystalline structure, and each of its grains contains a cleavage plane. 【0167】 As an example, the cleavage plane of target 5130, which has an In-Ga-Zn oxide, will be described. Figure 13(A) shows the crystal structure of InGaZnO4 contained in target 5130. As shown, Figure 13(A) shows InGaZnO with the c-axis pointing upwards and the b-axis parallel to it. This is the structure when observing crystal 4. 【0168】 Figure 13(A) shows that in two adjacent Ga-Zn-O layers, the acid in each layer It can be seen that elementary atoms are located in close proximity to each other. And, oxygen atoms have a negative charge. As a result, the two adjacent Ga-Zn-O layers repel each other. A ZnO4 crystal has a cleavage plane between two adjacent Ga-Zn-O layers. 【0169】 The substrate 5120 is positioned facing the target 5130, and the distance d(t The distance between the board and the substrate (also called the TS distance) is preferably 0.01m or more and 1m or less. The depth should be between 0.02 m and 0.5 m. The deposition chamber should be mostly filled with deposition gas (e.g., acid Filled with a mixed gas containing 5% or more by volume of ammonium, argon, or oxygen, and 0.01 The pressure is controlled to be between Pa and 100 Pa, preferably between 0.1 Pa and 10 Pa. By applying a voltage above a certain level to target 5130, discharge begins and plasma is confirmed. It is confirmed. Furthermore, a high-density plasma region is formed in the vicinity of target 5130 by the magnetic field. This is achieved. In the high-density plasma region, the film deposition gas is ionized, and ion 5101 is produced. It occurs. Ion 5101 is, for example, the cation of oxygen (O + ) and argon cations (A r + ) and so on. 【0170】 Ion 5101 is accelerated toward target 5130 by the electric field, and eventually reaches target 5 It collides with 130. At this time, the sputtered particles are flat or pellet-shaped from the cleavage plane. Pellet 5100a and pellet 5100b are detached and knocked out. 5100a and pellet 5100b undergo structural changes due to the impact of collisions with ion 5101. Distortion may occur. 【0171】 Pellet 5100a is a flat plate or pellet having a triangular, for example, equilateral triangle plane. These are sputtered particles. Also, pellet 5100b has a hexagonal, for example, regular hexagonal plane. These are flat or pellet-shaped sputtered particles. Note that pellet 5100a and Pellet 5100b and other flat or pellet-shaped sputtered particles are collectively referred to as pellet 5 It is called 100. The planar shape of pellet 5100 is not limited to triangles or hexagons, for example. In some cases, the shape may be formed by combining multiple triangles. For example, a triangle (for example, an equilateral triangle) In some cases, the shape may be a quadrilateral (for example, a rhombus) formed by combining two of the shapes. 【0172】 The thickness of pellet 5100 is determined by the type of film-forming gas used, etc. The reason will be explained later. The thickness of the pellet 5100 is preferably uniform. Also, the sputtered particles have a uniform thickness. A pellet shape is preferable to a thick, cube-shaped shape. T5100 has a thickness of 0.4 nm to 1 nm, preferably 0.6 nm to 0.8 nm. The following applies. Furthermore, for example, the pellet 5100 has a width of 1 nm to 3 nm, preferably. The size shall be between 1.2 nm and 2.5 nm. Pellet 5100 is (1) in Figure 11 above. This corresponds to the initial nucleus described above. For example, target 51 having In-Ga-Zn oxide. When ion 5101 is collided with 30, the Ga-Zn-O layer is as shown in Figure 13(B). Pellet 5100, which has three layers including an In-O layer and a Ga-Zn-O layer, is ejected. Figure 13(C) shows the structure of pellet 5100 when viewed from a direction parallel to the c-axis. Therefore, pellet 5100 consists of two Ga-Zn-O layers (pan) and In- It can also be called a nano-sized sandwich structure having an O layer (filling). 【0173】 Pellet 5100 receives an electric charge as it passes through the plasma, causing its sides to be negative or positive. It may become charged. Pellet 5100 has oxygen atoms on its side, and these oxygen atoms are negatively charged. It can become charged. In this way, the sides carry charges of the same polarity, Repulsion occurs between them, making it possible to maintain a flat shape. However, in the case of In-Ga-Zn oxide, the oxygen atom bonded to the indium atom is negatively charged. It is possible that an acid bonded to an indium atom, gallium atom, or zinc atom may be involved. Elementary atoms can become negatively charged. Also, when pellet 5100 passes through the plasma... It grows by bonding with indium atoms, gallium atoms, zinc atoms, and oxygen atoms, etc. This can occur. The difference in size between (2) and (1) in Figure 11 above indicates growth in plasma. This corresponds to minutes. Here, if the substrate 5120 is at room temperature, the pellet 5100 will last for a certain amount of time. Because it does not grow upwards, it becomes nc-OS (see Figure 12(B)). The temperature at which the film can be deposited is around room temperature. Therefore, nc-OS film deposition is possible even when the substrate 5120 has a large area. Furthermore, in order to grow pellet 5100 in plasma, the sputtering method is used. Increasing the film deposition power is effective. By increasing the film deposition power, the pellet 5100 It can stabilize the structure. 【0174】 As shown in Figures 12(A) and 12(B), for example, pellet 5100 is plasma It flies through the air like a kite, fluttering upwards onto circuit board 5120. Pellet 51 Because 00 is charged, it approaches an area where other pellets 5100 have already accumulated. This generates a repulsive force. Here, on the upper surface of the substrate 5120, in an orientation parallel to the upper surface of the substrate 5120 A magnetic field (also called a horizontal magnetic field) is generated. Also, the substrate 5120 and target 51 Since a potential difference is applied between 30, from substrate 5120 to target 5130 And current is flowing. Therefore, on the upper surface of the substrate 5120, A force (Lorentz force) is exerted by the action of a magnetic field and electric current. This is what Fleming described. This can be understood through the left-hand rule. 【0175】 Pellet 5100 has a larger mass than a single atom. Therefore, the upper surface of substrate 5120 In order to move something, it is important to apply some kind of external force. One of those forces is magnetism. It is possible that this force is generated by the action of a field and an electric current. In order to increase this, on the upper surface of the substrate 5120, in an orientation parallel to the upper surface of the substrate 5120 The magnetic field is 10G or more, preferably 20G or more, more preferably 30G or more. It is preferable to provide an area where the value is 50G or more. Alternatively, on the upper surface of the substrate 5120, The magnetic field parallel to the top surface of 5120 is 1.5 times the magnetic field perpendicular to the top surface of substrate 5120. More than double, preferably more than 2 times, more preferably more than 3 times, and more preferably more than 5 times. It would be good to create a designated area. 【0176】 At this time, the magnet and the substrate 5120 move or rotate relative to each other. Therefore, the direction of the horizontal magnetic field on the upper surface of the substrate 5120 continues to change. On the upper surface of 5120, the pellet 5100 is subjected to forces in various directions, and in various directions It can be moved. 【0177】 Furthermore, as shown in Figure 12(A), when the substrate 5120 is heated, the pellet 5100 The resistance between the pellet and the substrate 5120 due to friction and other factors is low. As a result, The pellet 5100 moves as if gliding across the top surface of the substrate 5120. The movement occurs with the flat surface facing the substrate 5120. Subsequently, other particles already deposited... When it reaches the side of the pellet 5100, the sides connect. At this point, pellet 510 The oxygen atom on the 0 side is eliminated. The eliminated oxygen atom then acts as an acid in CAAC-OS. Because primary defects may be filled, CAAC-OS results in a low defect level density. The temperature of the top surface of the 5120 is, for example, between 100°C and 500°C, and between 150°C and 450°C. It should be full, or between 170°C and 400°C. That is, the substrate 5120 has a large surface area. Even in this case, CAAC-OS film deposition is possible. 【0178】 Furthermore, when the pellet 5100 is heated on the substrate 5120, the atoms rearrange, The structural strain caused by the impact of ON 5101 is relieved. The strain-relieved pellet 510 0 is almost a single crystal. Because pellet 5100 is almost a single crystal, pellet 5 Even if the 100 pellets are heated after bonding together, the expansion and contraction of the 5100 pellets themselves is minimal. This is impossible. Therefore, the gaps between pellets 5100 will widen, causing defects such as grain boundaries. It does not form depressions or crevasses. 【0179】 Furthermore, CAAC-OS is not made of a single sheet of single-crystal oxide semiconductor, The aggregate of pellet 5100 (nanocrystals) is arranged like a stack of bricks or blocks. They are arranged in rows. Furthermore, there are no grain boundaries between them. Therefore, heating during film formation and after film formation. Even if deformation such as shrinkage occurs in CAAC-OS due to heating or bending, local stress It is possible to alleviate or release the strain. Therefore, flexible semiconductors It has a structure suitable for body devices. Furthermore, nc-OS uses pellet 5100 (nanocrystalline) without any constraints. The arrangement is like a series of overlapping elements. 【0180】 When a target is sputtered with ions, not only pellets but also zinc oxide and other materials are ejected. In some cases, zinc oxide, being lighter than pellets, reaches the top surface of substrate 5120 first. And, 0.1nm to 10nm, 0.2nm to 5nm, or 0.5 A zinc oxide layer 5102 with a wavelength of 2 nm or more is formed. A schematic cross-sectional view is shown in Figure 14. 【0181】 As shown in Figure 14(A), pellets 5105a and pellets are placed on the zinc oxide layer 5102. 5105b and pellet 5105b are deposited. Here, pellet 5105a and pellet 5105b are mutual They are arranged so that their sides are in contact with each other. Also, pellet 5105c is pellet 5105 After being deposited on b, it moves by sliding on pellet 5105b. Also, pellet 510 In another aspect of 5a, multiple particles 510 ejected from the target along with zinc oxide. 3 crystallizes upon heating of the substrate 5120, forming region 5105a1. Note that there are multiple grains. Substance 5103 may contain oxygen, zinc, indium, and gallium, among other things. 【0182】 Then, as shown in Figure 14(B), region 5105a1 assimilates with pellet 5105a. This becomes pellet 5105a2. Also, pellet 5105c has its side surface as pellet 51 Position it so that it is in contact with another side of 05b. 【0183】 Next, as shown in Figure 14(C), pellet 5105d is further placed on pellet 5105a2. And after being deposited on pellet 5105b, on pellet 5105a2 and pellet 51 It moves smoothly along 05b. It also moves towards another side of pellet 5105c. The pellet 5105e moves smoothly across the zinc oxide layer 5102. 【0184】 Then, as shown in Figure 14(D), the side of pellet 5105d is that of pellet 510 It is positioned so as to be in contact with the side of 5a2. Also, pellet 5105e has its side facing the pellet Position it so as to be in contact with another side of pellet 5105c. Also, position it so as to be in contact with another side of pellet 5105d. In this case, multiple particles 5103 that were ejected from the target along with zinc oxide onto the substrate 512 Upon heating at 0, crystallization occurs, forming region 5105d1. 【0185】 As described above, the piled pellets are arranged so that they are in contact with each other, and the sides of the pellets are formed As lengthening occurs, CAAC-OS is formed on the substrate 5120. Therefore, CAA C-OS pellets are larger than nc-OS pellets. (3) The difference in size between (1) and (2) corresponds to the growth after deposition. 【0186】 Furthermore, the gaps between the pellets 5100 become extremely small, allowing for the formation of one large pellet. This can happen. Large pellets have a single-crystal structure. For example, large pellets The size, when viewed from the top, is between 10nm and 200nm, and between 15nm and 100nm. Alternatively, it may be between 20nm and 50nm. Therefore, the transistor channel When the formation region is smaller than the large pellet, it has a single-crystal structure as a channel-forming region. This allows the use of a larger area. Also, as the pellet size increases, the transistor's chip size Regions having a single-crystal structure are used as the channel formation region, source region, and drain region. It is sometimes possible. 【0187】 Thus, the channel formation region of the transistor, etc., is formed in a region having a single crystal structure. This can sometimes improve the frequency characteristics of a transistor. 【0188】 Based on the above model, it is thought that the pellets 5100 will accumulate on the substrate 5120. Therefore, unlike epitaxial growth, if the surface to be formed does not have a crystalline structure... It can be seen that CAAC-OS can be deposited even in this case. For example, substrate 5120 Even if the structure of the upper surface (the surface to be formed) is amorphous (for example, amorphous silicon oxide), CAA It is possible to deposit C-OS into a film. 【0189】 Furthermore, CAAC-OS can be used even if the upper surface of the substrate 5120, which is the surface to be formed on, has irregularities. It can be seen that the pellets 5100 are arranged according to the shape. For example, the upper surface of the substrate 5120 If it is atomically flat, the pellet 5100 has a flat surface that is parallel to the ab plane. Arrange them side by side facing each other. If the thickness of the pellet 5100 is uniform, the thickness is uniform, flat, and high A crystalline layer is formed. Then, when n layers (where n is a natural number) are stacked on top of each other... And with that, you can obtain CAAC-OS. 【0190】 On the other hand, even if the upper surface of the substrate 5120 has irregularities, CAAC-OS can still use pellets 510 The structure consists of n layers (where n is a natural number) in which zeros are juxtaposed along the contours. (Substrate 51) Because 20 has an uneven surface, CAAC-OS is prone to gaps forming between pellets 5100. There is a fit. However, intermolecular forces act between pellets 5100, and even if there are irregularities between the pellets The gaps are arranged to be as small as possible. Therefore, even if there are irregularities, high crystallinity is achieved. It can be made into CAAC-OS. 【0191】 Therefore, CAAC-OS does not require laser crystallization and can be used on large-area glass substrates, etc. Even if there are particles present, uniform film formation is possible. 【0192】 Because CAAC-OS is deposited using this model, the sputtered particles have no thickness. Pellet-like form is preferable. Note that if the sputtered particles are in the form of thick cubes... In cases where the surface facing the substrate 5120 is not constant, and the thickness and crystal orientation cannot be made uniform, be. 【0193】 The film formation model described above allows for high crystallinity even on a film-forming surface having an amorphous structure. A CAAC-OS having the following characteristics can be obtained. 【0194】 Figure 15(A) is a high-resolution TEM image of a cross-section of the CAAC-OS film. Also, Figure 15(B) Figure 15(A) is a high-resolution TEM image of a cross-section that is further enlarged, making it easier to understand. The atomic arrangement is highlighted for this purpose. 【0195】 Figure 15(C) shows the area enclosed by a circle (diameter approximately 4n) between AO and A' in Figure 15(A). This is the local Fourier transform image of m). From Figure 15(C), the c-axis orientation in each region is It can be confirmed. Also, the orientation of the c-axis is different between A and O and between O and A', so different grades This suggests that it is in. Also, between A and O, the angle of the c axis is 14.3° and 16.6°. It can be seen that it changes gradually and continuously, such as ° and 26.4°. Similarly, O-A' In between, the angle of the c-axis changes gradually and continuously from -18.3°, -17.6°, to -15.9°. It can be seen that it has transformed. 【0196】 High-resolution TEM images of the cross-section and high-resolution TEM images of the planar region of the CAAC-OS film It can be seen that it has orientation. 【0197】 Furthermore, most of the crystalline parts contained in the CAAC-OS film are cubes with sides less than 100 nm long. It is small enough to fit inside. Therefore, the crystalline portion contained in the CAAC-OS film has a side length of 10n. This also includes cases that fit within a cube smaller than m, smaller than 5 nm, or smaller than 3 nm. Furthermore, multiple crystalline regions contained in the CAAC-OS film are linked together, forming one large crystalline region. This can sometimes form. For example, in a high-resolution planar TEM image, at 2500 nm 2 That's all. , 5μm 2 or greater than 1000 μm 2 In some cases, crystal regions exceeding the above size may be observed. 【0198】 From the above, it can be concluded that in CAAC-OS films, the orientation of the a-axis and b-axis is inconsistent between different crystalline regions. It is a rule, but it has c-axis orientation and the c-axis is parallel to the normal vector of the surface to be formed or the upper surface. It can be seen that it is facing in that direction. Therefore, as confirmed by the high-resolution TEM observation of the cross-section mentioned above, Each layer of metal atoms arranged in layers is a plane parallel to the ab-plane of the crystal. 【0199】 The crystalline portion is formed when the CAAC-OS film is deposited, or when crystallization treatment such as heat treatment is performed. It is formed when this occurs. As mentioned above, the c-axis of the crystal is the surface on which the CAAC-OS film is formed or It is oriented in a direction parallel to the normal vector of the upper surface. Therefore, for example, the shape of the CAAC-OS film When the shape is altered by etching or other means, the c-axis of the crystal becomes the surface on which the CAAC-OS film is formed. Alternatively, it may not be parallel to the normal vector of the top surface. 【0200】 Furthermore, the distribution of c-axis oriented crystalline regions within the CAAC-OS film does not need to be uniform. For example, the crystalline portion of the CAAC-OS film is formed by crystal growth from near the top surface of the CAAC-OS film. When formed in this way, the region near the top surface has a more c-axis oriented crystalline structure than the region near the surface being formed. The proportion of impurities can increase. Also, in CAAC-OS films with added impurities, the impurities The added region is altered, and regions with different proportions of partially c-axis-oriented crystals are formed. Sometimes. 【0201】 Oxide semiconductors include, for example, amorphous oxide semiconductors, microcrystalline oxide semiconductors, and CAAC- It may have two or more types of operating systems. 【0202】 When an oxide semiconductor has multiple structures, structural analysis can be performed using nanobeam electron diffraction. It may be possible. 【0203】 Figure 16(C) shows the electron gun chamber 1010, the optical system 1012 below the electron gun chamber 1010, and the optical system. The sample chamber 1014 below system 1012, the optical system 1016 below sample chamber 1014, and optical system 1 Observation room 1020 below 016, camera 1018 installed in observation room 1020, and observation room A transmission electron diffraction measuring apparatus having a film chamber 1022 below 1020 is shown. Camera 1 Unit 018 is installed facing the inside of observation room 1020. Note that there is no film room 1022. It's okay if you don't have to. 【0204】 Furthermore, Figure 16(D) shows the internal structure of the transmission electron diffraction measurement device shown in Figure 16(C). Inside the transmission electron diffraction measuring device, electrons emitted from the electron gun installed in the electron gun chamber 1010 The light is irradiated onto the substance 1028 placed in the sample chamber 1014 via the optical system 1012. Electrons that have passed through material 1028 are placed inside observation chamber 1020 via optical system 1016. The electrons are incident on the fluorescent screen 1032. The fluorescent screen 1032 displays a pattern according to the intensity of the incident electrons. The appearance of 'n' allows for the measurement of the transmission electron diffraction pattern. 【0205】 Camera 1018 is positioned facing the fluorescent board 1032, and when the fluorescent board 1032 appears, It is possible to photograph the turn. The center of the lens of camera 1018 and the fluorescent screen 10 The angle between the straight line passing through the center of 32 and the top surface of the fluorescent board 1032 is, for example, 15° or more and 80° The angle shall be less than or equal to 30° to 75°, or between 45° and 70°. However, the transmission electron diffraction pattern captured by camera 1018 will be highly distorted. If the angle is known in advance, the distortion of the obtained transmission electron diffraction pattern can be corrected. This is also possible. Furthermore, there are cases where camera 1018 may be installed in film chamber 1022. Yes, for example, the camera 1018 is placed in the film chamber 1022, opposite the direction of incidence of the electrons 1024. It may be installed in such a way. In this case, transmitted electrons with little distortion are transmitted from the back surface of the fluorescent board 1032. Diffraction patterns can be captured. 【0206】 A holder for fixing the sample substance 1028 is installed in the sample chamber 1014. The holder has a structure that allows electrons to pass through material 1028. The holder is, For example, it may have a function to move the substance 1028 along the X, Y, and Z axes. The movement function of the luda is, for example, between 1 nm and 10 nm, between 5 nm and 50 nm, and 10 nm. Examples include m to 100 nm, 50 nm to 500 nm, 100 nm to 1 μm, etc. It is sufficient to have the precision to move within a range. These ranges are determined by the structure of material 1028. You just need to set an appropriate range. 【0207】 Next, the transmission electron diffraction pattern of the material is measured using the transmission electron diffraction measuring device described above. I will explain the method. 【0208】 For example, as shown in Figure 16(D), the irradiation position of electron 1024, which is a nanobeam, in a material By changing its position (scanning), we can observe how the structure of a substance changes. This can be done. In this case, if substance 1028 is CAAC-OS, then as shown in Figure 16(A) Such diffraction patterns are observed. Alternatively, if material 1028 is nc-OS, then Figure 16( A diffraction pattern like that shown in B) is observed. 【0209】 By the way, even if substance 1028 is CAAC-OS, it may be partially nc-OS, etc. Similar diffraction patterns may be observed. Therefore, the quality of CAAC-OS is not determined by... The percentage of the region in a given range where the CAAC-OS diffraction pattern is observed (CAAC conversion rate) It can also be expressed as: ) In some cases, a good CAAC-OS is, The CAAC conversion rate is 60% or more, preferably 80% or more, and more preferably 90% or more. Preferably, it is 95% or more. Note that a diffraction pattern different from that of CAAC-OS is observed. The region where this occurs is referred to as the non-CAAC rate. 【0210】 As an example, immediately after formation (denoted as as-depo), CAAC-O after heat treatment at 450°C. For each sample containing S, a transmission electron diffraction pattern was acquired while scanning the upper surface. Here, the diffraction pattern was observed while scanning at a speed of 5 nm / second for 60 seconds, and the observed... The CAAC conversion rate was derived by converting the diffraction pattern into a still image every 0.5 seconds. Oh, as for the electron beam, a nanobeam with a probe diameter of 1 nm was used. 【0211】 Figure 17 shows the CAAC conversion rate for each sample. Compared to immediately after formation, the rate after 450°C heat treatment is shown. It can be seen that the CAAC conversion rate is high. In other words, heat treatment at 450°C or higher removes the CAAC. It can be seen that the conversion rate decreases (the CAAC conversion rate increases). Here, CAAC-OS is different Most of the diffraction patterns were similar to those of nc-OS. Therefore, Due to the heat treatment, regions with a structure similar to nc-OS are affected by the structure of adjacent regions. This suggests that it is being converted into CAAC. 【0212】 Using this measurement method, it becomes possible to analyze the structure of oxide semiconductors that have multiple structures. There are cases where this occurs. 【0213】 Although an example using an oxide semiconductor layer 108 is shown here, the embodiments of the present invention One aspect of this is not limited to this. Depending on the circumstances, oxide semiconductors may be used. Instead of body layer 108, a semiconductor film made of a different material may be used. For example, channel region In regions such as the source-drain region and LDD region, instead of the oxide semiconductor layer 108, Semiconductor films containing one or more elements such as silicon, germanium, gallium, and arsenic. You may also use [this]. 【0214】 [A-8: Electrode 109, Electrode 119] Electrodes 109 and 119 are connected to electrodes 102a, 103a, and 104a, and Furthermore, electrodes 102b, 103b, and 104b are formed using the same materials and methods. It is possible. 【0215】 Note that at least the portion of electrode 109 and electrode 119 that is in contact with the oxide semiconductor layer 108b It is preferable to use an oxygen-impermeable conductive material. By providing at least the oxide semiconductor layer 108b in contact with the oxide semiconductor layer 108b, the oxide semiconductor layer 108 contains The oxygen that is trapped can be made less likely to diffuse to electrodes 109 and 119. 【0216】 [A-9: Insulation layer 110] The insulating layer 110 can be formed using the same materials and methods as the insulating layer 105. 【0217】 The insulating layer 110 may consist of, for example, a silicon nitride layer as the first layer and a silicon oxide layer as the second layer. A multilayer film may also be used. In this case, the silicon oxide layer may be a silicon oxide nitride layer. Also, the silicon nitride layer can be a silicon nitride oxide layer. The silicon oxide layer has a defect density. It is preferable to use a small silicon oxide layer. Specifically, a layer with a g value of 2.001 in ESR. The spin density of the spins originating from the signal is 3 × 10⁻¹⁰ 17 spins / cm 3 The following are preferred 5 x 10 16 spins / cm 3 The following silicon oxide layer is used. The silicon nitride layer preferably uses a silicon oxide layer containing excess oxygen. A silicon nitride layer with low hydrogen and ammonia emissions is used. This can be measured using TDS analysis. 【0218】 Furthermore, in order to prevent an increase in the hydrogen concentration in the oxide semiconductor, the hydrogen concentration of the insulating layer 110 is reduced. It is preferable to do so. Specifically, the hydrogen concentration of the insulating layer 110 is set to 2 × 1 in SIMS. 0 20 atoms / cm 3 The following is preferably 5 × 10 19 atoms / cm 3 From here on Preferably 1 × 10 19 atoms / cm 3 More preferably 5 × 10 18 ato ms / cm 3 The following applies. In addition, to prevent an increase in nitrogen concentration in the oxide semiconductor, an insulating layer It is preferable to reduce the nitrogen concentration of 110. Specifically, the nitrogen concentration of the insulating layer 110 is In SIMS, 5 × 10 19 atoms / cm 3 Less than 5 × 10 18 at oms / cm 3 More preferably 1 × 10 18 atoms / cm 3 The following are further preferred Or 5x10 17 atoms / cm 3 The following applies: 【0219】 Furthermore, the insulating layer 110 uses an insulating layer that contains more oxygen than satisfies the stoichiometric composition requirement. It is preferable to form it in this way. An insulating material containing more oxygen than satisfactorily satisfying the stoichiometric composition. The layer undergoes some oxygen elimination upon heating. More oxygen than is needed to satisfy the stoichiometric composition. In the insulating layer containing [the substance], TDS analysis showed that the amount of oxygen desorption, converted to oxygen atoms, was 1.0 × 10⁻⁶. 1 8 atoms / cm 3 Preferably 3.0 × 10 20 atoms / cm 3The above is the case It is an insulating layer. The surface temperature of the film during the above TDS analysis is preferably 100°C or higher and 70 0°C or lower, or in the range of 100°C or higher and 500°C or lower. Also, in this specification and the like Oxygen that is more than the oxygen that satisfies the stoichiometric composition in the insulating layer is also referred to as "excess oxygen". Also, in this specification and the like, an insulating layer containing more oxygen than the oxygen that satisfies the stoichiometric composition is also referred to as an "insulating layer containing excess oxygen". 【0220】 〔A-10: Electrode 111〕 The electrode 111 can be formed by the same materials and methods as the electrodes 109 and 119. The thickness of the electrode 111 may be 10 nm or more and 500 nm or less, preferably 50 nm or more and 30 0 nm or less. 【0221】 〔A-11: Insulating layer 112〕 The insulating layer 112 can be formed by the same materials and methods as the insulating layer 106. The insulating layer 112 may have a thickness of 10 nm or more and 500 nm or less, preferably 50 nm or more and 300 nm or less as appropriate. 【0222】 <B: Example of manufacturing method of transistor 100 and capacitor element 130> Using the cross-sectional views shown in FIGS. 2 to 5, an example of the manufacturing method of the transistor 100 will be described. 【0223】 〔B-1: Formation of electrodes 102, 103, and 104〕 First, on the substrate 101, a conductive layer (not shown) for forming the electrodes 102a, 103a, and 104a and a conductive layer (not shown) for forming the electrodes 102b, 103b, and 104b are laminated. Each conductive layer can be formed using a sputtering method, CV D method, evaporation method, or the like. D method, evaporation method, or the like can be used to form it. 【0224】 For example, when depositing a tungsten film as a conductive layer, WF6 gas and B2H6 gas are used in sequence. Next, the initial tungsten film is deposited by repeatedly introducing the gas, and then WF6 gas and H2 gas are introduced. Sometimes, a tungsten film is deposited by introducing it. Note that SiH4 gas is used instead of B2H6 gas. That's fine. 【0225】 In this embodiment, for forming electrodes 102a, 103a, and 104a A 150 nm thick tungsten film is deposited as a conductive layer using the sputtering method. As a conductive layer for forming electrodes 102b, 103b, and 104b, A 50 nm thick film of nitrogen-containing indium gallium zinc oxide is deposited using the puttering method. ru. 【0226】 Next, a resist mask is used to selectively etch a portion of each conductive layer, and then the electrodes are formed. 102, electrode 103, and electrode 104 (other electrodes or components formed in the same layer as these) Forms (including lines). Resist mask formation is done by photolithography, printing, and ink. This can be done using methods such as the inkjet method as appropriate. The resist mask is shaped using the inkjet method. This eliminates the need for photomasks, thus reducing manufacturing costs. 【0227】 Each conductive layer can be etched using either a dry etching method or a wet etching method. Both methods may be used. Furthermore, the oxide semiconductor film is etched using the dry etching method. In such cases, a capacitively coupled plasma (CCP) is used as the plasma source. Inductively coupled plasma (ICP) Coupled Plasma, Electron Cyclotron Resonance (ECR) (H) Cyclotron Resonance plasma, helicon wave excited plasma (H) WP: Helicon Wave Plasma, Microwave-excited surface wave plasma (S WP (Surface Wave Plasma), etc. can be used. In particular, I CP, ECR, HWP, and SWP can generate high-density plasma. Etching performed by the dry etching method (hereinafter also referred to as "dry etching treatment") is desired To enable etching to the processed shape, etching conditions (electricity applied to the coil-type electrode) This is done by appropriately adjusting the force, the amount of power applied to the electrodes on the substrate, the temperature of the electrodes on the substrate, etc. After etching of each conductive layer is complete, remove the resist mask (see Figure 2(A)). 【0228】 [B-2: Formation of insulating layer 105] Next, an insulating layer 105 is formed on electrodes 102, 103, and 104. Layer 105 can be formed using methods such as sputtering, CVD, or vapor deposition. In particular, ALD, MOCVD, or thermal CVD methods do not use plasma, so they cause less damage. It is preferable. 【0229】 For example, when using the thermal CVD method to deposit silicon oxide as the insulating layer 105, Xachlorodisilane is adsorbed onto the film-forming surface, and chlorine contained in the adsorbed material is removed, resulting in an oxidizing gas. (O2, nitrous oxide) radicals are supplied and reacted with the adsorbed material. 【0230】 For example, when using thermal CVD to deposit hafnium oxide as the insulating layer 105, A liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide solution, typically a t A raw material gas obtained by vaporizing trachosdimethylamide hafnium (TDMAH), and an oxidizing agent Two types of gases are used: ozone (O3) and tetrakisdimethylamide hafniu. The chemical formula for Mu is Hf[N(CH3)2]4. Other material liquids include Tetrakiss. Examples include (ethylmethylamide)hafnium. 【0231】 In this embodiment, the insulating layer 105 is made of an oxide with a thickness of 250 nm, produced by plasma CVD. Silicon nitride is formed (see Figure 2(B)). 【0232】 Next, to expose the surfaces of electrodes 102b, 103b, and 104b, chemical Mechanical polishing (CMP) treatment The CMP process (hereinafter also referred to as "CMP processing") is performed (see Figure 2(C)). By performing this process, surface irregularities of the sample are reduced, improving the coverage of the insulating and conductive layers formed thereafter. It can improve. 【0233】 Here, the hydrogen, nitrogen, and water in electrodes 102, 103, 104, and the insulating layer 105 are... Heat treatment may be performed to reduce the following: Heat treatment should be performed at a temperature of 300°C to 800°C. Preferably, the process should be carried out at a temperature between 400°C and 700°C. The processing time should be within 24 hours. Heat treatment exceeding 24 hours is undesirable as it leads to a decrease in productivity. 【0234】 There are no special limitations on the heating equipment used for the heat treatment, and heat conduction from heat sources such as resistance heating elements is also possible. Alternatively, it may be equipped with a device that heats the object to be processed by thermal radiation. For example, an electric furnace, LRTA (Lamp Rapid Thermal Anneal) equipment, GRTA (G RTA (Rapid Thunder) devices such as Rapid Thermal Annealing (RTA) A stermal Anneal (LRTA) device can be used. The LRTA device uses halogen lamps. P, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium The light (electromagnetic waves) emitted from lamps such as um lamps and high-pressure mercury lamps is used to treat the object being processed. It is a device for heating objects. A GRTA device is a device that performs heat treatment using high-temperature gas. ru. 【0235】 In particular, when using a substrate 101 that has semiconductor elements mounted on a semiconductor substrate. This allows for a reduction in the hydrogen concentration contained in the substrate 101, thus eliminating the need for heat treatment. This is preferable. 【0236】 [B-3: Formation of insulating layer 106] Next, an insulating layer 106 is placed on electrodes 102, 103, 104, and insulating layer 105. The insulating layer 106 is formed using sputtering, CVD, vapor deposition, etc. This is possible. In particular, the ALD method, MOCVD method, or thermal CVD method do not use plasma. Therefore, it causes less damage, which is preferable. 【0237】 For example, when using the thermal CVD method to deposit aluminum oxide as the insulating layer 106: , a raw material gas obtained by vaporizing a liquid (such as TMA) containing a solvent and an aluminum precursor compound, Two types of gas, H2O, are used as oxidizing agents. The chemical formula for trimethylaluminum is: It is Al(CH3)3. Another material solution is Tris(dimethylamide)aluminum. Aluminum, triisobutylaluminum, aluminum tris(2,2,6,6-tetramethyl Examples include til-3,5-heptandionate. 【0238】 In this embodiment, the insulating layer 106 is made of 50 nm thick oxide by sputtering. It forms luminium. 【0239】 Next, a resist mask is used to superimpose electrodes 102, 103, and 104. A portion of the insulating layer 106 is selectively etched, and electrodes 102b, 103b, and electrodes are etched. The surface of 104b is exposed. Etching of the insulating layer 106 can also be done by dry etching. The wet etching method may be used, or both may be used. After etching of the insulating layer 106 is complete, Remove the resist mask (see Figure 2(D)). 【0240】 [B-4: Formation of insulating layer 107] Next, an insulating layer 107 is placed on electrodes 102, 103, 104, and 106. The insulating layer 107 is formed using sputtering, CVD, vapor deposition, etc. This is possible. In this embodiment, the insulating layer 107 is made with a thickness of 150n by CVD. It forms silicon oxidnitride containing more oxygen than satisfies the stoichiometric composition of m. 【0241】 Furthermore, an insulating layer containing excess oxygen can also be formed by adding oxygen to the insulating layer. It is possible. Processes that add oxygen include heat treatment in an oxygen atmosphere, ion implantation equipment, and ionization. This can be done using a doping device or a plasma processing device. As the doping apparatus, an ion doping apparatus with mass separation capabilities may be used. Oxygen is added. As for the gas used for this purpose, 16 O2 or18 Oxygen gas such as O2, nitrous oxide gas, Alternatively, ozone gas can be used. Note that in this specification, the process of adding oxygen is referred to as " This is also called "oxygen doping." 【0242】 Furthermore, CMP treatment may be performed to reduce surface irregularities of the sample. 【0243】 [B-5: Formation of oxide semiconductor layer 108a and oxide semiconductor layer 108b] Next, an oxide semiconductor layer 11 is formed on the insulating layer 107 to form an oxide semiconductor layer 108a. 8a and an oxide semiconductor layer 118b for forming an oxide semiconductor layer 108b are formed ( See Figure 3(A). 【0244】 In this embodiment, the oxide semiconductor layer 118a is made of In:G by sputtering. Using a target with an atomic ratio of a:Zn=1:3:4, a 20nm thick In-Ga-Z An n oxide is formed. Also, as the oxide semiconductor layer 118b, In:Ga:Zn=1:1 Using a target with an atomic ratio of :1, an In-Ga-Zn oxide with a thickness of 20 nm is formed. ru. 【0245】 Next, the water or hydrogen contained in the oxide semiconductor layer 118a and oxide semiconductor layer 118b Further reduction of impurities such as oxide semiconductor layer 118a and oxide semiconductor layer 118b To increase its purity, it is preferable to perform a heat treatment. 【0246】 For example, under a reduced pressure atmosphere, under an inert atmosphere such as nitrogen or a noble gas, under an oxidizing atmosphere, or in an ultra-dry atmosphere. Dry air (measured using a CRDS (Cavity Ring-Down Laser Spectroscopy) type dew point meter) In that case, the moisture content is 20 ppm or less (dew point equivalent to -55°C), preferably 1 ppm or less. Preferably in an atmosphere of 10 ppb or less air, the oxide semiconductor layer 118a and the oxide semiconductor layer The conductive layer 118b is subjected to heat treatment. Note that an oxidizing atmosphere refers to oxygen, ozone, or acid nitride. This refers to an atmosphere containing oxidizing gases such as ions at a concentration of 10 ppm or more. Furthermore, an inert atmosphere is defined as follows: The aforementioned oxidizing gas is less than 10 ppm, and the atmosphere is otherwise filled with nitrogen or noble gases. To be considerate. 【0247】 Furthermore, by performing the heat treatment, impurities are released, and at the same time, oxygen contained in the insulating layer 107 is removed. The oxide semiconductor layer 118a and oxide semiconductor layer 118b are diffused into the oxide semiconductor layer 11 This can reduce oxygen vacancies in 8a and the oxide semiconductor layer 118b. After heat treatment in a saturating atmosphere, an oxidizing gas of 10 ppm or more is added to replenish the desorbed oxygen. Heat treatment may be carried out in an atmosphere containing 1% or more or 10% or more of the acid. This can be done at any time after the formation of the oxide semiconductor layer 118a and the oxide semiconductor layer 118b. For example, after the formation of oxide semiconductor layer 108a and oxide semiconductor layer 108b, heat treatment is performed. You may go. 【0248】 The heat treatment should be carried out at a temperature of 250°C to 650°C, preferably 300°C to 500°C. Good. The processing time should be within 24 hours. Heating for more than 24 hours will lead to a decrease in productivity. Therefore, it is undesirable. 【0249】 Next, using a resist mask, oxide semiconductor layer 118a and oxide semiconductor layer 118b A portion of the oxide semiconductor layer 108a and oxide semiconductor layer 108b are selectively etched. To form the insulating layer 107. At the same time, the exposed insulating layer 107 is slightly etched, and the insulating layer 107 in that region The film thickness is reduced. The amount of etching of the insulating layer 107 at this time is 20 times the thickness of the insulating layer 107. A percentage of % or more and 80% or less is preferable, and a percentage of 30% or more and 70% or less is more preferable. In this way, An insulating layer 107 having protrusions can be formed (see Figure 3(B)). 【0250】 Etching of oxide semiconductor layer 118a, oxide semiconductor layer 118b, and insulating layer 107 Either a dry etching method or a wet etching method may be used, or both may be used. After the process is complete, remove the resist mask. 【0251】 Next, a resist mask is used to superimpose a portion of electrode 104b and a portion of insulating layer 106. The insulating layer 107 is selectively etched, and a portion of the electrode 104b and the insulating layer 106 are etched. Part of the layer is exposed (see Figure 3(C)). Etching of the insulating layer 107 is performed by dry etching. Either the etching method or the wet etching method may be used, or both may be used. After etching is complete, the resin Remove the stomach mask. 【0252】 [B-6: Formation of electrodes 109 and 119] Next, electrodes 109 and 11 are placed on the oxide semiconductor layer 118b and the insulating layer 107. A conductive layer is formed to form 9 (not shown). In this embodiment, the conductive layer is Then, a 100 nm thick layer of tungsten is formed by sputtering. 【0253】 Next, a resist mask is used to selectively etch a portion of the conductive layer, and electrode 109 and And form electrodes 119 (including other electrodes or wiring formed in the same layer as these). The etching of the electrode layer can be done using either the dry etching method or the wet etching method, or both can be used. It is acceptable to leave it there. Afterwards, remove the resist mask (see Figure 4(A)). 【0254】 Furthermore, when forming transistors with extremely short channel lengths L, electron beam lithography and EU are used. Suitable for fine wire processing using V (Extreme Ultraviolet) exposure, immersion exposure, etc. By forming a resist mask using the method and performing an etching process, electrode 109 And electrode 119 can be formed. As for the resist mask, a positive type resist is used. By using this method, the exposure area can be minimized, and throughput can be improved. Using this method, transistors with a channel length of 30 nm or less can be fabricated. It is possible. 【0255】 Also, electrodes 109 and 119 (and other electrodes or wiring formed in the same layer as these) It is preferable that the end of the part (including) be tapered. Specifically, the tapered end The angle θ is set to 80° or less, preferably 60° or less, and more preferably 45° or less. 【0256】 Also, electrodes 109 and 119 (and other electrodes or wiring formed in the same layer as these) By making the cross-sectional shape of the end of (including) a multi-step staircase shape, the coverage of the layer covering it improves It is also possible to improve this. Note that this is not limited to electrodes 109 and 119, but also the edges of each layer By making the cross-sectional shape a forward taper shape or a stepped shape, the layer formed to cover the end is This prevents the phenomenon of breakage at the end (step breakage) and improves the coverage. . 【0257】 [B-7: Formation of oxide semiconductor layer 108c] Next, an oxide semiconductor layer is placed on electrode 109, electrode 119, and oxide semiconductor layer 108b. An oxide semiconductor layer is formed to create 10⁸c (not shown). 【0258】 In this embodiment, as the oxide semiconductor layer for forming the oxide semiconductor layer 108c, I Using a target with an atomic ratio of n:Ga:Zn=1:3:4, a 5nm thick In-Ga -Forms Zn oxide 【0259】 Next, using a resist mask, an oxide semiconductor is formed to create an oxide semiconductor layer 108c. A portion of the layer is selectively etched to form an oxide semiconductor layer 108c (see Figure 4(B)). . ) . 【0260】 Etching of oxide semiconductor layers can be done using either dry etching or wet etching methods. Both methods may be used. After etching is complete, remove the resist mask. 【0261】 [B-8: Formation of insulating layer 110 and electrode 111] Next, an insulating layer 120 is formed on electrode 109, electrode 119, and oxide semiconductor layer 108c. The insulating layer 120 can be formed using sputtering, CVD, vapor deposition, etc. In this embodiment, the insulating layer 120 is made with a thickness of 20 nm by plasma CVD. It forms silicon oxide nitride. 【0262】 Next, a conductive layer 121 is formed on the insulating layer 120. In this embodiment, the conductive layer 121 is Then, a layer of titanium nitride with a thickness of 30 nm and tungsten with a thickness of 135 nm is sputtered. Formed by law (see Figure 4(C)). 【0263】 Next, using a resist mask, a portion of the insulating layer 120 and the conductive layer 121 is selectively removed. The insulating layer 110 and electrode 111 (other electrodes formed in the same layer or Forms (including wiring). Etching of the insulating layer 120 and the conductive layer 121 is performed by dry etching. Either the etching method or the wet etching method may be used, or both may be used. After that, the resist Remove the scum (see Figure 5(A)). 【0264】 Note that the insulating layer 120 does not necessarily need to be etched at this time. Cross-section in that case The diagram is shown in Figure 29. Furthermore, the plan view and cross-sectional view of the completed structure are shown in Figure 30. 【0265】 The etching of the insulating layer 120 and the conductive layer 121 is performed simultaneously in a single etching process. Alternatively, the etching method can be changed after the etching of the conductive layer 121 is complete. The insulating layer 120 may be etched using the mask. 【0266】 Furthermore, as shown in Figure 1(C), the transistor 100 has an insulating layer 107 with a protrusion. As a result, the electric field of electrode 111 electrically surrounds the oxide semiconductor layer 108b. This structure allows for the creation of a transistor, where the semiconductor is electrically surrounded by the electric field of the conductive film. This structure is called a surrounded channel (s-channel) structure. Therefore, when channels are formed throughout the entire (bulk) oxide semiconductor layer 108b, Yes, in an s-channel structure, the drain current of the transistor can be increased. Furthermore, an even larger on-current can be obtained. Also, the electric field of electrode 111 causes oxidation The entire channel formation region formed in the monocrystalline semiconductor layer 108b can be depleted. Therefore, in an s-channel structure, the off-current of the transistor is further reduced. It is possible. 【0267】 [B-9: Formation of insulating layer 112] Next, an insulating layer 112 is formed by covering electrodes 109, 119, and 111. The insulating layer 112 can be formed using sputtering, CVD, vapor deposition, etc. In this embodiment, the insulating layer 112 is made with a thickness of 50 nm by sputtering. Aluminum oxide is formed (see Figure 5(B)). 【0268】 Through the above process, the transistor 100 and the capacitive element 130 can be manufactured. 【0269】 According to one aspect of the present invention, it is possible to realize a transistor with less variation in electrical characteristics. Therefore, it is possible to realize a semiconductor device with less variation in electrical characteristics. This invention According to one embodiment, a transistor with good reliability can be realized. Therefore, This makes it possible to realize a semiconductor device with good performance. 【0270】 Furthermore, since oxide semiconductors have a band gap of 2 eV or more, channels are formed in semiconductors. A transistor using an oxide semiconductor in its body layer exhibits leakage current when the transistor is off. The current (also called "off-current") can be made extremely small. Specifically, the channel The off-current per 1 μm width is 1 × 10⁻¹⁶ at room temperature. -20 Less than A, preferably 1 × 10 -22 Less than A, more preferably 1 × 10 -24 It can be less than A. That is, The on / off ratio can be set to between 20 and 150 digits. 【0271】 According to one aspect of the present invention, a transistor with low power consumption can be realized. This makes it possible to realize semiconductor devices with low power consumption. 【0272】 This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case. 【0273】 (Embodiment 2) In this embodiment, a transistor, which is one aspect of the present invention, is used in a state where no power is supplied. Moreover, a semiconductor device (memory device) that can retain its contents and has no limit on the number of write cycles An example of placement will be explained using a diagram. 【0274】 Figure 18(A) shows a cross-sectional view of the semiconductor device. Figure 18(B) shows a circuit diagram of the semiconductor device. show. 【0275】 The semiconductor device shown in Figures 18(A) and 18(B) is a transistor with a substrate 700 at the bottom. A transistor 100 having a zista 750 and an oxide semiconductor on top, and a capacitive element It has 130. Note that in the circuit diagram, transistor 100 is made of an oxide semiconductor. The designation "OS" is added to clearly indicate that it is a Rangista. 【0276】 The substrate 700 can be a single-crystal semiconductor substrate made of silicon or silicon carbide, or a polycrystalline semiconductor substrate. Conductor substrates, compound semiconductor substrates made of silicon germanium, etc., and SOI (Silic A semiconductor substrate can be used. The formed transistors are easily capable of high-speed operation. 【0277】 In this embodiment, an example is shown in which a p-type single-crystal silicon substrate is used as the substrate 700. The transistor 750 is a transistor in which a channel is formed in the substrate 700. Rangista 750 has a channel formation region 753, LDD (Lightly Doped n-type impurity region 754, which functions as a drain region or extension region, source n-type impurity region 755, insulating layer 752, and electrode 751, which function as a region or drain region. It has the following: Electrode 751 functions as a gate electrode. Insulating layer 752 is a gate insulating layer and It functions in this way. Note that the impurity concentration in the n-type impurity region 755 is greater than that in the n-type impurity region 754. The side of electrode 751 is provided with a side wall insulating layer 756, and electrode 751 and side wall Using the insulating layer 756 as a mask, the n-type impurity region 754 and the n-type impurity region 755 are controlled. It can be formed using the self-integration method. 【0278】 Furthermore, the transistor 750 is formed on the substrate 700 by the element isolation region 789. It is separated from transistor 750. Also, around electrode 751 and side wall insulating layer 756, Insulating layer 790 and insulating layer 791 are formed. 【0279】 Furthermore, in Figure 18(A), an insulating layer 113 is formed on the transistor 100. The insulating layer 113 is formed using the same materials and methods as the insulating layer 105 shown in Embodiment 1. It is possible to do so. Also, an electrode 114 is formed on the insulating layer 113, and the insulating layer 113 and insulating An opening formed in layer 112 is electrically connected to electrode 119. 【0280】 Furthermore, an insulating layer 115 is formed on the insulating layer 113 and the electrode 114 as a planar insulating layer. The insulating layer 115 is made of polyimide, acrylic, benzocyclobutene, and polyam. Heat-resistant organic materials such as epoxy can be used. Other materials include low-dielectric materials (low-k materials), siloxane resins, PSG (phosphorus glass), and B PSG (limboron glass), etc., can be used. The insulating layer 115 may be formed by stacking multiple insulating films. 【0281】 Siloxane-based resins are formed using siloxane-based materials as the starting material for Si-OS. This corresponds to a resin containing i-bonds. Siloxane resins use organic groups (e.g., alkyl groups) as substituents. You may also use aryl groups or fluoro groups. Furthermore, organic groups may have fluoro groups. You can. 【0282】 The method for forming the insulating layer 115 is not particularly limited, and can be done by sputtering or SOG depending on the material. Spin coating, dipping, spray coating, droplet ejection (inkjet method, etc.), printing method (Screen printing, offset printing, etc.) can be used. The firing process of the insulating layer 115 and By combining this process with other heat treatment steps, it becomes possible to manufacture semiconductor devices efficiently. 【0283】 Furthermore, the insulating layer 115 is formed using the same materials and methods as the insulating layer 105 shown in Embodiment 1. After this, the insulating layer 115 may be subjected to CMP treatment. 【0284】 Furthermore, an electrode 116 is formed on the insulating layer 115, and the electrode is formed at an opening in the insulating layer 115. It is electrically connected to 114. 【0285】 Electrode 751 is electrically connected to electrode 103. Also, transistor 750 has One side of the n-type impurity region 755 is electrically connected to the wiring 3001, and the n-type impurity region 7 The other end of 55 is electrically connected to wiring 3002 (not shown). Also, electrode 11 9 is electrically connected to wiring 3003, and electrode 109 is connected to wiring 30 via capacitive element 130 Electrodes 111 and 102 are electrically connected to wiring 3004, and are electrically connected to 05. It is shown (not shown). 【0286】 Here, the material of the semiconductor layer in which the channel of transistor 750 is formed, and transistor 1 The material of the semiconductor layer in which the 00 channel is formed can be a material with different band gaps. Desirable. For example, an oxide semiconductor in the semiconductor layer where the channel of transistor 100 is formed. When using this, the semiconductor layer in which the channel of transistor 750 is formed contains a semiconductor other than an oxide semiconductor. It is preferable to use semiconductor materials such as crystalline silicon or other oxide semiconductor materials. Transistors using external semiconductor materials are faster than transistors using oxide semiconductors. It is easy to operate. On the other hand, transistors using oxide semiconductors have a low off-current. Its properties enable long-term charge retention. 【0287】 For example, if crystalline silicon is used in the semiconductor layer where the transistor channel is formed, It enables faster operation than transistors that use oxide semiconductors in the semiconductor layer where the channel is formed. This is possible. Therefore, by using the transistor in question as a readout transistor, This allows for high-speed retrieval of information. 【0288】 The above explanation assumes that all transistors are n-channel transistors. However, it goes without saying that p-channel transistors can be used. Also, Unless otherwise explained, information about semiconductor devices, such as the materials used and the structure of semiconductor devices, is not available. It is not necessary to limit the specific configuration to those shown here. 【0289】 Furthermore, as shown in Figure 18(A), a transistor is formed on the substrate on which the transistor 750 is formed. Since 100 and capacitive elements 130 can be formed, the integration density of the semiconductor device can be increased. It is possible. 【0290】 Figure 18(B) is a circuit diagram of the semiconductor device corresponding to Figure 18(A). Wiring 3001 is electrically connected to the source electrode of transistor 750, and wiring 300 2 is electrically connected to the drain electrode of transistor 750. Also, wiring 3003 It is electrically connected to either the source electrode or the drain electrode of transistor 100, and wiring 3004 is electrically connected to the gate electrode of transistor 100. The gate electrode of transistor 750, and the other of the source electrode or drain electrode of transistor 100. And one of the electrodes of the capacitive element 130 is electrically connected to node ND. Wiring 3005 is electrically connected to the other electrode of the capacitive element 130. 【0291】 Transistors that use oxide semiconductors in the semiconductor layer where the channel is formed have extremely low off-current. It can be made smaller. Transistor 100 is a semiconductor layer in which a channel is formed. By using an oxide semiconductor transistor, the charge of node ND can be maintained for a long period of time. Therefore, it is possible to maintain the charge of the gate electrode of transistor 750 for a long period of time. It is possible. 【0292】 In the semiconductor device shown in Figure 18(B), the charge of the gate electrode of transistor 750 can be retained. By taking advantage of these characteristics, it is possible to write, store, and read information as follows: . 【0293】 This section explains how to write and retain information. First, the potential of wiring 3004 is set by the transistor The potential is set so that transistor 100 is ON, and transistor 100 is turned ON. The potential of wiring 3003 is transmitted to the gate electrode of transistor 750 and the capacitive element 130. A predetermined charge is given. That is, a predetermined charge is given to the gate electrode of transistor 750. (Writing). Here, a charge that gives two different potential levels (hereinafter referred to as Low-level charge) It is assumed that either a high-level charge or a high-level charge is given. Then, wiring 300 Set the potential at point 4 to the potential at which transistor 100 is in the off state, and turn off transistor 100. By putting it into the "F" state, the charge applied to the gate electrode of transistor 750 is retained. (to hold). 【0294】 Because the off-current of transistor 100 is extremely small, the gate electrode of transistor 750 The electric charge is retained for a long period of time. 【0295】 Next, we will explain how to read the information. When a predetermined potential (constant potential) is applied to wiring 3001... When the appropriate potential (readout potential) is applied to wiring 3005, the gate of transistor 750 Depending on the amount of charge held in the electrode, the wiring 3002 takes on a different potential. Generally, If transistor 750 is an n-channel type, then the gate electrode of transistor 750 has a high frequency Apparent threshold V when Bell charge is given th_H The transistor 750 Apparent threshold V when a low level charge is applied to the gate electrode th_L twist This is because it becomes lower. Here, "apparent threshold voltage" refers to the voltage of transistor 750. It refers to the potential of the wiring 3005 necessary to set it to the OFF state. Therefore, the potential of the wiring 30 05 is set to V th_H and V th_L The potential V0 between them enables the discrimination of the charge applied to the gate electrode of the transistor 7 50. For example, in writing, when a High level charge is applied, if the potential of the wiring 3005 becomes V0 (> V th_H ), then the transistor 750 becomes "ON state". When a Low level charge is applied , even if the potential of the wiring 3005 becomes V0 (< V ), the transistor 750 th_L remains in the "OFF state". Therefore, by discriminating the potential of the wiring 3002, the information held can be read out. When the memory cells are arranged and used in an array, it is necessary to be able to read only the information of the desired memory cell. When the information is not read in this way, a potential such that the transistor 750 becomes OFF regardless of the state of the gate electrode, that is, a potential smaller than V 【0296】 th_H th_H th_H should be applied to the wiring 3005. Or, a potential such that the transistor 750 becomes ON regardless of the state of the gate electrode, that is, a potential larger than V th_L th_L th_L should be applied to the wiring 3 005. 【0297】 In the semiconductor device shown in this embodiment, by using a transistor with an extremely small off-current using an oxide semiconductor in the channel formation region, it is possible to hold the stored content for an extremely long time . That is, the refresh operation becomes unnecessary, or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced ​ Also, in the absence of power supply (however, it is desirable that the potential be fixed) However, it is possible to retain the contents of memories over a long period of time. 【0298】 Furthermore, the semiconductor device shown in this embodiment does not require a high voltage for writing information, and There are no issues with degradation of the child. For example, unlike conventional non-volatile memory, it does not use floating gates. Because there is no need to inject electrons into it or extract electrons from the floating gate, Problems such as degradation of the gate insulating film do not occur at all. In other words, the semiconductor according to the disclosed invention. The device does not have the limitations on the number of rewrite cycles that are a problem with conventional non-volatile memory, and Reliability improves dramatically. Furthermore, the on and off states of the transistors allow information to be transmitted. Because writing is performed, high-speed operation can be easily achieved. 【0299】 As described above, semiconductors that achieve miniaturization and high integration while also possessing high electrical characteristics. We can provide the device. 【0300】 This embodiment can be appropriately combined with other embodiments shown herein. . 【0301】 (Embodiment 3) In this embodiment, an example of a semiconductor device using a transistor, which is one aspect of the present invention, is provided. Next, we will explain using the drawings. Figure 19 is a circuit diagram of a semiconductor device according to one aspect of the present invention. This is an example. 【0302】 The semiconductor device shown in Figure 19 includes a capacitive element 660a, a capacitive element 660b, and a transistor 6 61a, transistor 661b, transistor 662a, transistor 662b Inverter 663a, Inverter 663b, Wiring BL, Wiring BLB, Wiring WL It has wiring CL and wiring GL. 【0303】 The semiconductor device shown in Figure 19 has inverters 663a and 663b connected in a ring configuration. This is a memory cell in which a flip-flop is formed. Output of inverter 663b The node from which the signal is output is designated as node VN1, and the output signal of inverter 663a is output. The node in question will be designated as node VN2. Furthermore, by arranging these memory cells in a matrix, A memory device (memory cell array) can be configured. 【0304】 The source and drain of transistor 662a are electrically connected to wiring BL, and the source, The other end of the drain is electrically connected to node VN1, and the gate is electrically connected to wiring WL. The source and drain of transistor 662b are electrically connected to node VN2, and The other end of the drain is electrically connected to wiring BLB, and the gate is electrically connected to wiring WL. do. 【0305】 The source and drain of transistor 661a are electrically connected to node VN1, and The other end of the drain is electrically connected to one electrode of the capacitive element 660a, and the gate is connected to wiring G Electrically connect to L. Here, the source and drain of transistor 661a are connected to each other. Let node NVN1 be the node between one electrode of the transistor 660a and the other electrode. One of the source and drains of 61b is electrically connected to node VN2, and the source and drain The other end is electrically connected to one electrode of the capacitive element 660b, and the gate is electrically connected to the wiring GL. To be continued. Here, the source and drain of transistor 661b, and the capacitive element 660b Let the node between one of the electrodes and be node NVN2. 【0306】 The other electrode of capacitive element 660a is electrically connected to the wiring CL. The other electrode of capacitive element 660b The electrodes are electrically connected to the wiring CL. 【0307】 The selection of the conduction and non-conduction states of transistors 662a and 662b is determined by the distribution It can be controlled by the potential applied to line WL. Transistor 661a and Transistor The conduction and non-conduction states of the Zistor 661b are controlled by the potential applied to the wiring GL. It is possible. 【0308】 The writing, retention, and reading operations of the memory cell shown in Figure 19 are described below. 【0309】 When writing, first, the potential corresponding to data 0 or data 1 is set on wiring BL and wiring BLB. Apply the solution. 【0310】 For example, if you want to write data 1, connect wiring BL to a high-level power supply potential (VDD), The wire BLB is set to ground potential. Next, connect transistor 662a and transistor 66 to the wiring WL. A potential (VH) greater than or equal to the potential obtained by adding VDD to the threshold voltage of 2b is applied. 【0311】 Next, the potential of the wiring WL is the threshold voltage of transistor 662a and transistor 662b. By setting it to full, the data 1 written to the flip-flop is retained. 【0312】 When reading, first set wiring BL and wiring BLB to VDD. Next, set wiring WL By applying VH, the wiring BL remains unchanged at VDD, but the wiring BLB becomes a transient. Discharge occurs via Ta662a and inverter663a, reaching ground potential. This wiring BL and The potential difference with the wiring BLB is amplified by a sense amplifier (not shown) and the data is held. Data 1 can be read. 【0313】 To write data 0, set wiring BL to ground potential and wiring BLB to VDD. Then, apply VH to the wiring WL. Next, set the potential of the wiring WL to transistor 662a By setting the threshold voltage of transistor 662b below this threshold voltage, the data is written to the flip-flop. Data 0 is retained. When reading, wiring BL and wiring BLB are set to VDD beforehand. By applying VH to wiring WL, wiring BLB remains unchanged at VDD, but wiring BL discharges via transistor 662b and inverter 663b, reaching ground potential. The potential difference between this wiring BL and wiring BLB is amplified and maintained by a sense amplifier. The data 0 can be read. 【0314】 Therefore, the semiconductor device shown in Figure 19 is a so-called SRAM (Static Random RAM). It functions as Access Memory. SRAM uses flip-flops. Since data is retained, a refresh operation is unnecessary. Therefore, data retention is not required. Power consumption can be reduced. Also, because capacitive elements are not used in the flip-flop. It is suitable for applications requiring high-speed operation. 【0315】 Furthermore, the semiconductor device shown in Figure 19 has a transistor 661a that connects from node VN1 to node It is possible to write data to the NVN1. Similarly, via transistor 661b Then, it is possible to write data from node VN2 to node NVN2. The data is used to put transistor 661a or transistor 661b into a non-conductive state. It is maintained by and. For example, even if the power supply is cut off, node VN1 and It may be possible to retain data from node VN2. 【0316】 Unlike conventional SRAMs, where data is immediately lost when the power supply is cut off, Figure 19 shows The semiconductor device shown can retain data even after the power supply is cut off. Therefore, as appropriate By cutting off the power supply potential, it is possible to realize semiconductor devices with low power consumption. For example, by using the semiconductor device shown in Figure 19 in the CPU's memory area, the CPU's memory can be reduced. It is also possible to reduce power consumption. 【0317】 Note that the period during which data is retained in nodes NVN1 and NVN2 is determined by transistor 6 It can be seen that it changes depending on the off-current of transistors 61a and 661b. Therefore Therefore, in order to extend the data retention period, transistor 661a and transistor 6 For 61b, a transistor with a low off-current should be used. Alternatively, a capacitive element could be used. This would require increasing the capacitance of 660a and the capacitive element 660b. 【0318】 For example, the transistor 100 and capacitive element 130 shown in Embodiment 1 are trans If used as element 661a and capacitive element 660a, the node NVN1 will be used for a long period of time. It becomes possible to hold the data. Similarly, transistor 100 and capacitive element 130 If used as transistor 661b and capacitive element 660b, it will provide long-term performance to node NVN2. It becomes possible to retain data over time. Therefore, transistor 661a and For transistor 661b, please refer to the description for transistor 100. Furthermore, regarding the capacitive elements 660a and 660b, the capacitive element 130 You should refer to the description. 【0319】 Furthermore, as described in the above embodiment, the transistor 100 and the capacitive element 130 are It can be fabricated by overlapping at least a portion of the transistor 750. (See Figure 19) Transistors included in inverter 662a, transistor 662b, and inverter 663a And the transistors included in inverter 663b are transistor 661a, transistor The element 661b, the capacitor element 660a, and the capacitor element 660b were fabricated by overlapping at least a portion of them. Therefore, the semiconductor device shown in Figure 19 can occupy more space compared to conventional SRAMs. In some cases, it is possible to manufacture them without significantly increasing the surface area. Transistor 6 62a, transistor 662b, inverter 663a, and transistors and inverters included in 62a, transistor 662b, and inverter 663a Regarding the transistors included in Verta 663b, the description is for transistor 750. You should refer to that. 【0320】 As described above, a semiconductor device according to one aspect of the present invention provides high performance relative to the occupied area. It can be seen that it possesses this capability. Furthermore, it can be seen that it is a highly productive semiconductor device. 【0321】 This embodiment can be appropriately combined with other embodiments shown herein. 【0322】 (Embodiment 4) In this embodiment, an example of a semiconductor device using a transistor, which is one aspect of the present invention, is provided. Let me explain. In this embodiment, a semiconductor, which is one aspect of the present invention, will be used as an example, with a CPU as the example. Let me explain the device. 【0323】 Figure 20 shows the configuration of an example of a CPU using at least some transistors according to one aspect of the present invention. Block. 【0324】 The CPU shown in Figure 20 is an ALU1191 (ALU: Arithmet) mounted on board 1190. IC logic unit, arithmetic circuit, ALU controller 1192, instruction Timing decoder 1193, interrupt controller 1194, timing controller 1195, Register 1196, Register Controller 1197, Bus Interface 1 198 (Bus I / F), rewritable ROM1199, and ROM interface It has a ROM I / F (1189). The substrate 1190 is a semiconductor substrate, SOI base A plate, glass substrate, etc. are used. ROM1199 and ROM interface 1189 are It may also be provided on a separate chip. Of course, the CPU shown in Figure 20 is a simplified representation of its configuration. This is just one example; actual CPUs have a wide variety of configurations depending on their application. For example, a configuration including the CPU or arithmetic circuit shown in Figure 20 is considered as one core, and multiple such cores are included Alternatively, the configuration may be such that each core operates in parallel. Furthermore, the CPU performs internal calculations. The number of bits that can be handled by circuits and data buses is, for example, 8 bits, 16 bits, 32 bits, 64 bits. This can be represented as a bit, etc. 【0325】 Instructions input to the CPU via the bus interface 1198 are instructions The signal is input to decoder 1193, decoded, and then processed by ALU controller 1192, interface Raptor controller 1194, register controller 1197, timing controller It is entered into 1195. 【0326】 ALU controller 1192, interrupt controller 1194, register controller R1197 and timing controller 1195 control various commands based on the decoded instructions. To perform the operation. Specifically, the ALU controller 1192 controls the operation of the ALU 1191. It generates a signal for that purpose. Also, the interrupt controller 1194 is the CPU programmer. During execution, interrupt requests from external input / output devices and peripheral circuits are prioritized and masked. The state is judged and processed. The register controller 1197 adds register 1196 It generates a response and reads or writes to register 1196 depending on the CPU state. 【0327】 Furthermore, the timing controller 1195 is connected to the ALU 1191 and the ALU controller 119 2. Instruction decoder 1193, interrupt controller 1194, and It generates signals to control the timing of the operation of the register controller 1197. For example, The timing controller 1195 uses the reference clock signal CLK1 to determine the internal clock signal It is equipped with an internal clock generation unit that generates CLK2, and the internal clock signal CLK2 is the above It supplies power to various circuits. 【0328】 In the CPU shown in Figure 20, a memory cell is located in register 1196. The transistors shown in the previous embodiment can be used as the 1196 memory cells. ru. 【0329】 In the CPU shown in Figure 20, the register controller 1197 receives information from the ALU 1191. Following the instructions, select the hold operation in register 1196. That is, register 11 In the memory cell of 96, data is retained by a flip-flop, or capacity Select whether to retain data using an element. Data retention using a flip-flop is If selected, power voltage is supplied to the memory cells in register 1196. If data retention in the capacitive element is selected, data rewriting to the capacitive element will not occur. This process can be performed to stop the supply of power voltage to the memory cells in register 1196. . 【0330】 Figure 21 is an example of a circuit diagram of a memory element that can be used as register 1196. The memory element 730 has a circuit 701 in which the stored data volatilizes when the power is cut off, and when the power is cut off the stored data Circuit 702 that does not volatilize, switch 703, switch 704, logic element 706 The circuit 702 includes a capacitive element 707 and a circuit 720 having a selection function. It has a child 708, a transistor 709, and a transistor 710. The 730 can also incorporate other elements such as diodes, resistors, and inductors as needed. It is acceptable to have it. 【0331】 Here, the memory device described in the above embodiment can be used in circuit 702. When the power supply voltage to component 730 is cut off, the gate of transistor 709 in circuit 702 The input to the terminal is continuously subjected to ground potential (0V) or a potential that turns off transistor 709. This configuration is defined as follows: For example, the gate of transistor 709 is grounded via a load such as a resistor. Let's assume that. 【0332】 Switch 703 is constructed using a single-conductivity (e.g., n-channel) transistor 713. Thus, switch 704 is configured to handle transistors with the opposite conductivity to a single-conductivity type (e.g., p-channel type). An example configuration using the ZISTA 714 is shown. Here, the first terminal of the switch 703 is connected to the transistor. Corresponding to either the source or drain of the switch 713, the second terminal of the switch 703 is connected to the transistor The other side of the source and drain of transistor 713 corresponds to switch 703, and the other side corresponds to transistor 713. The control signal RD input to the gate determines whether the first terminal and the second terminal are conducting or Non-conductivity (i.e., the ON or OFF state of transistor 713) is selected. The first terminal of transistor 704 corresponds to either the source or the drain of transistor 714, and the switch The second terminal of transistor 704 corresponds to the source and drain of transistor 714, and the switch Transistor 704 is controlled by the control signal RD input to the gate of transistor 714, which then controls the first terminal Continuity or non-conductivity between the first and second terminals (i.e., the ON state or OFF state of transistor 714) The "F" state is selected. 【0333】 One of the sources and drains of transistor 709 is one of the pair of electrodes of capacitive element 708. On the other hand, it is electrically connected to the gate of transistor 710. Here, the connection part is no Let's call it M2. One of the sources and drains of transistor 710 is supplied with a low power supply potential. It is electrically connected to a wire that can be connected (e.g., a GND wire), and the other is connected to switch 703. It is electrically connected to the first terminal (one of the source and drain of transistor 713). The second terminal of switch 703 (the other of the source and drain of transistor 713) is the switch The first terminal of 704 (one of the source and drain of transistor 714) is electrically connected. The second terminal of switch 704 (the other of the source and drain of transistor 714) It is electrically connected to wiring that can supply the power potential VDD. Terminal 2 (the source and drain of transistor 713) and the first terminal of switch 704 The terminals (one of the source and drain of transistor 714) and the input terminal of logic element 706 The connection part is electrically connected to one of the pair of electrodes of the capacitive element 707. Let the minute be node M1. The other electrode of the pair of electrodes of the capacitive element 707 is subjected to a constant potential input. This configuration can be achieved. For example, a low power supply potential (GND, etc.) or a high power supply potential (V A configuration can be made in which a DD (etc.) is input. One side is electrically connected to wiring that can supply a low power potential (e.g., a GND wire). The other electrode of the pair of electrodes in the capacitive element 708 is configured to receive a constant potential. This is possible. For example, when a low power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. This configuration can be achieved. The other electrode of the pair of electrodes of the capacitive element 708 is supplied with a low power supply potential. It is electrically connected to a power supply (e.g., a ground wire). 【0334】 Furthermore, capacitive elements 707 and 708 actively reduce parasitic capacitance of transistors and wiring. It is also possible to omit it by using it strategically. 【0335】 The gate of transistor 709 is input with the control signal WE. Switch 703 and Switch 704 controls the first terminal and the second terminal by a control signal RD which is different from the control signal WE. A conductive or non-conductive state is selected between the first and second terminals of one of the switches. When there is conductivity between the first and second terminals of the other switch, there is no conductivity between them. . 【0336】 The source and drain of transistor 709 are connected to the data held in circuit 701. A corresponding signal is input. In Figure 21, the signal output from circuit 701 is transmitted to the transistor. An example is shown where the source and drain of 709 are input to the other terminal of switch 703. The signal output from (the other side of the source and drain of transistor 713) is sent to logic element 70 The logic value is inverted by 6, resulting in an inverted signal which enters circuit 701 via circuit 720. To be empowered. 【0337】 Note that in Figure 21, the second terminal of switch 703 (source and slave of transistor 713) The signal output from the other side of the circuit is transmitted to circuit 701 via logic element 706 and circuit 720. An example of input is shown, but it is not limited to this. The second terminal of switch 703 (transistor The signals output from the source and drain (other side) of the TA713 can have their logic values ​​inverted. Alternatively, the input may be made to circuit 701. For example, the input from the input terminal may be made to circuit 701. If there is a node that holds a signal in which the logical value of the given signal is inverted, switch 703 The signal output from the second terminal (the other of the source and drain of transistor 713) Input can be made to the node. 【0338】 In Figure 21, transistor 709 is the same as transistor 100 exemplified in Embodiment 1 above. This can be used. Additionally, a control signal WE is input to the gate electrode, and the back gate electrode is connected. A control signal WE2 can be input to it. The control signal WE2 is a signal with a constant potential. That should suffice. This constant potential could be, for example, the ground potential (GND) or the source of transistor 709. A potential smaller than the threshold is selected. The control signal WE2 is the threshold of transistor 709. This is a potential signal used to control the value voltage, and it further reduces the Icut of transistor 709. This is possible. Note that transistor 709 is a transistor without a back gate electrode. You can also use a ZISTA. 【0339】 Furthermore, in Figure 21, among the transistors used in the memory element 730, Transistors other than 709 are placed on a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. A transistor in which a channel is formed can be formed. For example, a silicon layer or silicon A transistor can be formed on the circuit board to create a channel. Also, memory element 73 All transistors used in 0 are transistors whose channels are formed by an oxide semiconductor layer. It can also be called a ta. Alternatively, the memory element 730 may also have a cha in addition to the transistor 709. Nell may contain transistors formed from oxide semiconductor layers, and the remaining transistors The channel is formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. It can also be called a 'njista'. 【0340】 In Figure 21, circuit 701 can, for example, use a flip-flop circuit. Furthermore, logic elements 706 can be, for example, inverters or clocked inverters. It is possible. 【0341】 In one aspect of the present invention, in a semiconductor device, while the memory element 730 is not supplied with a power supply voltage, The data stored in circuit 701 is transferred by the capacitive element 708 provided in circuit 702. It can be held in place. 【0342】 Furthermore, transistors in which channels are formed in the oxide semiconductor layer exhibit extremely low off-current. For example, the off-current of a transistor in which a channel is formed in an oxide semiconductor layer has crystalline properties. It is significantly lower than the off-current of a transistor in which a channel is formed in silicon. Therefore, by using the transistor as transistor 709, the memory element 73 The signal held by the capacitive element 708 is maintained for a long period of time even when no power supply voltage is supplied to 0. In this way, the memory element 730 retains its stored contents (data) even when the power supply voltage is interrupted. It is possible to hold it. 【0343】 Furthermore, by providing switches 703 and 704, the pre-charge operation can be performed. Because it is a memory element characterized by performing the following, after the power supply voltage is restored, the circuit 701 returns to its original state This can shorten the time it takes to re-establish data retention. 【0344】 Furthermore, in circuit 702, the signal held by the capacitive element 708 is transmitted to transistor 71 It is input to the gate with value 0. Therefore, after the power supply voltage to memory element 730 is resumed... The signal held by the capacitive element 708 is transmitted to the state of transistor 710 (on state, ... It can be converted to an off state and read from circuit 702. Therefore, the capacitive element 7 Even if the potential corresponding to the signal held in 08 fluctuates slightly, the original signal can be read accurately. It is possible. 【0345】 Such memory elements 730 are used in the registers and cache memory of the processor. By using it in memory devices, it prevents the loss of data in memory devices due to the interruption of the power supply voltage. This is possible. Furthermore, after the power supply voltage is restored, it can quickly return to the state it was in before the power supply was interrupted. Therefore, the entire processor, or one of the components of the processor, Because power can be shut off even for a short time in multiple logic circuits, power consumption can be reduced. It is possible to obtain it. 【0346】 In this embodiment, although the memory element 730 was described as an example of being used as a CPU, the memory element 73 0 represents DSP (Digital Signal Processor) and custom LSI. LSIs such as PLDs (Programmable Logic Devices), RF ( It can also be applied to radio frequencies. 【0347】 This embodiment can be appropriately combined with other embodiments shown herein. . 【0348】 (Embodiment 5) In this embodiment, an example of a semiconductor device using a transistor, which is one aspect of the present invention, is provided. Let me explain. In this embodiment, we will use an RF tag as an example to illustrate one aspect of the present invention, which is a semiconductor Let me explain the body apparatus. 【0349】 An RF tag according to one aspect of the present invention has a memory circuit inside, stores information in the memory circuit, and It uses means of contact, such as wireless communication, to exchange information with the outside world. Therefore, RF tags are used for individual identification of items by reading their unique information. It can be used in systems and other applications. However, high reliability is required for these applications. Sex is required. 【0350】 The configuration of an RF tag will be explained using Figure 22. Figure 22 shows an example of an RF tag configuration. This is a lock diagram. 【0351】 As shown in Figure 22, the RF tag 800 is connected to the communicator 801 (also known as the interrogator, reader / writer, etc.). Antenna 8 receives a radio signal 803 transmitted from antenna 802 connected to ( It has 04. The RF tag 800 also has a rectifier circuit 805, a constant voltage circuit 806, and a demodulation circuit 8 It has a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Furthermore, the semiconductor of the transistor exhibiting rectification action included in the demodulation circuit 807 has a reverse current For example, an oxide semiconductor can be used to sufficiently suppress the reverse This suppresses the decrease in rectification due to directional current and prevents the output of the demodulation circuit from saturating. In other words, the output of the demodulation circuit can be made nearly linear with respect to the input of the demodulation circuit. Oh, the data transmission method is electromagnetic, where a pair of coils are placed facing each other and communicate through mutual induction. Coupling method, electromagnetic induction method which uses an inductive electromagnetic field for communication, radio wave method which uses radio waves for communication. These can be broadly categorized into three types. The RF tag 800 can be used in any of these methods. 【0352】 Next, the configuration of each circuit will be explained. Antenna 804 is connected to the communication device 801. This is for transmitting and receiving wireless signals 803 with Tenor 802. Also, a rectifier circuit 8 05 rectifies the input AC signal generated by receiving a wireless signal with antenna 804. For example, half-wave voltage doubling rectification is performed, and the rectified signal is smoothed by a subsequent capacitive element. This is a circuit for generating the input potential. Note that the input or output side of the rectifier circuit 805 It may have a limiter circuit. A limiter circuit is a circuit that, when the amplitude of the input AC signal is large, When the generated voltage is high, control is implemented to prevent power exceeding a certain level from being input to the subsequent circuit. This is a circuit for that purpose. 【0353】 The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. This is a circuit. Note that the constant voltage circuit 806 may also have an internal reset signal generation circuit. The reset signal generation circuit utilizes the stable rise of the power supply voltage to generate the logic circuit 80. This is a circuit for generating a reset signal for number 9. 【0354】 The demodulation circuit 807 demodulates the input AC signal by detecting its envelope and generates a demodulated signal. This is a circuit for that purpose. Furthermore, the modulation circuit 808 responds to the data output from the antenna 804. This is a circuit for performing modulation. 【0355】 Logic circuit 809 is a circuit for analyzing and processing demodulated signals. Memory circuit 810 is This is a circuit that holds the input information, and includes a row decoder, column decoder, memory area, etc. It has. Furthermore, ROM811 stores unique numbers (IDs), etc., and outputs them according to the processing. This is a circuit for that purpose. 【0356】 Furthermore, the circuits described above can be selected or omitted as appropriate. 【0357】 Here, the semiconductor device described in the above embodiment can be used in the memory circuit 810. A storage device according to one aspect of the present invention can retain information even when the power supply is cut off. Therefore, it is suitable for RF tags. Furthermore, a storage device according to one aspect of the present invention allows data to be written. Because the power (voltage) required is lower than that of conventional non-volatile memory, when reading data... Furthermore, it is possible to avoid creating a difference in the maximum communication distance during writing. This can prevent malfunctions or incorrect writing that may occur due to insufficient power during high load. 【0358】 Furthermore, a storage device according to one aspect of the present invention can be used as a non-volatile memory. Therefore, it can also be applied to ROM811. In that case, the manufacturer will need to provide the ROM811. A separate command is provided for writing the data, preventing users from freely rewriting it. It is preferable that the producer writes a unique number on the product before shipping it. Therefore, instead of assigning a unique number to every RF tag produced, we assign one to each good product that is shipped. It becomes possible to assign a unique number, and the unique numbers of products after shipment will not be discontinuous. This eliminates the need for post-shipment product management, making customer management easier. 【0359】 Below, an example of the use of an RF tag according to one aspect of the present invention will be explained with reference to Figure 23. F tags have a wide range of uses, including banknotes, coins, securities, bearer bonds, and certificates. Documents such as driver's licenses and resident registration certificates (see Figure 23(A)), packaging containers (wrapping paper, bottles, etc.) See Figure 23(C).), recording medium (DVDs, videotapes, etc., see Figure 23(B)), Items to be transported (bicycles, etc., see Figure 23(D)), personal belongings (bags, glasses, etc.), food products, plants. Animals, human bodies, clothing, household goods, medical products including drugs and pharmaceuticals, or electronic devices (LCD displays) Articles such as display devices, EL display devices, television equipment, or mobile phones, or each article It can be used by attaching it to luggage tags (see Figures 23(E) and 23(F)), etc. can. 【0360】 An RF tag 4000 according to one aspect of the present invention can be attached to or embedded in the surface of an object. It is fixed to the product. For example, in the case of a book, it is embedded in the paper, and in the case of a package made of organic resin. The RF tag is embedded inside the organic resin and fixed to each article. The 4000 is designed to be small, thin, and lightweight, and even after being fixed to an object, it does not affect the design of the object itself. It does not impair the integrity of banknotes, coins, securities, bearer bonds, or certificates. Authentication functionality can be provided to the same type of object using an RF tag 4000 according to one aspect of the present invention. This authentication function can be used to prevent counterfeiting. It can also be used for packaging containers and recording media. The present invention relates to the body, personal belongings, food products, clothing, household goods, or electronic devices, etc. By attaching RF tags 4000, the efficiency of systems such as inspection systems can be improved. This is possible. Furthermore, even vehicles can be fitted with an RF tag 4000 according to one aspect of the present invention. By attaching it, you can enhance security against theft and other crimes. 【0361】 As described above, an RF tag according to one aspect of the present invention can be used for each of the above-mentioned applications. can. 【0362】 This embodiment can be appropriately combined with other embodiments shown herein. 【0363】 (Embodiment 6) In this embodiment, an example of a semiconductor device, which is one aspect of the present invention, will be described with reference to the drawings. In this embodiment, a semiconductor device which is one aspect of the present invention is described using a display device as an example. explain. 【0364】 Figure 24(A) shows an example of a display device. The display device shown in Figure 24(A) has a pixel section 401 The scan line drive circuit 404 and the signal line drive circuit 406 are arranged in parallel or approximately parallel to each other. Furthermore, m scan lines 407 whose potential is controlled by the scan line drive circuit 404, and each The two are arranged in parallel or nearly parallel, and the potential is controlled by the signal line drive circuit 406. It has signal lines 409 and, furthermore, the pixel section 401 is arranged in a matrix of multiple It has 411 pixels. 【0365】 Furthermore, by using three pixels 411 as one pixel, color display can be achieved. For example, a pixel 411 that emits red light, a pixel 411 that emits green light, and a pixel 411 that emits blue light By making the 411 pixels function as a single pixel, color display can be achieved. The light emitted by each of the 411 pixels can be red, green, and blue, as well as yellow, cyan, magenta, and other colors. That's fine. 【0366】 Alternatively, four pixels 411 may be used as a single pixel. For example, four pixels 411 are The configuration may also consist of four pixels that emit red, green, blue, and yellow light, respectively. By increasing the number 11, the reproduction of midtones in particular can be improved. Therefore, the display device This can improve the display quality. Also, the four pixels 411 each represent red, green, blue, and white. It may also be configured to emit light. By providing a pixel 411 that emits white light, the brightness of the display area can be reduced. The degree can be increased. Also, depending on the application of the display device, two pixels 411 can be combined into one. It can also be used as a pixel. 【0367】 Furthermore, the display devices shown in Figure 24(A) are parallel or nearly parallel to each other along the scan line 407. It has capacity lines 415 arranged along the signal lines 409. They may be arranged in parallel or approximately parallel. Also, the scan line drive circuit 404 and signal The line drive circuit 406 is sometimes referred to collectively as the drive circuit section. 【0368】 Each scan line 407 is one of the pixels 411 arranged in m rows and n columns in the pixel section 401. It is electrically connected to n pixels 411 arranged in any row. Also, each signal line 409 m pixels 411, among the m rows and n columns of pixels 411, located in any of the columns. It is electrically connected to m and n, both of which are integers greater than or equal to 1. Also, each capacitance line 415 is , n pixels 411 located in any row out of the m rows and n columns of pixels 411 They are electrically connected. Furthermore, the capacitance line 415 runs parallel to the signal line 409, and each is parallel to the other. If they are arranged in roughly parallel directions, then any of the pixels 411 arranged in m rows and n columns It is electrically connected to m pixels 411 arranged in a row. 【0369】 Figures 24(B) and 24(C) are used for pixel 411 of the display device shown in Figure 24(A). This shows a circuit configuration that can be implemented. 【0370】 The pixel 411 shown in Figure 24(B) consists of a liquid crystal element 432, a transistor 431_1, and a capacitance. It has element 433_1 and, as transistor 431_1, disclosed in the above embodiment A transistor 100 can be used. 【0371】 The potential of one of the pair of electrodes of the liquid crystal element 432 is set appropriately according to the specifications of the pixel 411. The orientation state of the liquid crystal element 432 is set according to the data being written to it. A common potential (common potential) is applied to one of the pair of electrodes of the liquid crystal element 432 that each element 411 possesses. You may also assign a position to one of the pair of electrodes of the liquid crystal element 432 for each pixel 411 in each row. A different potential may be applied. 【0372】 For example, the driving method for a display device equipped with a liquid crystal element 432 may be TN mode, STN mode D, VA mode, ASM (Axially Symmetric Aligned Mi cro-cell) mode, OCB (Optically Compensated B irefringence) mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode, MVA mode, PVA (Patterned Ver (Critical Alignment) mode, IPS mode, FFS mode, or TBA You may also use modes such as (Transverse Bend Alignment). In addition, as a method of driving the display device, there is also ECB (Electric Ally Controlled Birefringence) mode, PDLC (P Olymer Dispersed Liquid Crystal (PNLC) mode, (Polymer Network Liquid Crystal) mode, guest host There are modes such as St Mode. However, this is not limited to these, and includes liquid crystal elements and their driving methods. Various materials can be used. 【0373】 Furthermore, a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent More liquid crystal elements may be constructed. Liquid crystals exhibiting the blue phase have a short response time of 1 msec or less. Furthermore, because it is optically isotropic, orientation processing is unnecessary, and it exhibits low dependence on the viewing angle. 【0374】 In pixel 411 at row m, column n, the source electrode and drain of transistor 431_1. One electrode is electrically connected to the signal line DL_n, and the other is connected to a pair of electrodes on the liquid crystal element 432. It is electrically connected to the other side. Also, the gate electrode of transistor 431_1 is connected to scan line G It is electrically connected to L_m. Transistor 431_1 is either on or off. This provides a function to control the writing of data to the data signal. 【0375】 One of the pair of electrodes of the capacitive element 433_1 is connected to a wiring to which a potential is supplied (hereinafter referred to as "capacitive wire CL"). It is electrically connected to the other side, and the other side is electrically connected to the other side of the pair of electrodes of the liquid crystal element 432. It is connected to the capacitance line CL. The potential value of the capacitance line CL is set appropriately according to the specifications of pixel 411. The capacitive element 433_1 has the function of a holding capacity that holds the written data. ru. 【0376】 For example, in the display device having pixels 411 as shown in Figure 24(B), the scan line driving circuit 404 Each row's pixel 411 is selected sequentially, and transistor 431_1 is turned on to generate the data signal. Write the data. 【0377】 Pixel 411, on which data has been written, is maintained by the transistor 431_1 being turned off. The image enters a state of being held. By performing this sequentially for each row, the image can be displayed. 【0378】 Furthermore, the pixel 411 shown in Figure 24(C) consists of a transistor 431_2 and a capacitive element 433_ It has transistor 434 and light-emitting element 435. Transistor 431_2 and Therefore, the transistor 100 disclosed in the above embodiment can be used. As transistor 434, the transistor 100 disclosed in the above embodiment can be used. Cut. 【0379】 One of the source and drain electrodes of transistor 431_2 receives a data signal. It is electrically connected to the wiring (hereinafter referred to as "signal line DL_n"). Furthermore, the transistor The gate electrode of the ZISTA 431_2 is connected to the wiring to which the gate signal is applied (hereinafter referred to as "scan line GL_ It is called "m". ) It is electrically connected. 【0380】 Transistor 431_2, by being in an ON or OFF state, controls the data signal. It has a function to control data writing. 【0381】 One of the pair of electrodes of the capacitive element 433_2 is electrically connected to node 436, and the other is connected to It is electrically connected to node 437. 【0382】 Capacitive element 433_2 functions as a retention capacitor for holding the written data. 【0383】 One of the source and drain electrodes of transistor 434 is connected to the potential supply line VL_a. They are electrically connected. Furthermore, the gate electrode of transistor 434 is electrically connected to node 436. It connects to the network. 【0384】 One of the anodes and cathodes of the light-emitting element 435 is electrically connected to the potential supply line VL_b. The other end is electrically connected to node 437. 【0385】 For example, the light-emitting element 435 is an organic electroluminescent element (also known as an organic EL element). (u) and the like can be used. However, the light-emitting element 435 is not limited to this, Inorganic EL elements made of inorganic materials may also be used. 【0386】 Furthermore, a high power supply potential VDD is supplied to one of the potential supply lines VL_a and VL_b. On the other hand, a low power supply potential VSS is applied. 【0387】 In the display device having pixels 411 shown in Figure 24(C), the scanning line driving circuit 404 drives each row of pixels Element 411 is selected sequentially, and transistor 431_2 is turned on to process the data signal. Write it down. 【0388】 The pixel 411 on which data has been written is maintained by the transistor 431_2 being turned off. It enters a holding state. Furthermore, the transistor 434's so The amount of current flowing between the drain electrode and the light-emitting element 435 is controlled by the current flowing through it. It emits light with brightness corresponding to the amount of light. By doing this sequentially for each row, an image can be displayed. 【0389】 This embodiment can be appropriately combined with other embodiments shown herein. . 【0390】 (Embodiment 7) In this embodiment, regarding a display module to which a semiconductor device according to one aspect of the present invention is applied: This will be explained using Figure 25. 【0391】 The display module 8000 shown in Figure 25 consists of an upper cover 8001 and a lower cover 8002. In between, the touch panel 8004 is connected to the FPC8003, and the FPC8005 is connected to the touch panel 8004. Cell 8006, backlight unit 8007, frame 8009, printed circuit board 801 0, has battery 8011. Note that backlight unit 8007, battery 8 It may not have features such as 011 or the touch panel 8004. 【0392】 A semiconductor device according to one aspect of the present invention can be used, for example, as cell 8006. 【0393】 The upper cover 8001 and the lower cover 8002 are the touch panel 8004 and cell 80 The shape and dimensions can be appropriately modified to match the size of 06. 【0394】 The touch panel 8004 uses a resistive or capacitive touch panel, and cell 8006 It can be used by superimposing it on the other substrate. Also, touch the opposing substrate (encapsulating substrate) of cell 8006. It is also possible to incorporate panel functionality. Alternatively, within each pixel of cell 8006... It is also possible to incorporate an optical sensor and use an optical touch panel. Alternatively, cell 8006 It is also possible to provide touch sensor electrodes within each pixel, thereby creating a capacitive touch panel. ru. 【0395】 The backlight unit 8007 has a light source 8008. The light source 8008 is used as the backlight. A configuration using a light-diffusing plate, which is provided at the end of unit 8007, may also be used. 【0396】 Frame 8009 provides protection for cell 8006, as well as the operation of printed circuit board 8010. It may also function as an electromagnetic shield to block the generated electromagnetic waves. The Mu8009 may also function as a heat sink. 【0397】 The printed circuit board 8010 is a power supply circuit and a signal for outputting video and clock signals. It has a power processing circuit. The power supply that provides power to the power supply circuit is an external commercial power supply. Alternatively, a power source provided separately by battery 8011 may be used. In that case, it is not necessary to have battery 8011. 【0398】 Furthermore, the display module 8000 includes additional components such as polarizing plates, phase difference plates, and prism sheets. They may also be provided. 【0399】 This embodiment can be appropriately combined with other embodiments shown herein. 【0400】 (Embodiment 8) This embodiment describes an example of an electronic device using a semiconductor device according to one aspect of the present invention. I will reveal it. 【0401】 Electronic devices using a semiconductor device according to one aspect of the present invention include display devices such as televisions and monitors. Lighting equipment, desktop or notebook personal computers, word processors The data is stored on recording media such as DVDs (Digital Versatile Discs). Image playback devices that play back still images or videos, portable CD players, radios, tapes Recorder, headphone stereo, stereo, desk clock, wall clock, cordless phone handset transceivers, mobile phones, car phones, portable game consoles, tablet devices, pachinko Large game consoles such as machines, calculators, personal digital assistants, electronic organizers, e-books, electronic translators, voice input devices High-frequency processing equipment such as power tools, video cameras, digital still cameras, electric shavers, and microwave ovens. Heating devices, electric rice cookers, electric washing machines, electric vacuum cleaners, water heaters, electric fans, hair dryers, air conditioners Air conditioning equipment such as conditioners, humidifiers, and dehumidifiers, dishwashers, dish dryers, and clothes dryers. Bedding dryer, electric refrigerator, electric freezer, electric refrigerator-freezer, DNA storage freezer, flashlight Examples include tools such as chainsaws, smoke detectors, and medical equipment such as dialysis machines. Furthermore, Emergency lights, traffic lights, conveyor belts, elevators, escalators, industrial robots, power storage Examples include storage systems, power leveling systems, and energy storage devices for smart grids. Furthermore, mobile devices propelled by electric motors using electricity from energy storage systems also fall under the category of electronic equipment. This shall be included in the above-mentioned mobile devices, for example, electric vehicles (EVs), internal combustion engines and electric vehicles. Hybrid electric vehicles (HEVs) and plug-in hybrid electric vehicles (PHEVs) that combine the two motives, Tracked vehicles that replace these tire wheels with tracks, and motorized vehicles including electric assist bicycles. Bicycles, motorcycles, electric wheelchairs, golf carts, small or large vessels, submarines, helicopters Examples include aircraft, rockets, satellites, space probes and planetary probes, and spacecraft. . 【0402】 Figure 26(A) shows an example of a portable game console, comprising a casing 901, casing 902, display unit 903, Display unit 904, microphone 905, speaker 906, operation keys 907, stylus It has 908 etc. Note that the portable game console shown in Figure 26(A) has two display units 903 It has a display unit 904, but the number of display units that a portable game console has is not limited to this. I can't. 【0403】 Figure 26(B) shows an example of a mobile data terminal, consisting of the first housing 911, the second housing 912, and Table 1. It has a display unit 913, a second display unit 914, a connection unit 915, an operation key 916, etc. First display unit 913 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connecting part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connecting part 915. The video in the first display unit 913 is connected to the first housing 911 and the second housing in the connection unit 915. The configuration may be such that it switches according to the angle between it and the housing 912. Also, the first display unit At least one of 913 and the second display unit 914 is provided with a function as a position input device. A display device may be used. Note that the function as a position input device is the display device. It can be added by installing a touch panel. Alternatively, it can be used as a position input device. This can also be achieved by installing a photoelectric conversion element, also called a photosensor, in the pixel section of the display device. It can be added. 【0404】 Figure 26(C) shows an example of a notebook personal computer, consisting of a casing 921 and a display unit 92 2. It has a keyboard 923, a pointing device 924, etc. 【0405】 Figure 26(D) shows an example of an electric refrigerator-freezer, and includes a casing 931, a door for the refrigerator compartment 932, and a freezer compartment It has doors 933, etc. 【0406】 Figure 26(E) shows an example of a video camera, consisting of a first housing 941, a second housing 942, and a display unit 9 43, it has an operation key 944, a lens 945, a connecting part 946, etc. Operation key 944 and The lens 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connecting part 946. The angle between the first housing 941 and the second housing 942 can be changed by the connecting part 946. It is possible. The video in the display unit 943 is connected to the first housing 941 and the second housing in the connection unit 946. The configuration may also be configured to switch according to the angle between it and body 942. 【0407】 Figure 26(F) is an example of an automobile, consisting of a body 951, wheels 952, dashboard 953, It has lights such as the 954. 【0408】 This embodiment can be appropriately combined with other embodiments shown herein. [Examples] 【0409】 In this embodiment, tungsten and silicon are added to indium tin oxide (hereinafter referred to as "ITO"). Also called "Si" (or "Indium Gallium Zinc Oxide"). , and nitrogen-added indium gallium zinc oxide (hereinafter also referred to as "IGZON") A sample in which an insulating layer containing more oxygen than satisfies the stoichiometric composition is formed on top of ( ) We will explain the results of analyzing the amount of oxygen molecules released by heating in each sample using TDS. . 【0410】 <Sample preparation> Figure 27(A) shows a schematic diagram of the cross-sectional structure of the sample. The sample is a single-crystal silicon substrate 2001 A thermal oxide film 2002 with a thickness of 100 nm is formed on top, and a barrier layer 201 is placed on top of the thermal oxide film 2002. Forming 3, oxygen molecules satisfying stoichiometric composition are applied to the barrier layer 2013 by sputtering. A 300 nm thick silicon oxide layer 2004 containing more oxygen than was formed. 【0411】 [Sample 2010] A 150 nm thick layer of tungsten was formed as the barrier layer 2013 using the sputtering method. The sample was designated as Sample 2010. 【0412】 〔Sample 2020〕 As the barrier layer 2013, a sample in which ITOSi with a thickness of 50 nm was formed by sputtering was used as Sample 2020. 【0413】 〔Sample 2030〕 As the barrier layer 2013, a target with an atomic ratio of In:Ga:Zn = 1:1:1 was used, and a mixed gas of oxygen and argon was used as the sputtering gas to form IGZO with a thickness of 50 nm, and this sample was used as Sample 2030. 【0414】 〔Sample 2040〕 As the barrier layer 2013, a target with an atomic ratio of In:Ga:Zn = 1:1:1 was used, and argon was used as the sputtering gas to form IGZO with a thickness of 50 nm, and this sample was used as Sample 2040. 【0415】 〔Sample 2050〕 As the barrier layer 2013, a target with an atomic ratio of In:Ga:Zn = 1:1:1 was used, and nitrogen was used as the sputtering gas to form IGZON with a thickness of 50 nm, and this sample was used as Sample 2050. 【0416】 <TDS Analysis Results> TDS analysis (temperature-programmed desorption gas analysis) was performed on Samples 2010 to 2050. In Fig. 27(B), the analysis results of the release amount of the gas with M / z = 32 (oxygen molecule) by TDS analysis are shown. In Fig. 27(B), the horizontal axis is the substrate temperature, and the vertical axis is the signal intensity proportional to the release amount of the gas having a specific molecular weight. The total amount of molecules released to the outside corresponds to the integral value of the signal intensity. Therefore, depending on the height of the peak intensity, the amount contained in the oxide insulating film is determined. The total amount of molecules can be evaluated. 【0417】 In Figure 27(B), samples 2020 to 2050 have a higher oxygen content compared to sample 2010. It can be seen that a large amount of molecules are released. From this, it can be seen that in sample 2010, silicon oxide layer 2 Most of the oxygen contained in 004 diffused into the tungsten barrier layer 2013. It can be inferred that... On the other hand, oxygen permeates through the barrier layer 2013 of samples 2020 to 2050. Because it is difficult to do so, oxygen contained in the silicon oxide layer 2004 is released to the outside, and as a result, oxygen It can be inferred that a large amount of molecular release was detected. 【0418】 This example demonstrates that tungsten is a material that readily permeates oxygen. TOSi, IGZO, and IGZON are materials that are poorly permeable to oxygen. . [Examples] 【0419】 In this example, a different sample from that used in Example 1 was used to produce tungsten, ITOSi, and IGZO. , or formed on IGZON, containing more oxygen than satisfactorily satisfying the oxygen composition. This section explains the results of a TDS analysis of the amount of oxygen molecules released from the insulating layer due to heating. 【0420】 <Sample preparation> Using Figures 28(A) and 28(B), the cross-sectional structure of the prepared sample and the method of preparation are shown. Let me explain. First, prepare a sample similar to that in Example 1, and add more oxygen than that which satisfies the stoichiometric composition. A cap layer 2005 is formed on a 300 nm thick silicon oxide layer 2004 containing oxygen. To achieve this, the cap layer 2005 is made using the sputtering method with an In:Ga:Zn ratio of 1:1:1. Using a target with a specific atomic ratio, a mixed gas of oxygen and argon is used as the sputtering gas. A 50 nm thick IGZO was formed using this method (see Figure 28(A)). 【0421】 Next, the above sample was subjected to a heat treatment at 450°C for 1 hour under a nitrogen atmosphere. Subsequently, The treatment was performed at 450°C for 1 hour under an oxygen atmosphere. After the heat treatment was completed, the cap layer 200 Layer 5 was removed, exposing the silicon oxide layer 2004 (see Figure 28(B)). 【0422】 [Sample 2110] A 150 nm thick layer of tungsten was formed as the barrier layer 2013 using the sputtering method. The sample was designated as sample 2110. 【0423】 [Sample 2120] As a barrier layer 2013, a 50nm thick ITOSi was formed using the sputtering method. The material was designated as sample 2120. 【0424】 [Sample 2130] As barrier layer 2013, an atomic ratio of In:Ga:Zn=1:1:1 was used by sputtering. Using the target, a mixture of oxygen and argon is used as the sputtering gas to determine the thickness. A sample on which 50 nm IGZO was formed was designated as sample 2130. 【0425】 [Sample 2140] As barrier layer 2013, an atomic ratio of In:Ga:Zn=1:1:1 was used by sputtering. Using the target and argon as the sputtering gas, a 50nm thick IGZ was created. The sample in which oxygen was formed was designated as sample 2140. 【0426】 [Sample 2150] As barrier layer 2013, an atomic ratio of In:Ga:Zn=1:1:1 was used by sputtering. Using the target of , nitrogen was used as the sputtering gas to form an IGZON with a thickness of 50 nm The sample was designated as Sample 2150. 【0427】 <TDS analysis results> TDS analysis (temperature-programmed desorption gas analysis) was performed on Samples 2110 to 2150. Fig 28(C) shows the analysis results of the emission amount of the gas with M / z = 32 (oxygen molecule) by TDS analysis In Fig 28(C), the horizontal axis is the substrate temperature, and the vertical axis is the signal intensity proportional to the emission amount of the gas having a specific molecular weight. 【0428】 In Fig 28(C), it can be seen that almost no oxygen molecule emission was confirmed in Sample 2110 Also, in Samples 2120 to 2150, oxygen molecule emission was clearly confirmed . By attaching the cap layer 2005 and performing heat treatment, in Sample 2110, most of the oxygen more than the oxygen satisfying the stoichiometric composition contained in the silicon oxide layer 2004 was presumably diffused into the barrier layer 2013 formed of tungsten. Also, the barrier layer 2013 and the cap layer 2005 of Samples 212 0 to 2150 are difficult for oxygen to permeate , so it can be inferred that more oxygen than the oxygen satisfying the stoichiometric composition remained in the silicon oxide layer 2004 even after heat treatment. From this example, it can be seen that tungsten is a material that easily permeates oxygen. Also, ITOSi, IGZO, and IGZON are materials that are difficult for oxygen to permeate 【0429】 It can be seen. . 【Explanation of symbols】 【0430】 100 Transistor 101 Substrate 102 electrode 103 Electrode 104 Electrode 105 Insulating layer 106 Insulating layer 107 Insulating layer 10⁸ Oxide semiconductor layer 109 Electrode 110 Insulating layer 111 Electrode 112 Insulating layer 113 Insulating layer 114 Electrode 115 Insulating layer 116 Electrode 119 Electrode 120 Insulating layer 121 Conductive layer 130 Capacitive elements 382 Ec 386 Ec 390 Trap Level 401 pixel section 404 Scan Line Drive Circuit 406 Signal Line Drive Circuit 407 scan lines 409 signal line 411 pixels 415 Capacity Line 432 liquid crystal elements 434 transistors 435 Light-emitting element 436 nodes 437 nodes 700 circuit boards 701 Circuit 702 Circuit 703 Switch 704 Switch 706 Logical Component 707 Capacitive element 708 Capacitive element 709 Transistors 710 transistors 713 Transistors 714 transistors 720 circuits 730 memory elements 750 transistors 751 Electrode 752 Insulating layer 753 Channel formation region 754 n-type impurity region 755 n-type impurity region 756 Sidewall insulation layer 789 element isolation region 790 Insulating layer 791 Insulating layer 800 RF tags 801 Communication device 802 Antenna 803 Wireless signal 804 Antenna 805 Rectifier circuit 806 Constant Voltage Circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuits 810 Memory circuit 811 ROM 901 cabinet 902 cabinet 903 Display section 904 Display section 905 Microphone 906 Speakers 907 Operation Keys 908 Stylus 911 cabinet 912 cabinet 913 Display section 914 Display section 915 Connection part 916 Operation Keys 921 cabinet 922 Display section 923 Keyboard 924 Pointing Devices 931 cabinet 932 Refrigerator door 933 Freezer door 941 cabinet 942 cabinets 943 Display section 944 Operation Keys 945 lens 946 Connection part 951 Body 952 wheels 953 Dashboard 954 Light 1010 Electronic gun chamber 1012 Optical system 1014 Sample Room 1016 Optical system 1018 Camera 1020 Observation Room 1022 Film Room 1024 electronic 1028 Substance 1032 Fluorescent board 1189 ROM Interface 1190 circuit board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM 2001 Single-crystal silicon substrate 2002 Thermal Oxide Film 2004 Silicon oxide layer 2005 Cap layer 2010 Sample 2013 Barrier layer 2020 Sample 2030 Sample 2040 samples 2050 samples 2110 Samples 2120 samples 2130 samples 2140 samples 2150 samples 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 4000 RF tags 8000 Display Module 8001 Top cover 8002 Lower cover 8003 FPC 8004 Touch Panel 8005 FPC 8006 cell 8007 Backlight Unit 8008 light source 8009 Frame 8010 Printed Circuit Board 8011 Battery 102a electrode 102b electrode 103a electrode 103b electrode 104a electrode 104b electrode 108a Oxide semiconductor layer 10⁸b oxide semiconductor layer 10⁸c oxide semiconductor layer 118a Oxide semiconductor layer 118b Oxide semiconductor layer 383a Ec 383b Ec 383c Ec 431_1 Transistor 431_2 Transistor 433_1 Capacitive element 433_2 Capacitive element 660a Capacitive element 660b Capacitive element 661a Transistor 661b Transistor 662a Transistor 662b transistor 663a Inverter 663b Inverter

Claims

[Claim 1] A semiconductor device having a transistor and a capacitive element electrically connected to one of the source electrode and drain electrode of the transistor, A first conductive layer having the function of the first gate electrode of the transistor, A second conductive layer having the same material as the first conductive layer, A third conductive layer having the same material as the first conductive layer, A first insulating layer having a region in contact with the upper surface of the first conductive layer, a region in contact with the upper surface of the second conductive layer, and a region in contact with the upper surface of the third conductive layer, An oxide semiconductor layer having a region located above the first insulating layer and having a channel formation region for the transistor, A second insulating layer having a region located above the oxide semiconductor layer, A fourth conductive layer having a region that overlaps with the oxide semiconductor layer via the second insulating layer and functioning as the second gate electrode of the transistor, A fifth conductive layer having a region in contact with the upper surface of the oxide semiconductor layer and a region overlapping with the second conductive layer, and functioning as one of the source electrode and drain electrode of the transistor, A sixth conductive layer having a region in contact with the upper surface of the oxide semiconductor layer and a region in contact with the upper surface of the third conductive layer through an opening in the first insulating layer, and having the same material as the fifth conductive layer, A third insulating layer having a region in contact with the upper surface of the fifth conductive layer and a region in contact with the upper surface of the sixth conductive layer, The opening in the first insulating layer does not overlap with the oxide semiconductor layer. The second conductive layer functions as one electrode of the capacitive element. In a plan view, the first conductive layer has a region that extends in a direction intersecting the channel length direction of the transistor. In a plan view, the second conductive layer has a region that extends in a direction intersecting the channel length direction of the transistor. A semiconductor device in which, in a plan view, the third conductive layer has a region that extends in a direction intersecting the channel length direction of the transistor. [Claim 2] A semiconductor device having a transistor and a capacitive element electrically connected to one of the source electrode and drain electrode of the transistor, A first conductive layer having the function of the first gate electrode of the transistor, A second conductive layer having the same material as the first conductive layer, A third conductive layer having the same material as the first conductive layer, A first insulating layer having a region in contact with the upper surface of the first conductive layer, a region in contact with the upper surface of the second conductive layer, and a region in contact with the upper surface of the third conductive layer, An oxide semiconductor layer having a region located above the first conductive layer and having a channel formation region for the transistor, A second insulating layer having a region located above the oxide semiconductor layer, A fourth conductive layer having a region that overlaps with the oxide semiconductor layer via the second insulating layer and functioning as the second gate electrode of the transistor, A fifth conductive layer having a region in contact with the upper surface of the oxide semiconductor layer and a region overlapping with the second conductive layer, and functioning as one of the source electrode and drain electrode of the transistor, A sixth conductive layer having a region in contact with the upper surface of the oxide semiconductor layer and a region in contact with the upper surface of the third conductive layer through an opening in the first insulating layer, and having the same material as the fifth conductive layer, A third insulating layer having a region in contact with the upper surface of the fifth conductive layer and a region in contact with the upper surface of the sixth conductive layer, The opening in the first insulating layer does not overlap with the oxide semiconductor layer. The second conductive layer functions as one electrode of the capacitive element. In a plan view, the first conductive layer has a region that extends in a direction intersecting the channel length direction of the transistor. In a plan view, the second conductive layer has a region that extends in a direction intersecting the channel length direction of the transistor. In a plan view, the third conductive layer has a region that extends in a direction intersecting the channel length direction of the transistor. A semiconductor device wherein the first insulating layer has an opening in a region that overlaps with the second conductive layer. [Claim 3] In claim 1 or 2, The fifth conductive layer and the sixth conductive layer have a laminated structure, wherein the semiconductor device is a semiconductor device.