Semiconductor equipment

Abstract

The present invention improves the characteristics in a semiconductor device produced from a wafer used in a shared manner in a plurality of production processes.　This semiconductor device comprises a pad opening, a wiring layer, and a dummy pattern. The pad opening in the semiconductor device is formed on the front surface of a substrate. In addition, a predetermined electrode pad is provided to the pad opening in the semiconductor device. A front surface-side wiring layer is formed within the substrate in the semiconductor device. The dummy pattern is formed around a dummy non-formation area passing through the semiconductor device from a rear surface opposite the front surface to the front surface-side wiring layer.

Description

Technical Field

[0001] This technology relates to semiconductor devices. More specifically, it relates to semiconductor devices provided with TSVs (Through Silicon Vias) and electrode pads.

Background Art

[0002] Conventionally, in semiconductor devices such as solid-state imaging devices, TSVs may be used for taking out terminals. For example, a semiconductor device has been proposed in which, with the light-receiving surface of a substrate as the front surface, rewiring is performed on the back surface side with respect to that surface using TSVs and solder balls are formed (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the above-mentioned conventional technology, by using TSVs for rewiring on the back surface side and forming solder balls, miniaturization is achieved compared to the case of using wire bonding. However, in the above-mentioned semiconductor device, when wafers are shared in a plurality of manufacturing processes, the parasitic capacitance between the back surface of the substrate and the wiring layer may increase. For example, when wafers are shared in each manufacturing process of a WLCSP (Wafer Level Chip Scale Package) or a ceramic package, the parasitic capacitance becomes larger than when not shared in the ceramic package. There is a problem that characteristics such as the operating speed and high-frequency characteristics deteriorate due to this increase in parasitic capacitance.

[0005] This technology was developed in light of these circumstances and aims to improve the characteristics of semiconductor devices manufactured from wafers shared across multiple manufacturing processes. [Means for solving the problem]

[0006] This technology was developed to solve the aforementioned problems, and its first aspect is a semiconductor device comprising a pad opening formed on the surface of a substrate and provided with a predetermined electrode pad, a wiring layer formed within the substrate, and a dummy pattern formed around a dummy non-formed region that penetrates from the back surface to the wiring layer relative to the surface. This reduces parasitic capacitance when wafers are shared in multiple manufacturing processes.

[0007] Furthermore, in this first aspect, the substrate is a substrate in which a pixel sensor substrate and a logic substrate are laminated, the pad openings are formed on the surface of the pixel sensor substrate, and the wiring layer and dummy pattern may be formed on the logic substrate. This results in a reduction of parasitic capacitance in the laminated substrate.

[0008] Furthermore, on this first side, the dummy non-formed region may be opened, and a TSV (Through Silicon Via) may be formed. This results in the terminals being accessible from the back side.

[0009] Furthermore, in this first aspect, the area of ​​the dummy-free region on the plane parallel to the substrate may be smaller the closer it is to the wiring layer. This results in a dummy occupancy rate that increases with the upper layers.

[0010] Furthermore, in this first aspect, the position of the pad opening on a plane parallel to the substrate and the position of the dummy non-formed area on the same plane may be different. This has the effect of suppressing cracks and the like.

[0011] Furthermore, in this first aspect, the shape of the boundary region between the wiring layer and the dummy non-formed region may be circular. This results in the upper end of the TSV being circular.

[0012] Furthermore, in this first aspect, the shape of the boundary region between the wiring layer and the dummy non-formed region may be ring-shaped. This results in the upper end of the TSV becoming ring-shaped.

[0013] Furthermore, in this first aspect, the dummy non-formed region may be in contact with the wiring layer at multiple boundary regions. This results in the TSV having multiple upper ends.

[0014] Furthermore, in this first aspect, a portion of the dummy pattern and the wiring layer may be short-circuited. This has the effect of reducing the contact resistance of the TSV.

[0015] Furthermore, in this first aspect, the density of the dummy pattern may be higher the closer it is to the wiring layer. This has the effect of relaxing the rules regarding the distance from the TSV to surrounding devices.

[0016] Furthermore, in this first aspect, the dummy pattern may include dummy wiring arranged in a mesh-like pattern. This results in a higher density of conductors compared to the island-like arrangement.

[0017] Furthermore, in this first aspect, the dummy wiring includes a first dummy wiring and a second dummy wiring routed between the first dummy wiring and the wiring layer, and the position of the second dummy wiring on a plane parallel to the substrate may differ from that of the first dummy wiring. This results in the dummy wiring being staggered between the upper and lower layers.

[0018] Also, in this first aspect, the dummy pattern may include a plurality of islands arranged in a two-dimensional lattice. This brings about the effect of reducing the parasitic capacitance.

[0019] Also, in this first aspect, the plurality of islands include a first island and a second island wired between the first island and the wiring layer, and the position of the second island on a plane parallel to the substrate may be different from that of the first island. This brings about the effect of reducing the density of the conductor compared to the mesh-like case.

[0020] Also, in this first aspect, the side surface of the dummy non-formation region may be formed in a tapered shape. This brings about the effect that the area of the upper end of the TSV becomes the smallest.

[0021] Also, in this first aspect, the side surface of the dummy non-formation region may be formed in a stepped shape. This brings about the effect that the area of the upper end of the TSV becomes the smallest.

Brief Description of the Drawings

[0022] [Figure 1] It is a cross-sectional view showing a configuration example of a stacked wafer used when manufacturing a WLCSP in an embodiment of the present technology. [Figure 2] It is a cross-sectional view showing a configuration example of a WLCSP in an embodiment of the present technology. [Figure 3] It is a block diagram showing a configuration example of a solid-state imaging device in an embodiment of the present technology. [Figure 4] It is a diagram showing an example of the stacked structure of a solid-state imaging device in an embodiment of the present technology. [Figure 5] It is a flowchart showing an example of the manufacturing process of a WLCSP in an embodiment of the present technology. <00​​​It is a cross-sectional view showing a configuration example of a ceramic package in an embodiment of the present technology. [Figure 8] It is a flowchart showing an example of a manufacturing process of a ceramic package in the first embodiment of the present technology. [Figure 9] It is a cross-sectional view showing a configuration example of a laminated wafer in the first comparative example. [Figure 10] It is a cross-sectional view showing a configuration example of a laminated wafer in the second comparative example. [Figure 11] It is a view showing an example of a cross-sectional view and a plan view of an opening for a TSV in an embodiment of the present technology. [Figure 12] It is a view showing another example of a cross-sectional view and a plan view of an opening for a TSV in an embodiment of the present technology. [Figure 13] It is a view showing an example of a cross-sectional view of a dummy pattern in an embodiment of the present technology. [Figure 14] It is a view showing an example of a plan view of a dummy pattern in an embodiment of the present technology. [Figure 15] It is a view showing an example of a cross-sectional view and a plan view of an opening for a TSV in the first modification of an embodiment of the present technology. [Figure 16] It is a view showing an example of a cross-sectional view of a dummy pattern in the second modification of an embodiment of the present technology. [Figure 17] It is a view showing an example of a cross-sectional view of a dummy pattern in the third modification of an embodiment of the present technology. <​​​​​​​​​​​​​​​​

[0023] The following describes the embodiments for implementing this technology. The description will proceed in the following order. 1. Embodiment (Example of forming a dummy pattern around a region where dummy patterns are not formed) 2. Examples of applications to mobile devices

[0024] <1. First Embodiment> [Example of a stacked wafer configuration] Figure 1 is a cross-sectional view showing an example of the configuration of a stacked wafer 200 used when manufacturing a WLCSP in an embodiment of this technology. This stacked wafer 200 is made up of two stacked wafers, one of which contains a predetermined number of pixel sensor substrates 210. The other wafer contains a predetermined number of logic substrates 220. Hereinafter, the axis parallel to the stacking direction of the wafers will be defined as the Z-axis. A predetermined axis perpendicular to the Z-axis will be defined as the X-axis, and the axis perpendicular to both the Z-axis and the X-axis will be defined as the Y-axis. The figure is a cross-sectional view taken from the Y-axis direction.

[0025] Multiple pixels (not shown) are provided on the light-receiving surface of the pixel sensor substrate 210. This light-receiving surface is considered the "front surface," and the "back surface" of the pixel sensor substrate 210 relative to this surface is connected to the logic board 220. On the logic board 220, the surface connected to the pixel sensor substrate 210 is considered the front surface. The direction toward the front surface is considered the "up" direction, and the direction toward the back surface is considered the "down" direction.

[0026] The pixel sensor substrate 210 also comprises a Si (semiconductor) substrate 211 on the front side and an interlayer film 212 on the back side. External connection wiring 214 and connection parts 215 are formed on this interlayer film 212. The external connection wiring 214 is for electrically connecting the pixel sensor substrate 210 to the outside (such as the logic board 220 or test equipment), and aluminum wiring or the like is used. The pixel sensor substrate 210 is electrically connected to the logic board 220 via the external connection wiring 214 and connection parts 215. As a method of connecting these substrates, for example, Cu-Cu connection is used.

[0027] Furthermore, a pad opening 213 is formed on the surface (i.e., the light-receiving surface) of the pixel sensor substrate 210, penetrating to the external connection wiring 214. Electrode pads, described later, are provided in this pad opening 213, and the pixel sensor substrate 210 is electrically connected to the outside via these electrode pads. In the WLCSP manufacturing process, the pixel sensor substrate 210 is connected to external test equipment and the like to evaluate its characteristics.

[0028] Circuits for processing pixel signals from pixels are formed on the logic board 220. This logic board 220 comprises an interlayer film 222 on the front side and a Si (semiconductor) substrate 221 on the back side. Dummy patterns 224, local wiring 225, global wiring 226, external connection wiring 227, connection parts 228 and local wiring 229 are formed on the interlayer film 222.

[0029] The external connection wiring 227 is for electrically connecting the logic board 220 and the pixel sensor board 210, and aluminum wiring or the like is used. The logic board 220 is electrically connected to the pixel sensor board 210 via the external connection wiring 227 and the connection part 228.

[0030] Global wiring 226 is wiring for connecting multiple circuit blocks. Local wiring 225 is wiring within those circuit blocks. Local wiring 225 is routed below global wiring 226. For example, local wiring 225 forms a surface wiring layer M5 and a surface wiring layer M4 below it. Although local wiring 225 is shown as having two layers, it is not limited to two layers as long as there is one or more layers.

[0031] The dummy pattern 224 is a conductive pattern that does not constitute a circuit. This dummy pattern 224 forms, for example, the back-side wiring layer M3 below the front-side wiring layer M4, the back-side wiring layer M2 below that, and the back-side wiring layer M1 below that. Although the dummy pattern 224 is shown as having three layers, it is not limited to three layers as long as there is one or more layers.

[0032] Furthermore, a TSV opening 223 is formed on the back surface of the logic board 220, penetrating to the surface wiring layer M5. The TSV opening 223 is provided for forming TSVs and rewiring, which will be described later.

[0033] The area of ​​the TSV opening 223 on the XY plane parallel to the logic board 220 is preferably smaller as it approaches the surface wiring layer M5. For example, the area of ​​the upper end of the TSV opening 223 is preferably 10 percent (%) or more of the area of ​​the lower end. In addition, the side surface of the TSV opening 223 is tapered.

[0034] Furthermore, it is preferable that the position of the pad opening 213 on the XY plane is different from the position of the TSV opening 223. For example, the coordinates of the center of the TSV opening 223 are X1, and the coordinates of the center of the pad opening 213 are X2.

[0035] Furthermore, the density of the dummy pattern 224 is higher the closer it is to the surface wiring layer M5 (in other words, the higher it is).

[0036] In the logic board 220 receiving the TSV, the local wiring layers (M4 and M5) should be formed on the upper side to reduce the capacitance increase when mounting the ceramic package, as described later. However, if dummy wiring cannot be laid out below the upper wiring layer, this may cause problems with smoothing during processing. Also, as the TSV becomes deeper, the stress around the TSV increases, and the KOZ (Keep Out Zone) rule becomes stricter. This KOZ rule requires that the distance from the TSV to surrounding devices be above a lower limit, and in the figure, the lower limit becomes smaller as you move upwards.

[0037] Therefore, as described above, the density of the dummy pattern 224 is increased towards the upper layers, and the sides of the TSV opening 223 are tapered to minimize the size of the bottom region of the TSV that is in contact with the local wiring 225.

[0038] Furthermore, in the wiring process of the lower wafer, the wiring density of the dummy pattern 224 must be above a certain level for smoothing purposes. As mentioned above, by making the area of ​​the upper end of the TSV opening 223 10 percent (%) or more of the lower end, a higher dummy occupancy rate can be secured, especially in the upper part where smoothing becomes more difficult. In addition, since the TSV diameter of the TSV receiving portion can be formed smaller, stress can be reduced, and the KOZ rule can be relaxed.

[0039] Furthermore, if the position of the pad opening 213 and the position of the TSV opening 223 overlap, the thickness of the interlayer films 212 and 222 from the lower end of the pad opening 213 to the upper end of the TSV opening 223 will be thinner than in other areas. This may result in insufficient mechanical strength. As illustrated in the figure, by offsetting the positions of the pad opening 213 and the TSV opening 223, it is possible to improve resistance to mechanical stress from the DAM material around the chip during WLCSP mounting. This makes it possible to suppress cracks and other damage caused by that stress.

[0040] Furthermore, the local wiring 229 is formed in locations other than the upper part of the TSV opening 223. Unlike the two layers of local wiring 225 above the TSV opening 223, this local wiring 229 forms five layers of wiring.

[0041] Although the dummy pattern 224 is not electrically necessary, its formation allows the wiring layers to be aligned to five layers above the TSV opening 223 and in other areas. This helps to suppress uneven abrasion when smoothing the back surface of the logic board 220.

[0042] In summary, a pad opening 213 is formed on the surface of the laminated wafer 200, and electrode pads for connecting to a test device are provided in this pad opening 213. In addition, a surface-side wiring layer M5 is formed inside the laminated wafer 200, and a TSV opening 223 is formed that penetrates from the back surface to the surface-side wiring layer M5. A dummy pattern 224 is formed around this TSV opening 223.

[0043] [WLCSP Configuration Example] Figure 2 is a cross-sectional view showing an example configuration of WLCSP310 in an embodiment of this technology. This WLCSP310 is manufactured by forming TSVs and redistributions on the aforementioned stacked wafer 200 and then dicing it.

[0044] Multiple pixels, such as pixels 216, are formed on the pixel sensor substrate 210. On the back surface of the logic substrate 220, a TSV 311 and rewiring 312 are formed in the TSV opening 223. External terminals 313, such as solder balls, are also provided on the back surface, and these external terminals 313 are connected to the circuit inside the logic substrate 220 via the rewiring 312.

[0045] [Example of a solid-state imaging device configuration] Figure 3 is a block diagram showing an example configuration of the solid-state imaging device 100 in an embodiment of this technology. The aforementioned WLCSP310 functions as the solid-state imaging device 100 in the figure. The solid-state imaging device 100 is an example of a semiconductor device described in the claims.

[0046] The solid-state imaging device 100 is a device for capturing image data and includes a vertical drive circuit 110, a control circuit 120, a pixel area 130, a column signal processing circuit 140, a horizontal drive circuit 150, and an output circuit 160. Multiple pixels are arranged in a two-dimensional grid within the pixel area 130.

[0047] The vertical drive circuit 110 is configured, for example, by a shift register, and drives pixels row by row, outputting pixel signals. The control circuit 120 controls the operating timing of the vertical drive circuit 110, the column signal processing circuit 140, and the horizontal drive circuit 150 in synchronization with an external vertical synchronization signal or the like.

[0048] The column signal processing circuit 140 performs signal processing, such as A / D (Analog to Digital) conversion, on the pixel signals from each column of the pixel region 130. For example, the column signal processing circuit 140 is equipped with an ADC (Analog to Digital Converter) for each column, and performs A / D conversion using a column ADC method. Furthermore, the column signal processing circuit 140 performs CDS (Correlated Double Sampling) processing to remove fixed pattern noise. The column signal processing circuit 140 supplies the processed pixel signals to the output circuit 160 according to the control of the horizontal drive circuit 150.

[0049] The horizontal drive circuit 150 supplies horizontal scanning pulse signals to the column signal processing circuit 140 in accordance with the control of the control circuit 120, causing the processed pixel signals to be output sequentially.

[0050] The output circuit 160 outputs image data, which is an array of pixel signals from the column signal processing circuit 140, to the outside.

[0051] Figure 4 shows an example of a stacked structure of a solid-state imaging device in an embodiment of the present technology. For example, as illustrated in figure a, the pixel area 130 and the control circuit 120 are arranged on the pixel sensor substrate 210, and the remaining circuits (such as the column signal processing circuit 140) are arranged on the logic substrate 220 as a logic circuit 170.

[0052] Alternatively, as illustrated in figure b, the pixel region 130 is arranged on the pixel sensor substrate 210, and the remaining control circuit 120 and logic circuit 170 are arranged on the logic substrate 220.

[0053] [WLCSP manufacturing method] Figure 5 is a flowchart showing an example of the manufacturing process for WLCSP310 in an embodiment of this technology. The semiconductor package manufacturing system first forms pixels and the like on the upper wafer (step S901), forms logic circuits 170 and the like on the lower wafer (step S902), and then bonds the upper and lower wafers together (step S903). The manufacturing system then forms the pad openings 213 (step S904). Steps S901 and S902 can also be performed in parallel.

[0054] Next, the manufacturing system places electrode pads in the pad openings 213 and performs characteristic evaluation (step S905). Subsequently, the manufacturing system bonds the glass substrate to the surface of the laminated substrate via DAM material (step S906) to form the TSV openings 223 (step S907). The cross-sectional view of the laminated wafer 200 mentioned above shows the cross-sectional view at step S907. The manufacturing system also forms TSVs and rewiring in the TSV openings 223 (step S908). Next, the manufacturing system dices the laminated wafer 200 to produce a predetermined number of WLCSP310 (step S909). After step S909, the manufacturing system completes the WLCSP310 manufacturing process.

[0055] In the manufacturing process shown in the figure, a stacked wafer 200 with the structure illustrated in Figure 1 is used. However, a ceramic package can be manufactured using a stacked wafer with the same structure, except that the TSV opening 223 is not opened.

[0056] Figure 6 is a cross-sectional view showing an example configuration of a laminated wafer 201 used in manufacturing a ceramic package in an embodiment of this technology. This laminated wafer 201 has the same structure as the laminated wafer 200, except that a dummy non-formed region 230 is placed in place of the TSV opening 223. In other words, the laminated wafer 201 has the same structure as the laminated wafer 200 before the TSV opening 223 is formed. The area enclosed by the dotted line in the figure indicates the dummy non-formed region 230.

[0057] The dummy non-formation region 230 is the area of ​​the Si substrate 221 and interlayer film 222 where the dummy pattern 224 is not formed. The dummy pattern 224 is formed around this dummy non-formation region 230, avoiding it.

[0058] [Example of ceramic package configuration] Figure 7 is a cross-sectional view showing one example configuration of a ceramic package 320 in an embodiment of this technology. This ceramic package 320 is manufactured by dicing the aforementioned stacked wafer 201 and mounting it on a ceramic substrate.

[0059] The ceramic package 320 comprises a glass 321, a ceramic substrate 322, and a stacked pixel sensor substrate 210 and logic substrate 220. The glass 321 is placed on top of the pixel sensor substrate 210.

[0060] External connection terminals 325, such as solder balls, are provided on the underside of the ceramic substrate 322. The external connection terminals 325 are connected to one end of a rewiring 324 that is routed within the ceramic substrate 322. The other end of the rewiring 324 is connected to a wire 323. In addition, electrode pads 217 are provided in the pad openings 213 of the pixel sensor substrate 210. These electrode pads 217 are connected to the rewiring 324 via the wire 323.

[0061] As illustrated in the figure, the ceramic package 320 is mounted by wire bonding to the electrode pads on the pixel sensor substrate 210 side, so there is no need to form a TSV on the back surface of the logic substrate 220. For this reason, as mentioned above, the back surface of the stacked wafer 201 is not opened.

[0062] [Method for manufacturing ceramic packages] Figure 8 is a flowchart showing an example of the manufacturing process for a ceramic package 320 in the first embodiment of this technology. The manufacturing system forms pixels and the like on the upper wafer (step S901), forms logic circuits 170 and the like on the lower wafer (step S902), and then bonds the upper and lower wafers together (step S903). The manufacturing system then forms the pad openings 213 (step S904). The cross-sectional view of the stacked wafer 201 mentioned above shows the cross-sectional view at step S904.

[0063] Next, the manufacturing system places electrode pads in the pad openings 213 and performs characteristic evaluation (step S905). Then, the manufacturing system dices the stacked wafer 200 (step S909), mounts it onto the ceramic substrate 322, and manufactures a predetermined number of ceramic packages 320 (step S910). After step S910, the manufacturing system completes the manufacturing process for the ceramic packages 320.

[0064] Furthermore, in the manufacturing process of the WLCSP310 described above, the structure of the stacked wafer 200 in step S904 before the formation of the TSV opening 223 is the same as the structure of the stacked wafer 201 in step S904 in the manufacturing process of the ceramic package 320. By forming the dummy pattern 224 while avoiding the dummy non-formation region 230, it becomes unnecessary to penetrate the layer of the dummy pattern 224 when forming the TSV in the manufacturing process of the WLCSP310, making TSV formation easier.

[0065] As illustrated in Figures 5 and 8, the manufacturing process for WLCSP310 and the manufacturing process for ceramic package 320 share the same steps up to step S904. Therefore, the stacked wafer can be shared between these manufacturing processes.

[0066] For example, steps S901 to S904 produce two sets of stacked wafers with the same structure. Steps S905 onwards in Figure 5 are performed on one of these sets to produce a WLCSP310. Meanwhile, steps S907 onwards in Figure 8 are performed on the remaining set to produce a ceramic package 320. This standardization of stacked wafers can reduce costs and improve production fluidity.

[0067] Here, we consider a stacked wafer in which a dummy pattern 224 is not provided below the local wiring 225 as the first comparative example.

[0068] Figure 9 is a cross-sectional view showing an example configuration of a laminated wafer in the first comparative example. In this first comparative example, no dummy pattern 224 is provided below the local wiring 225, and five layers are formed by the local wiring 225. Also, the pad opening 213 penetrates to the external connection wiring 227 of the logic board 220.

[0069] When the same stacked wafer is used for both the WLCSP310 manufacturing process and the ceramic package 320 manufacturing process, the number of wiring layers short-circuited to the external connection wiring 227 increases compared to the first embodiment in which the dummy pattern 224 is provided. As a result, the parasitic capacitance between the wiring layer and the back surface of the Si substrate 221 in the ceramic package 320 increases. This increase in parasitic capacitance may degrade characteristics such as operating speed and high-frequency performance.

[0070] Furthermore, we consider a stacked wafer with a configuration in which only a dummy pattern 224 is formed on the underside of the global wiring 226 as a second comparative example.

[0071] Figure 10 is a cross-sectional view showing an example configuration of a stacked wafer in the second comparative example. In this second comparative example, local wiring 225 is not provided below the global wiring 226, and five layers are formed by dummy patterns 224. Also, the pad openings 213 penetrate to the external connection wiring 227 of the logic board 220.

[0072] In the stacked wafer shown in the figure, local wiring 225 is not provided below the global wiring 226, thus reducing parasitic capacitance between the back surface and the main surface. However, because TSV cannot be formed on the back surface, it can only be used for the ceramic package 320, and the stacked wafer cannot be shared with the manufacturing process of the WLCSP310.

[0073] In contrast, in the stacked wafers 200 and 201 illustrated in Figures 1 and 6, a dummy pattern 224 is provided below the local wiring 225, thereby reducing parasitic capacitance compared to the first comparative example. This improves characteristics such as operating speed.

[0074] Furthermore, since the WLCSP310 manufacturing process and the ceramic package 320 manufacturing process can share the same stacked wafer, costs can be reduced and production flow can be improved compared to the second comparative example.

[0075] [Example of configuration for TSV opening] Figure 11 shows examples of a cross-sectional view and a plan view of the TSV opening 223 in an embodiment of the present technology. Figure a is an example of a cross-sectional view of the TSV opening 223, and figure b is an example of a plan view of the TSV opening 223 as seen from below the logic board 220.

[0076] The area enclosed by the thick line labeled b in the figure represents the boundary region between the TSV opening 223 and the local wiring 225. The shape of this boundary region is, for example, ring-shaped. The height of the center of the ring from the local wiring 225 is less than the boundary between the Si substrate 221 and the interlayer film 222, but the center of the ring may reach that boundary.

[0077] Furthermore, as illustrated in Figure 12b, the TSV opening 223 may be in contact with the local wiring 225 in multiple boundary regions. The shape of each boundary region may be, for example, circular.

[0078] [Example of a dummy pattern configuration] Figure 13 shows an example of a cross-sectional view of a dummy pattern 224 in an embodiment of the present technology. The dummy pattern 224 includes dummy wirings 224-3 and 224-2. Dummy wiring 224-3 is wired in the back wiring layer M3. Dummy wiring 224-2 is wired in the back wiring layer M2, which is below the back wiring layer M3. As illustrated in the figure, these dummy wirings 224-2 and 224-3 are insulated from the local wiring 225 and are electrically floating.

[0079] Dummy wiring 224-3 and 224-2 are examples of the first and second dummy wiring described in the claims.

[0080] Figure 14 shows an example of a plan view of the dummy pattern 224 in an embodiment of the present technology. Figure a is an example of a plan view of the back side wiring layer M3 on which dummy wiring 224-3 is wired, and figure b is an example of a plan view of the back side wiring layer M2 on which dummy wiring 224-2 is wired. For convenience of description, the patterns of dummy wiring 224-3 and dummy wiring 224-2 are shown to be different in the figure, but the material of these wires is the same.

[0081] As illustrated in Figure a, the dummy wiring 224-3 is routed in a mesh pattern in the XY plane. Similarly, as illustrated in Figure b, the dummy wiring 224-2 is also routed in a mesh pattern in the XY plane. However, the positions of the upper dummy wiring 224-3 and the lower dummy wiring 224-2 in the XY plane are different.

[0082] For example, at position X3, dummy wiring 224-3 is not routed, but dummy wiring 224-2 is routed along the Y-axis. Also, at position X4, dummy wiring 224-3 is routed along the Y-axis, but dummy wiring 224-2 is not routed.

[0083] Furthermore, dummy wiring 224-3 is not routed at position Y1, but dummy wiring 224-2 is routed along the X-axis. Also, dummy wiring 224-3 is routed along the X-axis at position Y2, but dummy wiring 224-2 is not routed.

[0084] Although the structure in Figure 1 is applied to the solid-state imaging device 100, it can also be applied to semiconductor devices other than the solid-state imaging device 100, as long as the rewiring is taken out from the back surface. One advantage of a configuration that takes out the rewiring from the back surface is that, for example, the silicon of the chip can be brought into contact with the mounting substrate equipped with a heat sink to improve heat dissipation efficiency.

[0085] This section explains how to improve heat dissipation efficiency. Typically, for both ceramic packages and WLCSPs, terminals are routed from the top side where the wiring layer is located. However, when mounting a WLCSP, if the side containing the heat-generating device is facing upwards, heat dissipation becomes difficult. This is because the heat dissipation mechanism relies solely on thermal radiation and convection. To address this, one possible method is to directly attach a heat sink to the mounting board and dissipate heat through conduction. Details of this method can be found, for example, at https: / / www.renesas.com / jp / ja / support / technical-resources / packaging / This is described in "characteristic / heat-dissipation".

[0086] If terminals are placed on the wiring layer side of the wiring layer and the insulating layer, the heat dissipation efficiency will be insufficient because the silicon substrate, which is the main source of heat generation, will be in contact with the mounting board via the insulating layer. This is because the thermal conductivity of the insulating layer is generally lower than that of silicon. For example, the thermal conductivity of silicon is 160 watts per meter per Kelvin (W / m·K), while the thermal conductivity of the silicon dioxide insulating layer is 1.3 watts per meter per Kelvin (W / m·K).

[0087] Therefore, if you want to improve heat dissipation efficiency, it is preferable to have a structure in which the terminals are taken out from the back of the silicon substrate, as shown in Figure 1, so that the silicon substrate can be directly attached to the mounting substrate. Furthermore, in semiconductor devices other than the solid-state imaging device 100, the structure in Figure 1 similarly provides the effect of complying with the KOZ rule and the effect of suppressing the increase in capacitance when wafers are used in the manufacturing process of ceramic packages.

[0088] Thus, according to this embodiment of the technology, a dummy pattern 224 is formed around the dummy non-formed region 230 that penetrates from the back surface of the stacked wafer 201 to the front-side wiring layer M5. This reduces parasitic capacitance between the back surface and the front-side wiring layers M4 and M5. As a result, characteristics such as operating speed can be improved.

[0089] [First variation] In the above-described embodiment, the shape of the boundary region between the TSV opening 223 and the local wiring 225 was ring-shaped, but it is not limited to this shape. The first modified stacked wafer 200 of this embodiment differs from the embodiment in that the shape of the boundary region is circular.

[0090] Figure 15 shows an example of a cross-sectional view and a plan view of a TSV opening in a first modified embodiment of the present technology. Figure a is an example of a cross-sectional view of the TSV opening 223, and figure b is an example of a plan view of the TSV opening 223 as seen from below the logic board 220.

[0091] As illustrated in Figure b, in the first modified embodiment, the shape of the boundary region between the TSV opening 223 and the local wiring 225 is circular. By making the boundary region a simpler circle than a ring, the formation of the TSV and rewiring becomes easier than in the case of a ring. Note that the shape of the boundary region is not limited to a circle or a ring, but may also be a polygon or the like.

[0092] As described above, according to the first modification of the embodiment, the shape of the boundary region is made circular, which facilitates the formation of TSVs and rewiring.

[0093] [Second variation] In the above-described embodiment, the dummy pattern 224 was in an electrically floating state, but the configuration is not limited to this. The stacked wafer 200 of the second modified example in the embodiment differs from the embodiment in that a part of the dummy pattern 224 and the wiring layer of the local wiring 225 are short-circuited.

[0094] Figure 16 shows an example of a cross-sectional view of a dummy pattern in a second modified embodiment of the present technology. As illustrated in the figure, a portion of the dummy pattern 224 and the surface wiring layer M4 of the local wiring 225 are short-circuited. In addition, the side surface of the TSV opening 223 is stepped. With the configuration shown in the figure, the metal forming the TSV and the metal of the local wiring 225 come into contact on the side surface of the TSV opening 223, thereby reducing the contact resistance of the TSV. As a result, the diameter of the TSV can be made smaller.

[0095] Thus, according to the second modification of the embodiment of this technology, since a part of the dummy pattern 224 and the surface wiring layer M4 are short-circuited, the contact resistance of the TSV can be reduced.

[0096] [Third variation] In the above-described embodiment, the dummy wirings 224-3 and 224-2 were wired in a mesh pattern, but the dummy pattern 224 is not limited to a mesh pattern. The stacked wafer 200 of the third modified example in this embodiment differs from the embodiment in that the dummy pattern 224 includes multiple islands.

[0097] Figure 17 shows an example of a cross-sectional view of a dummy pattern 224 in a third modified example of an embodiment of the present technology. The dummy pattern 224 comprises islands 224-6, 224-5, and 224-4. Islands 224-6, 224-5, and 224-4 are island-shaped conductors. Island 224-6 is arranged on the back side wiring layer M3. Island 224-5 is arranged on the back side wiring layer M2, which is below the back side wiring layer M3. Island 224-4 is arranged on the back side wiring layer M1, which is below the back side wiring layer M2.

[0098] Figure 18 shows an example of a plan view of a dummy pattern 224 in an embodiment of the present technology. Figure a is an example of a plan view of the back side wiring layer M3 with islands 224-6 arranged, and figure b is an example of a plan view of the back side wiring layer M2 with islands 224-5 arranged. Figure c is an example of a plan view of the back side wiring layer M1 with islands 224-4 arranged. For convenience of description, the patterns of islands 224-6 to 224-4 are shown to be different in the figure, but their material is the same.

[0099] As illustrated in Figure a, multiple islands 224-6 are arranged in a two-dimensional grid in the back-side wiring layer M3. As illustrated in Figure b, multiple islands 224-5 are also arranged in a two-dimensional grid in the back-side wiring layer M2. As illustrated in Figure c, multiple islands 224-4 are also arranged in a two-dimensional grid in the back-side wiring layer M1. The shape of each island is, for example, rectangular.

[0100] Furthermore, the position of island 224-6 on the XY plane is different from the position of island 224-5 on its lower layer. Also, the position of island 224-5 on the XY plane is different from the position of island 224-4 on its lower layer.

[0101] For example, at position X3, islands 224-6 and 224-4 are not arranged, but island 224-5 is arranged along the Y-axis. At position X4, islands 224-6 and 224-4 are arranged along the Y-axis, but island 224-5 is not arranged.

[0102] Furthermore, at position Y1, island 224-6 is not arranged, but islands 224-5 and 224-4 are arranged along the X-axis. Also, at position Y2, island 224-6 is arranged along the X-axis, but islands 224-5 and 224-4 are not arranged.

[0103] As illustrated in the figure, by making the dummy pattern 224 a pattern containing multiple islands, the parasitic capacity can be reduced compared to the case of a mesh-like structure.

[0104] Furthermore, as illustrated in Figure 19, the side surface of the TSV opening 223 can be stepped instead of tapered.

[0105] Alternatively, a portion of the dummy pattern 224 and the local wiring 225 may be short-circuited via a contact. In this case, only the inner region of the dummy pattern 224 within a certain distance from the outer circumference of the TSV opening 223 may be short-circuited. By short-circuiting only the inner region, the effect of parasitic capacitance can be reduced.

[0106] As described above, according to the third modification of the embodiment of this technology, the parasitic capacity can be further reduced because the dummy pattern 224 includes multiple islands.

[0107] <2. Examples of applications to mobile devices> The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein may be implemented as a device mounted on any type of mobile vehicle, such as an automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility device, airplane, drone, ship, or robot.

[0108] Figure 20 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0109] The vehicle control system 12000 comprises multiple electronic control units connected via a communication network 12001. In the example shown in Figure 20, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is also shown, consisting of a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0110] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0111] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0112] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0113] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0114] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0115] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking system based on information from inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0116] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0117] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0118] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 20, the output devices are exemplified as an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0119] Figure 21 shows an example of the installation position of the imaging unit 12031.

[0120] In Figure 21, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0121] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0122] Figure 21 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0123] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0124] For example, the microcomputer 12051, based on distance information obtained from imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to vehicle 12100). In particular, it can extract the nearest object on the vehicle 12100's path that is traveling in approximately the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0125] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, heavy vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0126] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0127] The above describes an example of a vehicle control system to which the technology described herein can be applied. The technology described herein can be applied to, for example, the imaging unit 12031 of the configuration described above. Specifically, for example, the solid-state imaging device 100 in Figure 3 can be applied to the imaging unit 12031. By applying the technology described herein to the imaging unit 12031, it becomes possible to reduce parasitic capacitance and improve characteristics such as operating speed. In addition to the above-mentioned in-vehicle applications, the technology described herein can also be applied to general-purpose cameras other than in-vehicle (surveillance, medical, industrial machinery, digital cameras, mobile devices, etc.), analog front-ends, RF (Radio Frequency), power management, etc.

[0128] The embodiments described above are merely examples of how to realize this technology, and there is a corresponding relationship between the matters in the embodiments and the inventive features in the claims. Similarly, there is a corresponding relationship between the inventive features in the claims and the matters in the embodiments of this technology that bear the same name. However, this technology is not limited to the embodiments and can be realized by making various modifications to the embodiments without departing from the gist of the technology.

[0129] The effects described herein are merely illustrative and not limited to those described herein, and other effects may also occur.

[0130] Furthermore, this technology can also be configured as follows. (1) A pad opening formed on the surface of the substrate, on which a predetermined electrode pad is provided, A wiring layer formed within the aforementioned substrate, A dummy pattern is formed around the dummy non-formed region that penetrates from the back surface to the wiring layer relative to the surface. A semiconductor device equipped with the following. (2) The substrate is a substrate in which a pixel sensor substrate and a logic substrate are stacked, The pad opening is formed on the surface of the pixel sensor substrate, The wiring layer and the dummy pattern are formed on the logic board. The semiconductor device described in (1) above. (3) The dummy non-formed region is opened up and a TSV (Through Silicon Via) is formed. The semiconductor device described in (1) or (2) above. (4) The semiconductor device according to any one of (1) to (3) above, wherein the area of ​​the dummy non-formed region on a plane parallel to the substrate is smaller the closer it is to the wiring layer. (5) The position of the pad opening on a plane parallel to the substrate and the position of the dummy non-formed area on the plane are different. A semiconductor device as described in any of (1) to (4) above. (6) The shape of the boundary region between the wiring layer and the dummy non-formed region is circular. A semiconductor device as described in any of (1) to (5) above. (7) The shape of the boundary region between the wiring layer and the dummy non-formed region is ring-shaped. A semiconductor device as described in any of (1) to (5) above. (8) The dummy non-formed region is in contact with the wiring layer at multiple boundary regions. A semiconductor device as described in any of (1) to (5) above. (9) A portion of the dummy pattern and the wiring layer are short-circuited. A semiconductor device as described in any of (1) to (8) above. (10) The density of the dummy pattern is higher the closer it is to the wiring layer. A semiconductor device according to any of (1) to (9) above. (11) The dummy pattern includes dummy wiring arranged in a mesh pattern. A semiconductor device as described in any of (1) to (10) above. (12) The dummy wiring includes a first dummy wiring and a second dummy wiring routed between the first dummy wiring and the wiring layer, The position of the second dummy wiring on a plane parallel to the substrate is different from that of the first dummy wiring. The semiconductor device described in (11) above. (13) The dummy pattern includes a plurality of islands arranged in a two-dimensional grid. A semiconductor device as described in any of (1) to (10) above. (14) The plurality of islands include a first island and a second island wired between the first island and the wiring layer, The position of the second island on a plane parallel to the substrate is different from that of the first island. The semiconductor device described in (13) above. (15) The semiconductor device according to any one of (1) to (14), wherein the side surface of the dummy non-formed region is formed in a tapered shape. (16) The semiconductor device according to any one of (1) to (14) wherein the side surface of the dummy non-formed region is formed in a stepped manner. [Explanation of symbols]

[0131] 100 Solid-state imaging device 110 Vertical drive circuit 120 Control circuits 130 pixel area 140-column signal processing circuit 150 Horizontal drive circuit 160 Output Circuit 170 Logic Circuits 200, 201 stacked wafers 210-pixel sensor board 211, 221 Si (semiconductor) substrate 212, 222 Interlaminar 213 Pad opening 214, 227 External connection wiring 215, 228 Connection part 216 pixels 217 Electrode Pads 220 Logic Board 223 Opening for TSV 224 Dummy Patterns 224-1~224-3 Dummy Wiring 224-4~224-6 Island 225, 229 Local wiring 226 Global Wiring 230 Dummy non-formation region 310 WLCSP 311 TSV 312, 324 rewiring 313, 325 External terminals 320 Ceramic Package 321 Glass 322 Ceramic substrate 323 Wire 12031 Imaging Unit

Claims

1. A pad opening formed on the surface of the substrate, in which a predetermined electrode pad is provided, A surface wiring layer formed within the substrate, A dummy pattern is formed around a dummy non-formed region that penetrates from the back surface to the surface-side wiring layer relative to the aforementioned surface. It is equipped with, The position of the pad opening on the plane parallel to the substrate and the position of the dummy non-formed region on the plane are different. Semiconductor equipment.

2. The aforementioned substrate is a substrate in which a pixel sensor substrate and a logic substrate are laminated, The pad opening is formed on the surface of the pixel sensor substrate, The surface wiring layer and the dummy pattern are formed on the logic board. The semiconductor device according to claim 1.

3. The aforementioned dummy non-formed region is opened, and a TSV (Through Silicon Via) is formed. The semiconductor device according to claim 1.

4. The semiconductor device according to claim 1, wherein the area of ​​the dummy non-formed region on a plane parallel to the substrate is smaller the closer it is to the surface wiring layer.

5. The shape of the boundary region between the surface wiring layer and the dummy non-formed region is circular. The semiconductor device according to claim 1.

6. The shape of the boundary region between the surface wiring layer and the dummy non-formed region is ring-shaped. The semiconductor device according to claim 1.

7. The aforementioned dummy non-formed region is in contact with the surface-side wiring layer at multiple boundary regions. The semiconductor device according to claim 1.

8. A portion of the dummy pattern and the surface wiring layer are short-circuited. The semiconductor device according to claim 1.

9. The density of the dummy pattern is higher the closer it is to the surface wiring layer. The semiconductor device according to claim 1.

10. The dummy pattern includes dummy wiring arranged in a mesh pattern. The semiconductor device according to claim 1.

11. The dummy wiring includes a first dummy wiring and a second dummy wiring routed between the first dummy wiring and the surface wiring layer. The position of the second dummy wiring on a plane parallel to the substrate is different from that of the first dummy wiring. The semiconductor device according to claim 10.

12. The dummy pattern includes a plurality of islands arranged in a two-dimensional grid. The semiconductor device according to claim 1.

13. The plurality of islands include a first island and a second island wired between the first island and the surface wiring layer, The position of the second island on a plane parallel to the substrate is different from that of the first island. The semiconductor device according to claim 12.

14. The semiconductor device according to claim 1, wherein the side surface of the dummy non-formed region is tapered.

15. The semiconductor device according to claim 1, wherein the side surface of the dummy non-formed region is formed in a stepped shape.

Images