Highly Selective Silicon Etching

Abstract

An exemplary semiconductor processing method may include providing a fluorine-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed in the processing region of the semiconductor processing chamber. The substrate may include at least one layer of a silicon-containing material and at least one layer of a silicon- and germanium-containing material along with the substrate. The method may include forming a plasma of the fluorine-containing precursor and the hydrogen-containing precursor in the processing region. The method may include contacting the at least one layer of the silicon-containing material and the at least one layer of the silicon- and germanium-containing material with plasma effluents of the fluorine-containing precursor and the hydrogen-containing precursor. The substrate may include removing the at least one layer of the silicon-containing material at a rate greater than the at least one layer of the silicon- and germanium-containing material.

Description

Technical Field

[0001] Cross - reference to related applications

[0001] This application claims the priority of U.S. Patent Application No. 17 / 674,127, filed on February 17, 2022, the entire disclosure of which is incorporated herein by reference for all purposes.

[0002] Technical Field

[0002] This technology relates to semiconductor systems, processes, and devices. More specifically, this technology relates to processes and systems for selectively etching silicon material with respect to silicon and germanium materials.

Background Art

[0003]

[0003] Integrated circuits are realized by a process of creating a complexly patterned material layer on a substrate surface. Manufacturing the patterned material on the substrate requires a controlled method for forming and removing the material. Memories including stacked memories such as vertical NAND or 3D NAND, and transistor structures including finFETs and gate - all - arounds may contain many layers and materials, and may be subjected to processes that selectively remove some materials while maintaining others. The material properties of the material layers, the process conditions and materials for etching, may affect the uniformity of the formed structures. Material defects may lead to inconsistent patterning and may further affect the uniformity of the formed structures.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used to create high - quality devices and structures. The above - mentioned need and other needs are addressed by this technology.

Summary of the Invention

[0005]

[0005] An exemplary semiconductor processing method may include providing a fluorine-containing precursor and a hydrogen-containing precursor to a processing area of ​​a semiconductor processing chamber. A substrate may be placed in the processing area of ​​the semiconductor processing chamber. The substrate may include at least one layer of silicon-containing material and at least one layer of silicon and germanium-containing material along the substrate. The method may include forming a plasma of the fluorine-containing precursor and the hydrogen-containing precursor in the processing area. The method may include bringing at least one layer of silicon-containing material and at least one layer of silicon and germanium-containing material into contact with plasma emissions of the fluorine-containing precursor and the hydrogen-containing precursor. The method may include removing at least one layer of silicon-containing material at a higher rate than at least one layer of silicon and germanium-containing material.

[0006]

[0006] In some embodiments, the fluorine-containing precursor may be one or both of nitrogen trifluoride and carbon tetrafluoride, or may include both. At least one layer of silicon-containing material may be selectively removed from at least one layer of silicon and germanium-containing material at a rate greater than 2:1 or about 2:1. The plasma of the fluorine-containing precursor and hydrogen-containing precursor may be generated with a source plasma power of less than 1,000 W or about 1,000 W. The bias applied to the plasma of the fluorine-containing precursor and hydrogen-containing precursor may be generated with a bias power of less than 100 W or about 100 W. The plasma of the fluorine-containing precursor and hydrogen-containing precursor may be generated with a duty cycle of less than 50% or about 50%. The method may include pulsed supply of source plasma power while forming plasma ejecta of the fluorine-containing precursor and hydrogen-containing precursor. The source plasma power may be pulsed at a frequency of less than 1,000 Hz or about 1,000 Hz. The temperature inside the semiconductor processing chamber may be maintained at less than 125°C or about 125°C. The pressure inside the semiconductor processing chamber may be maintained at less than 200 mTorr or about 200 mTorr. The method may include providing an inert precursor together with a fluorine-containing precursor and a hydrogen-containing precursor to the processing area of ​​the semiconductor processing chamber. The inert precursor may be a nitrogen-containing inert precursor, an argon-containing inert precursor, a helium-containing inert precursor, or a combination thereof, or may include them. The flow rate ratio of the hydrogen-containing precursor to the fluorine-containing precursor may be greater than 2:1 or about 2:1. The plasma may not contain oxygen.

[0007]

[0007] Some embodiments of the present technology may encompass semiconductor processing methods. The method may include providing a fluorine-containing precursor, a hydrogen-containing precursor, and a nitrogen-containing precursor. The method may include forming a plasma of the fluorine-containing precursor, the hydrogen-containing precursor, and the nitrogen-containing precursor. The method may include bringing at least one layer of silicon-containing material and at least one layer of silicon and germanium-containing material along a substrate into contact with plasma emissions of the fluorine-containing precursor, the hydrogen-containing precursor, and the nitrogen-containing precursor. The contact may selectively remove at least one layer of silicon-containing material.

[0008]

[0008] In some embodiments, the fluorine-containing precursor may be or contain carbon tetrafluoride. The nitrogen-containing precursor may be or contain nitrogen trifluoride. The fluorine-containing precursor and the nitrogen-containing precursor may form passivation compounds and etching compounds when in contact with at least one layer of silicon-containing material and at least one layer of silicon and germanium-containing material. The passivation compounds may include carbon materials, hydrogen materials, and fluorine materials. The etching compounds may include nitrogen materials, hydrogen materials, and fluorine materials. During the semiconductor processing method, the pressure may be maintained at less than 70 mTorr or about 70 mTorr. At least one layer of silicon and germanium-containing material may be characterized by a germanium concentration of less than 50 at.% or about 50 at.%. The etching compounds may remove at least one layer of silicon-containing material with a selectivity of greater than 3:2 or about 3:2 relative to at least one layer of silicon and germanium-containing material. This method may include providing a hydrogen-containing precursor and an inert precursor together with a fluorine-containing precursor and a nitrogen-containing precursor. The fluorine-containing precursor, nitrogen-containing precursor, hydrogen-containing precursor, and inert precursor can form a passivation compound and an etching compound. The passivation compound can passivate at least one layer of a silicon and germanium-containing material. The etching compound can remove at least one layer of a silicon-containing material.

[0009]

[0009] Some embodiments of the present technology may encompass semiconductor processing methods. The method may include providing a fluorine-containing precursor and a nitrogen-containing precursor to a processing area of ​​a semiconductor processing chamber. A substrate may be placed within the processing area of ​​the semiconductor processing chamber. The substrate may include at least one layer of silicon-containing material and at least one layer of silicon and germanium-containing material along the substrate. The method may include forming a plasma of the fluorine-containing precursor and the nitrogen-containing precursor within the processing area. The plasma may be generated with a discontinuous plasma power of less than 1,000 W or about 1,000 W. The method may include bringing at least one layer of silicon-containing material and at least one layer of silicon and germanium-containing material into contact with plasma emissions of the fluorine-containing precursor and the nitrogen-containing precursor. The contact may passivate at least one layer of silicon and germanium-containing material. The substrate may include removing at least one layer of silicon-containing material at a higher rate than at least one layer of silicon and germanium-containing material. At least one layer of silicon-containing material can be selectively removed from at least one layer of silicon and germanium-containing material at a rate greater than 3:2 or about 3:2.

[0010]

[0010] Such techniques may offer numerous advantages over conventional methods and techniques. For example, the process may further restrict etching by passivating materials such as silicon and germanium, thereby selectively etching a second material such as silicon. Furthermore, by passivating one material, the process may bring the stoichiometric ratio of the two different materials closer, thereby reducing the strain between the two materials. In addition, the process may not utilize oxygen, which can oxidize one or more layers of the material. These numerous advantages and features, along with other embodiments, will be described in more detail below in conjunction with the accompanying drawings.

[0011]

[0011] Further understanding of the nature and advantages of the disclosed technology can be obtained by referring to the following parts of this specification and the drawings. [Brief explanation of the drawing]

[0012] [Figure 1]

[0012] A schematic top view of an exemplary processing system according to several embodiments of the technology of the present invention is shown. [Figure 2]

[0013] A schematic cross-sectional view of an exemplary processing system according to several embodiments of the technology of the present invention is shown. [Figure 3]

[0014] Selected steps of a semiconductor processing method according to several embodiments of the technology of the present invention are shown. [Figure 4A-4B]

[0015] An exemplary schematic cross-sectional structure, comprising and generated by several embodiments of the technology of the present invention, is shown. [Figure 5A-5B]

[0016] The graph shows the selected operating characteristics for etching selectivity according to several embodiments of the technology of the present invention. [Modes for carrying out the invention]

[0013]

[0017] Some diagrams are included as schematics. It should be understood that diagrams are for illustrative purposes only and should not be considered to scale unless explicitly stated otherwise. Furthermore, as schematics, diagrams are provided to aid understanding and may not include all aspects or information compared to realistic depictions, and may include exaggerated material for illustrative purposes.

[0014]

[0018] In the accompanying drawings, similar components and / or features may have the same reference numeral. Furthermore, various components of the same kind may be distinguished according to their reference numerals by letters that distinguish similar components from each other. Where only a first reference numeral is used herein, the description is applicable to any one of the similar components having the same first reference numeral, regardless of the letters.

[0015]

[0019] In many integrated circuit applications, it is necessary to selectively remove one material from another. For example, in memory structures and gate-all-around devices, it may be necessary to selectively remove silicon material from adjacent silicon-germanium materials. When manufacturing memory structures and gate-all-around devices, stacks of materials may be developed that include adjacent layers of silicon material and silicon-germanium material. Subsequent manufacturing processes may require the selective removal of silicon material from silicon-germanium materials. While it is necessary to limit the removal of silicon-germanium materials (which may be silicon-germanium), etching may be used to remove silicon material (which may be silicon or contain silicon). Because silicon and silicon-germanium are chemically similar, it can be difficult to maintain high etching selectivity for silicon removal compared to silicon-germanium removal. Various precursors and processing conditions have been employed to improve etching selectivity.

[0016]

[0020] As semiconductor processing demands the use of more materials to provide improved patterning and material properties for various devices, silicon and germanium are increasingly being used not only for patterning other materials containing silicon, but also as materials for end devices. Conventional techniques have made it difficult to selectively remove silicon material from silicon and germanium materials, and etching rates have typically been limited to close to 1:1, especially in material layers with low germanium content, such as less than 50% or around 50%. Removing silicon material can result in excessive loss of some of the silicon and germanium material. Removal of silicon and germanium material can lead to material defects that can ultimately result in uniformity problems affecting the final device. Furthermore, conventional techniques may require processing at high pressure and the use of oxygen-containing precursors to increase selectivity. Higher pressures can result in more isotropic etching profiles, affecting the device structure and potentially generating particles. In addition, the presence of oxygen can cause the remaining material to oxidize, at least partially, which can reduce charge carrier mobility and adversely affect device performance. Therefore, many conventional technologies had limitations in their ability to prevent structural defects or performance degradation in the final device.

[0017]

[0021] This technology overcomes these problems by utilizing specific precursors that can be supplied under more specific processing conditions, thereby increasing silicon selectivity, while advantageously allowing etching at lower pressures without the use of oxygen-containing precursors. By providing specific precursor combinations, this technology can at least partially passivate or protect one layer of the material from being removed during processing, while another layer of the material can be removed more easily. Furthermore, by passivating or protecting one layer of the material from being removed during processing, this technology can develop structures in which adjacent layers may feature more similar chemical compositions, thereby reducing interlayer strain during formation and potentially improving removal selectivity.

[0018]

[0022] The following disclosures, while normally identifying specific etching processes utilizing the disclosed technology, will be readily apparent that the systems and methods are equally applicable to a variety of other processes that may be carried out in the described chambers. Therefore, this technology should not be considered limited to use in the etching processes described. Before describing exemplary process sequences, systems, methods, or processes in several embodiments of the technology, this disclosure describes one possible system and chamber that may be used in the technology. It should be understood that the technology is not limited to the described apparatus, and the processes discussed can be carried out in any number of processing chambers and systems.

[0019]

[0023] Figure 1 shows a top view of one embodiment of a processing system 10 comprising a deposition chamber, etching chamber, baking chamber, and / or curing chamber. The tool or processing system 10 depicted in Figure 1 may include a plurality of processing chambers 24a-d, a transfer chamber 20, a service chamber 26, an integrated measurement chamber 28, and a pair of load lock chambers 16a-b. The processing chambers may include any number of structures or components and any number or combination of processing chambers.

[0020]

[0024] To transfer the substrate between chambers, the transfer chamber 20 may include a robotic transfer mechanism 22. The transfer mechanism 22 may have a pair of substrate transfer blades 22a respectively attached to the distal ends of the extendable arms 22b. The blades 22a can be used to transport individual substrates between the processing chambers. During operation, one of the substrate transfer blades, such as the blade 22a of the transfer mechanism 22, retrieves the substrate W from one of the load lock chambers such as chambers 16a - b, and transports the substrate W to the first stage of processing in the processing chambers, for example, described below, within chambers 24a - d. Chambers may be included to perform individual or combined operations of the described techniques. For example, while one or more chambers may be configured to perform deposition or etching processes, one or more other chambers may be configured to perform the described pre - processing and / or one or more post - processing. Any number of configurations are encompassed by the present technology, and any number of additional manufacturing processes typically performed in semiconductor processes may also be executed.

[0021]

[0025] When the chamber is in use, the robot may wait until the processing is completed, then take out the processed substrate from the chamber using one blade 22a and insert a new substrate using the second blade. When the processing of the substrate is completed, the substrate can be moved to the second stage of processing. For each transfer, the transfer mechanism 22 generally transports the substrate with one blade to perform the substrate exchange, and the other blade may be empty. The transfer mechanism 22 can wait in each chamber until the exchange is completed.

[0022]

[0026] When the processing in the processing chamber is completed, the transfer mechanism 22 can move the substrate W from the last processing chamber and transport the substrate W to the cassettes in the load lock chambers 16a - b. The substrate can move from the load lock chambers 16a - b into the factory interface. The factory interface 12 can generally operate to transfer the substrate between the pod loaders 14a - d and the load lock chambers 16a - b in a clean environment at atmospheric pressure. The clean environment in the factory interface 12 can generally be provided through an air filtration process such as, for example, a HEPA filter. The factory interface 12 can also include a substrate aligner / orienter that can be used to properly align the substrate prior to processing. At least one substrate robot such as robots 18a - b can be arranged in the factory interface 12 to transfer the substrate between various positions and locations within the factory interface 12 and to other locations in communication with them. The robots 18a - 18b can be configured to move along a track system within the factory interface 12 from a first end to a second end of the factory interface 12.

[0023]

[0027] The processing system 10 can further include an integrated measurement chamber 28 to obtain a control signal that can provide adaptive control for any processing performed in the processing chamber. The integrated measurement chamber 28 can include any of a variety of measurement devices for measuring various film properties such as thickness, roughness, composition, etc., and the measurement devices can further be capable of characterizing lattice parameters such as critical dimensions, sidewall angles, and feature height by an automated method under vacuum.

[0024]

[0028] Each of the processing chambers 24a to d may be configured to perform one or more process steps in the manufacturing of semiconductor structures, and any number of processing chambers and combinations of processing chambers may be used on the multi-chamber processing system 10. For example, each processing chamber may be configured to perform any number of deposition processes, including periodic layer deposition, atomic layer deposition, chemical vapor deposition, and physical vapor deposition, as well as a number of substrate processing processes, including other processes such as etching, pre-cleaning, pre-treatment, post-treatment, annealing, plasma treatment, degassing, orientation, and other substrate treatments. Some specific processes that may be performed in any chamber or combination of chambers may include metal deposition, surface cleaning and treatment, thermal annealing such as rapid heat treatment, and plasma treatment. As will be readily apparent to those skilled in the art, any other processes may be similarly performed in any particular chamber incorporated into the multi-chamber processing system 10, including any of the processes described below.

[0025]

[0029] Figure 2 shows a schematic cross-sectional view of an exemplary processing chamber 100 suitable for patterning a material layer placed on a substrate 302 within the processing chamber 100. While the exemplary processing chamber 100 is suitable for performing a patterning process, it should be understood that embodiments of the art may be performed in any number of chambers, and the substrate support according to the art may be contained in an etching chamber, a deposition chamber, a processing chamber, or any other processing chamber. The plasma processing chamber 100 may include a chamber body 105 that defines a chamber volume 101 in which the substrate can be processed. The chamber body 105 may have side walls 112 and a bottom 118, which are connected to ground 126. The side walls 112 have liners 115 to protect the side walls 112, which may extend the time between maintenance cycles of the plasma processing chamber 100. The dimensions of the chamber body 105 and related components of the plasma processing chamber 100 are not limiting and may generally be larger in proportion to the size of the substrate 302 processed therein. Examples of substrate sizes include, in particular, those with diameters of 200 mm, 250 mm, 300 mm, and 450 mm, such as those used for displays or solar cell substrates.

[0026]

[0030] The chamber body 105 supports the chamber lid assembly 110 and surrounds the chamber space 101. The chamber body 105 may be manufactured from aluminum or other suitable material. A substrate access port 113 is formed through the side wall 112 of the chamber body 105, which facilitates the transfer of substrates 302 into and out of the plasma processing chamber 100. The access port 113 may be connected to the transfer chamber and / or other chambers of the substrate processing system as described above. A pumping port 145 may be formed through the side wall 112 of the chamber body 105 and connected to the chamber space 101. A pumping device may be connected to the chamber space 101 through the pumping port 145 to exhaust the processing space and control the pressure. The pumping device may include one or more pumps and throttle valves.

[0027]

[0031] The gas panel 160 may be connected to the chamber body 105 by a gas line 167 to supply a process gas into the chamber space 101. The gas panel 160 may include one or more process gas sources 161, 162, 163, 164, and may further include inert gases, non-reactive gases, and reactive gases that can be used for any number of processes. Examples of process gases that may be provided by the gas panel 160 include, but are not limited to, hydrocarbon-containing gases, including methane, sulfur hexafluoride, silicon chloride, carbon tetrafluoride, hydrogen bromide, hydrocarbon-containing gases, argon gas, chlorine, nitrogen, helium, and oxygen gas. Furthermore, the process gas may include nitrogen, chlorine, fluorine, oxygen, and hydrogen-containing gases such as BCl3, CF4, C2F4, C4F8, C4F6, CHF3, CH2F2, CH3F, NF3, NH3, CO2, SO2, CO, N2, NO2, N2O, and H2, among any number of additional precursors.

[0028]

[0032] Valve 166 can control the flow of processing gas from gas panel 160 sources 161, 162, 163, and 164, and can be managed by controller 165. The flow of gas supplied from gas panel 160 to chamber body 105 may include a combination of gases from one or more sources. Lid assembly 110 may include nozzles 114. Nozzles 114 may be one or more ports for introducing processing gas from gas panel 160 sources 161, 162, 164, and 163 into the chamber space 101. After the processing gas is introduced into the plasma processing chamber 100, the gas may be activated to form a plasma. Antennas 148, such as one or more inductor coils, may be provided adjacent to the plasma processing chamber 100. The antenna power supply 142 can supply power to the antenna 148 via the matching circuit 141 and inductively couple energy (e.g., RF energy) to the processing gas to maintain the plasma formed from the processing gas within the chamber space 101 of the plasma processing chamber 100. Alternatively, or in addition to the antenna power supply 142, processing electrodes located below and / or above the substrate 302 can be used to capacitively couple RF power to the processing gas to maintain the plasma within the chamber space 101. The operation of the power supply 142 can be controlled by a controller (e.g., controller 165) that also controls the operation of other components within the plasma processing chamber 100.

[0029]

[0033] A substrate support pedestal 135 may be positioned within the chamber space 101 to support the substrate 302 during the process. The substrate support pedestal 135 may include an electrostatic chuck 122 for holding the substrate 302 during the process. The electrostatic chuck ("ESC") 122 may hold the substrate 302 to the substrate support pedestal 135 using electrostatic attraction. The ESC 122 may be powered by an RF power supply 125 integrated with a matching circuit 124. The ESC 122 may include an electrode 121 embedded in a dielectric. The electrode 121 may be coupled to the RF power supply 125 and provide a bias to attract plasma ions formed by the processing gas in the chamber space 101 to the ESC 122 and the substrate 302 fixed on the pedestal. The RF power supply 125 may be switched on and off repeatedly or pulsed during the process of the substrate 302. The ESC122 may have an insulating section 128 to prevent the sidewalls of the ESC122 from being attracted to the plasma, in order to extend the maintenance life of the ESC122. In addition, the substrate support pedestal 135 may have a cathode dryer 136 to protect the sidewalls of the substrate support pedestal 135 from the plasma gas and to extend the maintenance interval of the plasma processing chamber 100.

[0030]

[0034] Electrode 121 may be connected to a power supply 150. The power supply 150 may provide electrode 121 with a chucking voltage of approximately 200 volts to approximately 2000 volts. The power supply 150 may also include a system controller for controlling the operation of electrode 121 by supplying DC current to electrode 121 for chucking and dechucking the substrate 302. ESC 122 may include a heater located within a pedestal and connected to the power supply for heating the substrate. Meanwhile, the cooling base 129 supporting ESC 122 may include conduits for circulating a thermal conductive fluid to maintain the temperature of ESC 122 and the substrate 302 placed on top of it. ESC 122 may be configured to operate within the temperature range required by the thermal balance of the device manufactured on the substrate 302. For example, ESC 122 may be configured to maintain the substrate 302 at a temperature from approximately -150°C or below to approximately 500°C or above, depending on the process being performed.

[0031]

[0035] A cooling base 129 may be provided to assist in temperature control of the substrate 302. To mitigate processing drift and time, the temperature of the substrate 302 may be kept substantially constant by the cooling base 129 while the substrate 302 is in the cleaning chamber. In some embodiments, the temperature of the substrate 302 may be maintained at a temperature between approximately -150°C and approximately 500°C throughout the subsequent cleaning process, although any temperature may be available. A covering 130 may be positioned on the ESC 122 and along the outer periphery of the substrate support pedestal 135. The covering 130 may be configured to shield the upper surface of the substrate support pedestal 135 from the plasma environment inside the plasma processing chamber 100 while containing etching gases in desired portions of the exposed upper surface of the substrate 302. As previously stated, lift pins may be selectively translated through the substrate support pedestal 135 to lift the substrate 302 above the substrate support pedestal 135 to facilitate access to the substrate 302 by a transfer robot or other suitable transfer mechanism.

[0032]

[0036] The controller 165 may be used to adjust the gas flow from the gas panel 160 to the plasma processing chamber 100 and other process parameters, and to control the process sequence. When executed by the CPU, the software routines translate the CPU into a purpose-specific computer (such as a controller) capable of controlling the plasma processing chamber 100, and as a result, the process is executed in accordance with this disclosure. The software routines may also be stored and / or executed by a second controller associated with the plasma processing chamber 100.

[0033]

[0037] The processing chambers described above may be used during the methods according to embodiments of this technology. Figure 3 shows a semiconductor processing method 300, which may be performed in one or more chambers 100 incorporated into a multi-chamber processing system 10, for example, as described above. Other chambers may also be used to perform one or more of the methods or processes described. Method 300 may include one or more processes, including front-end processing, deposition, etching, polishing, cleaning, or any other processes that may be performed before the described processes. This method may include a number of arbitrary processes shown in the drawings, which may or may not be particularly relevant to the methods according to this technology. For example, many of the processes described are provided to offer a broader range of semiconductor processes but may not be important to this technology, or may be performed by alternative methodologies, as will be discussed further below.

[0034]

[0038] Method 300 may include a number of processes that can be performed in numerous variations, including starting from different processes. Method 300 may generally include etching processes. While Method 300 will be described in a specific order, it should be understood that the method can be performed in numerous different variations according to embodiments of the Art. Method 300 can describe the processes schematically shown in Figures 4A-4B, which will be described in conjunction with the processes of Method 300. It should be understood that the structure 400 in Figures 4A-4B is only a partial schematic, and the substrate 405 may include any number of structural parts having the illustrated configuration, as well as alternative structural configurations that can still benefit from the processes of the Art.

[0035]

[0039] Referring to Figure 4A, the structure 400 may include a substrate 405. The substrate 405 may be placed within the processing area of ​​a semiconductor processing chamber. In embodiments, the substrate 405 may have a substantially flat surface or a surface with irregularities. The substrate 405 may be made of materials such as crystalline silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, silicon-on-insulator, carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, or sapphire. The substrate 405 may have various dimensions, such as wafers with a diameter of 200 mm or 300 mm, and rectangular or square panels. One or more layers of the material may be formed along the substrate 405. As shown, the substrate 405 may include at least one layer 410 of silicon-containing material and at least one layer 415 of silicon and germanium-containing material. However, the layers of material may be rearranged such that at least one layer 415 of silicon and germanium-containing material is placed between the substrate 405 and at least one layer 410 of silicon-containing material. Additional layers may also be formed on the substrate 405. For example, the silicon material layer and the silicon and germanium material layer may include any number of layers and any configuration, such as a layer for gate-all-around formation with any number of wires, or a layer for memory structures such as in 3D NAND topography. In any number of embodiments, an additional layer 420 of material may be deposited on top of at least one layer 415 of silicon and germanium-containing material, or on top of the silicon-containing material layer for patterning or other processing. In some embodiments of the art, the additional layer 420 of material may be a photoresist material.

[0036]

[0040] At least one layer 415 of the silicon and germanium-containing material may feature any germanium concentration, but in some embodiments, the material may feature a germanium concentration of less than 50 at.% or about 50 at.%. In the prior art, due to the chemical similarity between silicon materials such as polysilicon or amorphous silicon and silicon and germanium-containing materials containing silicon germanium, it was not possible to selectively etch silicon against silicon and germanium-containing materials characterized by a germanium concentration of less than 50 at.% or about 50 at.%. When silicon and silicon germanium are generally exposed to an etchant, etching selectivity may decrease based on the decreased germanium concentration as the amount of Si-Si bonds in the silicon and germanium material increases. However, as will be further described below, the precursor of the present art can passivate at least one layer 415 of the silicon and germanium-containing material, thereby increasing the etching selectivity of at least one layer 410 of the silicon-containing material against at least one layer 415 of the silicon and germanium-containing material. This makes it possible to apply this technology to layers with low germanium concentrations. Therefore, at least one layer 415 of the silicon and germanium-containing material may feature germanium concentrations of less than or about 45 at.%, less than or about 40 at.%, less than or about 35 at.%, less than or about 30 at.%, less than or about 25 at.%, less than or about 20 at.%, less than or about 20 at.%, less than or about 15 at.%. In embodiments, at least one layer 415 of the silicon and germanium-containing material may feature a germanium concentration greater than 50 at.%, which may result in an increase in the amount of germanium and, therefore, an increase in etching selectivity due to the difference from at least one layer 410 of the silicon-containing material.

[0037]

[0041] In step 305, method 300 may include providing one or more precursors. The precursors may be provided to a processing area of ​​a semiconductor processing chamber. Method 300 may include providing a fluorine-containing precursor, a hydrogen-containing precursor, and / or a nitrogen-containing precursor. The fluorine-containing precursors that may be used in step 305 may be any number of fluorine-containing precursors or may include fluorine-containing precursors. For example, the fluorine-containing precursors may be or include nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), fluoromethane (CH3F), difluoromethane (CH2F2), fluoroform (CHF3), any compound having carbon and fluorine, or any other fluorine compound including an oxygen-free fluorine-containing compound. In some embodiments, the fluorine-containing precursors may include both NF3 and CF4. By introducing carbon such as CF4, at least one layer 415 of the silicon and germanium-containing material may be passivated and more resistant to etching, as further described below. The hydrogen-containing precursors that may be used in step 305 may be any number of hydrogen-containing precursors or may include hydrogen-containing precursors. The hydrogen-containing precursors may include diatomic hydrogen (H2), hydrazine (N2H4), methane (CH4), or any other hydrogen compounds including oxygen-free hydrogen-containing precursors. The nitrogen-containing precursors that may be used in step 305 may be any number of nitrogen-containing precursors or may include nitrogen-containing precursors. The nitrogen-containing precursors may include diatomic nitrogen (N2), ammonia (NH3), NF3, or any other oxygen-free nitrogen compounds, although the nitrogen compounds may include oxygen in some embodiments, such as nitrous oxide, nitric oxide, or other compounds. In some embodiments, any number of additional carrier gases may be included, such as helium, argon, or other materials that help stabilize or generate the plasma, but the precursors used in embodiments may be limited to one or more fluorine-containing precursors, hydrogen-containing precursors, and / or nitrogen-containing precursors, as described above.

[0038]

[0042] The flow rate ratio of hydrogen-containing precursors to any or all of fluorine-containing precursors may be greater than or about 2.0:1, which may enable polymerization reactions that aid in the passivation of the silicon and germanium materials. At flow rate ratios less than 2.0:1, the plasma may not have enough hydrogen to passivate at least one layer of the silicon and germanium-containing material. As will be further described below, the precursors may interact to form a material having carbon, hydrogen, and fluorine on at least one layer 415 of the silicon and germanium-containing material. The carbon, hydrogen, and fluorine material can prevent at least one layer 415 of the silicon and germanium-containing material from being removed during subsequent processing. Therefore, the flow rate ratio of hydrogen-containing precursors to fluorine-containing precursors may be greater than or about 2.5:1, greater than or about 3.0:1, greater than or about 3.0:1, greater than or about 3.5:1, greater than or about 4.0:1, or about 4.0:1 for each fluorine-containing precursor, but the flow rate ratio may be less than or about 2.0:1 of the total flow rate of fluorine-containing precursors, for example, when both carbon tetrafluoride and nitrogen trifluoride are used, and the flow rate ratio may be less than or about 1.8:1, less than or about 1.6:1, less than or about 1.6:1, less than or about 1.5:1, less than or about 1.5:1, less than or about 1.4:1, or less than the combined flow rate of all fluorine-containing precursors. In some embodiments, the hydrogen-containing flow rate may be controlled within a range that enhances the selectivity between silicon-containing materials and silicon and germanium-containing materials. As shown in Figure 5A, etching selectivity may be higher at certain hydrogen-containing precursor flow rates than at lower and / or higher hydrogen-containing precursor flow rates. For example, at flow rate ratios of hydrogen-containing precursor to any individual fluorine-containing precursor less than 2.0:1 or about 2.0:1, etching selectivity may decrease due to reduced polymerization activity, although other embodiments may also exist. Similarly, at flow rate ratios of individual fluorine-containing precursors greater than 6.0:1 or about 6.0:1, etching selectivity may decrease due to the effects on etchant generation and plasma creation.Therefore, higher etching selectivity may be obtained depending on the flow rate of the hydrogen-containing precursor, and thus the flow rate ratio of the hydrogen-containing precursor to the fluorine-containing precursor between approximately 2.0:1 and approximately 6.0:1.

[0039]

[0043] The flow rate of individual fluorine-containing precursors may be greater than or approximately 20 sccm. The flow rate of fluorine-containing precursors may be measured as the cumulative flow rate of all fluorine-containing precursors. If the combined flow rate of fluorine-containing precursors is less than 40 sccm, there may not be enough fluorine for passivation of at least one layer 415 of the silicon and germanium-containing material and / or etching of at least one layer 410 of the silicon-containing material, which may result in longer etching times and longer exposure times to the etchant of the silicon and germanium-containing material, leading to reduced selectivity. Therefore, the combined flow rate of fluorine precursors may be greater than or approximately 50 sccm, greater than or approximately 60 sccm, greater than or approximately 70 sccm, greater than or approximately 80 sccm, greater than or approximately 90 sccm, greater than or approximately 100 sccm, greater than or approximately 110 sccm, or approximately 110 sccm, or exceed these values. Furthermore, the flow rate of the fluorine-containing precursor can be adjusted according to the amount of passivation and / or etching desired for each application.

[0040]

[0044] The flow rate of the hydrogen-containing precursor may be greater than or about 40 sccm. The flow rate of the hydrogen-containing precursor may be measured as the cumulative flow rate of all hydrogen-containing precursors. At flow rates less than 40 sccm, there may not be enough hydrogen to promote polymerization for passivation of at least one layer 415 of the silicon and germanium-containing material and / or etching of at least one layer of the silicon-containing material. Therefore, the flow rate of the hydrogen-containing precursor may be greater than or about 50 sccm, greater than or about 60 sccm, greater than or about 70 sccm, greater than or about 80 sccm, greater than or about 90 sccm, greater than or about 100 sccm, greater than or about 110 sccm, greater than or about 120 sccm, greater than or about 130 sccm, 140 sccm The flow rates may be greater than or about 140 sccm, greater than or about 150 sccm, greater than or about 160 sccm, greater than or about 170 sccm, greater than or about 180 sccm, greater than or about 190 sccm, greater than or about 200 sccm, greater than or about 210 sccm, greater than or about 220 sccm, or greater than or 220 sccm. Furthermore, the flow rate of the hydrogen-containing precursor may be adjusted according to the amount of passivation and / or etching desired for each application.

[0041]

[0045] The flow rate ratio of the nitrogen-containing precursor to the fluorine-containing precursor may be greater than 1:5 or about 1:5. At flow rates less than 1:5, there may not be enough nitrogen to passivate at least one layer 415 of the silicon and germanium-containing material and / or to etch at least one layer of the silicon-containing material. Therefore, the flow rate ratio of the nitrogen-containing precursor to the fluorine-containing precursor may be greater than 1:4 or about 1:4, greater than 1:3 or about 1:3, greater than 1:2 or about 1:2, greater than 1:1 or 1:1, greater than 3:2 or about 3:2, or higher.

[0042]

[0046] In embodiments, one or more inert precursors or carrier gases may also be provided in step 305. In embodiments, the inert precursor may be or include argon, helium, or other precious metals or inert materials. In embodiments using argon compared to helium, etching selectivity may be improved because argon has a lower activation energy compared to helium. The lower activation energy of argon may be due to argon's high ion impact energy, which can increase the overall etching rate and accelerate the etching process.

[0043]

[0047] In the embodiment, the flow rate of the inert precursor may be less than or greater than the flow rate of the fluorine-containing precursor. In the embodiment, the flow rate of the inert precursor may be less than or about 200 sccm, less than or about 190 sccm, less than or about 180 sccm, less than or about 170 sccm, less than or about 160 sccm, less than or about 150 sccm, less than or about 140 sccm, less than or about 130 sccm, less than or about 120 sccm, less than or about 110 sccm, less than or about 100 sccm, or less than that. In the embodiment, the flow rate of the inert precursor may be decreased and the flow rate of the nitrogen-containing precursor may be increased. Increasing the flow rate of the nitrogen-containing precursor may generate additional salts on the surface of at least one layer 410 of the silicon-containing material and at least one layer 415 of the silicon and germanium-containing material via the formation of NH4F, as will be further described below.

[0044]

[0048] In step 310, method 300 may include forming a plasma. The plasma may be formed from a fluorine-containing precursor, a hydrogen-containing precursor, a nitrogen-containing precursor, and / or an inert precursor. The plasma may be formed within the processing area of ​​a semiconductor processing chamber. In embodiments, a processing chamber, such as one of the chambers 100 incorporated into a multi-chamber processing system 10, may have two or more source plasma power supplies or electrodes. Method 300 may include providing power to less than one or all of the source plasma power supplies. Plasma formation may be carried out with source plasma power of less than 1,000 W or about 1,000 W. Source plasma power of more than 1,000 W or about 1,000 W may increase the plasma temperature and etching capability, increase the removal of silicon germanium by salt decomposition, and further decrease selectivity based on increased surface reactions described later. Therefore, plasma formation can be carried out with source plasma powers of less than 950W or about 900W, less than 850W or about 850W, less than 800W or about 800W, less than 750W or about 700W, less than 650W or about 650W, less than 600W or about 600W, or less than these. Furthermore, when the source plasma power is less than 100W or about 100W, the etching process may slow down, the residence time of the etchant may increase, and the selectivity may decrease. Therefore, plasma formation can be carried out with source plasma powers of more than 150W or about 150W, more than 200W or about 200W, more than 250W or about 250W, more than 300W or about 300W, more than 350W or about 350W, more than 400W or about 400W, or higher. Figure 5B is a graph illustrating the relationship between source plasma power and etching selectivity. As the source plasma power increases, etching selectivity may decrease. Similarly, as the source plasma power decreases, etching selectivity may decrease. Therefore, source plasma power between approximately 300W and 800W may provide higher etching selectivity.

[0045]

[0049] In the embodiments, the plasma of the carbon-containing precursor, hydrogen-containing precursor, nitrogen-containing precursor, and / or inert precursor may or may not be biased. The bias applied to the plasma of the carbon-containing precursor, hydrogen-containing precursor, nitrogen-containing precursor, and / or inert precursor may be generated with a bias power of less than 100 W or about 100 W. With bias powers greater than 100 W, the interaction between one or more precursors and the structure 400 may become more physical and less chemical. Greater physical interaction may reduce the selectivity of removal, and at least one layer 410 of the silicon-containing material and at least one layer 415 of the silicon and germanium-containing material may be removed at nearly equal rates, such as with etching selectivity close to 1:1. Therefore, the bias power applied to the plasma may be less than 90W or about 90W, less than 80W or about 80W, less than 70W or about 70W, less than 60W or about 60W, less than 50W or about 50W, less than 40W or about 40W, less than 30W or about 30W, less than 20W or about 20W, less than 10W or about 10W, and in some embodiments, no bias may be applied at all, which may further improve selectivity.

[0046]

[0050] Plasmas of fluorine-containing precursors, hydrogen-containing precursors, nitrogen-containing precursors, and / or inert precursors can be generated with duty cycles of less than 50% or about 50%. By operating with duty cycles of less than 50% or about 50%, the plasma power of the effective source and bias when used is reduced, and the reaction can be maintained as a chemical reaction rather than a physical reaction. Thus, plasmas can be generated with duty cycles of less than 45% or about 45%, less than 40% or about 40%, less than 35% or about 35%, less than 30% or about 30%, less than 25% or about 25%, less than 20% or about 20%, less than 15% or about 15%, less than 10% or about 10%, or less than these.

[0047]

[0051] In one embodiment, method 300 may include pulsed source plasma power while generating a precursor plasma emission. In embodiments, source plasma power can be pulsed at frequencies of less than 1,000 Hz or about 1,000 Hz, less than 950 Hz or about 950 Hz, less than 900 Hz or about 900 Hz, less than 850 Hz or about 850 Hz, less than 800 Hz or about 800 Hz, less than 750 Hz or about 750 Hz, less than 700 Hz or about 700 Hz, less than 650 Hz or about 650 Hz, less than 600 Hz or about 600 Hz, less than 550 Hz or about 550 Hz, less than 500 Hz or about 500 Hz, less than 450 Hz or about 450 Hz, less than 400 Hz or about 400 Hz, less than 350 Hz or about 350 Hz, less than 300 Hz or about 300 Hz, less than 250 Hz or about 250 Hz, less than 200 Hz or about 200 Hz, or lower.

[0048]

[0052] In the embodiments, the plasma may not contain oxygen. In the prior art where oxygen may be present in the plasma, at least one layer 410 of the silicon-containing material and / or at least one layer 415 of the silicon and germanium-containing material may oxidize to form Si-O bonds. Si-O bonds may be more difficult to etch than Si-Si bonds, Si-Ge bonds, or Ge-Ge bonds because their bond energy may be higher. When at least one layer 410 of the silicon-containing material is oxidized to form Si-O bonds, it may become more difficult to remove the at least one layer 410 of the silicon-containing material, and etching selectivity may decrease. Furthermore, the presence of oxygen may at least partially oxidize at least one layer 415 of the silicon and germanium-containing material and other materials, reducing the mobility of charge carriers.

[0049]

[0053] Plasma emissions may undergo a gas-phase reaction before contacting the structure 400. The gas-phase reaction may form intermediates that can react with at least one layer 410 of the silicon-containing material and at least one layer 415 of the silicon- and germanium-containing material. For example, precursors may react to form passivation compounds and etching compounds. Passivation compounds may include carbon materials, hydrogen materials, and fluorine materials. Passivation compounds may form a material on at least one layer 415 of the silicon- and germanium-containing material. The material formed by the passivation compound may produce a porous coating that can limit the removal of germanium. While removing the silicon material, some silicon may be removed through openings or pores in the passivation material. Silicon removal may result in an increase in germanium concentration on the surface of at least one layer 415 of the silicon- and germanium-containing material. Germanium may not be readily removed through the passivation material. Etching compounds may include nitrogen materials, hydrogen materials, and fluorine materials. The etching compound can simultaneously assist in the passivation of at least one layer 415 of the silicon and germanium-containing material and enhance the etching selectivity of at least one layer 410 of the silicon-containing material.

[0050]

[0054] Step 315 may include bringing at least one layer 410 of the silicon-containing material and at least one layer 415 of the silicon and germanium-containing material into contact with a plasma emission of precursors, which includes a fluorine-containing precursor and a hydrogen-containing precursor. The nitrogen, hydrogen, and fluorine precursors may form salts, such as ammonium salts, on at least one layer 410 of the silicon-containing material and / or at least one layer 415 of the silicon and germanium-containing material. The salts formed on at least one layer 410 of the silicon-containing material may have a lower decomposition temperature than the salts formed on at least one layer 415 of the silicon and germanium-containing material.

[0051]

[0055] For example, the salt formed on at least one layer 410 of the silicon-containing material may be or contain ammonium silicofluoride, and the salt formed on at least one layer 415 of the silicon and germanium-containing material may be or contain ammonium hexafluorogermanate. Ammonium silicofluoride may have a standard decomposition temperature of about 130°C, and ammonium hexafluorogermanate may have a standard decomposition temperature of about 380°C. Method 300 may be carried out at a temperature and other process conditions that allow sublimation of ammonium silicofluoride while minimizing or preventing sublimation of ammonium hexafluorogermanate. That is, Method 300 may be carried out at a temperature, pressure, and plasma power that allows ammonium hexafluorogermanate to remain on at least one layer 415 of the silicon and germanium-containing material. When Method 300 is carried out at a temperature below the decomposition temperature of ammonium silicofluoride, the plasma may increase the temperature in the processing area so that ammonium silicofluoride can decompose. As the ammonium silicate sublimates, at least one layer 410 of the silicon-containing material may be etched as ammonium silicate, and at least one layer 410 of the silicon-containing material may decompose into one or more volatiles that can then be purged from the processing area.

[0052]

[0056] In step 320, method 300 may include at least partially removing or denting at least one layer 410 of the silicon-containing material. The at least one layer 410 of the silicon-containing material may be removed at a higher rate than the at least one layer 415 of the silicon and germanium-containing material. The at least one layer 410 of the silicon-containing material may be selectively removed at a rate greater than 3:2 or about 3:2 relative to the at least one layer 415 of the silicon and germanium-containing material. In embodiments, the at least one layer 410 of the silicon-containing material may be selectively removed at a rate greater than 2:1 or about 2:1, greater than 3:1 or about 3:1, greater than 4:1 or about 4:1, greater than 5:1 or about 5:1, greater than 6:1 or about 6:1, greater than 7:1 or about 7:1, or higher relative to the at least one layer 415 of the silicon and germanium-containing material.

[0053]

[0057] The etching rate can be adjusted according to the precursor flow rate, as well as the plasma power characteristics, including source plasma power, bias plasma power, duty cycle, and frequency. In embodiments, the etching rate of at least one layer 410 of the silicon-containing material may be greater than or about 15.0 Å / s, greater than or about 16.0 Å / s, greater than or about 17.0 Å / s, greater than or about 18.0 Å / s, greater than or about 19.0 Å / s, greater than or about 20.0 Å / s, greater than or about 21.0 Å / s, 22.0 The speed may be greater than or approximately 22.0 Å / s, greater than or approximately 23.0 Å / s, greater than or approximately 24.0 Å / s, greater than or approximately 25.0 Å / s, greater than or approximately 26.0 Å / s, greater than or approximately 27.0 Å / s, greater than or approximately 28.0 Å / s, greater than or approximately 29.0 Å / s, greater than or approximately 30.0 Å / s, or exceeding these speeds.

[0054]

[0058] During method 300, the temperature in the semiconductor processing chamber, such as the substrate support temperature or substrate temperature, may be maintained at less than 125°C or about 125°C. At temperatures above 125°C, silicon and etching byproducts of both silicon and germanium may volatilize, increasing the etching of the silicon-germanium material and potentially reducing the etching selectivity of at least one layer 410 of the silicon-containing material to at least one layer 415 of the silicon- and germanium-containing material. Therefore, the temperature inside the semiconductor processing chamber can be maintained at a temperature of less than 120°C or approximately 120°C, less than 115°C or approximately 115°C, less than 110°C or approximately 110°C, less than 105°C or approximately 105°C, less than 100°C or approximately 100°C, less than 95°C or approximately 95°C, less than 80°C or approximately 80°C, less than 75°C or approximately 75°C, less than 70°C or approximately 70°C, less than 65°C or approximately 65°C, less than 60°C or approximately 60°C, less than 55°C or approximately 55°C, less than 50°C or approximately 50°C, or below these temperatures.

[0055]

[0059] Furthermore, the pressure in the semiconductor processing chamber can be maintained at less than 200 mTorr or approximately 200 mTorr. Pressures above 200 mTorr may make plasma formation more difficult, and Method 300 may be more prone to generating unwanted byproducts. In addition, pressures above 200 mTorr may result in a more isotropic etching profile, reducing etching selectivity. Therefore, the pressure in the semiconductor processing chamber can be maintained at less than 190 mTorr or approximately 190 mTorr, less than 180 mTorr or approximately 180 mTorr, less than 170 mTorr or approximately 170 mTorr, less than 160 mTorr or approximately 160 mTorr, less than 150 mTorr or approximately 150 mTorr, less than 140 mTorr or approximately 140 mTorr, less than 130 mTorr or approximately 130 mTorr, less than 120 mTorr or approximately 120 mTorr, less than 110 mTorr or approximately 110 mTorr, 1 It may be maintained at a pressure of less than 00 mTorr or about 100 mTorr, less than 90 mTorr or about 90 mTorr, less than 80 mTorr or about 80 mTorr, less than 70 mTorr or about 70 mTorr, less than 60 mTorr or about 60 mTorr, less than 50 mTorr or about 50 mTorr, less than 40 mTorr or about 40 mTorr, less than 30 mTorr or about 30 mTorr, less than 20 mTorr or about 20 mTorr, less than 10 mTorr or about 10 mTorr, or less than these.

[0056]

[0060] The above description includes numerous details for explanatory purposes to facilitate understanding of the various embodiments of this technology. However, it will be obvious to those skilled in the art that certain embodiments can be practiced without some of these details, or with additional details.

[0057]

[0061] While several embodiments have been disclosed, it will be recognized by those skilled in the art that various modifications, alternative structures, and equivalents can be used without departing from the essence of the embodiments. In addition, some well-known processes and elements have not been described in order to avoid unnecessarily obscuring the Art. Therefore, the above description should not be construed as limiting the scope of the Art.

[0058]

[0062] Where a range of values ​​is provided, each of the intervening values ​​between the upper and lower limits of that range is understood to be specifically disclosed down to the smallest unit of the lower limit (unless explicitly indicated otherwise in the context). Narrower ranges between any two listed values ​​or between any two unlisted intervening values ​​within a given range, and all other listed or intervening values ​​within such ranges, are included. The upper and lower limits of such narrower ranges may, individually, be included in or excluded from this range. Each range that includes either, neither, or both of the limit values ​​is also included in the Art, provided that there are any limit values ​​specifically excluded within the range. Where a range includes one or both of the limit values, a range that excludes either or both of the included limit values ​​is also included.

[0059]

[0063] In this book and the accompanying claims, the singular forms “a, an” and “the” imply a plural meaning (unless explicitly indicated otherwise in the context). Therefore, for example, “a fluorine-containing precursor” refers to multiple such precursors, and “the at least one layer of silicon-containing material” refers to one or more materials and equivalents well known to those skilled in the art; the same applies to other forms.

[0060]

[0064] Furthermore, when the words “comprise(s) / comprising,” “contain(s) / containing,” and “include(s) / including” are used in this specification and the following claims, they are intended to identify the presence of the described features, integers, components, or processes, but not to exclude the presence or addition of one or more other features, integers, components, processes, operations, or groups.

Claims

1. A semiconductor processing method, The present invention provides a fluorine-containing precursor and a hydrogen-containing precursor to a processing area of ​​a semiconductor processing chamber, wherein a substrate is placed within the processing area of ​​the semiconductor processing chamber, the substrate comprises at least one layer of silicon-containing material and at least one layer of silicon and germanium-containing material along the substrate, and the fluorine-containing precursor comprises nitrogen trifluoride. Plasma of the fluorine-containing precursor and the hydrogen-containing precursor is formed within the processing region. The process involves bringing at least one layer of the silicon-containing material and at least one layer of the silicon and germanium-containing material into contact with the plasma emissions of the fluorine-containing precursor and the hydrogen-containing precursor. Removing at least one layer of the silicon-containing material at a higher rate than removing at least one layer of the silicon and germanium-containing material, A semiconductor processing method, including the following.

2. The semiconductor processing method according to claim 1, wherein the fluorine-containing precursor further comprises carbon tetrafluoride.

3. The semiconductor processing method according to claim 1, wherein at least one layer of the silicon-containing material is selectively removed from at least one layer of the silicon and germanium-containing material at a rate greater than 2:1 or about 2:

1.

4. The semiconductor processing method according to claim 1, wherein the plasma of the fluorine-containing precursor and the hydrogen-containing precursor is generated with a source plasma power of less than 1,000 W or about 1,000 W.

5. The semiconductor processing method according to claim 1, wherein the bias applied to the plasma of the fluorine-containing precursor and the hydrogen-containing precursor is generated with a bias power of less than 100 W or about 100 W.

6. The semiconductor processing method according to claim 1, wherein the plasma of the fluorine-containing precursor and the hydrogen-containing precursor is generated with a duty cycle of less than 50% or about 50%.

7. The semiconductor processing method according to claim 4, further comprising supplying pulsed source plasma power while forming the plasma emitters of the fluorine-containing precursor and the hydrogen-containing precursor, wherein the source plasma power is supplied in pulses at a frequency of less than 1000 Hz or about 1000 Hz.

8. The temperature inside the semiconductor processing chamber is maintained at less than 125°C or approximately 125°C. The pressure inside the semiconductor processing chamber is maintained at less than 200 mTorr or approximately 200 mTorr. The semiconductor processing method according to claim 1.

9. To provide an inert precursor in the processing region of the semiconductor processing chamber containing the fluorine-containing precursor and the hydrogen-containing precursor, wherein the inert precursor includes a nitrogen-containing inert precursor, an argon-containing inert precursor, a helium-containing inert precursor, or a combination thereof. The semiconductor processing method according to claim 1, further comprising:

10. The semiconductor processing method according to claim 1, wherein the flow rate ratio of the hydrogen-containing precursor to the fluorine-containing precursor is greater than 2:1 or about 2:

1.

11. The semiconductor processing method according to claim 1, wherein the plasma does not contain oxygen.

12. A semiconductor processing method, To provide a fluorine-containing precursor, a hydrogen-containing precursor, and a nitrogen-containing precursor, Forming a plasma of the fluorine-containing precursor, the hydrogen-containing precursor, and the nitrogen-containing precursor, The method involves bringing at least one layer of silicon-containing material and at least one layer of silicon and germanium-containing material along a substrate into contact with plasma emitters of the fluorine-containing precursor, the hydrogen-containing precursor, and the nitrogen-containing precursor, wherein the contact selectively removes at least one layer of the silicon-containing material, and the method involves bringing at least one layer of silicon-containing material and at least one layer of silicon and germanium-containing material into contact with plasma emitters. Includes, The semiconductor processing method wherein the pressure is maintained at less than 50 mTorr.

13. A semiconductor processing method, To provide a fluorine-containing precursor, a hydrogen-containing precursor, and a nitrogen-containing precursor, Forming a plasma of the fluorine-containing precursor, the hydrogen-containing precursor, and the nitrogen-containing precursor, The method involves bringing at least one layer of silicon-containing material and at least one layer of silicon and germanium-containing material along a substrate into contact with plasma emitters of the fluorine-containing precursor, the hydrogen-containing precursor, and the nitrogen-containing precursor, wherein the contact selectively removes at least one layer of the silicon-containing material, and the method involves bringing at least one layer of silicon-containing material and at least one layer of silicon and germanium-containing material into contact with plasma emitters. Includes, The fluorine-containing precursor contains carbon tetrafluoride, A semiconductor processing method wherein the nitrogen-containing precursor contains nitrogen trifluoride.

14. A semiconductor processing method, To provide a fluorine-containing precursor, a hydrogen-containing precursor, and a nitrogen-containing precursor, Forming a plasma of the fluorine-containing precursor, the hydrogen-containing precursor, and the nitrogen-containing precursor, The method involves bringing at least one layer of silicon-containing material and at least one layer of silicon and germanium-containing material along a substrate into contact with plasma emitters of the fluorine-containing precursor, the hydrogen-containing precursor, and the nitrogen-containing precursor, wherein the contact selectively removes at least one layer of the silicon-containing material, and the method involves bringing at least one layer of silicon-containing material and at least one layer of silicon and germanium-containing material into contact with plasma emitters. Includes, A semiconductor processing method comprising the following steps: when the fluorine-containing precursor and the nitrogen-containing precursor come into contact with at least one layer of the silicon-containing material and at least one layer of the silicon and germanium-containing material, a passivation compound and an etching compound are formed, the passivation compound comprising a carbon material, a hydrogen material and a fluorine material, and the etching compound comprising a nitrogen material, a hydrogen material and a fluorine material.

15. The semiconductor processing method according to claim 12, 13, or 14, wherein the pressure is maintained at less than 30 mTorr or about 30 mTorr.

16. The semiconductor processing method according to claim 12, 13, or 14, wherein at least one layer of the silicon and germanium-containing material is characterized by a germanium concentration of less than 50 at.% or about 50 at.%.

17. The semiconductor processing method according to claim 14, wherein the etching compound removes at least one layer of the silicon-containing material with a selectivity of more than 3:2 or about 3:2 with respect to at least one layer of the silicon and germanium-containing material.

18. A semiconductor processing method, To provide a fluorine-containing precursor, a hydrogen-containing precursor, and a nitrogen-containing precursor, Forming a plasma of the fluorine-containing precursor, the hydrogen-containing precursor, and the nitrogen-containing precursor, The method involves bringing at least one layer of silicon-containing material and at least one layer of silicon and germanium-containing material along a substrate into contact with plasma emitters of the fluorine-containing precursor, the hydrogen-containing precursor, and the nitrogen-containing precursor, wherein the contact selectively removes at least one layer of the silicon-containing material, and the method involves bringing at least one layer of silicon-containing material and at least one layer of silicon and germanium-containing material into contact with plasma emitters. Includes, A semiconductor processing method further comprising providing a hydrogen-containing precursor and an inert precursor together with the fluorine-containing precursor and the nitrogen-containing precursor.

19. The fluorine-containing precursor, the nitrogen-containing precursor, the hydrogen-containing precursor, and the inert precursor form the passivation compound and the etching compound, The passivation compound passivates at least one layer of the silicon and germanium-containing material. The etching compound removes at least one layer of the silicon-containing material. The semiconductor processing method according to claim 14.

20. A semiconductor processing method, The present invention provides a fluorine-containing precursor and a nitrogen-containing precursor to a processing area of ​​a semiconductor processing chamber, wherein a substrate is placed within the processing area of ​​the semiconductor processing chamber, and the substrate comprises at least one layer of silicon-containing material and at least one layer of silicon and germanium-containing material along the substrate. The process involves forming a plasma of the fluorine-containing precursor and the nitrogen-containing precursor within the processing region, wherein the plasma is generated with a discontinuous plasma power of less than 1,000 W or approximately 1,000 W. The method involves bringing at least one layer of the silicon-containing material and at least one layer of the silicon and germanium-containing material into contact with the plasma emitters of the fluorine-containing precursor and the nitrogen-containing precursor, wherein the contact is passivated by bringing at least one layer of the silicon and germanium-containing material into contact with the plasma emitters. Removing at least one layer of the silicon-containing material at a higher rate than at least one layer of the silicon and germanium-containing material, wherein at least one layer of the silicon-containing material is selectively removed at a rate greater than 3:2 or about 3:2 with respect to at least one layer of the silicon and germanium-containing material. A semiconductor processing method, including the following.

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