Semiconductor equipment
The semiconductor device uses a low-phosphorus Ni plating layer with a convex partition wall and controlled substrate thickness to address miniaturization challenges and crack issues, enabling stable operation at high temperatures with reduced resistance.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- DENSO CORP
- Filing Date
- 2022-07-25
- Publication Date
- 2026-06-23
AI Technical Summary
Existing semiconductor devices face challenges in miniaturization due to the need for large current-carrying electrodes and the occurrence of cracks in Ni plating layers during high-temperature soldering processes, especially when using high-melting-point solder for clip mounting.
The semiconductor device employs a low-phosphorus Ni plating layer with a columnar crystal layer ratio of 50% or less and a convex-shaped partition wall to separate electrodes, along with a semiconductor substrate thickness of 70 μm or less, and a radius of curvature of 30 μm or more for the partition wall, to reduce stress and prevent cracking.
This configuration effectively suppresses crack formation in the Ni plating layer, allowing for miniaturization and stable operation at higher temperatures, such as 390°C, while maintaining low on-resistance and reducing parasitic resistance.
Smart Images
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Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor device.
Background Art
[0002] The semiconductor device described in Patent Document 1 is configured to be mounted on a printed circuit board. This semiconductor device includes a semiconductor element, a lead frame, a clip, and a sealing resin portion. The semiconductor element is, for example, a MOSFET or an IGBT. MOSFET is an abbreviation for Metal-Oxide-Semiconductor Field-Effect Transistor. IGBT is an abbreviation for Insulated-Gate Bipolar Transistor. A structure including the semiconductor device and a printed circuit board on which this semiconductor device is mounted is called an electronic device.
[0003] In the configuration described in Patent Document 1, electrodes are formed on both surfaces of the semiconductor element. Specifically, a drain electrode is provided on the back side of the semiconductor element. Also, a source electrode and a gate electrode are provided on the front side of the semiconductor element. The lead frame has a drain terminal and a source terminal. The drain terminal has the semiconductor element mounted on the mounting surface. That is, the drain terminal is electrically connected to the drain electrode via a conductive connection member such as solder. The source terminal is electrically connected to the source electrode via a clip. Specifically, the clip is made mainly of a conductive material such as a metal material, and has an electrode facing portion facing the source electrode, a terminal facing portion facing the source terminal, and a connecting portion connecting the electrode facing portion and the terminal facing portion. The electrode facing portion, the terminal facing portion, and the connecting portion are integrally formed. The electrode facing portion of the clip is electrically connected to the source electrode via solder. Also, the terminal facing portion of the clip is electrically connected to the source terminal via solder.
Prior Art Documents
Patent Documents
[0004] [Patent Document 1] Japanese Patent Publication No. 2021-15857 [Overview of the project] [Problems that the invention aims to solve]
[0005] For example, according to a configuration in which a module including semiconductor elements (e.g., a power module) and a circuit are mounted integrally on a printed circuit board, as described in Patent Document 1, miniaturization of semiconductor devices and electronic devices can be achieved. In this case, the current-carrying electrodes, such as drain terminals and source terminals, of the semiconductor elements need to be formed over the largest possible area. In particular, in order to eliminate parasitic resistance and achieve low on-resistance by employing so-called clip mounting, it is necessary to use solder with a higher melting point than the solder used for printed circuit board mounting in the semiconductor device, thereby increasing the area of the current-carrying electrodes. Furthermore, if control electrodes such as gate electrodes are formed on the same plane as the current-carrying electrodes, there is a concern that the element area will increase. The present invention has been made in view of the circumstances exemplified above. That is, the present invention provides a technology that can effectively achieve miniaturization of semiconductor devices, for example. [Means for solving the problem]
[0006] The semiconductor device (1) described in claim 1 is A semiconductor substrate (201) constituting the semiconductor device (2), A first electrode (231) is provided on one surface (22) of the semiconductor device and is formed of a Ni plating layer, A second electrode (232) is provided on one surface of the semiconductor element and is formed of a Ni plating layer, A partition wall portion (242;281) is provided on one surface of the semiconductor element to separate the first electrode and the second electrode, and is made of an insulating material, Equipped with, The semiconductor element is formed from the semiconductor substrate with a thickness of 70 μm or less. The phosphorus concentration in the Ni plating layer constituting the first electrode and the second electrode is 4% by weight or less. The Ni plating layer constituting the first electrode or the second electrode is formed such that the ratio of the thickness of the columnar crystal layer (207) to the total layer thickness is 50% or less. The partition wall portion has a convex shape toward the first electrode or the second electrode. It is formed such that the radius of curvature of the convex shape is 30 μm or more. ru. The semiconductor device (1) described in claim 2 is A semiconductor substrate (201) constituting the semiconductor device (2), A first electrode (231) is provided on one surface (22) of the semiconductor device and is formed of a Ni plating layer, A second electrode (232) is provided on one surface of the semiconductor element and is formed of a Ni plating layer, A partition wall portion (242;281) is provided on one surface of the semiconductor element to separate the first electrode and the second electrode, Equipped with, The semiconductor element is formed from the semiconductor substrate with a thickness of 160 μm or less. The phosphorus concentration in the Ni plating layer constituting the first electrode and the second electrode is 4% by weight or less. The Ni plating layer constituting the first electrode or the second electrode is formed such that the ratio of the thickness of the columnar crystal layer (207) to the total layer thickness is 50% or less. The partition wall portion has a convex shape toward the first electrode or the second electrode, and is formed such that the radius of curvature of the convex shape is 60 μm or more.
[0007] In addition, each element in the application documents may be denoted by a reference numeral in parentheses. In this case, the reference numeral is merely an example of the correspondence between the element and the specific configuration described in the embodiments below. Therefore, the present invention is not limited in any way by the notation of the reference numeral. [Brief explanation of the drawing]
[0008] [Figure 1] This is a side cross-sectional view showing a schematic configuration of a semiconductor device according to an exemplary embodiment of the present invention. [Figure 2] Figure 1 is a plan view showing a schematic of the in-plane shape of each part constituting the semiconductor device shown. [Figure 3] This is a side cross-sectional view showing an enlarged schematic of the semiconductor device in the thickness direction as shown in Figure 1. [Figure 4] Figure 3 is a plan view showing the schematic in-plane shape of the Ni plating layer and passivation film in the semiconductor device shown. [Figure 5] Figure 3 is a graph showing the results of computer simulations of the stress state when using Si substrates of various thicknesses as semiconductor substrates. [Figure 6] It is a graph showing the result of computer simulation of the stress state when SiC substrates with various thicknesses are used as the semiconductor substrate shown in FIG. 3. [Figure 7] It is a graph showing the relationship between the columnar crystal layer ratio and the crack generation rate in the Ni plating layer shown in FIG. 3. [Figure 8] It is a graph showing the relationship between the radius of curvature at the corner of the partition wall shown in FIG. 4, the thickness of the semiconductor substrate shown in FIG. 3, the columnar crystal layer ratio in the Ni plating layer, and the crack generation state. [Figure 9] It is a graph showing the relationship between the radius of curvature at the corner of the partition wall shown in FIG. 4, the thickness of the semiconductor substrate shown in FIG. 3, the columnar crystal layer ratio in the Ni plating layer, and the crack generation state. [Figure 10] It is a plan view showing a schematic in-plane shape according to a modified example of the Ni plating layer and the passivation film in the semiconductor element shown in FIG. 3. [Figure 11] It is a plan view showing a schematic in-plane shape according to another modified example of the Ni plating layer and the passivation film in the semiconductor element shown in FIG. 3. [Figure 12] It is a side sectional view showing an enlarged schematic configuration according to a modified example of the semiconductor element shown in FIG. 3.
Mode for Carrying Out the Invention
[0009] (First Embodiment) Hereinafter, embodiments of the present invention will be described based on the drawings. Note that various modifications applicable to a single embodiment may be impeded in the middle of a series of descriptions relating to that embodiment if they are inserted into the description. Therefore, modifications will not be inserted in the middle of a series of descriptions relating to that embodiment, but will be described collectively afterward. Furthermore, the descriptions in each drawing, and the corresponding descriptions of the device configurations, functions, or operations described below, are simplified for the purpose of concisely explaining the content of the present invention and do not limit the content of the present invention in any way. Therefore, it goes without saying that the exemplary configurations shown in each drawing do not necessarily correspond to the specific configurations actually manufactured and sold. In other words, unless explicitly limited by the applicant in the application history, the present invention should not be interpreted restrictively by the descriptions in each drawing, or the corresponding descriptions of the device configurations, functions, or operations described below.
[0010] (composition) First, the schematic configuration of the semiconductor device 1 according to this embodiment will be described with reference to Figures 1 and 2. Figure 1 corresponds to the II cross-sectional view in Figure 2. For the sake of explanation, as shown in the figure, a right-handed XYZ Cartesian coordinate system is set up such that the Z axis is parallel to the thickness direction of the semiconductor device 1 and each layer constituting it. That is, in the following explanation, "thickness direction" refers to the Z axis direction in the figure. Any direction perpendicular to the thickness direction will be called the "in-plane direction". The "in-plane direction" is the direction parallel to the XY plane in the figure. Furthermore, viewing the semiconductor device 1 and its components from above in Figure 1 with a line of sight opposite to the Z axis will be called a "plan view". That is, the shape of a certain component in a "plan view" corresponds to the shape when that component is mapped onto the XY plane in the figure. The shape in a plan view, that is, the shape in the in-plane direction, will be called the "in-plane shape". The "in-plane shape" corresponds to the shape in the plan view.
[0011] The semiconductor device 1 is mounted on a printed circuit board (not shown) by soldering to constitute an electronic device (not shown). As shown in Figure 1, the semiconductor device 1 comprises a semiconductor element 2, a lead frame 3, bonding wires 4, clips 5, a first solder layer 6, a second solder layer 7, a third solder layer 8, and a molding resin 9. The semiconductor element 2, lead frame 3, bonding wires 4, clips 5, the first solder layer 6, the second solder layer 7, and the third solder layer 8 are covered, or sealed, by a molding resin 9 made of an electrically insulating synthetic resin such as epoxy resin. The configuration of each part of the semiconductor device 1 according to this embodiment will be described in detail below.
[0012] In this embodiment, the semiconductor device 1 is a so-called power device and comprises a semiconductor element 2 having at least a component that functions as a MOSFET, which is a power semiconductor. As shown in Figure 2, the semiconductor element 2 is formed in a substantially rectangular shape in plan view. The bottom surface 21 of the semiconductor element 2, which is perpendicular to the thickness direction, is joined to the element mounting portion 31 of the lead frame 3 via a first solder layer 6 having a melting point of 290°C or higher. That is, the semiconductor element 2 is electrically connected to the element mounting portion 31 of the lead frame 3 via the first solder layer 6. On the other hand, the top surface 22 of the semiconductor element 2, which is perpendicular to the thickness direction, is joined to the clip 5 via a second solder layer 7 having a melting point of 290°C or higher. That is, the semiconductor element 2 is electrically connected to the clip 5 via the second solder layer 7.
[0013] The lead frame 3 is formed from a good conductive metal plate such as copper. The lead frame 3 has an element mounting section 31 and lead sections 32. Multiple lead sections 32 are provided around the element mounting section 31, also called a die pad. The source terminal section 33 of the multiple lead sections 32 is joined to the clip 5 via a third solder layer 8 having a melting point of 290°C or higher. That is, the source terminal section 33 is electrically connected to the clip 5 via the third solder layer 8. The gate terminal section 34 of the multiple lead sections 32 is electrically connected to a control electrode 232, described later, provided on the upper surface 22 of the semiconductor element 2, via a bonding wire 4.
[0014] Clip 5 is formed seamlessly and integrally from a good conductive metal plate such as copper. Clip 5 has an element-facing portion 51, a lead frame-facing portion 52, and a connecting portion 53. The element-facing portion 51, the lead frame-facing portion 52, and the connecting portion 53 are each formed in a flat, plate-like shape. The element-facing portion 51 is joined to the second solder layer 7. The lead frame-facing portion 52 is joined to the third solder layer 8. The element-facing portion 51 and the lead frame-facing portion 52 are provided parallel to each other. The lead frame-facing portion 52 is provided at a position offset from the element-facing portion 51 in the thickness direction, i.e., in the negative Z-axis direction in the figure. The connecting portion 53 is provided between the element-facing portion 51 and the lead frame-facing portion 52. In other words, Clip 5 is formed by bending at the boundary between the element-facing portion 51 and the connecting portion 53, and by bending at the boundary between the lead frame-facing portion 52 and the connecting portion 53.
[0015] As described above, the overall configuration of the semiconductor device 1 using the lead frame 3 and clip 5 is already well known at the time of filing this application. Therefore, further details regarding the configuration of the lead frame 3 and clip 5 will be omitted. The main components of the present invention will be described below with reference to Figures 3 and 4 in addition to Figures 1 and 2. Figure 3 corresponds to the III-III cross-sectional view in Figure 4.
[0016] As shown in Figure 3, the semiconductor element 2 comprises a semiconductor substrate 201, an underlay metal layer 202, a Ni plating layer 203, and a passivation film 204. The semiconductor substrate 201 is a thin plate-shaped member made of a silicon-based semiconductor material such as Si, SiC, or SiN, on which circuit elements such as MOSFETs are formed. Note that such circuit elements are not shown in Figure 3. The underlay metal layer 202 is provided on the semiconductor substrate 201 and is made of aluminum or an aluminum alloy. As the aluminum alloy constituting the underlay metal layer 202, for example, AlSi, AlCu, AlSiCu, etc., can be used. The Ni plating layer 203 and the passivation film 204 are provided on the underlay metal layer 202. The Ni plating layer 203 is a low-phosphorus Ni plating film with a phosphorus concentration of 4% by weight or less, and is formed in a substantially rectangular shape in a plan view that is slightly smaller than the in-plane shape of the semiconductor element 2. That is, the passivation film 204 is provided around the Ni plating layer 203. The passivation film 204 is formed of an insulating material such as polyimide resin. The first interlayer interface 205, which is the bonding interface between the semiconductor substrate 201 and the underlying metal layer 202, is formed flat along the in-plane direction. The second interlayer interface 206, which is the bonding interface between the underlying metal layer 202, the Ni plating layer 203, and the passivation film 204, is formed flat along the in-plane direction.
[0017] As shown in Figure 3, the Ni plating layer 203 has a columnar crystalline layer 207. The columnar crystalline layer 207, which is formed in the initial stages of deposition of the Ni plating layer 203, is located on the lower layer side of the Ni plating layer 203, i.e., on the second interlayer interface 206 side. In this embodiment, the Ni plating layer 203 is formed such that the ratio of the thickness of the columnar crystalline layer 207 to the overall layer thickness is 50% or less.
[0018] As shown in Figure 2, the upper surface 22 of the semiconductor element 2 is provided with a current-carrying electrode 231 and a control electrode 232. The current-carrying electrode 231 and the control electrode 232 are formed from a Ni plating layer 203. In this embodiment, the current-carrying electrode 231, which corresponds to the first electrode, and the control electrode 232, which corresponds to the second electrode, are arranged in the in-plane direction. Specifically, as shown in Figure 4, the control electrode 232 is provided in a relatively small area at one corner (i.e., the lower right corner in the figure) of the roughly rectangular in-plane shape of the Ni plating layer 203. In contrast, the current-carrying electrode 231 occupies the portion of the roughly rectangular in-plane shape of the Ni plating layer 203 other than the control electrode 232. The current-carrying electrode 231 is provided in a relatively large area so as to occupy most of the roughly rectangular in-plane shape of the Ni plating layer 203.
[0019] The passivation membrane 204 has a side wall portion 241 and a partition wall portion 242. The side wall portion 241 is provided so as to surround the periphery, i.e., the outside, of the current-carrying electrode 231 and the control electrode 232. The partition wall portion 242 is provided between the current-carrying electrode 231 and the control electrode 232 so as to divide the current-carrying electrode 231 and the control electrode 232. In this embodiment, the partition wall portion 242 has a convex shape toward the current-carrying electrode 231. That is, in a plan view, the partition wall portion 242 is formed in a substantially L-shape that opens toward the control electrode 232. In this way, the current-carrying electrode 231, the control electrode 232 and the partition wall portion 242 are arranged inside the side wall portion 241, which is formed in a substantially rectangular cylindrical shape. The side wall portion 241 and the partition wall portion 242 are formed in a wall shape that is erected substantially vertically from the second interlayer interface 206 along the positive Z-axis direction in the figure. In other words, the inner and outer wall surfaces of the side wall portion 241 and the partition wall portion 242, along the thickness direction, are provided approximately parallel to the YZ plane in the figure. The side wall portion 241 and the partition wall portion 242 are formed integrally from the same material without any seams.
[0020] The partition wall portion 242 has a protruding portion 243. The protruding portion 243 is the corner of the partition wall portion 242 closest to the center position of the current-carrying electrode 231 in the in-plane direction, and is convex toward the center in the in-plane direction of the current-carrying electrode 231. In plan view, the protruding portion 243 is formed in a rounded shape, specifically an R shape. Specifically, in this embodiment, the protruding portion 243 is formed such that the radius of curvature of the R shape is 30 μm or more.
[0021] (effect) The effects achieved by the configuration of this embodiment will be described below with reference to the drawings.
[0022] As described in Patent Document 1, a configuration in which a circuit and a semiconductor module (e.g., a power module) are mounted integrally on a printed circuit board enables cost reduction and miniaturization of electronic devices. Here, electrodes for current flow, such as drain terminals and source terminals, need to be formed over the largest possible area to allow relatively large currents to flow. Furthermore, by employing clip mounting, parasitic resistance is eliminated, resulting in low on-resistance. To realize such a configuration, it is necessary to use solder with a higher melting point than the solder used for printed circuit board mounting in the semiconductor device 1, and to increase the source area. If the melting point of such high-melting-point solder is, for example, 290°C or higher, a processing temperature of around 390°C is required in the mounting process. Here, the semiconductor element 2 as a semiconductor module is plated with Ni for solder bonding. In this regard, conventional medium-phosphorus Ni plating has the problem that cracks occur in the Ni plating due to thermal stress during reflow of high-melting-point solder.
[0023] Furthermore, as described in Patent Document 1, current-carrying electrodes such as source electrodes and control electrodes such as gate electrodes may be provided on the same plane. In such a configuration, in order to reduce the area of the element while maximizing the area of the current-carrying electrodes, it is necessary to house both electrodes within a single rectangle in a plan view, while forming the control electrode in a small area at one corner of that rectangle. At this time, from the viewpoint of insulation and electrode protection, it is preferable to provide a convex-shaped wall that separates the two electrodes. However, this convex shape causes stress concentration, which makes the Ni plating more prone to cracking.
[0024] In this regard, the inventors of the present invention focused on the following facts. As is clear from the NI-P binary phase diagram shown in Figure 2 of Japanese Patent Publication No. 6918209, in so-called low-phosphorus Ni plating with a phosphorus concentration of 4% by weight or less, the phase transition temperature at which the film stress changes is high. Also, as shown in Figure 3, columnar crystalline layers 207 are formed in the initial stages of Ni plating layer 203 deposition. Such columnar crystalline layers 207 become defects in the film. Therefore, as shown in Figures 3 and 4, in this embodiment, the ratio of the thickness of the columnar crystalline layer 207 to the thickness of the Ni plating layer 203 is set to 50% or less. Furthermore, the protruding portion 243 of the partition wall portion 242 that separates the current-carrying electrode 231 and the control electrode 232 and protrudes towards the current-carrying electrode 231 is formed in a rounded shape in plan view. Specifically, the protruding portion 243 is formed in an R shape in plan view. This makes it possible to effectively suppress crack formation in the Ni plating layer 203 provided on the semiconductor element 2.
[0025] Furthermore, regarding the preferred value of the planar shape, i.e., the radius of curvature, of the protruding portion 243, it is necessary to consider the variety of chip sizes and other factors, as well as variations during manufacturing. Specifically, for example, the thickness of the semiconductor substrate 201 may be around 70 μm or less, or it may be between 70 μm and 160 μm. Below, we will examine the specifications of the semiconductor element 2, such as the material and thickness of the semiconductor substrate 201 and the radius of curvature of the protruding portion 243 in the partition wall portion 242.
[0026] Figure 5 shows the relationship between the plate thickness, the radius of curvature of the protruding portion 243, and the stress acting on the Ni plating layer 203 when a Si substrate is used as the semiconductor substrate 201. Figure 6 shows the relationship between the plate thickness, the radius of curvature of the protruding portion 243, and the stress acting on the Ni plating layer 203 when a SiC substrate is used as the semiconductor substrate 201. The curves in the figures, from bottom to top, show the cases where the plate thickness is 50 μm, 70 μm, 140 μm, and 725 μm. The plating thickness, i.e., the film thickness of the Ni plating layer 203, was assumed to be 3 μm. The horizontal dashed line in the figure shows the calculated stress of 1259 MPa when a crack occurs with a plate thickness of 80 μm, a plating thickness of 4 μm, a radius of curvature of 22 μm, and a reflow temperature of 390°C. As shown in Figures 5 and 6, the larger the radius of curvature, the smaller the stress and the less likely crack is to occur. Specifically, for example, changing the radius of curvature from 20 μm to 60 μm reduces the generated stress by approximately 0.67 times. Furthermore, for the same radius of curvature, a smaller plate thickness results in lower stress and makes crack formation less likely. Specifically, for example, changing the plate thickness from 70 μm to 140 μm increases the generated stress by approximately 1.1 times. And, under the conditions below the dashed line in Figures 5 and 6, the generated stress is lower than that at which cracks occur.
[0027] However, various variations such as processing tolerances may occur during the actual manufacturing of the product. Therefore, it is necessary to take a margin that takes such variations into account. Specifically, for example, if the radius of curvature is 30 μm or more for a plate thickness of 70 μm, and 60 μm or more for a plate thickness of 140 μm, it is possible to take a sufficient margin that takes variations into account. In particular, for both SiC substrates and Si substrates, if the radius of curvature is 60 μm or more, the maximum stress will be less than 1000 MPa regardless of the plate thickness, and will not exceed the fracture stress. Furthermore, to take an even larger margin, for example, if we consider the case of a plate thickness of 70 μm, the variation in generated stress with respect to variations in plate thickness, plating thickness, and radius of curvature will be approximately ±5% each. Even if we consider a variation of 10% each, taking into account product development such as changes in chip size, and considering that stable manufacturing is possible, the radius of curvature that does not exceed 1259 MPa will be approximately 60 μm (i.e., see the X mark, which is the intersection with the horizontal dashed line in the figure). Similarly, for a plate thickness of 140 μm, the radius of curvature that does not exceed 1259 MPa is approximately 85 μm. In contrast, for medium phosphorus Ni plating, a plate thickness of 122 μm and a reflow temperature of 290°C require a radius of curvature of 94 μm or more. Similarly, for SiC substrates, for a plate thickness of 70 μm, the radius of curvature that does not exceed 1259 MPa is approximately 75 μm.
[0028] Figure 7 shows the results of evaluating the crack occurrence rate when the columnar crystal layer ratio is varied, using a Si substrate with a thickness of 70 μm as the semiconductor substrate 201 and a radius of curvature of 20 μm. The columnar crystal layer ratio is the ratio of the maximum thickness of the columnar crystal layer 207 to the thickness of the Ni plating layer 203. "Maximum thickness" is the maximum value obtained when the thickness is measured at multiple points in the in-plane direction. As shown in Figure 7, crack occurrence can be effectively suppressed by setting the columnar crystal layer ratio to 50% or less.
[0029] Figure 8 shows the results of evaluating the crack initiation state when a Si substrate was used as the semiconductor substrate 201, with a radius of curvature of 20 μm, and the plate thickness and columnar crystal layer ratio were varied. In the figure, circles indicate no crack initiation, and X marks indicate crack initiation. As shown in Figure 8, crack initiation can be effectively suppressed by setting the plate thickness to 70 μm or less and the columnar crystal layer ratio to 50% or less.
[0030] Figure 9 shows the results of evaluating the crack initiation state when a Si substrate was used as the semiconductor substrate 201, with a radius of curvature of 60 μm, and the plate thickness and columnar crystal layer ratio were varied. As shown in Figure 9, crack initiation can be effectively suppressed by setting the plate thickness to 725 μm or less and the columnar crystal layer ratio to 50% or less.
[0031] Considering the above findings comprehensively, when the semiconductor element 2 is formed from a semiconductor substrate 201 with a thickness of 70 μm or less (for example, 70-50 μm or 70-25 μm), it is preferable to have a columnar crystal layer ratio of 50% or less and a radius of curvature of 30 μm or more. Furthermore, when the semiconductor element 2 is formed from a semiconductor substrate 201 with a thickness of 160 μm or less (for example, 160-100 μm or 160-75 μm), it is preferable to have a columnar crystal layer ratio of 50% or less and a radius of curvature of 60 μm or more. This allows for better suppression of crack generation in the Ni plating layer 203 up to a higher temperature range than conventional methods, i.e., 390°C. In addition, even if the radius of curvature is reduced in the conventional temperature range, i.e., 290°C, crack generation in the Ni plating layer 203 can be well suppressed. Note that a columnar crystal layer ratio of 50% or less can be achieved by appropriately adjusting the plating conditions. In this regard, regarding the fact that the crystalline state in electroless Ni plating can be altered by complexing agents, trace amounts of additives, etc., please refer to the following reference, for example: Kamei, Masaru et al., "Influence of copper foil type, Ni plating crystal structure, and film thickness on the bending resistance of electroless Ni-P plated copper wiring," Abstracts of MES2016 (26th Microelectronics Symposium), September 2016, pp. 63-66. Furthermore, such plating conditions can be successfully set without excessive trial and error, for example, by simple and few trials using L8 orthogonal arrays or L12 orthogonal arrays in experimental design.
[0032] Furthermore, it is preferable that the step difference at the first interlayer interface 205 and the second interlayer interface 206 is small, at least at positions corresponding to the partition wall portion 242, i.e., the protruding portion 243, in the in-plane direction. This allows for good suppression of crack generation caused by stress concentration. Specifically, for example, it is preferable that the first interlayer interface 205 is flattened so that the step difference is 0.2 μm or less. Alternatively, for example, it is preferable that the second interlayer interface 206 is flattened so that the step difference is 10% or less of the thickness of the underlying metal layer 202. Such flattening can be achieved, for example, by using BPSG reflow technology, chemical mechanical polishing, or aluminum reflow technology. BPSG is an abbreviation for Boron Phosphorus Silicon Glass.
[0033] (Second embodiment) The second embodiment will be described below with reference to Figure 10. The following description of the second embodiment will primarily focus on the differences from the first embodiment. Parts that are identical or equivalent in the first and second embodiments are denoted by the same reference numerals. Therefore, in the following description of the second embodiment, the explanation in the first embodiment can be appropriately applied to components having the same reference numerals as those in the first embodiment, unless there is a technical inconsistency or additional explanation required. The same applies to other embodiments described later.
[0034] As shown in Figure 10, the semiconductor element 2 has an additional electrode 280 in addition to the current-carrying electrode 231 and the control electrode 232. Furthermore, the passivation film 204, which is seamlessly formed from an insulating material such as polyimide resin, has an additional partition wall portion 281 in addition to the side wall portion 241 and the partition wall portion 242. The current-carrying electrode 231 and the additional electrode 280 are separated by the additional partition wall portion 281. That is, in this embodiment, the current-carrying electrode 231 in the first embodiment is divided into two by the additional partition wall portion 281. In this embodiment, the additional partition wall portion 281 is provided along the X-axis direction in the figure. The additional partition wall portion 281 has a protrusion 282. In a plan view, the protrusion 282 is projected toward the current-carrying electrode 231 (i.e., in the negative Y-axis direction in the figure). In a plan view, a temperature sensor or the like may be provided at the position corresponding to the protrusion 282. The corners of the protrusion 282 are formed in an R shape with a predetermined radius of curvature in a plan view. With this configuration, the occurrence of cracks in the current-carrying electrode 231 at the locations where the partition wall 242 and the protrusion 282 are provided can be effectively suppressed.
[0035] (Third embodiment) The third embodiment will now be described with reference to Figure 11. In this embodiment, a plurality of terminal electrodes 283 are provided at the corners of the semiconductor element 2 in the in-plane direction. The terminal electrodes 283 are formed of a Ni plating layer 203, similar to the current-carrying electrodes 231 in the first embodiment and the like. In a plan view, the terminal electrodes 283 are formed in a substantially rectangular shape with recesses 284 at the corners that open toward the center of the semiconductor element 2. In a plan view, the recesses 284 are formed in an R shape with a predetermined radius of curvature.
[0036] Between the multiple terminal electrodes 283, a partition wall portion 242 is provided, which is roughly cross-shaped in plan view. The partition wall portion 242 has a projection portion 285. The projection portion 285 is positioned to correspond to the recess 284 in the terminal electrode 283. Furthermore, the projection portion 285 is provided so as to be in close contact with the recess 284 without any gaps in plan view. That is, the projection portion 285 is formed in an R shape with a predetermined radius of curvature corresponding to the radius of curvature of the recess 284 in plan view. With this configuration, the occurrence of cracks in the terminal electrode 283 at the location where the recess 284 is provided can be effectively suppressed.
[0037] (Fourth embodiment) The fourth embodiment will now be described with reference to Figure 12. This embodiment shows a case in which the semiconductor substrate 201 in the first embodiment and the like has a so-called trench gate structure. Such a trench gate structure is already publicly known or well known at the time of filing this application. The configuration of the semiconductor substrate 201 shown in Figure 12 is disclosed in Japanese Patent Application Publication No. 2022-7762, which is a prior application of the applicant of this application.
[0038] Specifically, referring to Figure 12, a source layer 2902 is formed on the surface of the channel layer 2901. A contact trench 2903 is formed in the semiconductor substrate 201 so as to penetrate the source layer 2902 and reach the channel layer 2901. As a result, the channel layer 2901 is exposed at the bottom surface of the contact trench 2903. In the portion of the channel layer 2901 exposed from the contact trench 2903, a first contact region 2904, which is a p+ type contact region for the channel layer that will become a contact, is formed. In the portion of the source layer 2902 exposed from the side of the contact trench 2903, a second contact region 2905, which is an n+ type contact region for the source layer that will become a contact, is formed.
[0039] Multiple trenches 2906 are formed in the semiconductor substrate 201 between the channel layer 2901 and the source layer 2902. Each trench 2906 is formed in a stripe pattern at equal intervals along one in-plane direction (i.e., the Y-axis direction in the figure) on one surface of the semiconductor substrate 201. The trenches 2906 are also provided so as to penetrate the channel layer 2901 in the thickness direction and reach a drift layer (not shown). The inside of each trench 2906 is filled with a gate insulating film 2907 formed to cover the wall surface of each trench 2906, and a gate element 2908 made of polysilicon or the like formed on top of this gate insulating film 2907. This constitutes a trench gate structure.
[0040] An interlayer insulating film 2909 is formed on one surface of the semiconductor substrate 201 on the channel layer 2901 side. A contact hole 2910 communicating with a contact trench 2903 is formed in the interlayer insulating film 2909. Embedded portions 2911, which are connected to the first contact region 2904 and the second contact region 2905, are arranged in the contact hole 2910 and the contact trench 2903. The embedded portions 2911 are made of tungsten plugs or the like.
[0041] A barrier metal layer 2912 is provided between the embedded portion 2911 and the base metal layer 202. The barrier metal layer 2912 is composed of, for example, titanium nitride and titanium laminated together. The first interlayer interface 205 is formed by the lower surface of the barrier metal layer 2912. The second interlayer interface 206 is formed by the upper surface of the base metal layer 202. A Pd layer 2913 and an Au layer 2914 are laminated on the Ni plating layer 203 in that order.
[0042] In this configuration, similar to the first embodiment described above, it is preferable to reduce the step difference at the first interlayer interface 205 and the second interlayer interface 206 at least at positions corresponding to the partition wall portion 242 (i.e., the protruding portion 243 and the projection portion 285) and the additional partition wall portion 281 (i.e., the convex portion 282). Specifically, for example, it is preferable to make the step difference at the first interlayer interface 205 less than or equal to the thickness of the barrier metal layer 2912, i.e., 0.2 μm or less. This effectively suppresses the occurrence of cracks in the Ni plating layer 203 due to stress concentration.
[0043] (modified version) The present invention is not limited to the embodiments described above. Therefore, the embodiments can be modified as appropriate. Representative modifications are described below. In the following description of modifications, the differences from the embodiments will be mainly described. In addition, parts that are the same or equivalent to each other in the embodiments and modifications are denoted by the same reference numerals. Therefore, in the following description of modifications, with respect to components that have the same reference numerals as in the embodiments, the descriptions in the embodiments can be appropriately applied unless there is a technical inconsistency or additional explanation is required.
[0044] The present invention is not limited to the specific device configurations described in the above embodiments. That is, as stated above, the descriptions of the above embodiments have been simplified in order to briefly explain the content of the present invention. For this reason, components that are usually provided in products actually manufactured and sold, such as casings, joining materials, terminals, and wiring, are appropriately omitted from the illustrations and descriptions in the above embodiments and corresponding drawings.
[0045] The present invention is suitably applicable to semiconductor devices 1 of various package types, such as SOP, QFP, SON, and QFN. SOP is an abbreviation for Small Outline Package. QFP is an abbreviation for Quad Flat Package. SON is an abbreviation for Small Outline Non-Leaded Package. QFN is an abbreviation for Quad Flat Non-Leaded Package.
[0046] The semiconductor device 2 may have an IGBT configuration or an RC-IGBT configuration that integrates an IGBT and a diode. RC stands for Reverse-Conducting.
[0047] As shown in Figure 12, the wall surface of the passivation film 204 along the thickness direction may be provided as an inclined surface that is tilted with respect to the Z-axis in the figure.
[0048] Referring to Figure 10, the additional partition wall 281 may be provided along the Y-axis direction in the figure. Also, the protrusion 282 may project toward the additional electrode 280 in a plan view. Alternatively, the protrusion 282 may project toward the current-carrying electrode 231 and the additional electrode 280 in a plan view.
[0049] In the above description, multiple components that were formed as a single, seamless unit may be formed by bonding together separate components. Similarly, multiple components that were formed by bonding together separate components may be formed as a single, seamless unit. Furthermore, in the above description, multiple components that were formed from the same material may be formed from different materials. Similarly, multiple components that were formed from different materials may be formed from the same material.
[0050] It goes without saying that the elements constituting the above embodiments are not necessarily essential unless explicitly stated as particularly essential or considered fundamentally essential. Furthermore, when numerical values such as the number, quantity, dimensions, or range of components are mentioned, the present invention is not limited to those specific numerical values unless explicitly stated as particularly essential or considered fundamentally limited to those specific numerical values. Similarly, when the shape, direction, positional relationship, etc., of components are mentioned, the present invention is not limited to those shape, direction, positional relationship, etc., unless explicitly stated as particularly essential or considered fundamentally limited to those specific shape, direction, positional relationship, etc.
[0051] Modifications are not limited to the examples given above. For example, multiple embodiments can be combined with each other as long as they do not conflict technically. That is, a part of one embodiment can be combined with a part of another embodiment as long as they do not conflict technically. Also, any one of the multiple embodiments can be combined with any one of the multiple modifications as long as they do not conflict technically. Similarly, one of the multiple modifications can be combined with another as long as they do not conflict technically.
[0052] (Disclosure details) As is evident from the above description of embodiments and modifications, this specification discloses at least the following aspects: <Perspective 1> The semiconductor device (1) is A semiconductor substrate (201) constituting the semiconductor device (2), A first electrode (231) is provided on one surface (22) of the semiconductor device and is formed of a Ni plating layer, A second electrode (232) is provided on one surface of the semiconductor element and is formed of a Ni plating layer, A partition wall portion (242;281) is provided on one surface of the semiconductor element to separate the first electrode and the second electrode, Equipped with, The phosphorus concentration in the Ni plating layer constituting the first electrode and the second electrode is 4% by weight or less. The partition wall portion has a convex shape toward the first electrode or the second electrode. <Perspective 2> From perspective 1, The semiconductor element is electrically connected to other components via solder layers (6, 7). The solder layer has a melting point of 290°C or higher. <perspective 3> From perspective 2, The other components are a lead frame (3) and / or a clip (5) fixed to the lead frame. <Perspective 4> From perspectives 1 to 3, The semiconductor element is formed from the semiconductor substrate with a thickness of 70 μm or less. The Ni plating layer constituting the first electrode or the second electrode is formed such that the ratio of the thickness of the columnar crystal layer (207) to the total layer thickness is 50% or less. The partition wall portion is formed such that the radius of curvature of the convex shape is 30 μm or more. <Perspective 5> From perspectives 1 to 3, The semiconductor element is formed from the semiconductor substrate with a thickness of 160 μm or less. The Ni plating layer constituting the first electrode or the second electrode is formed such that the ratio of the thickness of the columnar crystal layer (207) to the total layer thickness is 50% or less. The partition wall portion is formed such that the radius of curvature of the convex shape is 60 μm or more. <Perspective 6> In perspectives 1-5, The interlayer interface (205) formed between the Ni plating layer constituting the first electrode or the second electrode and the semiconductor substrate is flattened so that the step difference is 0.2 μm or less at least the position corresponding to the partition wall. <Perspective 7> In perspectives 1-6, The partition wall portion is formed of an insulating film such as polyimide resin. [Explanation of symbols]
[0053] 1 Semiconductor device 2 Semiconductor elements 22 Top side 201 Semiconductor substrate 203 Ni plating layer 231 Current-carrying electrode (first electrode) 232 Control electrode (second electrode) 204 Passivation membrane 241 Side wall section 242 Bulkhead
Claims
1. Semiconductor device (1), A semiconductor substrate (201) constituting the semiconductor element (2), A first electrode (231) is provided on one surface (22) of the semiconductor element and is formed of a Ni plating layer, A second electrode (232) is provided on one surface of the semiconductor element and is formed of a Ni plating layer, A partition wall portion (242; 281) is provided on one surface of the semiconductor element to separate the first electrode and the second electrode, Equipped with, The semiconductor element is formed from the semiconductor substrate with a thickness of 70 μm or less. The phosphorus concentration in the Ni plating layer constituting the first electrode and the second electrode is 4% by weight or less. The Ni plating layer constituting the first electrode or the second electrode is formed such that the ratio of the thickness of the columnar crystal layer (207) to the total layer thickness is 50% or less. The partition wall portion has a convex shape toward the first electrode or the second electrode, and is formed such that the radius of curvature of the convex shape is 30 μm or more. Semiconductor equipment.
2. A semiconductor device (1), A semiconductor substrate (201) constituting the semiconductor element (2), A first electrode (231) is provided on one surface (22) of the semiconductor element and is formed of a Ni plating layer, A second electrode (232) is provided on one surface of the semiconductor element and is formed of a Ni plating layer, A partition wall portion (242; 281) is provided on one surface of the semiconductor element to separate the first electrode and the second electrode, Equipped with, The semiconductor element is formed from the semiconductor substrate with a thickness of 160 μm or less. The phosphorus concentration in the Ni plating layer constituting the first electrode and the second electrode is 4% by weight or less. The Ni plating layer constituting the first electrode or the second electrode is formed such that the ratio of the thickness of the columnar crystal layer (207) to the total layer thickness is 50% or less. The partition wall portion has a convex shape toward the first electrode or the second electrode, and is formed such that the radius of curvature of the convex shape is 60 μm or more. Semiconductor equipment.
3. The aforementioned semiconductor element is electrically connected to other components via solder layers (6, 7). The aforementioned solder layer has a melting point of 290°C or higher. The semiconductor device according to claim 1 or 2.
4. The other components are a lead frame (3) and / or a clip (5) fixed to the lead frame. The semiconductor device according to claim 3.
5. The interlayer interface (205) formed between the Ni plating layer constituting the first electrode or the second electrode and the semiconductor substrate is flattened so that the step difference is 0.2 μm or less at least the position corresponding to the partition wall. The semiconductor device according to claim 1 or 2.
6. The partition wall portion is formed of an insulating film. The semiconductor device according to claim 1 or 2.
7. The insulating film is formed of polyimide resin. The semiconductor device according to claim 6.