Method for manufacturing epitaxial growth substrates and semiconductor devices

Abstract

To provide an epitaxial growth substrate capable of suppressing the occurrence of cracks on a semiconductor layer when separating a substrate from the semiconductor layer.SOLUTION: An epitaxial growth substrate includes: a substrate made of a group III-V compound semiconductor containing Ga or In as a group III element; a sacrificial layer epitaxially grown on the substrate; and a semiconductor layer epitaxially grown on the sacrificial layer. The sacrificial layer includes a layer consisting of a mixed crystal semiconductor containing Al or In as the group III element. The composition ratio of Al or In varies in a thickness direction. A portion where the composition ratio of Al or In exhibits a maximum value is located on the interior of the sacrificial layer, excluding the upper and lower surfaces.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a method for manufacturing epitaxial growth substrates and semiconductor devices. [Background technology]

[0002] A technique is known in which a sacrificial layer of AlGaAs or AlAs is epitaxially grown on a substrate such as GaAs, a semiconductor layer is epitaxially grown on top of the sacrificial layer, and then the sacrificial layer is etched to separate the semiconductor layer from the substrate (Patent Documents 1 and 2). When etching the sacrificial layer, a groove is formed that extends from the semiconductor layer to the bottom surface of the sacrificial layer. After forming the groove, the sacrificial layer is etched from the side of the groove. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 2658493 [Patent Document 2] Patent No. 5394091 [Overview of the project] [Problems that the invention aims to solve]

[0004] Etching of the sacrificial layer proceeds laterally from the exposed edge in the groove. Due to the crystal plane orientation dependence of the etching rate, the portion of the sacrificial layer in contact with the semiconductor layer may be etched faster than the portion in contact with the substrate. When etching proceeds under these conditions, the sacrificial layer and the semiconductor layer become connected in a minute area, while the sacrificial layer and the substrate become connected in a relatively wider area. If the substrate and sacrificial layer detach from the semiconductor layer while the sacrificial layer and semiconductor layer are connected in a minute area, cracks or other damage may occur in the semiconductor layer.

[0005] An object of the present invention is to provide an epitaxial growth substrate capable of suppressing the occurrence of cracks in the semiconductor layer when separating the substrate from the semiconductor layer. Another object of the present invention is to provide a method for manufacturing a semiconductor device using this epitaxial growth substrate. [Means for solving the problem]

[0006] According to one aspect of the present invention, A substrate made of a group III-V compound semiconductor containing Ga or In as a group III element, A sacrificial layer epitaxially grown on the aforementioned substrate, A semiconductor layer epitaxially grown on the aforementioned sacrificial layer and Equipped with, The sacrificial layer includes a layer made of a mixed crystal semiconductor containing Al or In as a group III element, the composition ratio of Al or In changes in the thickness direction, and the location where the composition ratio of Al or In shows a maximum value is located inside the sacrificial layer, other than the bottom and top surfaces. death, The layer made of the mixed crystal semiconductor contained in the sacrificial layer contains Ga in addition to Al or In as a group III element, and at least one of As and P as a group V element, and the maximum composition ratio of Al or In is 0.5 or more. An epitaxial growth substrate is provided.

[0007] According to another aspect of the present invention, A semiconductor element, at least one of a transistor and a diode, is formed on the semiconductor layer of the epitaxial growth substrate described above. A method for manufacturing a semiconductor device is provided, which involves etching away the sacrificial layer to separate the substrate from the semiconductor layer. [Effects of the Invention]

[0008] At locations where the composition ratio of Al or In in the sacrificial layer is at its maximum, the etching rate against acidic or alkaline etchants becomes relatively higher. Therefore, when the sacrificial layer is etched, etching proceeds relatively quickly in areas other than the bottom and top surfaces of the sacrificial layer, and the substrate-side portion and the semiconductor layer-side portion are separated at these areas. Because the separation occurs at locations away from the surface of the semiconductor layer, cracks are less likely to occur within the semiconductor layer during separation. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1A is a cross-sectional view of an epitaxial growth substrate according to the first embodiment, and Figure 1B is a graph showing an example of the etching rate distribution of each layer of the epitaxial growth substrate. [Figure 2] Figures 2A, 2B, and 2C are cross-sectional views of the epitaxial growth substrate, temporary substrate, and adhesive layer at an intermediate stage in the procedure for separating the semiconductor layer of the epitaxial growth substrate from the substrate according to the first embodiment. [Figure 3] Figures 3A and 3C are cross-sectional views of the epitaxial growth substrate, temporary substrate, and adhesive layer at an intermediate stage in the procedure for separating the semiconductor layer of the epitaxial growth substrate from the substrate according to the first embodiment. Figure 3B is a plan view showing the positional relationship of the substrate, semiconductor layer, and sacrificial layer at the intermediate stage shown in Figure 3A. Figure 3D is a cross-sectional view of the semiconductor layer, temporary substrate, and adhesive layer after the substrate has been separated. [Figure 4] Figures 4A and 4B show the procedure for separating the substrate from the semiconductor layer in an epitaxial growth substrate according to a comparative example. [Figure 5] Figure 5A is a graph showing the distribution of the Al composition ratio in the sacrificial layer of the epitaxial growth substrate in the thickness direction according to the first embodiment, and Figures 5B to 5F are graphs showing the distribution of the Al composition ratio in the sacrificial layer of the epitaxial growth substrate in the thickness direction according to a modified example of the first embodiment. [Figure 6]The drawings from FIG. 6A to FIG. 6F are graphs showing the thickness-direction distribution of the In composition ratio in the sacrificial layer of an epitaxial growth substrate according to another modification of the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view of an epitaxial growth substrate according to the second embodiment. [Figure 8] FIGS. 8A and 8B are cross-sectional views in the middle of the manufacturing process of a semiconductor device according to the third embodiment. [Figure 9] FIGS. 9A and 9B are cross-sectional views in the middle of the manufacturing process of a semiconductor device according to the third embodiment.

Embodiments for Carrying Out the Invention

[0010] [First Embodiment] Referring to the drawings from FIG. 1A to FIG. 4B, an epitaxial growth substrate according to the first embodiment will be described.

[0011] FIG. 1A is a cross-sectional view of an epitaxial growth substrate 40 according to the first embodiment. On a substrate 10 made of a III-V compound semiconductor containing Ga as a group III element, for example, GaAs, a sacrificial layer 20 and a semiconductor layer 30 are epitaxially grown in this order. The sacrificial layer 20 includes layers 20A and 20C made of a III-V mixed crystal semiconductor containing Al as a group III element, for example, AlGaAs. Further, between them, a layer 20B made of a compound semiconductor containing Al as a group III element, for example, AlAs, is included. The semiconductor layer 30 includes a layer made of a compound semiconductor lattice-matched to the substrate 10, for example, GaAs.

[0012] The epitaxial growth substrate 40 according to the first embodiment separates the semiconductor layer 30 from the substrate 10 by etching away the sacrificial layer 20 and is used as a thin semiconductor layer 30. For example, before separation from the substrate 10, various electronic circuit elements such as transistors, diodes, and other passive elements are formed in the semiconductor layer 30, and then, by separating from the substrate 10, a very thin integrated circuit element can be fabricated.

[0013] Figure 1B is a graph showing an example of the etching rate distribution of each layer of the epitaxial growth substrate 40. The horizontal axis represents the position in the thickness direction of the epitaxial growth substrate 40, and the vertical axis represents the etching rate. As the Al composition ratio increases, the etching rate when wet etching is performed with acidic or alkaline etchants increases. For this reason, the etching rate of layer 20B, which is made of AlAs, is faster than the etching rates of layers 20A and 20C, which are made of AlGaAs. The etching rates of the substrate 10 and semiconductor layer 30, which are made of GaAs, are sufficiently lower than the etching rates of the three layers 20A, 20B, and 20C included in the sacrificial layer 20.

[0014] Next, with reference to Figures 2A to 3D, the procedure for separating the semiconductor layer 30 of the epitaxial growth substrate 40 from the substrate 10 according to the first embodiment will be described. Figures 2A, 2B, 2C, 3A, and 3C are cross-sectional views of the epitaxial growth substrate 40, temporary substrate 50, and adhesive layer 51 at an intermediate stage in the procedure for separating the semiconductor layer 30 of the epitaxial growth substrate 40 from the substrate 10 according to the first embodiment. Figure 3B is a diagram showing the positional relationship of the substrate 10, semiconductor layer 30, and sacrificial layer 20 in a plan view at the intermediate stage shown in Figure 3A. Figure 3D is a cross-sectional view of the semiconductor layer 30, temporary substrate 50, and adhesive layer 51 from which the substrate 10 has been separated.

[0015] As shown in Figure 2A, the semiconductor layer 30 of the epitaxial growth substrate 40 according to the first embodiment is placed facing the temporary substrate 50, and the epitaxial growth substrate 40 is bonded to the temporary substrate 50 by an adhesive layer 51. For example, a silicon substrate is used as the temporary substrate 50, and a polyimide-based adhesive is used for the adhesive layer 51.

[0016] As shown in Figure 2B, the epitaxial growth substrate 40 is separated into multiple small pieces (chips) by dicing the epitaxial growth substrate 40 to form separation grooves 55. The multiple small pieces of the epitaxial growth substrate 40 are bonded to and supported by a temporary substrate 50.

[0017] As shown in Figure 2C, the epitaxial growth substrate 40, after being separated into small pieces, is immersed in an acidic or alkaline etchant to wet etch the sacrificial layer 20. The sacrificial layer 20 is etched laterally from the exposed edge. As shown in Figure 1B, the etching rate of the sacrificial layer 20 is high in the center in the thickness direction and low near the interface with the substrate 10 and the semiconductor layer 30. Therefore, the lateral etching depth of the sacrificial layer 20 in the central part in the thickness direction is relatively deeper compared to other parts.

[0018] Further etching results in a state where, as shown in Figures 3A and 3B, the portion of the sacrificial layer 20 on the substrate 10 side and the portion on the semiconductor layer 30 side are connected by minute, point-like regions 20D in the central part of the thickness direction of the sacrificial layer 20. Further etching results in a state where, as shown in Figure 3C, the sacrificial layer 20 is separated into a portion 20E on the substrate 10 side and a portion 20F on the semiconductor layer 30 side.

[0019] After the sacrificial layer 20 is separated into two parts 20E and 20F, etching is further carried out to completely remove the portion 20F (Figure 3C) that remained on the semiconductor layer 30 side, as shown in Figure 3D. At this point, the substrate 10 (Figure 3C) can be separated from the semiconductor layer 30. The semiconductor layer 30 is hardly etched by the etchant.

[0020] Next, we will explain the superior effects of the first embodiment in comparison with the comparative examples shown in Figures 4A and 4B.

[0021] Figures 4A and 4B show the procedure for separating the substrate 10 from the semiconductor layer 30 in the comparative epitaxial growth substrate 40. In the comparative epitaxial growth substrate 40, the Al composition ratio of the sacrificial layer 20 is constant in the thickness direction. When the sacrificial layer 20 is etched from the exposed edge, due to the crystal plane orientation dependence of the etching rate, the sacrificial layer 20 becomes a truncated pyramidal pyramid with the crystal plane with the slower etching rate as the slope, as shown in Figure 4A. The surface of the truncated pyramidal pyramid connected to the semiconductor layer 30 (top surface) is smaller than the surface connected to the substrate 10 (bottom surface).

[0022] Further etching leads to the formation of a truncated pyramidal sacrificial layer 20, where the upper surface becomes almost point-like, as shown in Figure 4B, and the sacrificial layer 20 is separated from the semiconductor layer 30. Just before the sacrificial layer 20 is separated from the semiconductor layer 30, it is supported by a tiny point-like region relative to the semiconductor layer 30. Stress concentrates in this tiny point-like region, making it prone to crack formation 30C in the semiconductor layer 30.

[0023] In contrast, in the first embodiment, the etching rate changes with respect to the thickness direction of the sacrificial layer 20, and the portion with the maximum etching rate is located inside the sacrificial layer 20. Therefore, as shown in Figures 3A and 3B, just before the substrate 10 is separated from the semiconductor layer 30, the portion of the sacrificial layer 20 on the substrate 10 side and the portion on the semiconductor layer 30 side are connected by minute point-like regions. That is, the connection points between the sacrificial layer 20 and the semiconductor layer 30 (Figures 3A and 3C) do not become minute point-like. Therefore, the excellent effect of making it difficult for cracks to occur in the semiconductor layer 30 is obtained. In order to preferentially etch away the sacrificial layer 20 from the substrate 10 and the semiconductor layer 30, it is preferable to set the maximum value of the Al composition ratio in the sacrificial layer 20 to 0.5 or more.

[0024] If the layer 20A made of AlGaAs (Figure 1A) is omitted and the layer 20B made of AlAs is directly epitaxially grown on the substrate 10, the crystal quality of the sacrificial layer 20 deteriorates due to lattice mismatch. As a result, the crystal quality of the semiconductor layer 30 epitaxially grown on the sacrificial layer 20 also deteriorates. The layer 20A made of AlGaAs, placed between the layer 20B made of AlAs and the substrate 10 made of GaAs, has the function of mitigating lattice mismatch. This makes it possible to suppress the deterioration of the crystallinity of the sacrificial layer 20 and the semiconductor layer 30.

[0025] Next, we will describe the preferred range for the thickness of the sacrificial layer 20. Due to lattice mismatch between the substrate 10 and the sacrificial layer 20, strain is generated within the sacrificial layer 20. However, if the sacrificial layer 20 is made too thick, dislocations will be generated within the sacrificial layer 20, easing the strain. It is preferable to make the sacrificial layer 20 thin enough so that strain easing does not occur. Also, if the sacrificial layer 20 is made too thin, it becomes difficult for the etchant to penetrate into the space where the sacrificial layer 20 is removed in the etching process shown in Figure 2C. It is preferable to make the sacrificial layer 20 thick enough so that the penetration of the etchant is not hindered.

[0026] Next, we will describe the preferred relationship between the thicknesses of the substrate 10, the sacrificial layer 20, and the semiconductor layer 30. In a semiconductor process in which various electronic circuit elements, such as transistors, diodes, capacitors, and inductors, are formed on a thin semiconductor layer 30, the substrate 10 functions as a support substrate that mechanically supports the semiconductor layer 30. The semiconductor layer 30 is so thin that it cannot maintain a stable shape on its own. Separating the substrate 10 from the semiconductor layer 30 is done to thin the component including the semiconductor layer 30 on which the electronic circuit elements are formed. Therefore, it is preferable that the thickness of the semiconductor layer 30 is thinner than the thickness of the substrate 10.

[0027] When forming transistors or the like on the semiconductor layer 30, it is preferable to use a substrate 10 that is lattice-matched with the compound semiconductor of one of the layers constituting the transistor. In other words, it is preferable that the semiconductor layer 30 includes a layer made of a compound semiconductor that is lattice-matched with the substrate 10.

[0028] If the sacrificial layer 20 is made too thick, dislocations are more likely to occur within the sacrificial layer 20, which degrades the crystal quality of the semiconductor layer 30 epitaxially grown on top of it. To suppress the degradation of the crystal quality of the semiconductor layer 30, it is preferable to make the sacrificial layer 20 as thin as possible. For example, it is preferable to make the thickness of the sacrificial layer 20 thinner than the thickness of the semiconductor layer 30. For example, the thickness of the sacrificial layer 20 is 0.01 μm or more and 0.5 μm or less, and the thickness of the semiconductor layer 30 is 0.5 μm or more and 10 μm or less.

[0029] Next, with reference to Figures 5A to 5F, the epitaxial growth substrate according to the first embodiment and a modification thereof will be described. Figure 5A is a graph showing the distribution of the Al composition ratio in the thickness direction within the sacrificial layer 20 of the epitaxial growth substrate 40 according to the first embodiment, and Figures 5B to 5F are graphs showing the distribution of the Al composition ratio in the thickness direction within the sacrificial layer 20 of the epitaxial growth substrate 40 according to a modification thereof. In all examples, the sacrificial layer 20 is Al x Ga 1-x It is formed of As. In the graphs shown in Figures 5A to 5F, the horizontal axis represents the position in the thickness direction of the substrate 10, sacrificial layer 20, and semiconductor layer 30, and the vertical axis represents the Al composition ratio x.

[0030] As shown in Figure 5A, in the first embodiment, the sacrificial layer 20 is composed of three layers, with the Al composition ratio x of the central layer 20B being 1, and the Al composition ratio x of the two outer layers 20A and 20C being the same and less than 1.

[0031] In the modified example shown in Figure 5B, the Al composition ratio x of the central layer of the sacrificial layer 20 is 1. However, the Al composition ratio x of the layer on the substrate 10 side is lower than that of the layer on the semiconductor layer 30 side. This configuration reduces lattice mismatch at the interface between the substrate 10 and the sacrificial layer 20, thereby enhancing the effect of suppressing the deterioration of the crystal quality of the sacrificial layer 20 and the semiconductor layer 30.

[0032] Furthermore, since the Al composition ratio x of the sacrificial layer 20 in contact with the semiconductor layer 30 is higher than that of the layer in contact with the substrate 10, the etching rate of the sacrificial layer 20 in contact with the semiconductor layer 30 is faster than that of the layer in contact with the substrate 10. As a result, the portion 20F of the sacrificial layer 20 on the semiconductor layer 30 side, as shown in Figure 3C, becomes smaller than the portion 20E on the substrate side. Consequently, after the substrate 10 is separated from the semiconductor layer 30, the portion 20F of the sacrificial layer 20 remaining on the semiconductor layer 30 side can be removed in a shorter time.

[0033] In the modified example shown in Figure 5C, two layers with different Al composition ratios x (less than 1) are placed between the layer with an Al composition ratio x of 1 and the substrate 10. Of these two layers, the layer on the substrate 10 side has a relatively lower Al composition ratio x. By gradually increasing the Al composition ratio from the substrate 10 toward the layer with an Al composition ratio of 1, it is possible to bring the lattice constant of the portion of the sacrificial layer 20 in contact with the substrate 10 closer to the lattice constant of the substrate 10, while suppressing abrupt changes in the lattice constant. This further suppresses the deterioration of crystal quality due to lattice mismatch.

[0034] In the modified example shown in Figure 5D, the Al composition ratio x is 1 at two locations in the thickness direction of the sacrificial layer 20. In the modified example shown in Figure 5E, the Al composition ratio x is 1 at three locations in the thickness direction of the sacrificial layer 20. The layer with the largest lattice mismatch with respect to the substrate 10, where the Al composition ratio x is 1, inherently contains relatively large strain due to the lattice mismatch. As the thickness of each layer with an Al composition ratio of 1 increases, dislocations occur and the strain is relieved.

[0035] By configuring the sacrificial layer 20 so that the Al composition ratio x is 1 at multiple locations in the thickness direction, it is possible to increase the thickness of the sacrificial layer 20 without relieving strain within the sacrificial layer 20 (without generating dislocations). Increasing the thickness of the sacrificial layer 20 makes it easier for the etchant to penetrate between the substrate 10 and the semiconductor layer 30 in the etching process shown in Figure 2C, thereby improving the stability of the etching process of the sacrificial layer 20.

[0036] In addition to two or three locations in the thickness direction of the sacrificial layer 20, locations where the Al composition ratio x is 1 may be placed in four or more locations.

[0037] Furthermore, in the modified example shown in Figure 5D, similar to the modified example shown in Figure 5B, the Al composition ratio x of the layer in contact with the substrate 10 is lower than the Al composition ratio x of the layer in contact with the semiconductor layer 30. Therefore, similar to the modified example in Figure 5B, lattice mismatch at the interface between the substrate 10 and the sacrificial layer 20 can be mitigated. In addition, in the modified example shown in Figure 5E, the Al composition ratio x of the layer in contact with the substrate 10 may also be lower than the Al composition ratio x of the layer in contact with the semiconductor layer 30.

[0038] In the modified example shown in Figure 5F, the Al composition ratio x changes continuously in the thickness direction within the sacrificial layer 20. Even in this case, similar to the modified example shown in Figure 5D, the Al composition ratio x is 1 at two locations in the thickness direction of the sacrificial layer 20. When the Al composition ratio x changes discontinuously, stress tends to concentrate at the interface of the layer where the Al composition ratio x becomes discontinuous. By continuously changing the Al composition ratio x, stress localization can be suppressed. As a result, the crystal quality of the sacrificial layer 20 can be improved.

[0039] Furthermore, similar to the modified example shown in Figure 5D, the Al composition ratio x of the sacrificial layer 20 at the interface with the substrate 10 is lower than the Al composition ratio x of the sacrificial layer 20 at the interface with the semiconductor layer 30. This suppresses lattice mismatch and improves the crystal quality of the semiconductor layer 30.

[0040] In the first embodiment shown in Figure 5A, and the modified version of the first embodiment shown in Figures 5B to 5F, the Al composition ratio x was set to 1 in the area where a relatively faster etching rate was desired. However, the Al composition ratio does not necessarily have to be 1. With respect to the thickness direction of the sacrificial layer 20, the Al composition ratio x may be set to a maximum value at at least one location inside the sacrificial layer 20 other than the interface with the substrate 10 and the interface with the semiconductor layer 30.

[0041] In the etching process of the sacrificial layer 20 shown in Figures 2C to 3D, it is preferable to increase the ratio of the etching rate of the sacrificial layer 20 to the etching rate of the semiconductor layer 30 (etching selectivity ratio) when using the etchant used in the etching process of the sacrificial layer 20, in order to reduce the etching damage to the semiconductor layer 30. For example, when the semiconductor layer 30 and the substrate 10 are formed of GaAs, it is preferable to make the Al composition ratio x at the location where the Al composition ratio x in the sacrificial layer 20 shows a maximum value 0.5 or more, and more preferably 0.7 or more. If the Al composition ratio x at the location where the Al composition ratio x in the sacrificial layer 20 shows a maximum value is less than 0.5, the etching time required to separate the semiconductor layer 30 and the substrate 10 becomes long, and as a result, the damage to the semiconductor layer 30 and the substrate 10 becomes large.

[0042] Next, other modifications of the first embodiment will be described with reference to Figures 6A to 6F. In the first embodiment, a GaAs substrate was used as the substrate 10 (Figure 1A), but a substrate made of other III-V compound semiconductors, such as an InP substrate, may also be used. When an InP substrate is used, the sacrificial layer 20 is In y Ga 1-y It is possible to use As.

[0043] Figures 6A to 6F are graphs showing the distribution of the In composition ratio y in the thickness direction within the sacrificial layer 20 of the epitaxial growth substrate 40 in other modifications of the first embodiment. In all examples, an InP substrate is used as the substrate 10, and the sacrificial layer 20 is In y Ga 1-y It is formed of As. The distribution of In composition ratio y within the sacrificial layer 20 shown in the graphs from Figure 6A to Figure 6F is the same as the distribution of Al composition ratio x within the sacrificial layer 20 shown in the graphs from Figure 5A to Figure 5F. The semiconductor layer 30 includes a layer made of a semiconductor material, such as InP, that is lattice-matched to the InP substrate.

[0044] The etching rate of InGaAs with respect to an acidic etchant or an alkaline etchant increases as the In composition ratio y increases. Therefore, by making the distribution of the In composition ratio y in the sacrificial layer 20 the same as the distribution shown in the graphs from FIG. 6A to FIG. 6F, excellent effects similar to those in the first embodiment and its modified examples shown in the graphs from FIG. 5A to FIG. 5F can be obtained. In order to preferentially etch and remove the sacrificial layer 20 with respect to the semiconductor layer 30 and the substrate 10, it is preferable to set the In composition ratio y to 0.5 or more. For example, when the semiconductor layer 30 and the substrate 10 are formed of InP, it is preferable that the In composition ratio y at the location where the In composition ratio y in the sacrificial layer 20 shows a maximum value is 0.5 or more, and more preferably 0.7 or more.

[0045] As another modification, the sacrificial layer 20 may be formed of a quaternary mixed crystal semiconductor of Al x In y Ga 1-x-y As. In this case, a GaAs substrate or an InP substrate may be used for the substrate 10. The distribution of the total composition ratio x + y of Al and In in the sacrificial layer 20 is preferably made the same as the distribution of the Al composition ratio x shown in the graphs from FIG. 5A to FIG. 5F. In addition, an InP substrate or a GaAs substrate may be used as the substrate 10, and InAlP may be used for the sacrificial layer 20.

[0046] [Second Embodiment] Next, an epitaxial growth substrate according to the second embodiment will be described with reference to FIG. 7. Hereinafter, descriptions of configurations common to the epitaxial growth substrate 40 according to the first embodiment described with reference to the drawings from FIG. 1A to FIG. 3D will be omitted.

[0047] FIG. 7 is a cross-sectional view of an epitaxial growth substrate 40 according to the second embodiment. Also in the second embodiment, similar to the first embodiment, the epitaxial growth substrate 40 includes a substrate 10, a sacrificial layer 20, and a semiconductor layer 30. In the second embodiment, the semiconductor layer 30 includes a stopper layer 30S that has grown epitaxially from the sacrificial layer 20 and a device layer 30D that has grown epitaxially from the stopper layer 30S.

[0048] The device layer 30D includes a layer made of a compound semiconductor that is lattice-matched to the substrate 10, for example, a layer made of the same compound semiconductor as the substrate 10. The stopper layer 30S has the function of protecting the device layer 30D from the etchant during the etching process of the sacrificial layer 20 (Figures 2C, 3A, 3C, and 3D). Therefore, in wet etching using an etchant to etch the sacrificial layer 20, the etching rate of the stopper layer 30S is slower than the etching rate of the layer at the interface between the device layer 30D and the stopper layer 30S.

[0049] For example, if the sacrificial layer 20 is formed of AlGaAs or AlAs, and the device layer 30D includes an AlGaAs layer, then an AlGaInP layer, a GaInP layer, an AlInP layer, a GaInAs layer, etc., can be used as the stopper layer 30S. By adjusting the composition ratio of group III elements in the mixed crystal semiconductor constituting the stopper layer 30S, it is possible to make the lattice constant of the stopper layer 30S approximately match the lattice constant of the substrate 10 made of GaAs. Even if the lattice constants cannot be perfectly matched, the generation of dislocations within the stopper layer 30S can be suppressed by making the stopper layer 30S thin enough so that strain relaxation does not occur. Alternatively, the impurity concentration of the stopper layer 30S and the device layer 30D can be made different, and the impurity concentration dependence of the etching rate can be utilized.

[0050] [Third Embodiment] Next, a method for manufacturing a semiconductor device using an epitaxial growth substrate according to the third embodiment will be described with reference to Figures 8A to 9B. Figures 8A to 9B are cross-sectional views of the semiconductor device during the manufacturing process according to the third embodiment.

[0051] As shown in Figure 8A, an epitaxial growth substrate 40 according to the first embodiment is prepared. The epitaxial growth substrate 40 includes a substrate 10, a sacrificial layer 20, and a semiconductor layer 30 made of n-type GaAs. By making a portion of the semiconductor layer 30 highly resistive, an element isolation region 30I is formed. Multiple active regions 30N made of n-type GaAs are defined by the element isolation region 30I, which are electrically separated from each other.

[0052] Semiconductor elements such as transistors 31 and diodes 32 are formed on each of the multiple active regions 30N of the semiconductor layer 30. Transistor 31 is a heterojunction bipolar transistor including, for example, a collector layer made of n-type GaAs, a base layer made of p-type GaAs, and an emitter layer made of n-type InGaP. Diode 32 includes, for example, a cathode layer made of n-type GaAs and an anode layer made of p-type GaAs, formed in the same process as the collector and base layers of transistor 31. The active regions 30N are used as current paths to supply carriers to the collector layer of transistor 31 and the cathode layer of diode 32.

[0053] An insulating film 33 is formed on the semiconductor layer 30 to cover the transistor 31 and the diode 32. The insulating film 33 can be made of an inorganic insulating material such as silicon nitride, an insulating resin, or the like.

[0054] As shown in Figure 8B, with the side on which the semiconductor layer 30 is formed facing the temporary substrate 50, the epitaxial growth substrate 40 is attached to the temporary substrate 50 via the adhesive layer 51. More specifically, the insulating film 33 is bonded to the temporary substrate 50.

[0055] As shown in Figure 9A, the epitaxial growth substrate 40 and the insulating film 33 are separated into multiple small pieces by dicing. Figure 9A shows only one small piece. As shown in Figure 9B, the substrate 10 is separated from the semiconductor layer 30 by etching off the sacrificial layer 20 of the epitaxial growth substrate 40. At this point, multiple thin electronic circuit chips, including transistors 31 and diodes 32, are obtained.

[0056] As an example, by separating these electronic circuit chips from the temporary substrate 50 and bonding the semiconductor layer 30 to another electronic circuit chip including a silicon substrate, an electronic circuit component including silicon-based electronic circuit elements and compound semiconductor-based electronic circuit elements can be fabricated.

[0057] Next, we will describe the excellent effects of the third embodiment. In the third embodiment, as in the first embodiment, the process of separating the substrate 10 from the semiconductor layer 30 shown in Figure 9B can suppress the occurrence of cracks in the semiconductor layer 30.

[0058] In the heterojunction transistor 31, an n-type compound semiconductor is used as the collector layer. It is preferable that the semiconductor layer 30 includes an n-type compound semiconductor layer in order to form a current path in the semiconductor layer 30 that supplies carriers to the collector layer. In the etching process of the sacrificial layer 20 shown in Figure 9B, the transistor 31 and diode 32 are covered with an insulating film 33 and are therefore not exposed to the etchant used to etch the sacrificial layer 20. For this reason, the transistor 31 and diode 32 may include a compound semiconductor layer whose etching selectivity ratio with respect to the sacrificial layer 20 is not sufficiently large.

[0059] The embodiments described above are illustrative, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. Similar effects and benefits from similar configurations in multiple embodiments will not be mentioned sequentially for each embodiment. Furthermore, the present invention is not limited to the embodiments described above. For example, it will be obvious to those skilled in the art that various modifications, improvements, and combinations are possible.

[0060] Based on the embodiments described herein, the following inventions are disclosed. <1> A substrate made of a group III-V compound semiconductor containing Ga or In as a group III element, A sacrificial layer epitaxially grown on the aforementioned substrate, A semiconductor layer epitaxially grown on the aforementioned sacrificial layer and Equipped with, The sacrificial layer comprises a layer made of a mixed crystal semiconductor containing Al or In as a group III element, the composition ratio of Al or In changes in the thickness direction, and the location where the composition ratio of Al or In shows a maximum value is located inside the sacrificial layer, excluding the bottom and top surfaces.

[0061] <2> The layer made of the mixed crystal semiconductor contained in the sacrificial layer contains Ga in addition to Al or In as a group III element, and at least one of As and P as a group V element, and the maximum composition ratio of Al or In is 0.5 or more. <1> The epitaxial growth substrate described in [reference].

[0062] <3> In the sacrificial layer, the composition ratio of Al or In in the portion in contact with the substrate is smaller than the composition ratio of Al or In in the portion in contact with the semiconductor layer. <1> or <2> The epitaxial growth substrate described in [reference].

[0063] <4> At multiple locations in the thickness direction of the sacrificial layer, the composition ratio of Al or In reaches a maximum value. <1> ~ <3> An epitaxial growth substrate as described in any one of the following.

[0064] <5> The thickness of the semiconductor layer is thinner than the thickness of the substrate and thicker than the thickness of the sacrificial layer. <1> ~ <4> An epitaxial growth substrate as described in any one of the following.

[0065] <6> The substrate is formed of GaAs or InP, and the semiconductor layer includes a layer made of a semiconductor that is lattice-matched to the substrate. <1> ~ <5> An epitaxial growth substrate as described in any one of the following.

[0066] <7> The semiconductor layer includes a stopper layer in contact with the sacrificial layer, and in wet etching using an acidic or alkaline etchant, the etching rate of the stopper layer is slower than the etching rate of the sacrificial layer. <1> ~ <6> An epitaxial growth substrate as described in any one of the following.

[0067] <8> The semiconductor layer includes a layer made of an N-type semiconductor. <1> ~ <7> An epitaxial growth substrate as described in any one of the following.

[0068] <9> In wet etching using an acidic or alkaline etchant, the portion of the sacrificial layer where the etching rate is maximized is located inside the sacrificial layer, excluding the bottom and top surfaces. <1> ~ <8> An epitaxial growth substrate as described in any one of the following.

[0069] <10> <1> ~ <9> A semiconductor element, at least one of a transistor and a diode, is formed on the semiconductor layer of the epitaxial growth substrate described in any one of the following: A method for manufacturing a semiconductor device, comprising etching away the sacrificial layer to separate the substrate from the semiconductor layer. [Explanation of symbols]

[0070] 10 circuit boards 20 layers of victims 20A AlGaAs layer 20B AlAs layer 20C AlGaAs layer 20D Point-like minute regions 20E Sacrificial layer, substrate side portion 20F Sacrificial layer on the semiconductor layer side 30 Semiconductor Layers 30C Crack 30D Device Layer 30I element isolation region 30N active area 30S Stopper Layer 31 transistors 32 diodes 33 Insulating film 40 Epitaxial Growth Substrates 50 Temporary circuit board 51 Adhesive layer 55 Separation groove

Claims

1. A substrate made of a group III-V compound semiconductor containing Ga or In as a group III element, A sacrificial layer epitaxially grown on the aforementioned substrate, A semiconductor layer epitaxially grown on the aforementioned sacrificial layer and Equipped with, The sacrificial layer includes a layer made of a mixed crystal semiconductor containing Al or In as a group III element, the composition ratio of Al or In changes in the thickness direction, and the location where the composition ratio of Al or In shows a maximum value is located inside the sacrificial layer, other than the bottom and top surfaces. The layer made of the mixed crystal semiconductor included in the sacrificial layer contains Ga in addition to Al or In as a group III element, and at least one of As and P as a group V element, and the maximum composition ratio of Al or In is 0.5 or more, in an epitaxial growth substrate.

2. A substrate made of a group III-V compound semiconductor containing Ga or In as a group III element, A sacrificial layer epitaxially grown on the aforementioned substrate, A semiconductor layer epitaxially grown on the aforementioned sacrificial layer and Equipped with, The sacrificial layer includes a layer made of a mixed crystal semiconductor containing Al or In as a group III element, the composition ratio of Al or In changes in the thickness direction, and the location where the composition ratio of Al or In shows a maximum value is located inside the sacrificial layer, other than the bottom and top surfaces. An epitaxial growth substrate in which the composition ratio of Al or In in the portion of the sacrificial layer in contact with the substrate is smaller than the composition ratio of Al or In in the portion in contact with the semiconductor layer.

3. The epitaxial growth substrate according to claim 1 or 2, wherein the composition ratio of Al or In takes a maximum value at multiple locations in the thickness direction of the sacrificial layer.

4. The epitaxial growth substrate according to claim 1 or 2, wherein the thickness of the semiconductor layer is thinner than the thickness of the substrate and thicker than the thickness of the sacrificial layer.

5. The epitaxial growth substrate according to claim 1 or 2, wherein the substrate is formed of GaAs or InP, and the semiconductor layer includes a layer made of a semiconductor that is lattice-matched to the substrate.

6. The epitaxial growth substrate according to claim 1 or 2, wherein the semiconductor layer includes a stopper layer in contact with the sacrificial layer, and in wet etching using an acidic etchant or an alkaline etchant, the etching rate of the stopper layer is slower than the etching rate of the sacrificial layer.

7. The epitaxial growth substrate according to claim 1 or 2, wherein the semiconductor layer includes a layer made of an N-type semiconductor.

8. A substrate made of a group III-V compound semiconductor containing Ga or In as a group III element, A sacrificial layer epitaxially grown on the aforementioned substrate, A semiconductor layer epitaxially grown on the aforementioned sacrificial layer and Equipped with, The sacrificial layer includes a layer made of a mixed crystal semiconductor containing Al or In as a group III element, the composition ratio of Al or In changes in the thickness direction, and the location where the composition ratio of Al or In shows a maximum value is located inside the sacrificial layer, other than the bottom and top surfaces. An epitaxial growth substrate in which, in wet etching using an acidic or alkaline etchant, the portion of the sacrificial layer where the etching rate is maximized is located inside the sacrificial layer, excluding the lower and upper surfaces.

9. A semiconductor element, at least one of a transistor and a diode, is formed in the semiconductor layer of the epitaxial growth substrate according to claim 1 or 2. A method for manufacturing a semiconductor device, comprising etching away the sacrificial layer to separate the substrate from the semiconductor layer.

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