Image sensor and imaging device

Abstract

An imaging element comprising: a plurality of pixels; a plurality of conversion units for converting an analog signal into a digital signal and temporarily storing the digital signal; a first output line connected to a first conversion unit among the plurality of conversion units and from which a signal obtained by conversion into the digital signal by the first conversion unit is output; a second output line connected to a second conversion unit among the plurality of conversion units and from which a signal obtained by conversion into the digital signal by the second conversion unit is output; and a read-out circuit by which digital signals temporarily stored in the plurality of first conversion units and digital signals temporarily stored in the plurality of second conversion units are read out at different timings.

Description

Technical Field

[0001] The present invention relates to an imaging element and an imaging device.

Background Art

[0002] An imaging element capable of processing signals output from a plurality of pixels in parallel is known (for example, Patent Document 1). Conventionally, an increase in power consumption caused by processing signals from pixels in parallel has been a problem. [Prior Art Documents] [Patent Documents] [Patent Document 1] International Publication WO2013 / 129202 General Disclosure

[0003] In a first embodiment of the present invention, the image sensor comprises: a first substrate having a pixel section in which a plurality of pixels, each containing at least a photoelectric conversion unit that converts light into electric charge, are arranged in a row direction; a processing circuit section on which a first pixel circuit, each containing at least a first pixel memory for storing a first pixel signal from a first pixel among the plurality of pixels, and a second pixel circuit, each containing at least a second pixel memory for storing a second pixel signal from a second pixel among the plurality of pixels, are arranged; and a second substrate having a read control circuit for reading the first pixel signal stored in the first pixel memory and the second pixel signal stored in the second pixel memory at different timings. The second pixels may be arranged next to the first pixels in the row direction. The second pixel circuit may be arranged next to the first pixel circuit in the row direction. The image sensor may also include a first select line on which a first control signal for reading the first pixel signal stored in the first pixel memory is output, and a second select line on which a second control signal for reading the second pixel signal stored in the second pixel memory is output. The read control circuit may be controlled so that the timing of outputting the first control signal to the first selected line and the timing of outputting the second control signal to the second selected line are different. The read control circuit may be controlled so that the timing of starting to output the first control signal and the timing of starting to output the second control signal are different. The read control circuit may start outputting the second control signal after starting to output the first control signal. The read control circuit may start outputting the second control signal after ending the output of the first control signal. It may include a first output line to which the first pixel signal read from the first pixel memory is output, and a second output line to which the second pixel signal read from the second pixel memory is output. The read control circuit may be controlled so that the timing of reading the first pixel signal from the first pixel memory to the first output line is different from the timing of reading the second pixel signal from the second pixel memory to the second output line. The read control circuit may be controlled so that the timing of starting to read the first pixel signal and the timing of starting to read the second pixel signal are different. The readout control circuit may start reading the second pixel signal after it has started reading the first pixel signal. The readout control circuit may start reading the second pixel signal after it has finished reading the first pixel signal.The first pixel circuit may have a first comparator used to convert the first pixel signal from the first pixel into a digital signal. The second pixel circuit may have a second comparator used to convert the second pixel signal from the second pixel into a digital signal. The first pixel memory may store the first pixel signal converted into a digital signal using the first comparator. The second pixel memory may store the second pixel signal converted into a digital signal using the second comparator. The first pixel memory and the second pixel memory may each be composed of SRAM. The first and second substrates may be arranged such that at least a portion of the pixel section and at least a portion of the processing circuit section face each other. The first and second substrates may be arranged such that at least a portion of the first pixel and at least a portion of the first pixel circuit face each other. The first and second substrates may be arranged such that at least a portion of the second pixel and at least a portion of the second pixel circuit face each other. The second substrate may have a pixel control circuit that controls the first pixel and the second pixel, respectively. The pixel control circuit may control the exposure time of the first pixel and the exposure time of the second pixel. The pixel control circuit may control the reading of the first pixel signal from the first pixel and the reading of the second pixel signal from the second pixel. The processing circuit may be arranged between the readout control circuit and the pixel control circuit in the row direction. The second substrate may have an image processing unit that performs image processing on the first pixel signal stored in the first pixel memory and the second pixel signal stored in the second pixel memory. The third substrate may also have an image processing unit that performs image processing on the first pixel signal stored in the first pixel memory and the second pixel signal stored in the second pixel memory.

[0004] In a second embodiment of the present invention, an imaging device comprises the image sensor. The device may also include a control unit connected to the image sensor. The control unit may generate image data based on a first pixel signal and a second pixel signal.

[0005] It should be noted that the above summary of the invention does not enumerate all of its features. Furthermore, subcombinations of these features may also constitute an invention. [Brief explanation of the drawing]

[0006] [Figure 1] This diagram shows an overview of the image sensor 400 according to this embodiment. [Figure 2] An example of a planar layout of the first substrate 100 is shown. [Figure 3] An example of a planar layout of the second substrate 200 is shown. [Figure 4] An example of the circuit configuration of pixel 112 and pixel circuit 212 is shown. [Figure 5] This is a schematic diagram illustrating the circuit for reading data from the pixel memory 220 to the image processing and output unit 280. [Figure 6] This is a schematic diagram illustrating in more detail the circuit for reading from the pixel memory 220 within the processing circuit section 210. [Figure 7] Figure 6 is an example of a timing chart showing the read operation from the pixel memory 220. [Figure 8] Figure 6 is an example of a timing chart showing the read operation from the pixel memory 220. [Figure 9] This is a schematic diagram illustrating in detail the circuit for reading from the pixel memory 220, which is one of the other processing circuit sections 310. [Figure 10] Figure 9 is an example of a timing chart showing the read operation from the pixel memory 220. [Figure 11] Figure 9 is an example of a timing chart showing the read operation from the pixel memory 220. [Figure 12] Furthermore, this is a schematic diagram illustrating in detail the circuit for reading from the pixel memory 220, which is one of the other processing circuit sections 410. [Figure 13] Figure 12 is an example of a timing chart showing the read operation from the pixel memory 220. [Figure 14] Figure 12 is an example of a timing chart showing the read operation from the pixel memory 220. [Figure 15] This is a block diagram showing an example configuration of the imaging device 500 according to the embodiment. [Modes for carrying out the invention]

[0007] The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0008] In this specification, the X and Y axes are orthogonal to each other, and the Z axis is orthogonal to the XY plane. The XYZ axes form a right-handed system. The direction parallel to the Z axis may be referred to as the stacking direction of the image sensor 400. In this specification, the terms "up" and "down" are not limited to the up and down directions in the direction of gravity. These terms merely refer to relative directions in the Z axis direction. In this specification, the arrangement in the X axis direction is described as a "row," and the arrangement in the Y axis direction is described as a "column," but the matrix direction is not limited to these. Also, the Z axis direction is the optical axis direction from which light from the subject is incident.

[0009] Figure 1 is a diagram illustrating the overview of the image sensor 400 according to this embodiment. The image sensor 400 captures an image of a subject. The image sensor 400 generates image data of the captured subject. The image sensor 400 comprises a first substrate 100 and a second substrate 200. As shown in Figure 1, the first substrate 100 is stacked on the second substrate 200.

[0010] The first substrate 100 has a pixel section 110. The pixel section 110 outputs a pixel signal based on incident light. The first substrate 100 is sometimes referred to as a pixel chip.

[0011] The second substrate 200 has a processing circuit section 210 and a peripheral circuit section 230. The second substrate 200 is sometimes referred to as a signal processing chip.

[0012] The processing circuit unit 210 receives the pixel signals output from the first substrate 100. The processing circuit unit 210 processes the input pixel signals. For example, the processing circuit unit 210 performs a process of converting an analog signal into a digital sentence. Specifically, the processing circuit unit 210 performs a process of converting the input pixel signals into digital signals. The processing circuit unit 210 may perform other signal processing.

[0013] In this example, the processing circuit unit 210 is disposed on the second substrate 200 at a position facing the pixel unit 110. That is, the processing circuit unit 210 is arranged so as to at least partially overlap the pixel unit 110 in the optical axis direction. The processing circuit unit 210 may output a control signal for controlling the driving of the pixel unit 110 to the pixel unit 110.

[0014] The peripheral circuit unit 230 controls the driving of the processing circuit unit 210. The peripheral circuit unit 230 is disposed on the second substrate 200 around the processing circuit unit 210. Also, the peripheral circuit unit 230 is electrically connected to the first substrate 100 and may control the driving of the pixel unit 110.

[0015] In addition to the first substrate 100 and the second substrate 200, the imaging device 400 may include a third substrate stacked on the second substrate 200. For example, the third substrate is a memory chip, which performs image processing according to the signal output from the second substrate 200 and stores it. Also, the structure of the imaging device 400 may be a back-illuminated type or a front-illuminated type. Hereinafter, an example of the back-illuminated type will be described.

[0016] FIG. 2 shows an example of the planar layout of the first substrate 100. The pixel unit 110 is disposed near the center in the plane of the first substrate 100.

[0017] The pixel unit 110 includes a plurality of pixels 112 arranged side by side along the row direction and the column direction. The pixel unit 110 in this example has M×N pixels 112 (M and N are natural numbers). In this example, the case where M is different from N is illustrated, but M and N may be equal.

[0018] FIG. 3 shows an example of the planar layout of the second substrate 200. A processing circuit section 210 is arranged near the center in the plane of the second substrate 200.

[0019] The processing circuit section 210 has a plurality of pixel circuits 212 arranged side by side along the row direction and the column direction. The processing circuit section 210 in this example has M×N pixel circuits 212.

[0020] In this embodiment, the pixel circuit 212 and the pixel 112 are arranged at overlapping positions when viewed from the optical axis direction. In this case, the areas of the pixel circuit 212 and the pixel 112 may be substantially the same including the margins between adjacent blocks.

[0021] The pixel circuit 212 controls the driving of the electrically connected pixel 112. The pixel circuit 212 and the pixel 112 being electrically connected may sometimes be referred to as being corresponding.

[0022] In this embodiment, the pixel circuit 212 and the pixel 112 arranged at overlapping positions are connected. However, instead of the pixel circuit 212 and the pixel 112 arranged at overlapping positions being connected, the pixel circuit 212 and the pixel 112 arranged at non-overlapping positions may be connected.

[0023] Around the processing circuit section 210, there are arranged a pixel control circuit 250, a readout control circuit 260, and an image processing / output section 280 as an example of the peripheral circuit section 230. The pixel control circuit 250 controls the pixel 112 and the pixel circuit 212. The pixel control circuit 250 supplies, for example, a control signal for the pixel circuit 212 to AD-convert a signal from the pixel 112. Also, the pixel control circuit 250 controls, for example, the exposure time of the pixel 112. The readout control circuit 260 controls the readout for outputting the pixel signal stored in the pixel circuit 212 to the image processing / output section 280.

[0024] FIG. 4 shows an example of the circuit configuration of the pixel 112 and the pixel circuit 212. The pixel 112 includes a photoelectric conversion section 130, a reset section 132, an accumulation section 134, and a transfer section 136.

[0025] The photoelectric conversion unit 130 has a photoelectric conversion function that converts light into electric charge and a storage function that stores the photoelectrically converted charge. The photoelectric conversion unit 130 is, for example, a photodiode.

[0026] The storage unit 134 converts the charge generated in the photoelectric conversion unit 130 into a voltage corresponding to its amount. The storage unit 134 is an example of floating diffusion (FD).

[0027] The reset unit 132 discharges the charge from the storage unit 134 to the power supply wiring supplied with a predetermined power supply voltage VDD, based on the control signal φRST. The gate terminal of the reset unit 132 is connected to the pixel control circuit 250.

[0028] The transfer unit 136 transfers the charge stored in the photoelectric conversion unit 130 to the storage unit 134 based on the control signal φTX. The transfer unit 136 also resets the charge stored in the photoelectric conversion unit 130 based on the control signal φTX. For example, the transfer unit 136 resets the amount of charge stored in the photoelectric conversion unit 130 to 0 by simultaneously supplying the control signals φTX and φRST. The transfer unit 136 is an example of a transfer gate that transfers charge from the photoelectric conversion unit 130. In other words, the transfer unit 136 acts as the gate, the photoelectric conversion unit 130 as the source, and the storage unit 134 as the drain, and these together constitute a so-called transfer transistor.

[0029] The pixel circuit 212 comprises a comparator 216, a control circuit 214, and a pixel memory 220. The comparator 216 compares the voltage of the storage unit 134 with a reference voltage RAMP supplied from the pixel control circuit 250 and outputs the comparison result to the control circuit 214. The comparator 216 is configured, for example, as a differential pair. Alternatively, the comparator 216 may have a source follower circuit between it and the storage unit 134, for example. The control circuit 214 controls the pixel memory 220 based on the signal from the comparator 216 and the signal from φCTL.

[0030] The pixel memory 220 stores the pixel signals that have been converted into digital signals. For example, the pixel memory 220 receives a count signal supplied from the pixel control circuit 250, and stores the value of the count signal when the control signal output from the control circuit 214 is inverted. The pixel memory 220 further outputs the stored pixel signals based on the selection signal φSEL. An example of the pixel memory 220 is SRAM.

[0031] An example of the operation of pixel 112 and pixel circuit 212 for one frame will be described. First, at the start of accumulation for one frame, the pixel control circuit 250 resets the charge accumulated in the photoelectric conversion unit 130 by simultaneously supplying control signals φTX and φRST. Next, during the readout period at the end of one frame, the pixel control circuit 250 resets the voltage of the accumulation unit 134 to a predetermined voltage by supplying the control signal φRST. Subsequently, the pixel control circuit 250 stores a value corresponding to the reset voltage of the accumulation unit 134 in the pixel memory 220 by controlling the control signal φCTL, the reference voltage RAMP, and the count signal supplied to the pixel memory 220 (DARK conversion). Then, the readout control circuit 260 reads the DARK conversion result data stored in the pixel memory 220 to the image processing / output unit 280 by controlling the selection signal φSEL. The data readout from the pixel memory 220 will be described further later. Furthermore, the pixel control circuit 250 transfers the charge stored in the photoelectric conversion unit 130 to the storage unit 134 by supplying the control signal φTX. Subsequently, the pixel control circuit 250 controls the control signal φCTL, the reference voltage RAMP, and the count signal supplied to the pixel memory 220 to store a value corresponding to the voltage of the storage unit 134 after the charge transfer in the pixel memory 220 (SIG conversion). Finally, the readout control circuit 260 reads the SIG conversion result data stored in the pixel memory 220 to the image processing and output unit 280 by controlling the selection signal φSEL.

[0032] In this embodiment, one pixel circuit 212 is provided for each pixel 112, and all pixels 112 and pixel circuits 212 are controlled simultaneously. Therefore, a so-called global shutter operation is possible, in which multiple pixels 112 included in the pixel unit 110 are exposed at the same time. It is also possible to expose each pixel 112 at different times. The above conversion from analog signal to digital signal in the pixel circuit 212 is a so-called single-slope method. However, the conversion method is not limited to this, and other methods such as a successive approximation method may be used. The same applies to other embodiments.

[0033] Figure 5 is a schematic diagram illustrating the circuit for reading data from the pixel memory 220 to the image processing and output unit 280. Components that are not explained are omitted from the diagram.

[0034] M×N pixel memories 220 are arranged corresponding to M×N pixels 121. These pixel memories 220 are connected to row selection lines 264 and 265 of the row selection circuit 262 of the read control circuit 260. Row selection signals φSEL, which are an example of control signals for reading pixel signals stored in the pixel memories 220, are output to row selection lines 264 and 265. Row selection lines 264 and 265 are sometimes also called word selection lines.

[0035] On the other hand, these pixel memories 220 are connected in common to output lines 266 to the image processing and output unit 280, row by row. Pixel signals read from the pixel memories 220 are output to the output lines 266. The output lines 266 are sometimes also called bit lines.

[0036] Here, the pixel memory 220 stores a digital signal with a number of bits corresponding to the gradation of the image signal, and therefore each pixel 112 has a memory cell corresponding to that number of bits. For example, if 8 bits are used to represent the pixel signal of one pixel with 256 monochrome gradations, then 8 memory cells will be used. Therefore, even for the output from the pixel memory 220, if time division is not used, at least the number of output lines 266 corresponding to the number of bits will be used for one row of pixel memory 220. In Figures 5 and later, diagonal lines are drawn on the wiring, as in output line 266 in Figure 5, to indicate that multiple wirings are represented by a single line.

[0037] In the read operation using the configuration shown in Figure 5, if read operations are performed from many pixel memories 220 at once, the current during read operation increases. Therefore, in this embodiment, the current during read operation is suppressed by reading from multiple pixel memories 220 at different timings. For example, the pixel memories 220 in even-numbered rows are designated as memory group A, and the pixel memories 220 in odd-numbered rows are designated as memory group B, and the read timings for memory group A and memory group B are made different. For the sake of explanation, unless otherwise specified, rows and columns are counted from 0.

[0038] Figure 6 is a schematic diagram illustrating in more detail the circuit for reading from the pixel memory 220 within the processing circuit section 210. Components that are not explained are omitted from the diagram.

[0039] In the example in Figure 6, each pixel memory 220 is connected to output lines 266 and 267 via a switch 222. Furthermore, output line 266 is provided with a D flip-flop 224 and a switch 226 on its output side for each predetermined number of pixel memories 220. In the example shown in Figure 6, a D flip-flop 224 and a switch 226 are provided for every three pixel memories 220 in the same row. This can be said to form a memory subgroup for each corresponding number. That is, in the example in Figure 6, memory group A has memory subgroups A0 through Ak.

[0040] Similarly, memory group B has memory subgroups B0 to Bk. Each memory subgroup may contain two or fewer pixel memories 220, or four or more. Furthermore, the number of pixel memories 220 in each memory subgroup may differ from one another. Note that, corresponding to the number of output lines 266 and 267 corresponding to the number of bits, there are also a number of D flip-flops 224 corresponding to the number of bits, but only one is shown as a representative example.

[0041] In the example shown in Figure 6, there are numerous row selection lines for selecting and reading pixel signals from the pixel memory 220. To avoid complexity in notation, the reference numbers for the row selection lines will be omitted below, and the explanation will use signal symbols.

[0042] The signal φ_en_A turns on and off switch 226 on output line 266 of memory group A. The signal φ_rd_A(j) (where j=0, 1, 2) turns on and off switch 222 of the j-th row pixel memory 220 in each of memory subgroups A0 to Ak. The signal Clk_A is the clock that drives the D flip-flops 224 (DA0 to DAk) of memory group A.

[0043] The signal φ_en_B turns on and off switch 226 on output line 267 of memory group B. The signal φ_rd_B(j) (where j=0, 1, 2) turns on and off switch 222 of the j-th row pixel memory 220 in each of memory subgroups B0 to Bk. The signal Clk_B is the clock that drives the D flip-flops 224 (DB0 to DBk) of memory group B.

[0044] Figures 7 and 8 are examples of timing charts showing the read operation from the pixel memory 220 in Figure 6. The timing charts for the conversion and readout of the DARK signal and the conversion and readout of the SIG signal are the same, so the DARK signal chart is shown, and the SIG signal chart is omitted.

[0045] The enable signal Cnt_en for AD conversion is turned on, supplying a reference voltage RAMP, and the magnitude of the reference voltage RAMP is associated with the number of pulses and counted using the signal Gry_out. The pixel signal and the reference voltage RAMP are compared in comparator 216, and the pulse count Latch when the output of comparator 216 goes high is temporarily stored in the pixel memory. This operation may be performed synchronously and at the same timing in memory groups A and B.

[0046] Subsequently, with respect to memory group A, by turning on signal φ_rd_A(1) while signal φ_en_A is ON, the pixel signals of the first row of each memory subgroup Ap (p=0,1,···k) pixel memory 220 are output to the input side of the corresponding D flip-flop DAp. In this state, when signal Clk_A is input (k-1) times consecutively, the value of the D flip-flop is shifted sequentially from p to p+1, and all the pixel signals of memory subgroup Ap are output to the image processing / output unit 280. The pixel signals of memory group A are read out from the second row onward by the same operation. It should also be noted that the D flip-flop can be said to be functioning as a shift register.

[0047] Meanwhile, while the signal φ_rd_A(j) is turned off and the signal Clk_A is input to memory group A, the signals φ_en_B and φ_rd_B(j) are turned on to memory group B, and the pixel signals of the j-th row of each pixel memory 220 in memory subgroup Bp are output to the input side of the corresponding D flip-flop DBp. In this state, when the signal Clk_B is input (k-1) times consecutively, the value of the D flip-flop is passed sequentially from p to p+1, and all the pixel signals of memory group B are output to the image processing / output unit 280.

[0048] This means that reading from memory group B is started while reading from memory group A is still in progress. As a result, the output QpA of the D flip-flop is as shown in Figure 8. <j>and QpB <j>The timing is different, which can reduce the current consumption during reading.

[0049] Figure 9 is a schematic diagram illustrating in detail the circuit for reading from the pixel memory 220, which is one of the other processing circuit units 310. In the processing circuit unit 310, components identical to those in the processing circuit unit 210 in Figure 6 are given the same reference numerals and their explanations are omitted.

[0050] In the example in Figure 9, the pixel memory of the first column<A0,p,j> Each of the (p=0,1,···k:j=0,1) is connected to the output line 268 via switch 222. Additionally, the output line 268 is provided with a D flip-flop 224 and a switch 226 on its output side for every predetermined number of pixel memories (2 in the example in Figure 9).

[0051] Similarly, pixel memory in the same row<B0,p,j> Each of the (p=0,1,···k:j=0,1) is connected to the output line 270 via switch 222. Additionally, the output line 270 is provided with a D flip-flop 224 and a switch 226 on its output side for every predetermined number of pixel memories (2 in the example in Figure 9).

[0052] Furthermore, the pixel memory of other columns<A1,p,j> Each of (p=0,1,···k:j=0,1) is connected to output line 272 via switch 222, and output line 268 is provided with a D flip-flop 224 and a switch 226 on its output side for each predetermined number of pixel memories.<B1,p,j> Each of (p=0,1,···k:j=0,1) is connected to the output line 274 via switch 222, and the output line 274 is provided with a D flip-flop 224 and a switch 226 on its output side for each predetermined number of pixel memories.

[0053] The signal line of signal φ_rd_A(j) is the row-direction pixel memory.<Aq,p,j> It is commonly connected to (q=0,1,···N-1). Similarly, the signal line of signal φ_rd_B(j) is the row-direction pixel memory.<Bq,p,j> They are all connected in common. Therefore, it can be said that the pixel memories in even-numbered rows form memory group A, and the pixel memories in odd-numbered rows form memory group B. Also, two of each of memory group A in the same column form memory subgroup Aqp. Similarly, two of each of memory group B in the same column form memory subgroup Bqp.

[0054] Figures 10 and 11 are examples of timing charts showing the read operation from the pixel memory 220 in Figure 9. The timing charts for the conversion and readout of the DARK signal and the conversion and readout of the SIG signal are the same, so the DARK signal chart is shown, and the SIG signal chart is omitted.

[0055] For memory group A, the enable signal Cnt_en_A for AD conversion is turned on, supplying a reference voltage RAMP, and the magnitude of the reference voltage RAMP is associated with the number of pulses and counted using the signal Gry_out_A. For memory group A, the pixel signal and the reference voltage RAMP are compared in comparator 216, and the number of pulses Latch_A when the output of comparator 216 goes high is temporarily stored in the pixel memory.

[0056] After the above operation of memory group A begins, the enable signal Cnt_en_B for AD conversion is turned on for memory group B, supplying a reference voltage RAMP, and the magnitude of the reference voltage RAMP is associated with the number of pulses and counted using the signal Gry_out_B. For memory group B, the pixel signal and the reference voltage RAMP are compared in comparator 216, and the number of pulses Latch_B when the output of comparator 216 goes high is temporarily stored in the pixel memory.

[0057] For memory group A, once the above AD conversion is complete, signals φ_en_A and φ_rd_A(j) are turned on, and the pixel signals of the j-th row of each pixel memory 220 in memory subgroup Aqp are output to the input side of the corresponding D flip-flop DAqp. In this state, when (k-1) signals Clk_A are input consecutively, the value of the D flip-flop is sequentially passed from p to p+1, and all the pixel signals of memory group A are output to the image processing / output unit 280.

[0058] After all the pixel signals of memory group A have been output to the image processing / output unit 280, for memory group B, signals φ_en_B and φ_rd_B(j) are turned on, and the pixel signals of the j-th row of each pixel memory 220 of memory subgroup Bqp are output to the input side of the corresponding D flip-flop DBqp. In this state, when (k-1) signals Clk_B are input consecutively, the value of the D flip-flop is sequentially passed from p to p+1, and all the pixel signals of memory group B are output to the image processing / output unit 280.

[0059] As described above, the processing circuit 310 starts reading from memory group B after reading from memory group A. Therefore, as shown in Figure 11, the output QpA of the D flip-flop <j>and QpB <j>The timing of these operations differs, which can reduce the current consumption during reading. The start timing of AD conversion for memory group B may correspond to the start timing of reading for memory group B. For example, the start timing of AD conversion for memory group B may be delayed by the time it takes for reading for memory group A to start and end.

[0060] Figure 12 is a schematic diagram illustrating in detail the circuit for reading from the pixel memory 220, which is another processing circuit in the 410. The processing circuit in the 410 is the same as the processing circuit in the 210 in Figure 6, except for the configuration described in particular.

[0061] In the processing circuit section 410, even-numbered rows form memory group A, and odd-numbered rows form memory group B. Furthermore, three pixel memories 220 each form memory subgroups Ap and Bp, respectively. However, unlike the processing circuit section 210, the signal line for signal φ_rd is connected in common to memory groups A and B.

[0062] Figures 13 and 14 are examples of timing charts showing the read operation from the pixel memory 220 in Figure 12. The timing charts for the conversion and readout of the DARK signal and the conversion and readout of the SIG signal are the same, so the DARK signal chart is shown, and the SIG signal chart is omitted.

[0063] The AD conversion of the DARK signal in Figure 13 is the same as in Figure 7. Subsequently, by turning on signals φ_en and φ_rd(j), the pixel signals are read from the j-th row of the pixel memory 220 of memory subgroups Ap and Bp and output to the input side of the corresponding D flip-flops DAp and DBp.

[0064] In this state, signal Clk_A is supplied before signal Clk_B. For example, the phase of signal Clk_B is delayed compared to signal Clk_A. As a result, the output QpA of the D flip-flop is as shown in Figure 14. <j>and QpB <j>The timing of these signals differs, which can reduce the current consumption during reading. Alternatively, instead of delaying the phase, the supply of signal Clk_B may be started a few clock cycles after signal Clk_A.

[0065] As described above, according to this embodiment, the amount of current flowing during reading can be reduced. In the above embodiment, one control circuit 214 is provided for one pixel 112. Alternatively, one control circuit 214 may be provided for multiple pixels 112. In that case, if the multiple pixels 112 corresponding to one control circuit 214 are called a pixel block, then the pixels 112 included in one pixel block are arranged in m rows and n columns (where m is a natural number of 2 or more and less than M, and n is a natural number of 2 or more and less than N), and multiple such pixel blocks may be arranged in the matrix direction.

[0066] Figure 15 is a block diagram showing an example configuration of an imaging device 500 according to an embodiment. The imaging device 500 comprises an image sensor 400, a system control unit 501, a drive unit 502, a photometer 503, a work memory 504, a recording unit 505, a display unit 506, a drive unit 514, and a photographic lens 520.

[0067] The imaging lens 520 guides the subject light beam incident along the optical axis OA to the image sensor 400. The imaging lens 520 is composed of multiple optical lens groups and forms an image of the subject light beam from the scene near its focal plane. The imaging lens 520 may be an interchangeable lens that can be attached to and detached from the imaging device 500. In Figure 15, the imaging lens 520 is represented by a single virtual lens positioned near the pupil.

[0068] The drive unit 514 drives the photographic lens 520. In one example, the drive unit 514 moves the optical lens group of the photographic lens 520 to change the focus position. The drive unit 514 may also drive the iris diaphragm within the photographic lens 520 to control the amount of light beam incident on the image sensor 400.

[0069] The drive unit 502 has a control circuit that performs charge accumulation control such as timing control and area control of the image sensor 400 according to instructions from the system control unit 501. The operation unit 508 receives instructions from the imager via a release button or the like.

[0070] The image sensor 400 passes pixel signals to the image processing unit 511 of the system control unit 501. The image processing unit 511 uses the work memory 504 as a workspace to generate image data after performing various image processing steps. For example, when generating image data in JPEG file format, it generates a color video signal from the signal obtained by the Bayer array and then performs compression processing. The generated image data is recorded in the recording unit 505 and converted into a display signal, which is then displayed in the display unit 506 for a preset time.

[0071] Prior to the series of shooting sequences that generate image data, the photometering unit 503 detects the brightness distribution of the scene. The photometering unit 503 includes, for example, an AE sensor with about 1 million pixels. The calculation unit 512 of the system control unit 501 receives the output of the photometering unit 503 and calculates the brightness of each region of the scene.

[0072] The calculation unit 512 determines the shutter speed, aperture value, and ISO sensitivity according to the calculated brightness distribution. The photometering unit 503 may also be integrated into the image sensor 400. The calculation unit 512 also performs various calculations for operating the imaging device 500. The drive unit 502 may be partially or entirely mounted on the image sensor 400. Part of the system control unit 501 may also be mounted on the image sensor 400.

[0073] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0074] It should be noted that the execution order of operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be performed in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, this does not mean that it is mandatory to perform the operations in that order.< / j> < / j> < / j> < / j> < / j> < / j>

Claims

1. A first substrate having a pixel section in which a first pixel containing at least a first photoelectric conversion unit that converts light into electric charge and a second pixel containing at least a second photoelectric conversion unit that converts light into electric charge are arranged in a row direction, A second substrate, laminated together with the first substrate, having a processing circuit section arranged along the row direction, the first substrate having a first pixel circuit including at least a first comparison unit for converting a first pixel signal read from the first pixel into a first digital signal and a first pixel memory for storing the first digital signal, a second pixel circuit including at least a second comparison unit for converting a second pixel signal read from the second pixel into a second digital signal and a second pixel memory for storing the second digital signal, and a read control circuit that controls the timing of reading the first digital signal from the first pixel memory and the timing of reading the second digital signal from the second pixel memory to be different timings. An image sensor equipped with the following features.

2. In the image sensor according to claim 1, A first selection line on which a first control signal for reading the first digital signal from the first pixel memory is output, A second selection line on which a second control signal for reading the second digital signal from the second pixel memory is output, Equipped with, The readout control circuit controls the timing at which it outputs the first control signal to the first selection line and the timing at which it outputs the second control signal to the second selection line to be different. Image sensor.

3. In the image sensor according to claim 2, The readout control circuit controls the timing at which the output of the first control signal to the first selected line begins and the timing at which the output of the second control signal to the second selected line begins to begin to be different. Image sensor.

4. In the image sensor according to claim 3, The readout control circuit starts outputting a first control signal to the first selection line, and then starts outputting a second control signal to the second selection line. Image sensor.

5. In the image sensor according to claim 4, The readout control circuit terminates the output of the first control signal to the first selection line, and then starts outputting the second control signal to the second selection line. Image sensor.

6. In the image sensor according to claim 1, A first output line on which the first digital signal read from the first pixel memory is output, The second output line on which the second digital signal read from the second pixel memory is output, Equipped with, The readout control circuit controls the timing of reading the first digital signal from the first pixel memory to the first output line and the timing of reading the second digital signal from the second pixel memory to the second output line to be different. Image sensor.

7. In the image sensor according to claim 6, The readout control circuit controls the timing at which the first digital signal is read out of the first output line and the timing at which the second digital signal is read out of the second output line to be different. Image sensor.

8. In the image sensor according to claim 7, The readout control circuit starts reading the first digital signal on the first output line, and then starts reading the second digital signal on the second output line. Image sensor.

9. In the image sensor according to claim 8, The readout control circuit starts reading the second digital signal on the second output line after it has finished reading the first digital signal on the first output line. Image sensor.

10. In the image sensor according to claim 1, The second pixel is arranged adjacent to the first pixel in the row direction. Image sensor.

11. In the image sensor according to claim 10, The second pixel circuit is arranged adjacent to the first pixel circuit in the row direction. Image sensor.

12. In the image sensor according to claim 1, The aforementioned pixel section includes a third pixel which contains at least a third photoelectric conversion unit that converts light into electric charge. The processing circuit unit includes a third pixel circuit which comprises at least a third comparison unit for converting the third pixel signal read from the third pixel into a third digital signal, and a third pixel memory for storing the third digital signal. The readout control circuit controls the timing of reading the second digital signal from the second pixel memory and the timing of reading the third digital signal from the third pixel memory to be different. Image sensor.

13. In the image sensor according to claim 12, The second pixel is positioned between the first pixel and the third pixel in the row direction. Image sensor.

14. In the image sensor according to claim 13, A first selection line from which a first control signal is output for reading the first digital signal and the third digital signal from the first pixel memory and the third pixel memory, respectively, A second selection line on which a second control signal for reading the second digital signal from the second pixel memory is output, Equipped with, The readout control circuit controls the timing at which it outputs the first control signal to the first selection line and the timing at which it outputs the second control signal to the second selection line to be different. Image sensor.

15. In the image sensor according to claim 14, The readout control circuit controls the timing at which the output of the first control signal to the first selected line begins and the timing at which the output of the second control signal to the second selected line begins to begin to be different. Image sensor.

16. In the image sensor according to claim 15, The readout control circuit starts outputting a first control signal to the first selection line, and then starts outputting a second control signal to the second selection line. Image sensor.

17. In the image sensor according to claim 16, The readout control circuit terminates the output of the first control signal to the first selection line, and then starts outputting the second control signal to the second selection line. Image sensor.

18. In the image sensor according to claim 13, A first output line on which the first digital signal read from the first pixel memory is output, A second output line on which the second digital signal read from the second pixel memory is output, The third output line on which the third digital signal read from the third pixel memory is output, An image sensor equipped with the following features.

19. In the image sensor according to claim 18, The readout control circuit controls the timing of reading the first digital signal from the first pixel memory to the first output line and the timing of reading the second digital signal from the second pixel memory to the second output line to be different. Image sensor.

20. In the image sensor according to claim 19, The readout control circuit controls the timing at which the second digital signal is read from the second pixel memory to the second output line and the timing at which the third digital signal is read from the third pixel memory to the third output line to be different. Image sensor.

21. In the image sensor according to claim 19, The readout control circuit controls the timing at which the first digital signal is read out of the first output line and the timing at which the second digital signal is read out of the second output line to be different. Image sensor.

22. In the image sensor according to claim 21, The readout control circuit controls the timing at which the second digital signal is read out of the second output line and the timing at which the third digital signal is read out of the third output line to be different. Image sensor.

23. In the image sensor according to claim 21, The readout control circuit starts reading the first digital signal on the first output line, and then starts reading the second digital signal on the second output line. Image sensor.

24. In the image sensor according to claim 23, The readout control circuit starts reading the third digital signal on the third output line, and then starts reading the second digital signal on the second output line. Image sensor.

25. In the image sensor according to claim 23, The readout control circuit starts reading the second digital signal on the second output line after it has finished reading the first digital signal on the first output line. Image sensor.

26. In the image sensor according to claim 25, The readout control circuit starts reading the second digital signal on the second output line after it has finished reading the third digital signal on the third output line. Image sensor.

27. ​​In the image sensor according to claim 13, The second pixel is arranged adjacent to the first pixel in the row direction. Image sensor.

28. In the image sensor according to claim 27, The second pixel circuit is arranged adjacent to the first pixel circuit in the row direction. Image sensor.

29. In the image sensor according to claim 27, The second pixel is arranged adjacent to the third pixel in the row direction. Image sensor.

30. In the image sensor according to claim 29, The second pixel circuit is arranged adjacent to the third pixel circuit in the row direction. Image sensor.

31. In the image sensor according to any one of claims 1 to 30, The first pixel memory and the second pixel memory are each composed of SRAM. Image sensor.

32. An imaging device comprising the image sensor described in Claim 31.

33. In the imaging device according to claim 32, An imaging device comprising a control unit electrically connected to the image sensor and which generates image data based on the first digital signal and the second digital signal.

34. In the image sensor according to any one of claims 1 to 30, At least a portion of the pixel portion and at least a portion of the processing circuit portion are arranged to face each other in the stacking direction in which the first substrate and the second substrate are stacked. Image sensor.

35. An imaging device comprising the image sensor described in claim 34.

36. In the imaging device according to claim 35, An imaging device comprising a control unit electrically connected to the image sensor and which generates image data based on the first digital signal and the second digital signal.

37. In the image sensor according to claim 34, At least a portion of the first pixel and at least a portion of the first pixel circuit are arranged to face each other in the stacking direction. Image sensor.

38. An imaging device comprising the image sensor described in Claim 37.

39. In the imaging device according to claim 38, An imaging device comprising a control unit electrically connected to the image sensor and which generates image data based on the first digital signal and the second digital signal.

40. In the image sensor according to claim 37, At least a portion of the second pixel and at least a portion of the second pixel circuit are arranged to face each other in the stacking direction. Image sensor.

41. An imaging device comprising the image sensor described in claim 40.

42. In the imaging device according to claim 41, An imaging device comprising a control unit electrically connected to the image sensor and which generates image data based on the first digital signal and the second digital signal.

43. In the image sensor according to any one of claims 1 to 30, The second substrate has a pixel control circuit that controls the first pixel and the second pixel, respectively. Image sensor.

44. An imaging device comprising the image sensor described in claim 43.

45. In the imaging device according to claim 44, An imaging device comprising a control unit electrically connected to the image sensor and which generates image data based on the first digital signal and the second digital signal.

46. In the image sensor according to claim 43, The pixel control circuit controls the exposure time of the first pixel and the exposure time of the second pixel. Image sensor.

47. An imaging device comprising the image sensor described in claim 46.

48. In the imaging device according to claim 47, An imaging device comprising a control unit electrically connected to the image sensor and which generates image data based on the first digital signal and the second digital signal.

49. In the image sensor according to claim 43, The pixel control circuit controls the reading of the first pixel signal from the first pixel and the reading of the second pixel signal from the second pixel. Image sensor.

50. An imaging device comprising the image sensor described in Claim 49.

51. In the imaging device according to claim 50, An imaging device comprising a control unit electrically connected to the image sensor and which generates image data based on the first digital signal and the second digital signal.

52. In the image sensor according to claim 43, The processing circuit section is arranged between the readout control circuit and the pixel control circuit in the row direction. Image sensor.

53. An imaging device comprising the image sensor described in Claim 52.

54. In the imaging device according to claim 53, An imaging device comprising a control unit electrically connected to the image sensor and which generates image data based on the first digital signal and the second digital signal.

55. In the image sensor according to any one of claims 1 to 30, The second substrate has an image processing unit that performs image processing on the first digital signal stored in the first pixel memory and the second digital signal stored in the second pixel memory. Image sensor.

56. An imaging device comprising the image sensor described in claim 55.

57. In the imaging device according to claim 56, An imaging device comprising a control unit electrically connected to the image sensor and which generates image data based on the first digital signal and the second digital signal.

58. In the image sensor according to any one of claims 1 to 30, An image sensor comprising a third substrate, which is laminated together with the first substrate, and which has an image processing unit that performs image processing on the first digital signal stored in the first pixel memory and the second digital signal stored in the second pixel memory.

59. An imaging device comprising the image sensor described in claim 58.

60. In the imaging device according to claim 59, An imaging device comprising a control unit electrically connected to the image sensor and which generates image data based on the first digital signal and the second digital signal.

61. An imaging device comprising an image sensor according to any one of claims 1 to 30.

62. In the imaging device according to claim 61, An imaging device comprising a control unit electrically connected to the image sensor and which generates image data based on the first digital signal and the second digital signal.

Images