Manufacturing method for semiconductor devices
The method uses selective growth masks to form nitride semiconductor layers, addressing the challenge of connecting electrodes to a two-dimensional electron gas channel in nitride semiconductors, ensuring high electrical performance by avoiding interface damage.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- NIPPON TELEGRAPH & TELEPHONE CORP
- Filing Date
- 2022-11-04
- Publication Date
- 2026-06-23
Smart Images
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Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a semiconductor device.
Background Art
[0002] A heterojunction field effect transistor (HFET) or a high electron mobility transistor (HEMT) is a transistor that performs ON / OFF by changing the carrier density in a channel by an electric field generated by a gate voltage.
[0003] When using a nitride semiconductor, for example, by laminating a barrier layer made of AlGaN and a channel layer made of GaN, a two-dimensional electron gas (2DEG) formed by electrons gathering near the interface to compensate for the difference in the magnitude of polarization between them is used as a channel. In a HEMT composed of a general Ga-polarity nitride semiconductor, a gate electrode is formed on a barrier layer of about several nm to several tens of nm, and the 2DEG concentration near the interface between the barrier layer and the channel layer is controlled. Also, there are cases where a channel layer is formed on the barrier layer and a gate electrode is formed on the channel layer.
[0004] In the transistor using the nitride semiconductor described above, a source electrode and a drain electrode are electrically connected (ohmic connection) to the 2DEG serving as a channel. Here, the nitride semiconductor has a problem of high contact resistance due to a large bandgap. To reduce this contact resistance, there is a technique of regrowing n-type impurity-introduced GaN (n-GaN) as a contact layer in the region where the source electrode and the drain electrode are provided. In this technique, the region of the nitride semiconductor layer where the source electrode and the drain electrode are arranged is etched to make it thin, and n-GaN is regrown near the 2DEG serving as a channel.
Prior Art Documents
[0005] [Non-Patent Document 1] SJ Pearton1 et al., "A Review of Dry Etching of GaN and Related Materials", Materials Research Society Internet Journal of Nitride Semiconductor Research, vol. 5, Issue 1, 2000. [Non-Patent Document 2] Shinji Yamada et al., "Reduction of plasma-induced damage in n-type GaN by multistep-bias etching in inductively coupled plasma reactive ion etching", Applied Physics Express, vol. 13, 016505, 2020. [Overview of the project] [Problems that the invention aims to solve]
[0006] Incidentally, as is well known, nitride semiconductors cannot be subjected to general wet etching, so the thinning described above must be carried out by dry etching. However, in dry etching, the etching target surface is struck by etching gas atoms and ions, leaving a damaged layer with many crystal defects on the etched surface (Non-Patent Literature 1). This damaged layer is at the interface with the regrowthed n-GaN layer, and when current is passed through the electrode formed via the n-GaN layer, the drain current flows across this interface. As a result, the many crystal defects formed in the damaged layer at this interface act as traps for carrier electrons, becoming a factor in degrading the electrical characteristics of the transistor.
[0007] To remove the aforementioned damaged layer, there is a technique that involves performing a wet treatment after a dry etching treatment. There is also a technique that gradually reduces the plasma power during the dry etching treatment to thin the remaining damaged layer (Non-Patent Literature 2). However, even with this technique, it is not possible to completely remove the damage. Thus, conventional techniques have had the problem that it is not easy to connect electrodes to the two-dimensional electron gas channel formed near the heterojunction interface of nitride semiconductors without degrading the characteristics of the transistor.
[0008] This invention was made to solve the above-mentioned problems, and aims to connect electrodes to a channel formed by a two-dimensional electron gas near the heterojunction interface of a nitride semiconductor without degrading the characteristics of the transistor. [Means for solving the problem]
[0009] The semiconductor device manufacturing method according to the present invention comprises: a first step of forming a first semiconductor layer by crystal growing a first nitride semiconductor on a substrate in the c-axis direction; a second step of forming a frame-shaped first selective growth mask on the first semiconductor layer, which has a rectangular first aperture in plan view and two wide portions in the center of each of the opposite sides of the rectangle that are wider than other regions; and by selective growth using the first selective growth mask, a second nitride semiconductor different from the first nitride semiconductor is crystal grown in the c-axis direction on the first semiconductor layer exposed at the first aperture, thereby making the first region between the two wide portions wider than the first region. The method comprises: a third step of forming a second semiconductor layer that is thicker than the outer second and third regions; a fourth step of removing the first selective growth mask and then forming a second selective growth mask on the first semiconductor layer that covers the periphery of the second semiconductor layer and the first region of the second semiconductor layer, with a second opening in the second region and a third opening in the third region; and a fifth step of forming a third semiconductor layer and a fourth semiconductor layer by selective growth using the second selective growth mask to crystallize a third nitride semiconductor in the c-axis direction, with n-type impurities introduced in the second and third regions of the second semiconductor layer, respectively. [Effects of the Invention]
[0010] As described above, according to the present invention, a frame-shaped first selective growth mask is used which has a rectangular first aperture in plan view and two wider portions in the center of each of the opposite sides of the rectangle, with a wider width than the other regions. Therefore, electrodes can be connected to a channel formed by a two-dimensional electron gas near the heterojunction interface of the nitride semiconductor without degrading the characteristics of the transistor. [Brief explanation of the drawing]
[0011] [Figure 1A] Figure 1A is a cross-sectional view showing the state of a semiconductor device during an intermediate step in the manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 1B] Figure 1B is a cross-sectional view showing the state of a semiconductor device during an intermediate step in the manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 1C] Figure 1C is a plan view showing the state of a semiconductor device during an intermediate step in the manufacturing process of an embodiment of the present invention. [Figure 1D] Figure 1D is a cross-sectional view showing the state of a semiconductor device during an intermediate step in the manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 1E] Figure 1E is a cross-sectional view showing the state of a semiconductor device during an intermediate step in the manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 1F] Figure 1F is a cross-sectional view showing the state of a semiconductor device during an intermediate step in the manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 1G] Figure 1G is a plan view showing the state of a semiconductor device during an intermediate step in the manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 1H] Figure 1H is a cross-sectional view showing the state of a semiconductor device during an intermediate step in the manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 1I]Figure 1I is a cross-sectional view showing the state of a semiconductor device during an intermediate step in the manufacturing process of a semiconductor device according to an embodiment of the present invention. [Modes for carrying out the invention]
[0012] Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to Figures 1A to 1I.
[0013] First, as shown in Figure 1A, a first nitride semiconductor is crystallized on a substrate 101 in the c-axis direction to form a first semiconductor layer 102 (first step). For example, a buffer layer 111 can be formed on the substrate 101, and the first semiconductor layer 102 can be formed on the buffer layer 111. For example, the first semiconductor layer 102 can be formed by crystallizing the first nitride semiconductor using known epitaxial growth techniques for nitride semiconductors, such as metal-organic vapor deposition (MOVPE). The same applies to the formation of semiconductor layers described later.
[0014] The substrate 101 can be, for example, a sapphire substrate with a chamfered main surface. Alternatively, the substrate 101 can be a crystalline substrate such as SiC, Si, or GaN.
[0015] The buffer layer 111 can be a single-layer or multi-layer structure of a nitride semiconductor such as GaN. Depending on the substrate 101 and the desired performance, the materials of the buffer layer 111 can be appropriately configured. For example, when using a Si substrate, a nucleation layer made of AlN is required in the early stages of growth. In addition, the buffer layer 111 may be a high-resistance layer, in which case carbon-doped GaN can be included in the buffer layer 111.
[0016] For example, by crystal-growing GaN in group-III polarity (Ga polarity) (in the +c-axis direction) on the substrate 101, a buffer layer 111 is formed. Subsequently, by crystal-growing GaN in group-III polarity, a first semiconductor layer 102 made of GaN (a first nitride semiconductor) can be formed. In this case, the surface of the first semiconductor layer 102 becomes the (0001) plane. Also, the first semiconductor layer 102 composed of GaN can be used as a channel layer in a HEMT.
[0017] Also, for example, by crystal-growing GaN in group-V polarity (N polarity) (in the -c-axis direction) on the substrate 101, a buffer layer 111 is formed. Subsequently, by crystal-growing AlGaN in group-V polarity, a first semiconductor layer 102 made of AlGaN (a first nitride semiconductor) can be formed. In this case, the surface of the first semiconductor layer 102 becomes the (000-1) plane. Also, the first semiconductor layer 102 composed of AlGaN can be used as a barrier layer in a N-polarity HEMT.
[0018] Next, as shown in FIGS. 1B and 1C, a first selective growth mask 103 is formed on the first semiconductor layer 102 (second step). Since the first selective growth mask 103 is exposed to a high temperature exceeding 1000°C during selective growth, it is preferably composed of a material with high heat resistance. For example, it can be composed of SiO2.
[0019] The first selective growth mask 103 is formed in a frame shape having a rectangular first opening 103a in plan view. The region of the first opening 103a is the region where the element is formed. Also, in plan view, two wide portions 104 having a wider width than other regions are provided at the center of each of the opposite sides of the rectangle of the first opening 103a.
[0020] Hereinafter, the area between the two wide sections 104 is designated as the first region 131, and the areas outside the first region 131 within the first opening 103a are designated as the second region 132 and the third region 133. In a plan view, the second region 132 and the third region 133 are arranged so as to sandwich the first region 131. Also, in a plan view, the second region 132 and the third region 133 can have the same area. If the element formed in the region of the first opening 103a is, for example, a transistor such as an HEMT, the gate electrode is placed in the first region 131, and the source electrode and drain electrode, which are ohmic electrodes, are placed in the second region 132 and the third region 133.
[0021] Next, by selective growth using the first selective growth mask 103, a second nitride semiconductor, different from the first nitride semiconductor, is crystallized in the c-axis direction on the first semiconductor layer 102 exposed at the first aperture 103a, thereby forming a second semiconductor layer 105 as shown in Figure 1D (third step). The first semiconductor layer 102 and the second semiconductor layer 105 can have different band gaps. A two-dimensional electron gas is formed near the heterojunction interface between the first semiconductor layer 102 and the second semiconductor layer 105.
[0022] When the first semiconductor layer 102 is made of GaN grown with Group III polarity and serves as a channel layer, the second semiconductor layer 105 can be made of AlGaN (second nitride semiconductor). For example, a second semiconductor layer 105 made of AlGaN can be formed by growing AlGaN with Group III polarity on the first semiconductor layer 102 exposed at the first aperture 103a. In this case, the surface of the second semiconductor layer 105 is the (0001) plane. The second semiconductor layer 105 made of AlGaN can serve as a barrier layer in a HEMT.
[0023] Furthermore, when the first semiconductor layer 102 is made of AlGaN grown with group V polarity and used as a barrier layer, the second semiconductor layer 105 can be made of GaN (second nitride semiconductor). For example, a second semiconductor layer 105 made of GaN can be formed by growing GaN with group V polarity on the first semiconductor layer 102 exposed at the first aperture 103a. In this case, the surface of the second semiconductor layer 105 will be the (000-1) plane. The second semiconductor layer 105 made of GaN can be used as the channel layer in a HEMT.
[0024] In the second semiconductor layer 105, the first region 131 between the two wide portions 104 is formed to be thicker than the second region 132 and the third region 133 which are outside the first region 131. As is well known, in crystal growth using a selective growth mask, elements are less likely to adhere to the surface of the selective growth mask than to the surface of the semiconductor layer. For this reason, many of the group III elements such as Ga and In supplied near the surface of the selective growth mask move horizontally across the surface of the selective growth mask relative to the plane of the semiconductor layer (surface migration), and crystals selectively grow on the surface of the semiconductor layer where the selective growth mask is not formed.
[0025] Therefore, the larger the mask area, the more raw material elements move into the surrounding mask-free regions, resulting in a higher crystal growth rate. In other words, crystals growing near a wide mask will be thicker than those growing near a narrow mask.
[0026] The first selective growth mask 103 has a wide portion 104 in the first region 131, and the second region 132 and third region 133, which have narrower mask widths on either side of this, are expected to produce thinner films when selectively grown compared to the first region 131.
[0027] Furthermore, it is desirable that the thickness of the first selective growth mask 103 be approximately the same as or greater than the thickness of the second semiconductor layer 105 to be selectively grown. For example, if the second semiconductor layer 105 is a barrier layer for a GaN HEMT, a typical one has a thickness of about 20 nm, so the thickness of the first selective growth mask 103 can be about the same. Also, if the second semiconductor layer 105 is a channel layer, the thickness of the second semiconductor layer 105 is less restricted compared to the case of a barrier layer. For example, the thickness can be 20 nm in the thicker region of the first region 131 and 5 nm in the thinner regions of the second region 132 and third region 133. In this case, the thickness of the first selective growth mask 103 can be uniformly about 20 nm throughout the entire region of the first region 131 and second region 132.
[0028] Next, after removing the first selective growth mask 103, a second selective growth mask 106 is formed on the first semiconductor layer 102 as shown in Figures 1E, 1F, and 1G (fourth step). Figure 1E shows a cross-section along the aa' line in Figure 1G, and Figure 1F shows a cross-section along the bb' line in Figure 1G.
[0029] The second selective growth mask 106 covers the periphery of the second semiconductor layer 105 and the first region 131 of the second semiconductor layer 105, and has a second opening 106a in the second region 132 and a third opening 106b in the third region 133. Since the second selective growth mask 106 is exposed to high temperatures exceeding 1000°C during selective growth, it is desirable to make it from a heat-resistant material, for example, from SiO2. The first selective growth mask 103 made of SiO2 can be selectively removed by wet etching using hydrofluoric acid. In wet etching using hydrofluoric acid, the nitride semiconductor is not etched.
[0030] Next, a third semiconductor layer 107 and a fourth semiconductor layer 108 are formed by selective growth using a second selective growth mask 106, as shown in Figure 1H (fifth step). The third semiconductor layer 107 and the fourth semiconductor layer 108 can be formed by crystal growth in the c-axis direction of a third nitride semiconductor in which n-type impurities are introduced on the second region 132 and the third region 133 of the second semiconductor layer 105, respectively. The third semiconductor layer 107 and the fourth semiconductor layer 108 are so-called contact layers used to reduce the contact resistance of the device (HEMT), and can be made of n-type GaN, for example.
[0031] After forming the third semiconductor layer 107 and the fourth semiconductor layer 108 as described above, the second selective growth mask 106 is removed. The second selective growth mask 106, which is made of SiO2, can be selectively removed by wet etching using hydrofluoric acid. In wet etching using hydrofluoric acid, the nitride semiconductor is not etched.
[0032] Next, as shown in Figure 1I, the first electrode 109 and the second electrode 110 are formed (step 6). The first electrode 109 and the second electrode 110 are ohmic connected to the third semiconductor layer 107 and the fourth semiconductor layer 108, respectively. For example, a lift-off mask (not shown) having openings in each electrode formation region is formed, and Ti / Al / Ni / Au is deposited on it by sputtering or vapor deposition. After this, the lift-off mask is removed (lift-off) to form the first electrode 109 and the second electrode 110.
[0033] The first electrode 109 and the second electrode 110 can be used as the source and drain electrodes of a transistor such as a HEMT. Furthermore, after forming the first electrode 109 and the second electrode 110, a Schottky junction gate electrode (not shown) can be formed on the surface of the second semiconductor layer 105 between the first electrode 109 and the second electrode 110 to create a field-effect transistor (HEMT).
[0034] As described above, according to the present invention, a frame-shaped first selective growth mask is used which has a rectangular first aperture in plan view and two wider portions in the center of each of the opposite sides of the rectangle, with a wider width than the other regions. This makes it possible to connect electrodes to a channel formed by a two-dimensional electron gas near the heterojunction interface of the nitride semiconductor without degrading the characteristics of the transistor. According to the present invention, since the contact layer can be formed by thinning without using dry etching, no interface damage layer is formed between the thinned semiconductor layer surface and the contact layer, and the electrical characteristics of the transistor are not degraded.
[0035] It should be noted that the present invention is not limited to the embodiments described above, and it is clear that many modifications and combinations can be implemented within the technical concept of the present invention by those with ordinary skill in the art. [Explanation of symbols]
[0036] 101...Substrate, 102...First semiconductor layer, 103...First selective growth mask, 103a...First aperture, 104...Wide portion, 105...Second semiconductor layer, 106...Second selective growth mask, 106a...Second aperture, 106b...Third aperture, 107...Third semiconductor layer, 108...Fourth semiconductor layer, 109...First electrode, 110...Second electrode, 111...Buffer layer, 131...First region, 132...Second region, 133...Third region.
Claims
1. A first step involves growing a first nitride semiconductor crystal on a substrate in the c-axis direction to form a first semiconductor layer, A second step of forming a frame-shaped first selective growth mask on the first semiconductor layer, the first selective growth mask having a rectangular first aperture in plan view, and having two wider portions in the center of each of the opposite sides of the rectangle, which are wider than the other regions; A third step involves selective growth using the first selective growth mask to grow a second nitride semiconductor, different from the first nitride semiconductor, in the c-axis direction on the first semiconductor layer exposed in the first opening, thereby forming a second semiconductor layer in the first region between the two wide portions, which is thicker than the second and third regions outside the first region. A fourth step is to remove the first selective growth mask and then form a second selective growth mask on the first semiconductor layer, covering the periphery of the second semiconductor layer and the first region of the second semiconductor layer, with a second opening in the second region and a third opening in the third region. A fifth step involves selective growth using the second selective growth mask to form a third semiconductor layer and a fourth semiconductor layer by crystal growing a third nitride semiconductor in the c-axis direction, in which n-type impurities are introduced on the second and third regions of the second semiconductor layer, respectively. A method for manufacturing a semiconductor device comprising the same equipment.
2. In the method for manufacturing a semiconductor device according to claim 1, A method for manufacturing a semiconductor device, characterized in that the first semiconductor layer and the second semiconductor layer have different band gaps, and a two-dimensional electron gas is formed near the heterojunction interface between the first semiconductor layer and the second semiconductor layer.
3. In the method for manufacturing a semiconductor device according to claim 1 or 2, A method for manufacturing a semiconductor device, further comprising a sixth step of removing the second selective growth mask and then forming ohmic-connected first and second electrodes on the third and fourth semiconductor layers, respectively.