Semiconductor equipment

Abstract

Provided is a semiconductor device with which it is possible to improve the reliability of insulation around a bonding wire. This semiconductor device comprises: a semiconductor chip (3) having a first main electrode (31) on the upper surface side and a second main electrode (33) on the lower surface side; a bonding wire (4b) connected to the first main electrode (31); an insulating layer (9b) covering the outer periphery of the bonding wire (4b); and a sealing member (7) for sealing the semiconductor chip (3), the bonding wire (4b) and the insulating layer (4b). The ratio of the Young's modulus of the insulating layer (9b) to the Young's modulus of the sealing member (7) is 10 or more.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device (semiconductor module).

Background Art

[0002] Patent Document 1 discloses coating the connection portion of bonding wires on a chip with resin. Patent Document 2 discloses that aluminum wires bonded to a semiconductor element are coated with a primer layer, and the aluminum wires coated with the primer layer are covered with a first sealing layer. Patent Document 3 discloses a circuit board having a semiconductor element mounted via bonding wires and covering the semiconductor element and the bonding wires with a resin coating material, and covering the surface of the resin coating material with silicone gel.

[0003] Patent Document 4 discloses a power semiconductor device in which a semiconductor element and aluminum wires are sealed with an epoxy resin and sealed with a silicone gel-based resin so as to cover the epoxy resin. Patent Document 5 discloses coating bonding wires connected to a semiconductor element with resin. Patent Document 6 discloses that bonding wires connected between a substrate and a case and their connection portions are coated with a resin having a higher hardness than gel.

[0004] Patent Document 7 discloses a semiconductor device including wiring connected to a semiconductor element, a resin sealing member for sealing the semiconductor element, and a semiconductive film covering at least a part of the wiring and disposed between at least a part of the wiring and the resin sealing member. Patent Document 8 discloses a semiconductor device including bonding wires joined to a semiconductor element, a resin layer covering the joining portion of the bonding wires on the surface of the semiconductor element, and a gel filler for sealing the semiconductor element, the bonding wires, and the resin layer.

[0005] Patent Document 9 discloses a bonding wire for a semiconductor device comprising a bonding wire and a copper ion diffusion suppression layer covering the surface of the bonding wire. Patent Document 10 discloses coating a bonding wire with a foam polymer. Patent Document 11 discloses a coated wire in which the core wire is coated with a coating resin. Patent Document 12 discloses a semiconductor device in which the metal terminals and leads of a semiconductor chip are connected by a coated wire, and the coated wire and the connection portion of the coated wire are covered with resin.

[0006] Patent document 13 discloses a coated wire in which the core wire is covered with a coating resin. Patent documents 14 and 15 each disclose connecting the metal terminals and leads of a semiconductor chip using a coated wire in which the surface of a metal wire is covered with an insulating coating film. Patent document 16 discloses a semiconductor device having a bonding wire for connecting a substrate and a semiconductor element, a first sealing layer that seals the space below the top of the bonding wire, and a second sealing layer provided on top of the first sealing layer via the bonding wire. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2007-012831 [Patent Document 2] Japanese Patent Publication No. 2021-150466 [Patent Document 3] Japanese Patent Publication No. 2000-228482 [Patent Document 4] Japanese Patent Publication No. 2012-15222 [Patent Document 5] Japanese Patent Publication No. 2019-9171 [Patent Document 6] Japanese Patent Publication No. 2022-7343 [Patent Document 7] Japanese Patent Publication No. 2017-224778 [Patent Document 8] Japanese Patent Publication No. 2017-147327 [Patent Document 9] Japanese Patent Publication No. 2012-231034 [Patent Document 10] Japanese Patent Publication No. 2002-170842 [Patent Document 11] Japanese Patent Application Publication No. 9-260414 [Patent Document 12] Japanese Patent Application Publication No. 8-316264 [Patent Document 13] Japanese Patent Application Publication No. 2-304943 [Patent Document 14] Japanese Patent Application Publication No. 2-266541 [Patent Document 15] Japanese Patent Publication No. 63-318132 [Patent Document 16] International Publication No. 2019 / 31513 [Overview of the project] [Problems that the invention aims to solve]

[0008] When voids form around bonding wires connected to semiconductor chips, such as air bubbles inside the sealing material or delamination of the sealing material, the electric field strength increases in these voids, reducing insulation reliability.

[0009] In view of the above issues, this disclosure aims to provide a semiconductor device that can improve the insulation reliability around bonding wires. [Means for solving the problem]

[0010] One aspect of the present disclosure is a semiconductor device comprising a semiconductor chip having a first main electrode on its upper surface and a second main electrode on its lower surface, a bonding wire connected to the first main electrode, an insulating layer covering the outer circumference of the bonding wire, and a sealing member for sealing the semiconductor chip, the bonding wire, and the insulating layer, wherein the ratio of the Young's modulus of the insulating layer to the Young's modulus of the sealing member is 10 or more. [Effects of the Invention]

[0011] According to the present disclosure, a semiconductor device capable of improving the insulation reliability around a bonding wire can be provided.

Brief Description of the Drawings

[0012] [Figure 1] It is a cross-sectional view of an example of a semiconductor device according to an embodiment. [Figure 2] It is a perspective view of another example of a semiconductor device according to an embodiment. [Figure 3] It is a schematic view of a bonding wire, an insulating layer, and a sealing member according to an embodiment. [Figure 4] It is a graph showing the relationship between the coating thickness and the electric field strength of a bonding wire according to an embodiment. [Figure 5] It is a graph showing the relationship between the wire diameter and the electric field strength of a bonding wire according to an embodiment.

Embodiments for Carrying Out the Invention

[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and duplicate descriptions are omitted. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of the respective layers, etc. may be different from the actual ones. Also, there may be parts where the dimensional relationships and ratios are different between the drawings. Further, the embodiments shown below are examples of devices and methods for embodying the technical idea of the present disclosure, and the technical idea of the present disclosure does not specify the materials, shapes, structures, arrangements, etc. of the components as the following.

[0014] Also, the definitions of directions such as up and down, left and right in the following description are merely for convenience of explanation and do not limit the technical idea of the present disclosure. For example, if the object is rotated 90° and observed, up and down are read as left and right, and if it is rotated 180° and observed, up and down are read in reverse, which is of course.

[0015] Furthermore, in the following explanation, the "first main electrode" of a semiconductor chip refers to the electrode through which the main current flows in or out of the semiconductor chip. If the semiconductor chip is a field-effect transistor (FET) or electrostatic induction transistor (SIT), the "first main electrode" refers to either the source electrode or the drain electrode. If the semiconductor chip is an insulated-gate bipolar transistor (IGBT), the "first main electrode" refers to either the emitter electrode or the collector electrode. If the semiconductor chip is an electrostatic induction (SI) thyristor or a gate-turn-off (GTO) thyristor, the "first main electrode" refers to either the anode electrode or the cathode electrode. Furthermore, if the semiconductor chip is an FET or SIT, the "second main electrode" refers to either the source electrode or the drain electrode that is not the first main electrode. If the semiconductor chip is an IGBT, the "second main electrode" refers to either the emitter electrode or the collector electrode that is not the first main electrode. If the semiconductor chip is an SI thyristor or a GTO thyristor, the "second main electrode" refers to either the anode electrode or the cathode electrode that is not the first main electrode. In other words, if the "first main electrode" of a semiconductor chip is the source electrode, then the "second main electrode" is the drain electrode. If the "first main electrode" of a semiconductor chip is the emitter electrode, then the "second main electrode" is the collector electrode. If the "first main electrode" of a semiconductor chip is the anode electrode, then the "second main electrode" is the cathode electrode.

[0016] (Embodiment) <Configuration of semiconductor device> As shown in Figure 1, the semiconductor device (semiconductor module) according to the embodiment comprises an insulating circuit board 1 and a power semiconductor chip (semiconductor chip) 3 provided on one main surface (upper surface) of the insulating circuit board 1 via a bonding layer 2. A case 5 is arranged to surround the outer periphery of the insulating circuit board 1, the bonding layer 2, and the semiconductor chip 3. Terminals (external connection terminals) 6a and 6b are attached to the case 5. The insulating circuit board 1, the semiconductor chip 3, and the external connection terminals 6a and 6b are electrically connected to each other via bonding wires 4a to 4c. Inside the case 5, a sealing member (sealing resin) 7 is provided to seal the insulating circuit board 1, the bonding layer 2, the semiconductor chip 3, the bonding wires 4a to 4c, the insulating layers 9a to 9c, etc.

[0017] The insulating circuit board 1 is made of, for example, a direct copper bond (DCB) substrate or an activated brazing (AMB) substrate. The insulating circuit board 1 comprises an insulating plate 10, conductive layers 11a and 11b provided on one main surface (upper surface) of the insulating plate 10, and a conductive layer 12 provided on the other main surface (lower surface) of the insulating plate 10. The insulating plate 10 is made of, for example, a ceramic substrate using aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), etc., or a resin insulating substrate using polymer materials, etc. The conductive layers 11a, 11b, and 12 are made of, for example, conductive foil using copper (Cu) or aluminum (Al).

[0018] The bonding layer 2 is composed of, for example, solder or sintered material. As for the solder, lead-free solders such as tin-antimony (Sn-Sb), tin-copper (Sn-Cu), tin-copper-silver (Sn-Cu-Ag), tin-silver (Sn-Ag), tin-silver-copper (Sn-Ag-Cu), tin-silver-bismuth-copper (Sn-Ag-Bi-Cu), tin-indium-silver-bismuth (Sn-In-Ag-Bi), tin-zinc (Sn-Zn), tin-zinc-bismuth (Sn-Zn-Bi), tin-bismuth (Sn-Bi), and tin-indium (Sn-In) systems, or lead solders such as tin-lead (Sn-Pb) systems can be used. Sintered materials are constructed by heating and pressurizing a sheet-like sintered sheet or a paste-like conductive paste containing fine metal particles with a particle size of several nanometers to several micrometers, such as gold (Au), silver (Ag), or copper (Cu), and organic components (binders), and sintering them.

[0019] The semiconductor chip 3 is composed of, for example, an insulated-gate bipolar transistor (IGBT), a field-effect transistor (FET), an electrostatic induction (SI) thyristor, a gate turn-off (GTO) thyristor, a freewheeling diode (FWD), etc. Here, the case where the semiconductor chip 3 is a MOSFET is given as an example. The semiconductor chip 3 may be constructed on, for example, a silicon (Si) substrate, or on a semiconductor substrate using a wide-bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), or diamond.

[0020] The maximum rated voltage of semiconductor chip 3 is, for example, approximately 1.7kV or higher. The maximum rated voltage of semiconductor chip 3 may be approximately 1.7kV or lower, or approximately 3.3kV or higher. The higher the maximum rated voltage of semiconductor chip 3, the greater the required insulation distance between each component.

[0021] The semiconductor chip 3 has a first main electrode (source electrode) 31 and a gate electrode 32 on one main surface (top surface), and a second main electrode (drain electrode) 33 on the other main surface (bottom surface). The second main electrode 33 is bonded to the conductive layer 11a via a junction layer 2. Figure 1 shows an example of one semiconductor chip 3, but the number of semiconductor chips can be appropriately set according to the current capacity of the semiconductor module, and there may be two or more semiconductor chips.

[0022] Case 5 is composed of a thermoplastic resin such as polyphenylene sulfide (PPS) or polybutylene terephthalate (PBT).

[0023] The external connection terminals 6a and 6b are made of a metallic material such as copper (Cu) or aluminum (Al). The external connection terminals 6a and 6b can be connected to an external circuit. The shape, position, and number of the external connection terminals 6a and 6b are not particularly limited. The external connection terminals 6a and 6b may be joined to the conductive layers 11a and 11b via a bonding layer such as solder or sintered material, without using bonding wires 4a and 4c.

[0024] One end of the bonding wire 4a is connected to the conductive layer 11a, and the other end of the bonding wire 4a is connected to the external connection terminal 6a. The second main electrode 33 of the semiconductor chip 3 is electrically connected to the external connection terminal 6a via the conductive layer 11a and the bonding wire 4a.

[0025] One end of bonding wire 4b is connected to the first main electrode 31 of the semiconductor chip 3, and the other end of bonding wire 4b is connected to the conductive layer 11b. One end of bonding wire 4c is connected to the conductive layer 11b, and the other end of bonding wire 4c is connected to the external connection terminal 6b. The first main electrode 31 of the semiconductor chip 3 is electrically connected to the external connection terminal 6b via bonding wire 4b, conductive layer 11b, and bonding wire 4c.

[0026] Although not shown in Figure 1, the gate electrode 32 of the semiconductor chip 3 is electrically connected to other external connection terminals (not shown) that can be connected to an external circuit via bonding wires (not shown), etc.

[0027] In Figure 1, the potential of bonding wire 4a is the same as that of external connection terminal 6a, which is electrically connected to the second main electrode 33 of semiconductor chip 3, and is different from that of external connection terminal 6b, which is electrically connected to the first main electrode 31 of semiconductor chip 3. The potentials of bonding wires 4b and 4c are the same as that of external connection terminal 6b and are different from that of external connection terminal 6a.

[0028] For example, the bonding wire 4a may be at a distance of 5 mm or less from the external connection terminal 6b, which has a different potential from the bonding wire 4a, via the sealing member 7. The bonding wires 4b and 4c may be at a distance of 5 mm or less from the external connection terminal 6a, which has a different potential from the bonding wires 4b and 4c, via the sealing member 7.

[0029] The bonding wires 4a to 4c are made of a metallic material such as copper (Cu), aluminum (Al), or gold (Au). The diameter of the bonding wires 4a to 4c is, for example, approximately 125 μm or more and 500 μm or less. The diameter of the bonding wires 4a to 4c may be approximately 400 μm or less, or approximately 300 μm or less. The smaller the diameter of the bonding wires 4a to 4c, the smaller the pads connecting the bonding wires 4a to 4c can be, and the smaller the size of the element can be. On the other hand, the smaller the diameter of the bonding wires 4a to 4c, the higher the electric field strength around the bonding wires 4a to 4c, so the required insulation distance between the bonding wires 4a to 4c and each component becomes larger.

[0030] The sealing member 7 is made of a resin material such as gel-like silicone (silicone gel) or fluorine-based gel. The Young's modulus of the sealing member 7 is, for example, about 1 kPa or more and 100 kPa or less. The relative permittivity of the sealing member 7 is, for example, about 3 or more and 5 or less.

[0031] The sealing member 7 has the function of mechanically protecting the internal circuit from foreign matter. For example, if conductive foreign matter adheres to exposed circuitry, the circuit will short-circuit and fail. Even foreign matter with low conductivity can cause a short-circuit failure due to tracking. By covering the internal circuitry with the sealing member 7, such failures can be prevented.

[0032] Furthermore, the sealing member 7 has the function of insulating between electrodes (between circuits). By covering and filling the circuit surface including the element surface, bonding wire surface, terminal surface, and between electrodes (between circuits) with the sealing member 7, insulation reliability is ensured. With insulation between electrodes using the sealing member 7, the insulation distance can be made significantly shorter than with insulation using air, enabling miniaturization of modules through high-density mounting.

[0033] The gels, such as silicone gel, that make up the sealing member 7 are soft and highly flexible, making them difficult to peel off, but they are also highly hygroscopic (moisture-permeable), making them prone to generating air bubbles. While hardening the sealing member 7 can suppress the generation of air bubbles, it reduces its flexibility to conform to bonding wires 4a-4c, making it more prone to peeling. Furthermore, there are countless tiny gaps in the joint between the sealing member 7 and the other members, making it technically difficult to completely eliminate voids during construction. Also, filling the voids with resin would lead to excessive stress during thermal cycling, increasing the risk of failure during heat cycles and power cycles. Moreover, completely filling the voids in large modules is difficult.

[0034] Since the silicone gel or other gel that constitutes the sealing member 7 has a higher dielectric constant than air, if air bubbles or delamination of the sealing member 7 occur between the electrodes, the electric field strength increases in the air gap, reducing insulation reliability. For example, if an air gap occurs, the discharge initiation voltage drops to about 1 / 3. In particular, electric field concentration is likely to occur on the surface of bonding wires 4a to 4c, so the discharge initiation voltage drops to about 1 / 6 compared to other regions, and the thinner the bonding wires 4a to 4c are, the lower the insulation performance becomes.

[0035] If the maximum rated voltage of semiconductor chip 3 is around 1.7kV or less, even if there is an air gap between the electrodes, the required insulation distance for bonding wires 4a to 4c is relatively small, so there are few design constraints (for miniaturization). However, if the maximum rated voltage of semiconductor chip 3 is high-voltage, such as 3.3kV or more, the required insulation distance for bonding wires 4a to 4c with a diameter of about 300μm becomes larger than the required insulation distance for bonding wires 4a to 4c with a diameter of about 125μm when the maximum rated voltage is around 1.7kV or less, which becomes an obstacle to miniaturization.

[0036] For example, if the distance between the different potentials of bonding wires 4a and 4c is short, such as 5 mm or less, the electric field strength increases, and if bubbles form around the bonding wires 4a and 4c, the insulation performance deteriorates significantly, increasing the risk of discharge and short-circuit failure. Increasing the distance between the different potentials of bonding wires 4a and 4c can reduce the risk of short-circuit failure due to bubble formation, but with increasing voltage, miniaturization, and high-density mounting, it is becoming difficult to maintain a sufficient insulation distance. While using thicker bonding wires is effective in mitigating the electric field, it increases chip area and cost, and it is also necessary to avoid damaging the pads to which the bonding wires are connected.

[0037] Therefore, in the semiconductor device according to this embodiment, the outer circumference of the bonding wires 4a to 4c is covered with insulating layers (coating layers) 9a to 9c. The insulating layers 9a to 9c include, for example, at least one resin selected from polyamide resin, polyimide resin, polyamide-imide resin, polyester resin, epoxy resin, phenolic resin, fluororesin, acrylic resin, silicone resin, polyolefin resin, and polyetherimide resin. The insulating layers 9a to 9c may also include two or more resins selected from the above resins.

[0038] As a method for forming insulating layers 9a to 9c on the outer circumference of bonding wires 4a to 4c, the bonding wires 4a to 4c may be bonded to the first main electrode 31, conductive layers 11a and 11b, external connection terminals 6a and 6b, etc. of the semiconductor chip 3, and then the insulating layers 9a to 9c may be formed by spray coating, dipping coating, or dispensing coating. Alternatively, bonding wires 4a to 4c that are pre-coated with insulating layers 9a to 9c, such as enameled wire, may be prepared, and these bonding wires 4a to 4c may be bonded to the first main electrode 31, conductive layers 11a and 11b, external connection terminals 6a and 6b, etc. of the semiconductor chip 3.

[0039] Figure 1 illustrates a case where all bonding wires 4a to 4c are covered with insulating layers 9a to 9c, but only some of the bonding wires 4a to 4c may be covered with insulating layers. For example, if bonding wire 4b is close to an external connection terminal 6a or other part with a different potential than bonding wire 4b, only the bonding wire 4b close to the part with the different potential may be covered with insulating layer 9b. By selectively covering only some of the bonding wires 4a to 4c with insulating layers, material costs and process costs can be reduced.

[0040] The insulating layers 9a to 9c are harder than the sealing member 7, and the Young's modulus of the insulating layers 9a to 9c is higher than that of the sealing member 7. The Young's modulus of the insulating layers 9a to 9c is, for example, about 100 kPa or more and 10 GPa or less, more preferably about 100 kPa or more and 1 GPa or less. By having a Young's modulus of 100 kPa or more for the insulating layers 9a to 9c, the generation of air bubbles inside the insulating layers 9a to 9c can be effectively suppressed. By having a Young's modulus of 1 GPa or less for the insulating layers 9a to 9c, good conformability of the insulating layers 9a to 9c to the bonding wires 4a to 4c can be ensured.

[0041] The ratio of the Young's modulus of the insulating layers 9a to 9c to the Young's modulus of the sealing member 7 is, for example, about 10 or more. By setting the ratio of the Young's modulus of the insulating layers 9a to 9c to the Young's modulus of the sealing member 7 to 10 or more, the generation of air bubbles inside the insulating layers 9a to 9c can be effectively suppressed.

[0042] The dielectric constant of the insulating layers 9a to 9c may be higher or lower than the relative permittivity of the sealing member 7. The lower the relative permittivity of the insulating layers 9a to 9c, the more the electric field strength can be mitigated even if air bubbles are generated inside the sealing member 7 and an air layer with a dielectric constant of 1 is inserted. The relative permittivity of the insulating layers 9a to 9c is, for example, about 7 or less, and more preferably about 3 or less. By setting the relative permittivity of the insulating layers 9a to 9c to 7 or less, the electric field strength can be mitigated even if air bubbles are generated inside the sealing member 7. By setting the relative permittivity of the insulating layers 9a to 9c to 3 or less, the electric field strength can be further reduced even if air bubbles are generated inside the sealing member 7. Lowering the relative permittivity of the insulating layers 9a to 9c is the opposite of the technical concept of stepped insulation, which averages the electric field strength applied to each layer by stacking insulating layers with higher dielectric constants closer to the core material.

[0043] The smaller the ratio of the dielectric constant of the insulating layers 9a to 9c to the dielectric constant of the sealing member 7, the more the electric field strength on the surface side (sealing member 7 side) of the insulating layers 9a to 9c can be reduced. The ratio of the dielectric constant of the insulating layers 9a to 9c to the dielectric constant of the sealing member 7 is, for example, about 3 or less. By having a ratio of the dielectric constant of the insulating layers 9a to 9c to the dielectric constant of the sealing member 7 of 3 or less, the electric field strength on the surface side of the insulating layers 9a to 9c can be effectively reduced. The ratio of the dielectric constant of the insulating layers 9a to 9c to the dielectric constant of the sealing member 7 may be about 2 or less, about 1 or less, or about 0.5 or less.

[0044] The thickness of the insulating layers 9a to 9c can be adjusted by adjusting the viscosity of the insulating layers 9a to 9c before curing, the lifting speed in the case of dip coating, and the number of coats in the case of spray coating or dip coating. The thickness of the insulating layers 9a to 9c may be approximately constant, or it may not be constant, with some parts being thicker and others thinner. The thicker the insulating layers 9a to 9c, the more the electric field strength on the surface side (sealing member 7 side) of the insulating layers 9a to 9c can be reduced. The thickness of the insulating layers 9a to 9c is, for example, about 25 μm or more and 500 μm or less. By making the thickness of the insulating layers 9a to 9c 25 μm or more, the electric field strength on the surface side of the insulating layers 9a to 9c can be effectively reduced.

[0045] A heat dissipation base 8 is provided on the other main surface (bottom surface) of the insulating circuit board 1 via a bonding layer 14. The bonding layer 14 is made of, for example, a sintered material or solder. The bonding layer 14 may be made of the same material as the bonding layer 2, or it may be made of a different material. The heat dissipation base 8 is made of, for example, a metal such as copper (Cu).

[0046] A heat dissipation fin 13 is provided on the lower side of the heat dissipation base 8 via a bonding layer 15. Alternatively, the heat dissipation fin 13 may be provided on the lower side of the insulating circuit board 1 via the bonding layer 15 without the heat dissipation base 8. Heat dissipation base 8 The underside may be exposed.

[0047] The heat dissipation fins 13 are made of a metal such as copper (Cu). The bonding layer 15 is made of a sintered material, solder, or thermal interface material (TIM). As the TIM, thermal conductive materials (thermal compounds) such as thermal conductive grease, elastomer sheets, room-temperature curing (RTV) rubber, gel, phase change material, and silver solder can be used. The bonding layer 15 may be made of the same material as bonding layers 2 and 14, or it may be made of a different material.

[0048] Figure 2 is a perspective view of another example of a semiconductor device according to the embodiment. Multiple semiconductor chips 3a to 3d are provided on the upper surface of the conductive layer 11a via bonding layers 2a to 2d. An external connection terminal 6a is provided on the upper surface of the conductive layer 11a via bonding layer 2e. An external connection terminal 6b is provided on the upper surface of the conductive layer 11b via bonding layer 2f. A case 5 is provided so as to surround the conductive layers 11a, 11b, bonding layers 2a to 2f and semiconductor chips 3a to 3d. In Figure 2, the sealing member 7 that is filled inside the case 5 and seals the conductive layers 11a, 11b, bonding layers 2a to 2f and semiconductor chips 3a to 3d is not shown.

[0049] Multiple bonding wires 4a, each coated with an insulating layer 9a, electrically connect the first main electrode on the upper surface of semiconductor chip 3a, the first main electrode on the upper surface of semiconductor chip 3c, and the conductive layer 11b. Bonding wires 4b, coated with an insulating layer 9b, electrically connect the first main electrode on the upper surface of semiconductor chip 3b, the first main electrode on the upper surface of semiconductor chip 3d, and the conductive layer 11b.

[0050] In Figure 2, the potential of the bonding wires 4a and 4b is the same as that of the external connection terminal 6b, which is electrically connected to the first main electrode on the upper surface of the semiconductor chips 3a to 3d, and is different from the potential of the external connection terminal 6a, which is electrically connected to the second main electrode on the lower surface of the semiconductor chips 3a to 3d. The distance between the bonding wires 4a and 4b and the external connection terminal 6a, which has a different potential from that of the bonding wires 4a and 4b, via the sealing member 7 may be approximately 5 mm or less. For example, only the bonding wire 4a closest to the external connection terminal 6a may be close to the external connection terminal 6a at a distance of approximately 5 mm or less and covered with the insulating layer 9a, while the other bonding wires 4a and 4b may be further away from the external connection terminal 6a than 5 mm and may not be covered with the insulating layer.

[0051] Figure 3 shows the bonding wire 4a, insulating layer 9a, and sealing member 7 in a longitudinal cross-section of the bonding wire 4a, with the sealing member 7 modeled as a cylinder coaxial with the bonding wire 4a. The outer surface of the sealing member 7 corresponds to the terminal surface at a different potential. The electric field concentration around the bonding wire 4a is maximum.

[0052] In Figure 3, ε1 is the relative permittivity of the insulating layer 9a, ε2 is the relative permittivity of the sealing member 7, a is the radius of the bonding wire 4a, b is the distance between the center of the bonding wire 4a and the terminal surface, and c is the outer radius of the insulating layer 9a.

[0053] Here, let a' be the radius of the uncoated bonding wire and b' be the distance between the center of the uncoated bonding wire and the terminal surface. The electric field strength E(r) of the uncoated bonding wire can be expressed by the following equation (1).

[0054]

number

[0055] On the other hand, as shown in Figure 3, in a bonding wire 4a covered with an insulating layer 9a, the electric field strength E1(r) inside the insulating layer 9a and the electric field strength E2(r) outside the insulating layer 9a can be expressed by the following equations (2) and (3), respectively.

[0056]

number

[0057]

number

[0058] In the semiconductor device according to this embodiment, the thickness (ca) of the insulating layer 9a is set such that E2(a,b,c,r=c)≦E(a',b',r=a'). This is particularly effective in regions where the distance between different potentials (ba) and (b'-a') is about 5 mm or less.

[0059] Figure 4 shows the relationship between the thickness of the insulating layer and the electric field strength on the surface side (sealing member side) of the insulating layer when a bonding wire covered with an insulating layer is applied between the bonding wire and a terminal of different potential, with a distance of 5 mm between the bonding wire and the terminal. The bonding wires have two diameters, 300 μm and 400 μm, and the ratio of the relative permittivity ε1 of the insulating layer to the relative permittivity ε2 of the sealing member (ε1 / ε2) is 0.5, 1, and 2.

[0060] Figure 5 shows, as a comparative example of a semiconductor device according to the embodiment, the relationship between the diameter of the bonding wire and the electric field strength on the surface side of the bonding wire when the distance between the bonding wire and a terminal at a different potential is 5 mm and 3.3 kV is applied between the bonding wire and the terminal. For convenience, in Figures 4 and 5, auxiliary dashed lines are added at the positions of the electric field strengths corresponding to the diameters of the uncoated bonding wire in Figure 5, which are 400 μm and 500 μm, respectively.

[0061] As shown in Figure 4, in a bonding wire coated with an insulating layer, the electric field strength can be reduced as the thickness of the insulating layer increases, regardless of whether the diameter is 300 μm or 400 μm. Furthermore, in a bonding wire coated with an insulating layer, the electric field strength can be reduced as the ratio (ε1 / ε2) of the relative permittivity ε1 of the insulating layer to the relative permittivity ε2 of the sealing member is small, regardless of whether the diameter is 300 μm or 400 μm.

[0062] As shown in Figures 4 and 5, in a bonding wire covered with an insulating layer, if the ratio of the relative permittivity ε1 of the insulating layer to the relative permittivity ε2 of the sealing member (ε1 / ε2) is 0.5 and the diameter is 300 μm, then if the thickness of the insulating layer is 25 μm or more, the electric field strength can be reduced to the same extent as in the case of an uncoated bonding wire with a diameter of 400 μm.

[0063] Furthermore, as shown in Figures 4 and 5, in the case of a bonding wire covered with an insulating layer, where the ratio of the relative permittivity ε1 of the insulating layer to the relative permittivity ε2 of the sealing member (ε1 / ε2) is 0.5 and the diameter is 300 μm, if the thickness of the insulating layer is 50 μm or more, the electric field strength can be reduced to the same extent as in the case of an uncoated bonding wire with a diameter of 500 μm.

[0064] Furthermore, as shown in Figures 4 and 5, in the case of a bonding wire covered with an insulating layer, where the ratio of the relative permittivity ε1 of the insulating layer to the relative permittivity ε2 of the sealing member (ε1 / ε2) is 0.5 and the diameter is 400 μm, if the thickness of the insulating layer is 25 μm or more, the electric field strength can be reduced to the same extent as in the case of an uncoated bonding wire with a diameter of 500 μm.

[0065] In the semiconductor device according to the embodiment, as shown in Figures 1 and 2, the outer circumference of the bonding wires 4a to 4c, where electric fields tend to concentrate, is covered with insulating layers 9a to 9c that are harder than the sealing member 7, such as silicone gel. This suppresses the generation of air bubbles inside the insulating layers 9a to 9c, and thus suppresses the generation of air bubbles between the bonding wires 4a to 4c and the sealing member 7. Therefore, even if peeling of the sealing member 7 or air bubbles cannot be completely suppressed, the insulating layers 9a to 9c are interposed between the sealing member 7 and the bonding wires 4a to 4c, thereby improving insulation reliability.

[0066] For example, with uncoated bonding wires, bubbles generated in the sealing member near the bonding wire or at the interface between the sealing member and other materials cling to the bonding wire, forming voids around the bonding wire similar to those caused by delamination. In contrast, according to the semiconductor device of this embodiment, the outer circumference of the bonding wires 4a to 4c is covered by insulating layers 9a to 9c, so bubbles generated at the interface between the sealing member and other materials do not reach the bonding wire. This also suppresses the generation of bubbles near the bonding wire and prevents the formation of voids.

[0067] Therefore, according to the semiconductor device of this embodiment, even if the maximum rated voltage of the semiconductor chip 3 is high-voltage, such as 3.3kV or more, an electric field relaxation effect equivalent to that of thicker wires can be obtained without changing the wire diameter, making it possible to design a miniaturized device equivalent to one with a maximum rated voltage of approximately 1.7kV for the semiconductor chip 3. For example, even if the maximum rated voltage of the semiconductor chip 3 is approximately 3.3kV, relatively thin bonding wires 4a to 4c with a diameter of approximately 300μm can be used, and the size of the gate pad used only for signal input on the element surface can be reduced. In particular, with SiC elements and the like, which are more expensive than Si elements, the element size can be reduced, thus reducing costs.

[0068] Furthermore, according to the semiconductor device of this embodiment, since the insulating layers 9a to 9c are provided only on the outer circumference of the bonding wires 4a to 4c, even if the insulating layers 9a to 9c are harder than the sealing member 7, the conformability of the insulating layers 9a to 9c to the bonding wires 4a to 4c can be maintained, and peeling of the bonding wires 4a to 4c and the insulating layers 9a to 9c can be suppressed.

[0069] (Other embodiments) As described above, this disclosure is described by embodiments, but the statements and drawings that constitute part of this disclosure should not be understood as limiting this disclosure. Various alternative embodiments, examples and operational techniques will become apparent to those skilled in the art from this disclosure.

[0070] For example, while the bonding wires 4a to 4c of the semiconductor device according to the embodiment are shown as being connected to the first main electrode 31, conductive layers 11a and 11b, and external connection terminals 6a and 6b of the semiconductor chip 3, the destinations to which the bonding wires 4a to 4c are connected are not limited and can be selected as appropriate. Furthermore, the number of bonding wires 4a to 4c of the semiconductor device according to the embodiment is not limited and can be selected as appropriate.

[0071] Furthermore, the configurations disclosed in the embodiments can be combined as appropriate, within a non-contradictory scope. Thus, this disclosure naturally includes various embodiments not described herein. Therefore, the technical scope of this disclosure is determined solely by the inventive features relating to the claims that are reasonable given the above description. [Explanation of symbols]

[0072] 1…Insulated circuit board 2,2a~2f...Joining layer 3,3a~3d... Semiconductor chips 4a~4c...Bonding wire 5…case 6a, 6b… External connection terminals 7...Sealing member 8… Heat dissipation base 9a~9c...Insulating layer 10…Insulating board 11a, 11b, 12...conductive layer 13… Heat dissipation fins 14,15...Joining layer 31...1st main electrode 32… Terminal gate 33…Second main electrode

Claims

1. A semiconductor chip having a first main electrode on the upper side and a second main electrode on the lower side, A bonding wire connected to the first main electrode, An insulating layer covering the outer circumference of the bonding wire, A sealing member that seals the semiconductor chip, the bonding wire, and the insulating layer, Equipped with, A semiconductor device in which the ratio of the Young's modulus of the insulating layer to the Young's modulus of the sealing member is 10 or more, and the ratio of the dielectric constant of the insulating layer to the dielectric constant of the sealing member is 0.5 or less.

2. A semiconductor chip having a first main electrode on the upper side and a second main electrode on the lower side, A bonding wire connected to the first main electrode, An insulating layer covering the outer circumference of the bonding wire, A sealing member that seals the semiconductor chip, the bonding wire, and the insulating layer, Equipped with, The ratio of the Young's modulus of the insulating layer to the Young's modulus of the sealing member is 10 or more, and the ratio of the dielectric constant of the insulating layer to the dielectric constant of the sealing member is 3 or less. A semiconductor device having a plurality of bonding wires, wherein the outer circumference of bonding wires within 5 mm of a terminal having a potential different from the potential of the plurality of bonding wires is covered with the insulating layer, and the outer circumference of bonding wires located more than 5 mm from a terminal is not covered with the insulating layer.

3. The Young's modulus of the insulating layer is 100 kPa or more and 10 GPa or less. A semiconductor device according to claim 1 or 2.

4. The relative permittivity of the insulating layer is 7 or less. A semiconductor device according to claim 1 or 2.

5. The diameter of the bonding wire is 300 μm or more. A semiconductor device according to claim 1 or 2.

6. The thickness of the insulating layer is 25 μm or more. A semiconductor device according to claim 1 or 2.

7. The thickness of the insulating layer is 500 μm or less. A semiconductor device according to claim 1 or 2.

8. The maximum rated voltage of the semiconductor chip is 1.7 kV or higher. A semiconductor device according to claim 1 or 2.

9. The bonding wire is provided via the sealing member at a distance of 5 mm or less from a terminal having a potential different from that of the bonding wire. The semiconductor device according to claim 1.

10. The second main electrode is electrically connected to the terminal. A semiconductor device according to claim 2 or 9.

11. The insulating layer contains at least one resin selected from polyamide resin, polyimide resin, polyamideimide resin, polyester resin, epoxy resin, phenolic resin, fluororesin, acrylic resin, silicone resin, polyolefin resin, and polyetherimide resin. A semiconductor device according to claim 1 or 2.

12. The sealing member includes a silicone gel or a fluorine-based gel. A semiconductor device according to claim 1 or 2.

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