Semiconductor device and method for manufacturing a semiconductor device

Abstract

The semiconductor device (1000) according to this disclosure comprises a semiconductor element (100), a member to be bonded (200) on which the semiconductor element is mounted, a bonding layer (300) made of a paste-like bonding material provided to bond the lower surface of the semiconductor element and the upper surface of the member to be bonded, and a bonding material blocking portion (400) provided on the semiconductor element to block the bonding material from spreading onto the upper surface of the semiconductor element. As a result, even when bonding a semiconductor element to a member to be bonded via a paste-like bonding material, it is possible to suppress the spreading of the bonding material onto the upper surface of the semiconductor element, thereby suppressing a decrease in the reliability of the semiconductor device.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.

Background Art

[0002] Conventionally, a semiconductor device has been disclosed that includes a semiconductor element, a joined member such as a die pad to which the semiconductor element is joined, and a joining layer provided to join the lower surface of the semiconductor element and the upper surface of the joined member. Further, it has been disclosed that the joining layer is composed of a paste-like joining material such as silver paste. (For example, see Patent Document 1)

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When joining a semiconductor element to a joined member via a paste-like joining material, the joining material creeps up onto the upper surface of the semiconductor element. When the joining material creeps up onto the upper surface of the semiconductor element, for example, there is a problem that a short circuit occurs between different electrodes and the reliability of the semiconductor device decreases.

[0005] The present disclosure has been made to solve the above problems, and even when joining a semiconductor element to a joined member via a paste-like joining material, it is possible to suppress the joining material from creeping up onto the upper surface of the semiconductor element, and an object thereof is to provide a semiconductor device and a method for manufacturing a semiconductor device that can suppress a decrease in the reliability of the semiconductor device.

Means for Solving the Problems

[0006] The semiconductor device according to the present disclosure includes a semiconductor element, a joined member on which the semiconductor element is mounted, A lower electrode layer provided on the lower surface of a semiconductor element, and a lower plating layer provided on the lower surface of the lower electrode layer and having a predetermined thickness,The semiconductor element comprises a bonding layer made of a paste-like bonding material, which is provided to bond the lower surface of the semiconductor element to the upper surface of the member to be bonded, and a bonding material sealing portion provided on the semiconductor element to block the bonding material from spreading up to the upper surface of the semiconductor element, wherein the bonding material sealing portion is located on the outer circumference of the lower surface of the semiconductor element. , below the semiconductor element at a predetermined height from the lower plating layer This is a lower protruding portion that is positioned to protrude. Furthermore, the semiconductor device relating to this disclosure includes a semiconductor element and a bonded member on which the semiconductor element is mounted, An upper electrode layer provided on the upper surface of a semiconductor element, and an upper plating layer provided on the upper surface of the upper electrode layer and having a predetermined thickness, The semiconductor element comprises a bonding layer made of a paste-like bonding material, which is provided to bond the lower surface of the semiconductor element to the upper surface of the member to be bonded, and a bonding material sealing portion provided on the semiconductor element to block the bonding material from spreading up to the upper surface of the semiconductor element, wherein the bonding material sealing portion is provided on the upper surface of the semiconductor element In the outer peripheral portion, which is further outward from the upper electrode layer and the upper plating layer, a predetermined height above the semiconductor element is located above the upper plating layer. This is an upper protruding portion that is positioned to protrude.

[0007] A method for manufacturing a semiconductor device according to this disclosure comprises: a bonding material sealing portion formation step of forming a bonding material sealing portion on a semiconductor device to prevent the paste-like bonding material from spreading onto the upper surface of the semiconductor device; a bonding step of bonding the lower surface of the semiconductor device and the upper surface of a member to be bonded with a paste-like bonding material, wherein the bonding material sealing portion formation step comprises: a plating layer formation step of forming a plating layer having a predetermined thickness on the surface of the lower electrode layer formed on the lower surface of the semiconductor device, or on the upper surface of the semiconductor device, outward in the peripheral direction from the upper electrode layer formed on the upper surface of the semiconductor device; and a dicing step of dicing a semiconductor wafer along a dicing line to form a plurality of semiconductor devices. The device has the following characteristics: In the dicing process, among the plating layers formed in the plating layer formation process, the plating layer formed on the dicing line protrudes to a predetermined height, forming a bonding material sealing portion. . [Effects of the Invention]

[0008] According to the semiconductor device and method for manufacturing the semiconductor device described herein, even when a semiconductor element is bonded to a member to be bonded via a paste-like bonding material, it is possible to suppress the bonding material from creeping up onto the upper surface of the semiconductor element, thereby suppressing a decrease in the reliability of the semiconductor device. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic top view of a semiconductor device according to Embodiment 1. [Figure 2] This is a schematic plan view of the semiconductor device according to Embodiment 1. [Figure 3] This is a schematic cross-sectional view of XX in Figure 1 of the semiconductor device according to Embodiment 1. [Figure 4] This is a schematic plan view showing the semiconductor wafer formation process of the semiconductor device manufacturing method according to Embodiment 1. [Figure 5] This is a schematic cross-sectional view of XX in Figure 4, showing the semiconductor wafer formation process of the semiconductor device manufacturing method according to Embodiment 1. [Figure 6] This is a schematic cross-sectional view showing the dicing process of the semiconductor device manufacturing method according to Embodiment 1. [Figure 7] This is a schematic cross-sectional view showing the bonding process of the semiconductor device manufacturing method according to Embodiment 1. [Figure 8] This is a schematic top view of a semiconductor device according to a modified example of Embodiment 1. [Figure 9] This is a schematic plan view of a semiconductor device according to a modified example of Embodiment 1. [Figure 10] This is a schematic cross-sectional view of XX in Figure 8 of a semiconductor device according to a modified example of Embodiment 1. [Figure 11] This is a schematic cross-sectional view of the YY area in Figure 8 of a semiconductor device according to a modified example of Embodiment 1. [Figure 12] This is a schematic plan view showing the semiconductor wafer formation process of a semiconductor device manufacturing method according to a modified example of Embodiment 1. [Figure 13] This is a schematic cross-sectional view of XX in Figure 12, showing the semiconductor wafer formation process of the semiconductor device manufacturing method according to Embodiment 1. [Figure 14] This is a schematic cross-sectional view of YY in Figure 12, showing the semiconductor wafer formation process of the semiconductor device manufacturing method according to Embodiment 1. [Figure 15] This is a schematic cross-sectional view showing the dicing process of a semiconductor device manufacturing method according to a modified example of Embodiment 1. [Figure 16]It is a schematic cross-sectional view showing a dicing process of a method for manufacturing a semiconductor device according to a modification of Embodiment 1. [Figure 17] It is a schematic top view of a semiconductor device according to Embodiment 2. [Figure 18] It is a schematic plan view of a semiconductor device according to Embodiment 2. [Figure 19] It is an X-X schematic cross-sectional view in FIG. 17 of a semiconductor device according to Embodiment 2. [Figure 20] It is a schematic cross-sectional view showing a semiconductor wafer formation process of a method for manufacturing a semiconductor device according to Embodiment 2. [Figure 21] It is a schematic cross-sectional view showing a dicing process of a method for manufacturing a semiconductor device according to Embodiment 2. [Figure 22] It is a schematic top view of a semiconductor device according to a modification of Embodiment 2. [Figure 23] It is an X-X schematic cross-sectional view in FIG. 22 of a semiconductor device according to a modification of Embodiment 2. [Figure 24] It is a Y-Y schematic cross-sectional view in FIG. 22 of a semiconductor device according to a modification of Embodiment 2. [Figure 25] It is an X-X schematic cross-sectional view in FIG. 12 showing a semiconductor wafer formation process of a method for manufacturing a semiconductor device according to a modification of Embodiment 2. [Figure 26] It is a Y-Y schematic cross-sectional view in FIG. 12 showing a semiconductor wafer formation process of a method for manufacturing a semiconductor device according to a modification of Embodiment 2. [Figure 27] It is a schematic cross-sectional view showing a dicing process of a method for manufacturing a semiconductor device according to a modification of Embodiment 2. [Figure 28] It is a schematic cross-sectional view showing a dicing process of a method for manufacturing a semiconductor device according to a modification of Embodiment 2. [Figure 29] It is a schematic top view of a semiconductor device according to Embodiment 3. [Figure 30] It is a schematic plan view of a semiconductor device according to Embodiment 3. [Figure 31] It is an X-X schematic cross-sectional view in FIG. 29 of a semiconductor device according to Embodiment 3. [Figure 32]This is a schematic cross-sectional view showing the dicing process of the semiconductor device manufacturing method according to Embodiment 3. [Figure 33] This is a schematic cross-sectional view showing the dicing process of the semiconductor device manufacturing method according to Embodiment 3. [Figure 34] This is a schematic top view of the semiconductor device according to Embodiment 4. [Figure 35] This is a schematic plan view of the semiconductor device according to Embodiment 4. [Figure 36] This is a schematic cross-sectional view of XX in Figure 34 of the semiconductor device according to Embodiment 4. [Figure 37] This is a schematic cross-sectional view showing the dicing process of the semiconductor device manufacturing method according to Embodiment 4. [Figure 38] This is a schematic cross-sectional view showing the dicing process of the semiconductor device manufacturing method according to Embodiment 4. [Modes for carrying out the invention]

[0010] <Introduction> In semiconductor devices, one side parallel to the depth direction is referred to as "upper," and the other side as "lower." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the upper surface, and the other surface as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0011] Furthermore, for the sake of convenience, in the following explanation, the width direction of the semiconductor device will be referred to as the X direction, the depth direction of the semiconductor device intersecting the X direction will be referred to as the Y direction, and the thickness direction or depth direction of the semiconductor device, that is, the direction normal to the XY plane, will be referred to as the Z direction.

[0012] Furthermore, the drawings are schematic representations, and the relative sizes and positions of images shown in different drawings are not necessarily accurately depicted and may be modified as appropriate. In the following explanation, similar components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed explanations of these components may be omitted.

[0013] Embodiment 1. Embodiment 1 will be described below with reference to the drawings. Figure 1 is a schematic top view of the semiconductor device 1000 (1000A) according to Embodiment 1. Figure 2 is a schematic plan view of the semiconductor device 1000 (1000A) according to Embodiment 1. Note that Figure 2 is a horizontal cross-sectional view with the lower surface of the lower plating layer 150 as the cross-section. The horizontal cross-sectional view described above will be referred to as a plan view. In the following description of the present invention, "plan view" will be a horizontal cross-sectional view with the lower surface of the lower plating layer 150 of the semiconductor device as the cross-section, similar to Figure 2. Note that a plan view means viewing from the viewpoint shown in Figure 2 above. In the following description of the present invention, "plan view" will be a viewpoint from below, with the lower surface of the lower plating layer 150 of the semiconductor device as the cross-section, as shown in Figure 2. Figure 3 is a schematic cross-sectional view of the semiconductor device 1000 (1000A) according to Embodiment 1. Note that Figure 3 shows the cross-section along the dashed line X-X shown in Figure 1.

[0014] An example configuration of the semiconductor device 1000 will be explained using Figures 1 to 3. As shown in Figures 1 to 3, the semiconductor device 1000A includes a semiconductor element 100 (100A), a member to be bonded 200, a bonding layer 300, and a bonding material sealing portion 400.

[0015] An example of the configuration of the semiconductor element 100 is described below. The semiconductor element 100A of this embodiment has a semiconductor substrate 110, an upper electrode layer 120, an upper plating layer 130, a lower electrode layer 140, and a lower plating layer 150. The thickness of the semiconductor element 100 (100A) is, for example, 100 μm or less.

[0016] The semiconductor substrate 110 is constructed using various semiconductor materials, such as silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). The semiconductor substrate 110 may also be composed of, for example, GaNonSiC, GaNonSi, or GaNonGaN.

[0017] As shown in Figure 3, the upper electrode layer 120 is provided on the upper surface 111 side of the semiconductor substrate 110. The upper electrode layer 120 may be made of an aluminum alloy. For example, the upper electrode layer 120 is formed of an aluminum-silicon alloy (Al-Si alloy).

[0018] As shown in Figure 3, the upper plating layer 130 is provided on the upper surface of the upper electrode layer 120. In this embodiment, as shown in Figure 3, the upper plating layer 130 is provided in the center of the upper surface 101 of the semiconductor element 100. The upper plating layer 130 may be composed of, for example, Au, or nickel or a nickel alloy. The upper plating layer 130 may also have a laminated structure including, for example, two or more metal layers. This laminated structure may be composed of, for example, a Ti layer, a Ni layer, and an Au layer in that order from the bottom surface of the upper plating layer 130.

[0019] As shown in Figure 3, the lower electrode layer 140 is provided on the lower surface 112 side of the semiconductor substrate 110. The lower electrode layer 140 may be made of an aluminum alloy. For example, the lower electrode layer 140 is made of an aluminum-silicon alloy (Al-Si alloy).

[0020] As shown in Figure 3, the lower plating layer 150 is provided on the lower surface of the lower electrode layer 140. In this embodiment, as shown in Figure 3, the lower plating layer 150 is provided on the entire lower surface 102 of the semiconductor element 100. The lower plating layer 150 is preferably composed of Au, but may be composed of nickel or a nickel alloy, for example. The lower plating layer 150 may also have a laminated structure including two or more metal layers. This laminated structure may be composed of a Ti layer, a Ni layer, and an Au layer in that order from the lower surface of the lower plating layer 150. It is preferable that the lower plating layer 150 is configured so that the Au layer is the outermost layer. The height of the lower plating layer 150 (h1 in Figure 2) is, for example, 5 μm, of which the height of the Au layer is 3 μm.

[0021] Next, the member to be joined 200 will be described. As shown in Figure 3, a semiconductor element 100 (100A) is joined to the member to be joined 200. The member to be joined 200 is, for example, a die pad or insulating substrate of a lead frame.

[0022] Next, the bonding layer 300 will be described. As shown in Figure 3, the bonding layer 300 is provided to bond the lower surface 102 of the semiconductor element 100 (100A) to the upper surface 201 of the member to be bonded 200. The bonding layer 300 is composed of a paste-like bonding material. The paste-like bonding material is preferably a conductive adhesive such as Ag paste or sintered Ag paste, but it may also be, for example, paste solder.

[0023] Next, the bonding material blocking portion 400 will be described. As shown in Figures 2 and 3, the bonding material blocking portion 400 is provided on the semiconductor element 100. The bonding material blocking portion 400 has the function of blocking the bonding material so that it does not creep up onto the upper surface 101 of the semiconductor element 100 (100A). In the semiconductor device 1000A of this embodiment, as shown in Figures 2 and 3, the bonding material blocking portion 400 is a lower protrusion 410 that protrudes from the outer peripheral portion 104 of the lower surface 102 of the semiconductor element 100A. As shown in Figure 2, it is desirable that the lower protrusion 410 be provided around the entire circumference of the outer peripheral portion 104 of the lower surface 102 of the semiconductor element 100A. The height of the lower protrusion 410 (h2 in Figure 2) is preferably, for example, 10 μm or more and 20 μm or less. In addition, although the lower protrusion 410 in this embodiment is a plating layer 411, it may be a resin layer, for example, and is arbitrary. If the lower protrusion 410 is a plating layer 411, it is desirable that the plating layer 411 be made of a highly ductile material. As shown in Figure 3, it is desirable that the plating layer 411 be provided integrally with the lower plating layer 150. In this embodiment, the plating layer 411 has burrs 412. The burrs 412 are formed on the plating layer 411 during the dicing process described later. As mentioned above, it is desirable that the plating layer 411 be made of a highly ductile material, thereby increasing the height of the burrs 412. For example, if the outermost layer of the plating layer 411 is made of an Au layer and the height of the Au layer is 3 μm, the height of the burrs 412 can be made about 10 μm.

[0024] As described above, the semiconductor device 1000 of this embodiment is configured. By providing the semiconductor element 100 with a bonding material sealing portion 400, even when the semiconductor element 100 is bonded to the member to be bonded 200 via a paste-like bonding material, it is possible to suppress the bonding material from creeping up onto the upper surface 101 of the semiconductor element 100, thereby suppressing a decrease in the reliability of the semiconductor device.

[0025] In the semiconductor device 1000A of this embodiment, the bonding material sealing portion 400 is a lower protrusion 410 that protrudes from the outer peripheral portion 104 of the lower surface 102 of the semiconductor element 100A. By doing so, it is possible to suppress the bonding material interposed between the lower surface 102 of the semiconductor element 100A and the upper surface 201 of the member to be bonded 200 from creeping up onto the side surface 103 of the semiconductor element 100A, and thus it is possible to suppress the bonding material from creeping up onto the upper surface 101 of the semiconductor element 100A.

[0026] In the semiconductor device 1000A of this embodiment, the bonding material sealing portion 400 is a lower protrusion 410 provided that protrudes from the outer peripheral portion 104 of the lower surface 102 of the semiconductor element 100A. By doing so, it is possible to suppress the bonding material interposed between the lower surface 102 of the semiconductor element 100A and the upper surface 201 of the member to be bonded 200 from being repelled to the outside of the outer peripheral portion 104 of the lower surface 102 of the semiconductor element 100A, thereby ensuring a constant thickness of the bonding layer 300 and suppressing a decrease in the reliability of the semiconductor device.

[0027] Next, an example of a manufacturing method for the semiconductor device 1000 (1000A) of this embodiment will be described using Figures 4 to 7. Figure 4 is a schematic plan view showing the semiconductor wafer formation process of the manufacturing method for the semiconductor device 1000 (1000A) according to Embodiment 1. Figure 5 is a schematic cross-sectional view showing the semiconductor wafer formation process of the manufacturing method for the semiconductor device 1000 (1000A) according to Embodiment 1. Note that Figure 5 shows a cross-section along the dashed line X-X shown in Figure 4. Figure 6 is a schematic cross-sectional view showing the dicing process of the manufacturing method for the semiconductor device 1000 (1000A) according to Embodiment 1. Figure 7 is a schematic cross-sectional view showing the bonding process of the manufacturing method for the semiconductor device 1000 (1000A) according to Embodiment 1. The manufacturing method for the semiconductor device 1000 (1000A) of this embodiment is basically the same as conventional semiconductor device manufacturing methods, except for the bonding material sealing portion formation process, so some parts will be omitted from the explanation.

[0028] The method for manufacturing the semiconductor device 1000 includes a bonding material sealing portion formation step and a bonding step.

[0029] First, the bonding material sealing portion formation process will be described. The bonding material sealing portion formation process in the manufacturing method of the semiconductor device 1000A of this embodiment includes a semiconductor wafer formation process and a dicing process. The semiconductor wafer formation process is performed before the dicing process.

[0030] The semiconductor wafer formation process of the manufacturing method for the semiconductor device 1000A in this embodiment includes an upper electrode layer formation process, an upper plating layer formation process, a lower electrode formation process, and a lower plating layer formation process. First, the semiconductor wafer formation process will be described.

[0031] As shown in Figure 4, a semiconductor wafer 1 (1A) has multiple semiconductor elements 100 (100A) formed in a matrix. In Figure 4, each semiconductor element 100 is schematically shown by a solid line. For the sake of explanation, the boundary between adjacent semiconductor elements 100, which is the dividing line when the semiconductor wafer 1 is later divided into multiple semiconductor elements 100, is called the dicing line 11. The dicing line 11 is not an actual line drawn on the semiconductor wafer 1, but a virtual line. The dicing line 11 may be an actual line or groove drawn on the semiconductor wafer 1 so that it can be seen with the naked eye.

[0032] In the upper electrode layer formation process, as shown in Figure 5, first, the semiconductor substrate 110 is formed, and then the upper electrode layer 120 is formed on the upper surface 111 side of the semiconductor substrate 110. The upper electrode layer 120 is formed by a PVD method such as sputtering or vapor deposition.

[0033] In the upper plating layer formation process, as shown in Figure 5, the upper plating layer 130 is formed on the upper surface of the upper electrode layer 120. The upper plating layer 130 is formed, for example, by electroless plating or electrolytic plating. In this embodiment, multiple upper plating layers 130 are formed on the upper surface 111 of the semiconductor substrate 110 at intervals from each other.

[0034] In the lower electrode layer formation process, as shown in Figure 5, the lower electrode layer 140 is formed on the lower surface 112 side of the semiconductor substrate 110. The lower electrode layer 140 is formed by a PVD method such as sputtering or vapor deposition.

[0035] In the lower plating layer formation process, as shown in Figure 5, the lower plating layer 150 is formed on the lower surface of the lower electrode layer 140. The lower plating layer 150 is formed, for example, by electroless plating or electrolytic plating. In this embodiment, the lower plating layer 150 is formed over the entire lower surface 112 of the semiconductor substrate 110. In this embodiment, a portion of the lower plating layer 150 functions as a bonding material sealing portion 400. It is desirable that the lower plating layer 150 be formed of Au. As mentioned above, it is desirable that the plating layer 411, which is the bonding material sealing portion 400, be provided integrally with the lower plating layer 150. By doing so, a portion of the lower plating layer 150 can function as the bonding material sealing portion 400, thereby improving the efficiency of the semiconductor device manufacturing process.

[0036] Next, the dicing process will be described. In the dicing process, as shown in Figure 6, the semiconductor wafer 1 is diced along the dicing line 11 to form a plurality of semiconductor elements 100. In this embodiment, since the lower plating layer 150 is formed over the entire lower surface 112 of the semiconductor substrate 110 in the lower plating layer formation process, when the semiconductor wafer 1 is diced in the dicing process, burrs 412 are generated on the dicing line 11 of the lower plating layer 150. In this embodiment, the burrs 412 function as bonding material sealing portions 400. Since the dicing line 11 exists as shown in Figure 4, the burrs 412 are formed over the entire circumference of the outer peripheral portion 104 of the lower surface 102 of each semiconductor element 100. Note that by optimizing the conditions of the dicing process or the material of the plating layer 411, it is possible to form burrs 412 of a desired height.

[0037] Next, the bonding process will be described. In the bonding process, as shown in Figure 7, the lower surface 102 of the semiconductor element 100 and the upper surface 201 of the member to be bonded 200 are bonded together with a paste-like bonding material 301.

[0038] The semiconductor device 1000 is manufactured through the process described above. As stated above, the manufacturing method of the semiconductor device 1000 of this embodiment further comprises a bonding material sealing portion formation step. By forming the bonding material sealing portion 400, even when the semiconductor element 100 is bonded to the member to be bonded 200 via a paste-like bonding material 301 during the bonding process, it is possible to suppress the bonding material 301 from spreading onto the upper surface 101 of the semiconductor element 100, thereby suppressing a decrease in the reliability of the semiconductor device.

[0039] Furthermore, in the manufacturing method of the semiconductor device 1000A of this embodiment, in the lower plating layer formation step, the lower plating layer 150 is formed on the entire lower surface of the lower electrode layer 140, and in the dicing step, the semiconductor wafer 1A is diced along the dicing line 11 to form a plurality of semiconductor elements 100A. In this way, burrs 412 are generated on the dicing line 11 of the lower plating layer 150, and the burrs 412 are formed around the entire circumference of the outer peripheral portion 104 of the lower surface 102 of each semiconductor element 100A. In the bonding step, since the burrs 412 function as bonding material blocking portions 400, the bonding material 301 interposed between the lower surface 102 of the semiconductor element 100A and the upper surface 201 of the member to be bonded 200 can be prevented from creeping up onto the side surface 103 of the semiconductor element 100, thus preventing the bonding material 301 from creeping up onto the upper surface 101 of the semiconductor element 100A.

[0040] Next, a modified example of Embodiment 1 will be described using Figures 8 to 11. Figure 8 is a schematic top view of the modified semiconductor device 1000B. Figure 9 is a schematic plan view of the modified semiconductor device 1000B. Figures 10 and 11 are schematic cross-sectional views of the modified semiconductor device 1000B. Figure 10 shows a cross-sectional view of the cross section along the dashed line X-X shown in Figure 8, viewed from the negative Y-axis side. Figure 11 shows a cross-sectional view of the cross section along the dashed line Y-Y shown in Figure 8, viewed from the negative X-axis side.

[0041] As shown in Figure 9, the semiconductor element 100B is rectangular in plan view, and the bonding material sealing portion 400 is provided only in the first region 105 located on a pair of opposing sides in plan view, on the outer peripheral portion 104 of the lower surface 102 of the semiconductor element 100B. In the modified example 1, the bonding material sealing portion 400 is a lower protrusion 410.

[0042] As shown in Figure 8, in this embodiment, the upper electrode layer 120 (not shown) and the upper plating layer 130 are provided only in the second region 107 located on a pair of opposing sides in a top view of the outer peripheral portion 106 of the upper surface 101 of the semiconductor element 100B. As shown in Figure 10, the first region 105 and the second region 107 are assumed to be on the same axis in the Z-axis direction.

[0043] The semiconductor device 1000B, having the above-described configuration, can suppress the bonding material 301 interposed between the lower surface 102 of the semiconductor element 100B and the upper surface 201 of the member to be bonded 200 from creeping up onto the side surface 103 of the semiconductor element 100B on the side of the first region 105. Therefore, it can suppress the bonding material 301 from creeping up onto the second region 107 side of the upper surface 101 of the semiconductor element 100B. As described above, when the upper electrode layer 120 and the upper plating layer 130 are provided only on the second region 107 located on a pair of opposing sides of the outer peripheral portion 106 of the upper surface 101 of the semiconductor element 100B when viewed from above, it is possible to suppress the bonding material 301 from creeping up onto the second region 107 side of the upper surface 101 of the semiconductor element 100B. Therefore, it is possible to suppress the occurrence of a short circuit between dissimilar electrodes and the resulting decrease in the reliability of the semiconductor device.

[0044] Next, an example of a method for manufacturing the semiconductor device 1000B will be described using Figures 12 to 16. Figure 12 is a schematic plan view showing the semiconductor wafer formation process of a method for manufacturing the semiconductor device 1000B according to a modified example of Embodiment 1. Figure 13 is a schematic cross-sectional view showing the semiconductor wafer formation process of a method for manufacturing the semiconductor device 1000B according to a modified example of Embodiment 1. Figure 13 shows a cross-section along the dashed line X-X shown in Figure 12. Figure 14 is a schematic cross-sectional view showing the semiconductor wafer formation process of a method for manufacturing the semiconductor device 1000B according to a modified example of Embodiment 1. Figure 14 shows a cross-section along the dashed line Y-Y shown in Figure 12. Figure 15 is a schematic cross-sectional view showing the dicing process of a method for manufacturing the semiconductor device 1000B according to a modified example of Embodiment 1. Figure 15 shows the state after dicing the semiconductor wafer 1B shown in Figure 13. Figure 16 is a schematic cross-sectional view showing the dicing process of a method for manufacturing the semiconductor device 1000B according to a modified example of Embodiment 1. Figure 16 shows the state after dicing the semiconductor wafer 1B shown in Figure 14.

[0045] In the manufacturing method of the semiconductor device 1000B, in the lower plating layer formation step of the wafer formation step described above, the lower plating layer 150 is provided so as shown in Figures 13 and 14, extending only over the dicing line 11 located in the first region 105. In this way, in the dicing step, as shown in Figures 15 and 16, burrs 412 are generated only on the dicing line 11 located in the first region 105 of the lower plating layer 150. In other words, burrs 412 are formed only in the first region 105 of the outer peripheral portion 104 of the lower surface 102 of each semiconductor element 100B. In the bonding process, the burr 412 functions as a bonding material blocking portion 400, which prevents the bonding material 301 interposed between the lower surface 102 of the semiconductor element 100B and the upper surface 201 of the member to be bonded 200 from creeping up onto the side surface 103 of the semiconductor element 100B on the side of the first region 105. Thus, it is possible to prevent the bonding material 301 from creeping up onto the side of the upper surface 101 of the semiconductor element 100B on the side of the second region 107.

[0046] Embodiment 2. The semiconductor device 1000C in Embodiment 2 will be described using Figures 17 to 19. Figure 17 is a schematic top view of the semiconductor device 1000C according to Embodiment 2. Figure 18 is a schematic plan view of the semiconductor device 1000C according to Embodiment 2. Figure 19 is a schematic cross-sectional view of the semiconductor device 1000C according to Embodiment 2. Note that Figure 19 shows the cross section along the dashed line X-X shown in Figure 17.

[0047] In the semiconductor device 1000C of Embodiment 2, the bonding material sealing portion 400 is provided on the upper surface 101 of the semiconductor element 100C. In other words, in the semiconductor device 1000C of Embodiment 2, the position where the bonding material sealing portion 400 is provided is different from that of Embodiment 1.

[0048] In this embodiment, as shown in Figures 17 and 19, the bonding material sealing portion 400 is an upper protrusion 420 that protrudes from the outer peripheral portion 106 of the upper surface 101 of the semiconductor element 100C. As shown in Figures 17 and 19, the upper protrusion 420 is provided further outward in the outer peripheral direction than the upper electrode layer 120 and the upper plating layer 130. If other members (such as a guard ring) other than the upper electrode layer 120 and the upper plating layer 130 are provided on the upper surface 111 of the semiconductor substrate 110, the upper protrusion 420 may be provided further outward in the outer peripheral direction than the other members. Furthermore, as shown in Figure 17, it is desirable that the upper protrusion 420 be provided around the entire circumference of the outer peripheral portion 106 of the upper surface 101 of the semiconductor element 100C. The height of the upper protrusion 420 (h2 in Figure 19) is, for example, 10 μm or more and 20 μm or less. As shown in Figure 19, the upper protrusion 420 may be provided so as to be in contact with the upper surface 101 of the semiconductor element 100C without contacting the side surface 103. In this embodiment, the upper protrusion 420 is preferably a plating layer 421, but it may be a resin layer, for example, and is optional. If the upper protrusion 420 is a plating layer 421, it is preferable that the plating layer 421 be made of a highly ductile material, for example, it is preferable that the Au layer be the outermost surface. As shown in Figures 17 and 19, the plating layer 421 may be provided with a gap between it and the upper plating layer 130, or it may be provided integrally with the upper plating layer 130. In this embodiment, the plating layer 421 has burrs 422. The burrs 422 are formed on the plating layer 421 during the dicing process described later. As mentioned above, it is preferable that the plating layer 421 be made of a highly ductile material, which allows the height of the burrs 422 to be increased.

[0049] In this embodiment, as shown in Figures 18 and 19, the lower plating layer 150 is provided in the center of the lower surface 102 of the semiconductor element 100C, and not on the outer peripheral portion 104 of the lower surface 102 of the semiconductor element 100C.

[0050] As described above, the semiconductor device 1000C of Embodiment 2 is configured. Similar to Embodiment 1, by providing the bonding material sealing portion 400 on the semiconductor element 100C, even when the semiconductor element 100C is bonded to the member to be bonded 200 via a paste-like bonding material, it is possible to suppress the bonding material from spreading onto the upper surface 101 of the semiconductor element 100C, thereby suppressing a decrease in the reliability of the semiconductor device.

[0051] In this embodiment, the bonding material sealing portion 400 is an upper protrusion 420, and the upper protrusion 420 is provided to protrude from the outer peripheral portion 106 of the upper surface 101 of the semiconductor element 100C. In this way, even if the bonding material 301 interposed between the lower surface 102 of the semiconductor element 100C and the upper surface 201 of the member to be bonded 200 creeps up onto the side surface 103 of the semiconductor element 100C, it is possible to suppress the bonding material 301 from creeping up onto the upper surface 101 of the semiconductor element 100C, thereby preventing the bonding material 301 from creeping up onto the upper surface 101 of the semiconductor element 100C.

[0052] Furthermore, the upper protrusion 420, which is a unique configuration of this embodiment, may be combined with the lower protrusion 410 of Embodiment 1. By doing so, even when a semiconductor element is bonded to a member to be bonded 200 via a paste-like bonding material, it is possible to further suppress the bonding material from spreading onto the upper surface 101 of the semiconductor element, thereby further suppressing the deterioration of the reliability of the semiconductor device.

[0053] Next, an example of a manufacturing method for the semiconductor device 1000C of Embodiment 2 will be described using Figures 20 and 21. Figure 20 is a schematic cross-sectional view showing the semiconductor wafer formation process of the manufacturing method for the semiconductor device 1000C according to Embodiment 2. Note that Figure 20 is a diagram showing the cross-section along the dashed line X-X shown in Figure 4. Figure 21 is a schematic cross-sectional view showing the dicing process of the manufacturing method for the semiconductor device 1000C according to Embodiment 2. The manufacturing method for the semiconductor device 1000C of Embodiment 2 differs from that of Embodiment 1 in its semiconductor wafer formation process. The semiconductor wafer formation process will be described below, while the other processes will be the same as those of Embodiment 1.

[0054] The semiconductor wafer formation process of this embodiment includes an upper electrode layer formation process, an upper plating layer formation process, a lower electrode formation process, and a lower plating layer formation process. First, the semiconductor wafer formation process will be described.

[0055] In the upper electrode layer formation process, as shown in Figure 20, first, the semiconductor substrate 10 is formed, and then the upper electrode layer 120 is formed on the upper surface 111 side of the semiconductor substrate 110. The upper electrode layer 120 is formed by a PVD method such as sputtering or vapor deposition.

[0056] In the upper plating layer formation process, as shown in Figure 20, the upper plating layer 130 is formed on the upper surface of the upper electrode layer 120. The upper plating layer 130 is formed, for example, by electroless plating or electrolytic plating. In this embodiment, the plating layer 421 is formed simultaneously with the upper plating layer 130. As described above, it is desirable to make the upper protrusion 420 the plating layer 421, so that the upper plating layer 130 and the upper protrusion 420 can be formed simultaneously, thereby improving the efficiency of the semiconductor device manufacturing process. In this embodiment, as shown in Figure 20, the plating layer 421 is formed with a gap between it and the upper plating layer 130. As shown in Figure 20, the plating layer 421 is formed on the dicing line 11 of the upper surface 101 of the semiconductor element 100C. In this embodiment, the plating layer 421 functions as a bonding material sealing portion 400. The height of the plating layer 421 (h1 in Figure 20) is, for example, 5 μm, of which the height of the Au layer is 3 μm.

[0057] In the lower electrode layer formation process, the lower electrode layer 140 is formed on the lower surface 102 side of the semiconductor substrate 10. The lower electrode layer 140 is formed by a PVD method such as sputtering or vapor deposition.

[0058] In the lower plating layer formation process, the lower plating layer 150 is formed on the lower surface of the lower electrode layer 140. The lower plating layer 150 is formed, for example, by electroless plating or electrolytic plating. In this embodiment, as shown in Figure 20, the lower plating layer 150 is not formed on the dicing line 11.

[0059] The semiconductor device 1000C is manufactured through the process described above. As stated above, the manufacturing method of the semiconductor device 1000C in this embodiment further includes a bonding material sealing portion formation step, similar to that in Embodiment 1. By forming the bonding material sealing portion 400, even when the semiconductor element 100C is bonded to the member to be bonded 200 via a paste-like bonding material 301 during the bonding process, it is possible to suppress the bonding material 301 from spreading onto the upper surface 101 of the semiconductor element 100C, thereby suppressing a decrease in the reliability of the semiconductor device.

[0060] Furthermore, in this embodiment, since the plating layer 421 is formed on the dicing line 11 of the upper surface 101 of the semiconductor element 100C during the upper plating layer formation process, burrs 422 of the plating layer 421 are generated on the dicing line 11 when the semiconductor wafer 1C is diced during the dicing process. In this embodiment, the burrs 422 function as bonding material sealing portions 400. As shown in Figure 21, the burrs 422 are formed around the entire circumference of the outer peripheral portion 106 of the upper surface 101 of each semiconductor element 100C. In the bonding process, since the burrs 422 function as bonding material sealing portions 400, even if the bonding material 301 interposed between the lower surface 102 of the semiconductor element 100C and the upper surface 201 of the member to be bonded 200 creeps up onto the side surface 103 of the semiconductor element 100C, it is possible to suppress the bonding material 301 from creeping up onto the upper surface 101 of the semiconductor element 100C.

[0061] Next, a modified example of Embodiment 2 will be described using Figures 22 to 24. Figure 22 is a schematic top view of the modified semiconductor device 1000D. A schematic plan view of the modified semiconductor device 1000D is omitted as it is the same as in Figure 18. Figures 23 and 24 are schematic cross-sectional views of the modified semiconductor device 1000D. Figure 23 shows a cross-sectional view of the cross section X-X shown in Figure 22, viewed from the negative Y-axis side. Figure 24 shows a cross-sectional view of the cross section Y-Y shown in Figure 22, viewed from the negative X-axis side.

[0062] As shown in Figure 22, the semiconductor element 100D is rectangular in top view, and the bonding material sealing portion 400 is provided only in the second region 107 located on a pair of opposing sides in top view, out of the outer peripheral portion 106 of the upper surface 101 of the semiconductor element 100D. In a modified example, the bonding material sealing portion 400 is an upper projection 420.

[0063] As shown in Figure 22, in this embodiment, the upper electrode layer 120 (not shown) and the upper plating layer 130 are provided only in the second region 107 located on a pair of opposing sides in a top view of the outer peripheral portion 106 of the upper surface 101 of the semiconductor element 100D.

[0064] The semiconductor device 1000D, having the above-described configuration, can suppress the bonding material 301 interposed between the lower surface 102 of the semiconductor element 100D and the upper surface 201 of the member to be bonded 200 from creeping up to the second region 107 side of the upper surface 101 of the semiconductor element 100D. As described above, when the upper electrode layer 120 and the upper plating layer 130 are provided only in the second region 107 located on a pair of opposing sides in a top view of the outer peripheral portion 106 of the upper surface 101 of the semiconductor element 100D, the bonding material 301 can be suppressed from creeping up to the second region 107 side of the upper surface 101 of the semiconductor element 100D, thereby suppressing the occurrence of short circuits between dissimilar electrodes and the reduction in the reliability of the semiconductor device.

[0065] Next, an example of a method for manufacturing the semiconductor device 1000D will be described using Figures 25 to 28. The schematic plan view showing the semiconductor wafer formation process of the method for manufacturing the semiconductor device 1000D according to a modified example of Embodiment 2 is omitted as it is the same as in Figure 12. Figure 25 is a schematic cross-sectional view showing the semiconductor wafer formation process of the method for manufacturing the semiconductor device according to a modified example of Embodiment 2. Note that Figure 25 shows the cross section along the dashed line X-X shown in Figure 12. Figure 26 is a schematic cross-sectional view showing the semiconductor wafer formation process of the method for manufacturing the semiconductor device 1000D according to a modified example of Embodiment 2. Note that Figure 26 shows the cross section along the dashed line Y-Y shown in Figure 12. Figure 27 is a schematic cross-sectional view showing the dicing process of the method for manufacturing the semiconductor device 1000D according to a modified example of Embodiment 2. Note that Figure 27 shows the state after dicing the semiconductor wafer 1D shown in Figure 25. Figure 28 is a schematic cross-sectional view showing the dicing process of the method for manufacturing the semiconductor device 1000D according to Embodiment 2. Note that Figure 28 shows the state after dicing the semiconductor wafer 1D shown in Figure 26.

[0066] In the manufacturing method of the semiconductor device 1000D, in the upper plating layer formation step of the wafer formation step described above, the plating layer 421 is provided only on the dicing line 11 located in the second region 107, as shown in Figures 25 and 26. By doing so, in the dicing step, burrs 422 are generated only on the dicing line 11 located in the second region 107, as shown in Figures 27 and 28. In other words, burrs 422 are formed only in the second region 107 of the outer peripheral portion 106 of the upper surface 101 of each semiconductor element 100D. In the bonding step, since the burrs 422 function as bonding material blocking portions 400, it is possible to suppress the bonding material 301 interposed between the lower surface 102 of the semiconductor element 100D and the upper surface 201 of the member to be bonded, from creeping up to the second region 107 side of the upper surface 101 of the semiconductor element 100D.

[0067] Embodiment 3. The semiconductor device 1000E in Embodiment 3 will be described using Figures 29 to 31. Figure 29 is a schematic top view of the semiconductor device 1000E according to Embodiment 3. Figure 30 is a schematic plan view of the semiconductor device 1000E according to Embodiment 3. Figure 31 is a schematic cross-sectional view of the semiconductor device 1000E according to Embodiment 3. Note that Figure 31 shows the cross section along the dashed line X-X shown in Figure 29.

[0068] In the semiconductor device 1000E of Embodiment 3, the bonding material sealing portion 400 is an inclined portion 430 provided on the side surface 103 of the semiconductor element 100E. In other words, the semiconductor device 1000E of Embodiment 3 differs from Embodiments 1 and 2 in that the bonding material sealing portion 400 is an inclined portion 430 rather than a protruding portion 410 or 420.

[0069] In this embodiment, as shown in Figures 30 and 31, the bonding material sealing portion 400 is an inclined portion 430 provided on the side surface 103 of the semiconductor element 100E. As shown in Figure 31, the inclined portion 430 is provided so as to widen from the lower surface 102 to the upper surface 101 of the semiconductor element 100E. Furthermore, as shown in Figure 30, it is desirable that the inclined portion 430 be provided around the entire circumference of the side surface 103 of the semiconductor element 100E.

[0070] In this embodiment, as shown in Figures 30 and 31, the lower plating layer 150 may be provided over the entire lower surface 102 of the semiconductor element 100E.

[0071] As described above, the semiconductor device 1000E of Embodiment 3 is configured. Similar to Embodiments 1 and 2, by providing a bonding material sealing portion 400 on the semiconductor element 100E, even when the semiconductor element 100E is bonded to the member to be bonded 200 via a paste-like bonding material, it is possible to suppress the bonding material from spreading onto the upper surface 101 of the semiconductor element 100E, thereby suppressing a decrease in the reliability of the semiconductor device.

[0072] In this embodiment, the bonding material sealing portion 400 is an inclined portion 430, and the inclined portion 430 is provided on the side surface 103 of the semiconductor element 100E. By doing so, the surface area of ​​the side surface 103 of the semiconductor element 100E can be increased, so that even if the bonding material 301 interposed between the lower surface 102 of the semiconductor element 100E and the upper surface 201 of the member to be bonded 200 creeps up onto the side surface 103 of the semiconductor element 100E, it is possible to suppress the bonding material 301 from creeping up onto the upper surface 101 of the semiconductor element 100E.

[0073] Furthermore, the inclined portion 430, which is a unique configuration of this embodiment, may be combined with the protruding portions 410 and 420 of Embodiments 1 and 2. By doing so, even when a semiconductor element is bonded to a member to be bonded 200 via a paste-like bonding material, it is possible to further suppress the bonding material from spreading onto the upper surface 101 of the semiconductor element, thereby further suppressing the deterioration of the reliability of the semiconductor device.

[0074] Next, an example of a manufacturing method for the semiconductor device 1000E according to Embodiment 3 will be described using Figures 32 and 33. Figures 32 and 33 are schematic cross-sectional views showing the dicing process of the manufacturing method for the semiconductor device 1000E according to Embodiment 3. The manufacturing method for the semiconductor device 1000E according to Embodiment 3 differs from that of Embodiments 1 and 2 in its dicing process. The dicing process will be described below, while the other processes will be the same as those in Embodiment 1. Note that in Figure 32, the detailed internal structure of the semiconductor wafer 1E is omitted.

[0075] In the dicing process of this embodiment, as shown in Figure 32, the upper surface of the semiconductor wafer 1E is fixed to the dicing sheet 2000, and the semiconductor wafer 1E is diced by bevel cutting. By dicing the semiconductor wafer 1E by bevel cutting, inclined portions 430 can be formed on the side surfaces 103 of each semiconductor element 100E, as shown in Figure 33. In the dicing process of this embodiment, as shown in Figure 32, the semiconductor wafer 1E is diced using, for example, a dicing blade 3000. For example, the semiconductor wafer 1E is diced with the tip portion 3001 of the dicing blade 3000 having a taper 3002.

[0076] The semiconductor device 1000E is manufactured through the process described above. As stated above, the manufacturing method of the semiconductor device 1000E in this embodiment further includes a bonding material sealing portion formation step, similar to embodiments 1 and 2. By forming the bonding material sealing portion 400, even when the semiconductor element 100E is bonded to the member to be bonded 200 via a paste-like bonding material 301 during the bonding process, it is possible to suppress the bonding material 301 from spreading onto the upper surface 101 of the semiconductor element 100E, thereby suppressing a decrease in the reliability of the semiconductor device.

[0077] Furthermore, in this embodiment, the inclined portion 430 is formed on the side surface 103 of the semiconductor element 100E during the dicing process. In this embodiment, since the inclined portion 430 functions as a bonding material blocking portion 400, even if the bonding material 301 interposed between the lower surface 102 of the semiconductor element 100E and the upper surface 201 of the member to be bonded 200 crawls up onto the side surface 103 of the semiconductor element 100E, it is possible to suppress the bonding material 301 from crawling up onto the upper surface 101 of the semiconductor element 100E.

[0078] Embodiment 4. The semiconductor device 1000F in Embodiment 4 will be described using Figures 34 to 36. Figure 34 is a schematic top view of the semiconductor device 1000F according to Embodiment 4. Figure 35 is a schematic plan view of the semiconductor device 1000F according to Embodiment 4. Figure 36 is a schematic cross-sectional view of the semiconductor device 1000F according to Embodiment 4. Note that Figure 36 shows the cross section along the dashed line X-X shown in Figure 34.

[0079] In the semiconductor device 1000F of Embodiment 4, the bonding material sealing portion 400 is a recess 440 provided on the semiconductor element 100F. In other words, the semiconductor device 1000F of Embodiment 4 differs from Embodiments 1 and 2 in that the bonding material sealing portion 400 is a recess 440 rather than a protruding portion 410 or 420.

[0080] In this embodiment, as shown in Figures 35 and 36, the bonding material sealing portion 400 is a recess 440 provided on the side surface 103 of the semiconductor element 100F. It is desirable that the width of the recess 440 be large. For example, in a side view, the width of the recess 440 may be 50% or more of the total width of the semiconductor element 100F. Furthermore, as shown in Figure 35, it is desirable that the recess 440 be provided around the entire circumference of the side surface 103 of the semiconductor element 100F. The recess 440 may, for example, be provided in the center of the lower surface 102 of the semiconductor element 100F.

[0081] In this embodiment, as shown in Figures 35 and 36, the lower plating layer 150 may be provided over the entire lower surface 102 of the semiconductor element 100F.

[0082] As described above, the semiconductor device 1000F of Embodiment 4 is configured. Similar to Embodiments 1 and 2, by providing a bonding material sealing portion 400 on the semiconductor element 100F, even when the semiconductor element 100F is bonded to the member to be bonded 200 via a paste-like bonding material 301, it is possible to suppress the bonding material 301 from spreading onto the upper surface 101 of the semiconductor element 100F, thereby suppressing a decrease in the reliability of the semiconductor device.

[0083] In this embodiment, the bonding material sealing portion 400 is a recess 440, and the recess 440 is provided on the semiconductor element 100F. This allows the bonding material 301 to enter the recess 440, so that even if the bonding material 301 interposed between the lower surface 102 of the semiconductor element 100F and the upper surface 201 of the member to be bonded 200 creeps up onto the side surface 103 of the semiconductor element 100F, it is possible to suppress the bonding material 301 from creeping up onto the upper surface 101 of the semiconductor element 100F. As mentioned above, it is desirable for the width of the recess 440 to be larger, so that more bonding material 301 can enter the recess 440, so that even if the bonding material 301 interposed between the lower surface 102 of the semiconductor element 100F and the upper surface 201 of the member to be bonded 200 creeps up onto the side surface 103 of the semiconductor element 100F, it is possible to further suppress the bonding material 301 from creeping up onto the upper surface 101 of the semiconductor element 100F.

[0084] Furthermore, the recess 440, which is a unique configuration of this embodiment, may be combined with the protrusions 410 and 420 of Embodiments 1 and 2. By doing so, even when a semiconductor element is bonded to a member to be bonded 200 via a paste-like bonding material, it is possible to further suppress the bonding material from spreading onto the upper surface 101 of the semiconductor element, thereby further suppressing the deterioration of the reliability of the semiconductor device.

[0085] Next, an example of a manufacturing method for the semiconductor device 1000F of Embodiment 4 will be described using Figures 37 and 38. Figures 37 and 38 are schematic cross-sectional views showing the dicing process of the manufacturing method for the semiconductor device 1000F according to Embodiment 4. The manufacturing method for the semiconductor device 1000F of Embodiment 4 differs from Embodiments 1 and 2 in its dicing process. The dicing process will be described below, while the other processes will be the same as in Embodiment 1. Note that in Figure 37, the detailed internal structure of the semiconductor wafer 1F is omitted.

[0086] In the dicing process of this embodiment, as shown in Figure 37, the upper surface of the semiconductor wafer 1F is fixed to the dicing sheet 2000, and the semiconductor wafer 1F is diced by step cutting. By dicing the semiconductor wafer 1F by step cutting, recesses 440 can be formed in each semiconductor element 100F, as shown in Figure 38. In the dicing process of this embodiment, as shown in Figure 37, the semiconductor wafer 1F is diced using, for example, a dicing blade 3000. For example, as shown in Figure 37(a), the first cut is made with a wide dicing blade 3000, and as shown in Figure 37(b), the second cut is made with a narrow dicing blade 3000 to dice the semiconductor wafer 1F.

[0087] The semiconductor device 1000F is manufactured through the process described above. As stated above, the manufacturing method of the semiconductor device 1000F in this embodiment further includes a bonding material sealing portion formation step, similar to embodiments 1 and 2. By forming the bonding material sealing portion 400, even when the semiconductor element 100F is bonded to the member to be bonded 200 via a paste-like bonding material 301 during the bonding process, it is possible to suppress the bonding material 301 from spreading onto the upper surface 101 of the semiconductor element 100F, thereby suppressing a decrease in the reliability of the semiconductor device.

[0088] Furthermore, in this embodiment, a recess 440 is formed in the semiconductor element 100F during the dicing process. In this embodiment, since the recess 440 functions as a bonding material sealing portion 400, even if the bonding material 301 interposed between the lower surface 102 of the semiconductor element 100F and the upper surface 201 of the member to be bonded 200 creeps up onto the side surface 103 of the semiconductor element 100F, it is possible to suppress the bonding material 301 from creeping up onto the upper surface 101 of the semiconductor element 100F.

[0089] The configurations shown in the embodiments described above are merely examples of the content of this disclosure and can be combined with other known technologies. Furthermore, the embodiments can be combined with each other, as well as with each other, and variations can be combined. Additionally, parts of the configuration can be omitted or modified without departing from the gist of this disclosure. [Explanation of symbols]

[0090] 1 1A 1B 1C 1D 1E 1F Semiconductor wafer, 11 Dicing line, 100 100A 100B 100C 100D 100E 100F Semiconductor element, 101 Top surface, 102 Bottom surface, 103 Side surface, 104 106 Outer periphery, 105 First region, 107 Second region, 110 Semiconductor substrate, 111 Top surface, 112 Bottom surface, 120 Upper electrode layer, 130 Upper plating layer, 140 Lower electrode layer, 150 Lower plating layer, 200 Member to be bonded, 201 Top surface, 300 Bonding layer, 301 Bonding material, 400 Bonding material sealing part, 410 Lower protrusion, 411 Plating layer, 412 Burr, 420 Upper protrusion, 421 Plating layer, 422 Burr, 430 Inclined part, 440 Recess, 1000 1000A 1000B 1000C 1000D 1000E 1000F Semiconductor device

Claims

1. Semiconductor elements and The member to be bonded on which the semiconductor element is mounted, A lower electrode layer provided on the lower surface of the semiconductor element, A lower plating layer having a predetermined thickness is provided on the lower surface of the lower electrode layer, A bonding layer is provided to bond the lower surface of the semiconductor element and the upper surface of the member to be bonded, and is composed of a paste-like bonding material. The semiconductor element is provided with a bonding material blocking portion that blocks the bonding material so that it does not crawl up onto the upper surface of the semiconductor element, The bonding material sealing portion is a lower protrusion provided on the outer periphery of the lower surface of the semiconductor element, protruding from the lower plating layer to a predetermined height below the semiconductor element, in a semiconductor device.

2. In a plan view, the semiconductor element is rectangular in shape. The semiconductor device according to claim 1, wherein the lower protrusion is provided only in a first region located on a pair of opposing sides in a plan view of the outer periphery of the lower surface of the semiconductor element.

3. Semiconductor elements and The member to be bonded on which the semiconductor element is mounted, An upper electrode layer provided on the upper surface of the semiconductor element, An upper plating layer having a predetermined thickness is provided on the upper surface of the upper electrode layer, A bonding layer is provided to bond the lower surface of the semiconductor element and the upper surface of the member to be bonded, and is composed of a paste-like bonding material. The semiconductor element is provided with a bonding material blocking portion that blocks the bonding material so that it does not crawl up onto the upper surface of the semiconductor element, The bonding material sealing portion is an upper protrusion provided on the upper surface of the semiconductor element at an outer peripheral portion that is outward in the outer peripheral direction from the upper electrode layer and the upper plating layer, and protrudes above the semiconductor element by a predetermined height from the upper plating layer.

4. In a plan view, the semiconductor element is rectangular in shape. The semiconductor device according to claim 3, wherein the upper protrusion is provided only in a second region located on a pair of opposing sides in a plan view of the outer periphery of the upper surface of the semiconductor element.

5. The semiconductor device according to claim 3 or claim 4, wherein the upper protrusion is provided in contact with the upper surface of the semiconductor element so as not to contact the side surface.

6. The semiconductor device according to claim 1 or claim 3, wherein the surface layer of the plating layer is made of Au.

7. The semiconductor device according to any one of claims 1 to 4, wherein the semiconductor element is composed of GaN.

8. The semiconductor device according to any one of claims 1 to 4, wherein the bonding material is a sintered Ag paste.

9. A bonding material sealing portion forming step, which involves forming a bonding material sealing portion on the semiconductor element to prevent the paste-like bonding material from spreading onto the upper surface of the semiconductor element, The bonding process includes joining the lower surface of the semiconductor element and the upper surface of the member to be bonded with a paste-like bonding material, The aforementioned process of forming the sealing portion of the joining material is as follows: A plating layer formation step in which a plating layer having a predetermined thickness is formed on the surface of the lower electrode layer formed on the lower surface of the semiconductor element, or on the upper surface of the semiconductor element, outward in the outer peripheral direction from the upper electrode layer formed on the upper surface of the semiconductor element, The process includes a dicing step of dicing a semiconductor wafer along a dicing line to form a plurality of semiconductor elements, A method for manufacturing a semiconductor device, wherein in the dicing step, the plating layer formed on the dicing line of the plating layer formed in the plating layer forming step protrudes to a predetermined height to form the bonding material sealing portion.

10. The method for manufacturing a semiconductor device according to claim 9, wherein the dicing step involves dicing the semiconductor wafer by bevel cutting.

11. The method for manufacturing a semiconductor device according to claim 9, wherein the semiconductor wafer is diced by step cutting in the dicing step.

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