Silicon carbide semiconductor equipment

Abstract

To provide a silicon carbide semiconductor device that can improve resistance against breakage.SOLUTION: An active region 10 and an edge terminal region 20 have the same SJ structure in which parallel pn layers 3 are formed as drift layers. In the edge terminal region 20, a p+ type extension part 14a to fix a JTE structure 21 to a potential of a source electrode 18 is provided between the active region 10 and the JTE structure 21. Between a p-type base extension part 4a and the parallel pn layers 3, the p+ type extension part 14a is provided in contact with these regions. The p+ type extension part 14a is an extension part of an upper part 14 of a p+ type region 12 provided in the active region 10 for relieving an electric field near a bottom surface of a gate trench 7. Between the p-type base extension part 4a and the parallel pn layers 3, an extension part of a lower part 13 of the p+ type region 12 is not provided. Therefore, a length of the edge terminal region 20 in a depth direction Z of a p-type column region 32 is longer than a length of the active region 10 in the depth direction Z of the p-type column region 32.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] This invention relates to a silicon carbide semiconductor device. [Background technology]

[0002] Conventionally, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors: MOS-type field-effect transistors with an insulated gate consisting of a three-layer structure of metal-oxide-semiconductor) are known, which have a superjunction (SJ) structure in which the drift layer is a parallel pn layer formed by alternately arranging n-type and p-type regions adjacent to each other in a direction parallel to the main surface of the semiconductor substrate (semiconductor chip).

[0003] By making the drift layer an SJ structure, n - Compared to a conventional drift layer composed only of mold regions, the impurity concentration of the drift layer can be increased, significantly reducing on-resistance. Furthermore, by using an SJ structure for the drift layer, the increase in on-resistance during high-temperature operation is suppressed. High-temperature operation refers to the operation of a semiconductor device when the semiconductor substrate (semiconductor chip) is at a high temperature due to a high-temperature environment, high voltage application, or high current flow.

[0004] The breakdown voltage structure of a power semiconductor device consists of multiple p-type regions selectively provided on the surface region of the front side of the semiconductor substrate in the edge termination region between the active region and the edge of the semiconductor substrate. In SiC-MOSFETs, it is well known that a double-zone junction termination extension (JTE) structure, composed of two p-type regions with different impurity concentrations, is used as the breakdown voltage structure.

[0005] FIG. 11 is a plan view showing a layout of a conventional silicon carbide semiconductor device as viewed from the front side of a semiconductor substrate. FIG. 12 is a cross-sectional view showing a cross-sectional structure taken along the cutting line AA-AA' of FIG. 11. FIG. 13 is a plan view showing a layout of an inner portion of an edge termination region in FIG. 12 as viewed from the front side of the semiconductor substrate. FIG. 14 is a plan view showing an enlarged view of the inside of the rectangular frame BB in FIG. 13. In FIG. 14, a layout of a p + -type extending portion 111a in a straight portion of the semiconductor substrate 140 is shown.

[0006] FIGS. 15 and 16 are plan views showing an enlarged view of the inside of the rectangular frame CC-CC' in FIG. 11. In FIGS. 15 and 16, layouts of a p + -type extending portion 111a and a p + -type extending portion 114a in a corner (chip corner) of the semiconductor substrate 140 are shown, respectively. In FIG. 11, a p-type column region 132 is shown by hatching. In FIGS. 12 and 13, an inner circumference (inner circumference of a p - -type region 122) 124a of a JTE structure is shown by a broken line. In FIG. 12, the numbers of n-type column regions 131 and p-type column regions 132 are simplified and are different from those in FIG. 16.

[0007] In FIGS. 13 and 14, a gate trench 107 is shown by a broken line. In FIGS. 14 and 15, a p + -type region 111, a lower portion 113 of a p + -type region 112, a p + -type extending portion 111a and a lower portion 115 of a p + -type connecting portion are shown by the same hatching. In FIG. 16, an upper portion 114 of a p + -type region 112, a p + -type extending portion 114a and an upper portion 116 of a p + -type connecting portion are shown by the same hatching. In FIGS. 15 and 16, the gate trench 107 is shown by a thick line, and the inner circumference 124a of the JTE structure 121 is shown by a broken line. A reference numeral 124b is an outer circumference (outer circumference of a p -- -type region 123) of the JTE structure 121.

[0008] The conventional silicon carbide semiconductor device 150 shown in Figures 11-16 is a trench gate type SiC-MOSFET with an SJ structure, comprising a parallel pn layer 103 acting as a drift layer inside a semiconductor substrate 140 made of silicon carbide (SiC) as the semiconductor material. The semiconductor substrate 140 is made of n + The material is formed by sequentially epitaxially growing parallel pn layers 103 and p-type base regions 104, respectively, on a starting substrate 141.

[0009] The parallel pn layer 103 is formed by alternately arranging n-type regions (hereinafter referred to as n-type column regions) 131 and p-type regions (hereinafter referred to as p-type column regions) 132 adjacent to each other in a first direction X parallel to the main surface of the semiconductor substrate 140. The n-type column regions 131 and p-type column regions 132 extend in a stripe-like manner across the entire area of ​​the semiconductor substrate 140 in a second direction Y parallel to the main surface of the semiconductor substrate 140 and perpendicular to the first direction X.

[0010] Both the active region 110 and the edge-terminal region 120 have drift layers composed of the same SJ structure. Both the n-type column region 131 and the p-type column region 132 have approximately the same width (short-side width) Wn101, Wp101, and approximately the same impurity concentration. Approximately the same width and approximately the same impurity concentration mean that they are the same width and the same impurity concentration, respectively, within a range that includes tolerances due to process variations.

[0011] In both the active region 110 and the edge-terminal region 120, the charge balance is generally maintained between the adjacent n-type column region 131 and the p-type column region 132. Charge balance is an indicator of the degree of equilibrium between the charge amount, which is expressed as the product of the carrier concentration (impurity concentration) and width Wn101 of the n-type column region 131, and the charge amount, which is expressed as the product of the carrier concentration and width Wp101 of the p-type column region 132.

[0012] In the active region 110, a trench gate structure is provided between the front surface of the semiconductor substrate 140 (the main surface on the p-type epitaxial layer 143 side) and the parallel pn layer 103. The trench gate structure is n + Type source area 105, p ++ It consists of a type contact region 106, a gate trench 107, a gate insulating film 108, and a gate electrode 109. The bottom surface of the gate trench 107 is n + Deep within the drain region 101, p + Type regions 111 and 112 are selectively provided.

[0013] p + The type regions 111 and 112 have the function of mitigating the electric field applied to the gate insulating film 108 at the bottom surface of the gate trench 107. + The mold region 111 is provided separately from the p-type base region 104 and faces the bottom surface of the gate trench 107. + The type region 112 is adjacent to the p-type base region 104 between the gate trenches 107, and p + It is located away from the mold region 111 and the gate trench 107.

[0014] p + The type region 112 is formed by epitaxially growing an n-type epitaxial layer 142, which will serve as a drift layer, on a parallel pn layer 103 in two stages (twice), and then ion implanting p-type impurities into each layer. The lower part adjacent to the depth Z (n + Type drain region 101 side portion) 113 and upper (n + This is a diffusion region composed of the part (114) on the source region 105 side. + Type region 111 is p + It is formed simultaneously with the lower part 113 of the mold region 112.

[0015] The edge termination region 120 surrounds the active region 110. The outer portion of the p-type epitaxial layer 143 (the edge side of the semiconductor substrate 140: the chip edge side) is removed, and a step 144 is formed on the front surface of the semiconductor substrate 140 within the edge termination region 120. The front surface of the semiconductor substrate 140 is recessed towards the drain electrode 119 on the second surface 140b, which is outside the first surface 140a on the chip center (center of the semiconductor substrate 140) side, with the step 144 as the boundary.

[0016] Due to this step 144, the p-type epitaxial layer 143 remains in a mesa-like (convex) shape in the center of the chip on the front surface of the semiconductor substrate 140. The first surface 140a of the front surface of the semiconductor substrate 140 is formed of the p-type epitaxial layer 143, and the second surface 140b is formed of the n-type epitaxial layer 142 that is exposed when the p-type epitaxial layer 143 is removed in the edge termination region 120.

[0017] In the edge termination region 120, outside the step 144, there are multiple p-type regions (in this case, two) with different impurity concentrations as a pressure-resistant structure. - type region 122, p -- A JTE structure 121 composed of type region 123) is provided. - Type region 122 and p -- The mold region 123 is provided between the second surface 140b of the front surface of the semiconductor substrate 140 and the parallel pn layer 103, in contact with the parallel pn layer 103, and concentrically surrounds the active region 110.

[0018] The parallel pn layer 103 extends beyond the JTE structure 121. The portion between the edge of the semiconductor substrate 140 and the parallel pn layer 103 is a normal n-type drift region 133 that is not an SJ structure. The second surface 140b of the front surface of the semiconductor substrate 140 is covered with an insulating layer (either a single-layer structure of interlayer insulating film 117, or a laminated structure in which a field oxide film (not shown) and interlayer insulating film 117 are stacked in sequence).

[0019] Furthermore, in the edge termination region 120, inside the step 144, between the first surface 140a of the front surface of the semiconductor substrate 140 and the parallel pn layer 103, p + Mold extension part 111a, p + A mold extension portion 114a and a p-type base extension portion 104a are provided. + Mold extension part 111a, p + The type extension portion 114a and the p-type base extension portion 104a are, respectively, p + type region 111, p + This is the upper part 114 of the mold region 112 and the extended portion of the p-type base region 104.

[0020] p + The mold extensions 111a, 114a and the p-type base extension 104a extend inward in the first direction X, reaching the outermost gate trench 107 in the first direction X (hereinafter referred to as the outermost gate trench 107a), and reach the longitudinal ends of all gate trenches 107 in the second direction Y, while extending outward to reach the third surface (mesa edge of the step) 140c that connects the first surface 140a and the second surface 140b of the front surface of the semiconductor substrate 140.

[0021] p + Mold extension part 111a, p + The type extension portion 114a and the p-type base extension portion 104a are provided over the entire area from the active region 110 to the step 144, surrounding the active region 110 (Figures 15, 16). + At least p + The mold extension portion 111a has an outer circumference 124c that extends beyond the inner circumference 124a of the JTE structure 121, and the innermost part of the JTE structure 121 is p - It overlaps with the inner edge of mold region 122 (Figures 12, 13).

[0022] The JTE structure 121 is provided in the inner portion 120a of the edge termination region 120 + In contact with the mold extension portion 111a, p + The p-type extended portions 111a, 114a and the p-type base extended portion 104a are fixed to the potential of the source electrode 118. The p-type column region 132 of the active region 110 is p+ It is adjacent to type region 112, p + Type region 112, p-type base region 104 and p ++ The potential of the source electrode 118 is fixed via the contact region 106.

[0023] The p-type column region 132 inside the JTE structure 121 of the edge-terminal region 120 is p + In contact with the mold extension portion 111a, p + The p-type extended portions 111a, 114a and the p-type base extended portion 104a are fixed to the potential of the source electrode 118. The p-type column region 132 in contact with the JTE structure 121 is fixed to the potential of the source electrode 118 via the JTE structure 121. The p-type column region 132 outside the JTE structure 121 is electrically free-floating.

[0024] In conventional vertical silicon carbide semiconductor devices with an SJ structure, a device has been proposed in which either a long p-type column region, where the length from the top surface to the bottom of the semiconductor substrate is relatively long, or a short p-type column region, where the length from the top surface to the bottom of the semiconductor substrate is relatively short, is arranged as the p-type column region of the parallel pn layer. By creating a charge balance with a high proportion of n-type impurities in the region where the short p-type column region is located, the location of avalanche generation is guided to the bottom of the short p-type column region, thereby eliminating current concentration in the channel and suppressing the decrease in avalanche breakdown voltage (see, for example, Patent Document 1 below). [Prior art documents] [Patent Documents]

[0025] [Patent Document 1] Japanese Patent Publication No. 2020-191441 [Overview of the project] [Problems that the invention aims to solve]

[0026] However, as mentioned above, in conventional SJ structure SiC-MOSFETs (see Figures 11-16), the drift layer is composed of the same SJ structure (n-type column region 131 and p-type column region 132) in both the active region 110 and the edge termination region 120. As a result, the breakdown voltage of the edge termination region 120 is lower than that of the active region 110, making it prone to avalanche breakdown in the edge termination region 120. This leads to the problem that the breakdown withstand voltage is lower compared to the case where avalanche breakdown occurs in the active region 110, which has a large area occupying most of the surface area of ​​the semiconductor substrate 140.

[0027] The purpose of this invention is to provide a silicon carbide semiconductor device that can improve fracture resistance in order to solve the problems of the conventional technology described above. [Means for solving the problem]

[0028] To solve the above-mentioned problems and achieve the objectives of the present invention, the silicon carbide semiconductor device according to this invention has the following features: An active region is provided on a semiconductor substrate made of silicon carbide. A termination region surrounds the active region. Parallel pn layers are provided inside the semiconductor substrate, extending from the active region to the termination region. The parallel pn layers are arranged in a first direction parallel to the front surface of the semiconductor substrate, with first conductivity type column regions and second conductivity type column regions alternately and repeatedly adjacent to each other. Between the first main surface of the semiconductor substrate and the parallel pn layers, a first semiconductor region of the second conductivity type is provided, extending from the active region to the termination region.

[0029] In the active region, a second semiconductor region of a first conductivity type is selectively provided between the first main surface and the first semiconductor region. The trench penetrates the second semiconductor region and the first semiconductor region in the depth direction and reaches the column region of the first conductivity type. A gate electrode is provided inside the trench via a gate insulating film. In the active region and the termination region, a high-concentration region of a second conductivity type is selectively provided between the first semiconductor region and the parallel pn layer. The high-concentration region of the second conductivity type has a higher impurity concentration than the second semiconductor region.

[0030] The breakdown structure is selectively provided between the first main surface and the parallel pn layer outside the first semiconductor region and the second conductivity type high-concentration region, and consists of one or more second conductivity type breakdown regions concentrically surrounding the active region. The first electrode is electrically connected to the second semiconductor region, the first semiconductor region and the second conductivity type high-concentration region. The second electrode is electrically connected to the second main surface of the semiconductor substrate. In the portion of the active region, the second conductivity type high-concentration region reaches a position deeper on the second main surface side than the bottom surface of the trench, and in the portion of the termination region, the surface on the second main surface side is shallower on the first main surface side than the portion of the active region.

[0031] Furthermore, in the silicon carbide semiconductor device according to this invention, the active region of the second conductivity type high concentration region has a first portion that is deeper on the second main surface side than the bottom surface of the trench, and a second portion that is shallower on the first main surface side than the bottom surface of the trench. The termination region of the second conductivity type high concentration region is characterized in that the second portion extends into the termination region.

[0032] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the first portion of the second conductivity type high concentration region surrounds the active region while maintaining a predetermined distance from the outermost side wall adjacent to the end region of the trench.

[0033] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the first portion of the second conductivity type high concentration region is terminated outward by a predetermined width of 0.35 μm or less from the outermost side wall adjacent to the termination region of the trench.

[0034] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the first portion of the second conductivity type high concentration region surrounds the active region while maintaining a predetermined distance from the inner circumference of the pressure-resistant structure.

[0035] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the portion of the termination region of the second conductivity type high concentration region is provided over the entire area between the active region and the breakdown structure.

[0036] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the above-described invention, the portion of the termination region of the second conductivity type high concentration region is selectively provided.

[0037] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the portion of the termination region of the second conductivity type high concentration region is provided only between the first semiconductor region and the second conductivity type column region.

[0038] Furthermore, in the silicon carbide semiconductor device according to this invention, the first conductivity type column region and the second conductivity type column region extend in a stripe shape in a second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction. The portion of the terminal region of the second conductivity type high-concentration region is provided in a stripe shape in the second direction.

[0039] Furthermore, in the silicon carbide semiconductor device according to this invention, the first conductivity type column region and the second conductivity type column region extend in a stripe shape in a second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction. The portion of the termination region of the second conductivity type high concentration region is scattered in the second direction and arranged in a matrix shape between the active region and the breakdown structure.

[0040] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the width in the first direction of the terminal region portion of the second conductivity type high concentration region is narrower than the width in the first direction of the second conductivity type column region.

[0041] According to the invention described above, the breakdown voltage of the termination region can be improved, so that the location where avalanche breakdown occurs can be changed to a large active region that occupies most of the surface area of ​​the semiconductor substrate. [Effects of the Invention]

[0042] The silicon carbide semiconductor device according to the present invention has the effect of improving fracture resistance. [Brief explanation of the drawing]

[0043] [Figure 1] This is a plan view showing the layout of the silicon carbide semiconductor device according to Embodiment 1 as seen from the front side of the semiconductor substrate. [Figure 2] This is a cross-sectional view showing the cross-sectional structure along the cutting line A-A' in Figure 1. [Figure 3] This is a plan view showing the layout of the inner portion of the edge termination region in Figure 2, as seen from the front side of the semiconductor substrate. [Figure 4] This is a plan view showing an enlarged view of the area within the rectangular frame B in Figure 3. [Figure 5] This is a plan view showing an enlarged view of the area within the rectangular frame C1-C1' in Figure 1. [Figure 6] This is a plan view showing an enlarged view of the area within the rectangular frame C1-C1' in Figure 1. [Figure 7] This is a plan view showing an enlarged view of the area within the rectangular frame C1-C1' in Figure 1. [Figure 8] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 2. [Figure 9] This is a plan view showing an enlarged view of the area within the rectangular frame C1-C1' in Figure 1. [Figure 10] This is a characteristic diagram showing the withstand voltage characteristics of Examples 1 and 2. [Figure 11] This is a plan view showing the layout of a conventional silicon carbide semiconductor device as seen from the front side of the semiconductor substrate. [Figure 12] This is a cross-sectional view showing the cross-sectional structure along the cutting line AA-AA' in Figure 11. [Figure 13] Figure 12 is a plan view showing the layout of the inner portion of the edge termination region as seen from the front side of the semiconductor substrate. [Figure 14] This is a plan view showing an enlarged view of the area within the rectangular frame BB in Figure 13. [Figure 15] This is a plan view showing an enlarged view of the area within the rectangular frame CC-CC' in Figure 11. [Figure 16] This is a plan view showing an enlarged view of the area within the rectangular frame CC-CC' in Figure 11. [Modes for carrying out the invention]

[0044] Preferred embodiments of the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these signs. In the following description of embodiments and in the accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted.

[0045] (Embodiment 1) The structure of the silicon carbide semiconductor device according to Embodiment 1 will now be described. Figure 1 is a plan view showing the layout of the silicon carbide semiconductor device according to Embodiment 1 as seen from the front side of the semiconductor substrate. Figure 2 is a cross-sectional view showing the cross-sectional structure along the cutting line A-A' in Figure 1. Figure 3 is a plan view showing the layout of the inner (chip center side) portion of the edge termination region in Figure 2 as seen from the front side of the semiconductor substrate. Figure 4 is a plan view showing an enlarged view of the area within the rectangular frame B in Figure 3. Figures 5-7 are plan views showing an enlarged view of the area within the rectangular frame C1-C1' in Figure 1.

[0046] Figures 3 and 4(a) show the p of the straight section (edge) of the semiconductor substrate 40. + The layout of type region 11a is shown. Figure 4(b) shows n + Type source region 5 and p ++ The layout of the type contact area 6 is shown. Figures 5 and 6 show the p at the corner (chip corner: apex) of the semiconductor substrate 40. + An example layout of the mold region 11a is shown. The upper figure of Figures 5 and 6 shows an enlarged view of the area within the rectangular frame C1-C1' in Figure 1, and the lower figure shows an enlarged view of the area within the rectangular frame C2 and C3 in the upper figure. Figure 7 shows the p at the corner of the semiconductor substrate 40. + The layout of the mold extension portion 14a is shown.

[0047] In Figure 2, the p-type column region 32 is shown by hatching. In Figure 2, the inner circumference (p) of the JTE structure 21 - (Inner circumference of type region 22) 24a, p + The portion overlapping with the mold extension 14a is shown with a dashed line, and the gate runner 45 is omitted from the illustration. In Figure 2, the number of n-type column regions 31 and p-type column regions 32 is simplified and differs from Figure 7. In Figures 3 to 6, the n-type column regions 31 and p-type column regions 32 are omitted from the illustration. In Figure 3, the inner circumference 24a of the JTE structure 21 is shown with a dashed line. In Figures 3 and 4(a), the gate trench 7 is shown with a dashed line.

[0048] In Figure 4(b), p ++ The type contact region 6 is shown by hatching. In Figures 4(a), 5, and 6, p + Type area 11, 11a, p + Lower part 13 and p of type region 12+ The lower part 15 of the mold connection is shown with the same hatching. In the upper part of Figure 5, the upper part of Figure 6, and Figure 7, the gate trench 7 is shown with a thick line, and the inner circumference 24a and outer circumference (p -- The outer perimeter of type region 23) 24b is shown by a dashed line. In Figure 7, p + Upper part 14 of type region 12, p + mold extension portion 14a and p + The upper part 16 of the mold connection section is shown with the same hatching.

[0049] The silicon carbide semiconductor device 50 according to Embodiment 1 shown in Figures 1 to 7 is a vertical SiC-MOSFET with an SJ structure, in which a trench gate structure (device structure) is provided on the front side (first main surface) of the semiconductor substrate (semiconductor chip) 40 made of silicon carbide (SiC) in the active region 10, and the drift layer (drift region) is a parallel pn layer 3. The active region 10 is the region in which the main current flows when the MOSFET is in the ON state. The active region 10 is located approximately in the center of the semiconductor substrate 40 (center of the chip).

[0050] The active region 10 is located inside (towards the center of the chip) the outermost gate trench 7 (outermost gate trench 7a) in the first direction X (described later) (towards the edge of the semiconductor substrate 40: towards the chip edge), and in the second direction Y (described later) n + This is the portion inside the edge (not shown) of the type source region 5. Multiple unit cells (element constituent units) of the same structure (trench gate structure) are arranged adjacent to each other in the active region 10. The trench gate structure is provided in the active region 10 between the front surface of the semiconductor substrate 40 and the parallel pn layer 3.

[0051] The area between the active region 10 and the edge (chip edge) of the semiconductor substrate 40 is the edge termination region 20. The edge termination region 20 surrounds the active region 10. The edge termination region 20 has the function of mitigating the electric field on the front side of the semiconductor substrate 40 of the drift layer and maintaining the breakdown voltage. Breakdown voltage is the limit voltage at which leakage current does not increase excessively and the element does not malfunction or break down. In the edge termination region 20, a JTE structure 21, which will be described later, is arranged between the front side of the semiconductor substrate 40 and the parallel pn layer 3 as a breakdown voltage structure.

[0052] The semiconductor substrate 40 is made of n + The semiconductor substrate 40 is an epitaxial semiconductor formed by sequentially depositing parallel pn layers 3 and epitaxial layers 42 and 43, which form the p-type base region (first semiconductor region) 4, on the front surface of a type starting substrate 41. The main surface of the p-type epitaxial layer 43 is the front surface, and n + The main surface on the mold starting substrate 41 side is designated as the back surface (second main surface). + The starting substrate 41 is n + This is the drain region 1. The parallel pn layer 3 uses, for example, the multi-stage epitaxial method or the trench-embedded epitaxial method described later, n + It is formed on the mold starting substrate 41.

[0053] The parallel pn layer 3 is formed by alternately arranging n-type regions (n-type column regions: first conductivity type column regions) 31 and p-type regions (p-type column regions: second conductivity type column regions) 32 adjacent to each other in a first direction X parallel to the main surface of the semiconductor substrate 40. The n-type column regions 31 and p-type column regions 32 extend in a stripe-like manner across almost the entire area of ​​the semiconductor substrate 40 in a second direction Y parallel to the main surface of the semiconductor substrate 40 and perpendicular to the first direction X. Both the active region 10 and the edge termination region 20 are composed of drift layers with the same SJ structure. A charge balance is generally maintained between adjacent n-type column regions 31 and p-type column regions 32.

[0054] Charge balance is an index that indicates the degree of balance between the charge amount, which is expressed as the product of the carrier concentration (impurity concentration) and width Wn1 of the n-type column region 31, and the charge amount, which is expressed as the product of the carrier concentration and width Wp1 of the p-type column region 32. For example, both the n-type column region 31 and the p-type column region 32 have approximately the same width (short-side width) Wn1 and Wp1, and approximately the same impurity concentration. Approximately the same width and approximately the same impurity concentration means that they are the same width and the same impurity concentration within a range that includes tolerances due to variations in the manufacturing process.

[0055] n-type epitaxial layer 42, parallel pn layer 3 and n + The portion between the drain region 1 and the n-type buffer region (an n-type region that is not an SJ structure) 2 may be used. The n-type buffer region 2 consists of a parallel pn layer 3, n + It is in contact with the n-type drain region 1 and the normal n-type drift region 33 which is not an SJ structure as described later. The impurity concentration of the n-type buffer region 2 is less than or equal to the impurity concentration of the n-type column region 31. The n-type column region 31 and the p-type column region 32 are in contact with the n-type buffer region 2 in the depth direction Z (if the n-type buffer region 2 is not provided, then n + The drain region (1) is reached.

[0056] The p-type column region 32 of the active region 10 is the p + It is adjacent to type region 12, p + Type region 12, p-type base region 4 and p ++ The potential of the source electrode 18 is fixed via the type contact region 6. The p-type column region 32 of the edge termination region 20 is p + In contact with the mold extension portion 14a, p + The p-type column region 32, located outside the JTE structure 21, is electrically connected to the source electrode 18 via the p-type extension 14a and the p-type base extension 4a (described later), or via these regions and the JTE structure 21.

[0057] The trench gate structure has a p-type base region 4, n + Type source region (second semiconductor region) 5, p ++It is composed of a p-type contact region 6, a gate trench (trench) 7, a gate insulating film 8, and a gate electrode 9. The p-type base region 4 is provided between the front surface of the semiconductor substrate 40 and the parallel pn layer 3. The p-type base region 4 is the part of the p-type epitaxial layer 43 excluding the n + type source region 5 and p ++ type contact region 6. The p-type base region 4 extends outward from the active region 10 to a step 44 described later.

[0058] n + type source region 5 and p ++ type contact regions 6 are selectively provided between the front surface of the semiconductor substrate 40 and the p-type base region 4 in the active region 10 respectively. n + type source region 5 and p ++ type contact regions 6 are in contact with the p-type base region 4 and are exposed on the front surface of the semiconductor substrate 40. n + type source region 5 and p ++ That the n-type source region 5 and the p-type contact region 6 are exposed on the front surface of the semiconductor substrate 40 means that these regions are in contact with the source electrode (first electrode) 18 described later at the first surface 40a of the front surface of the semiconductor substrate 40.

[0059] n + type source region 5 and p ++ type contact regions 6 extend linearly, for example, in the second direction Y between adjacent gate trenches 7. n + The n-type source region 5 is arranged closer to the gate trench 7 than the p ++ type contact region 6 and is in contact with the gate insulating film 8 on the side wall of the gate trench 7. The p ++ type contact region 6 may not be provided. p ++ When the p-type contact region 6 is not provided, p ++ instead of the p-type contact region 6, the p-type base region 4 is exposed on the first surface 40a of the front surface of the semiconductor substrate 40.

[0060] The gate trench 7 extends in the depth direction Z from the first surface 40a of the front surface of the semiconductor substrate 40, n +The gate trenches penetrate the p-type source region 5 and the p-type base region 4 to reach the n-type column region 31 (or the n-type current diffusion region if an n-type current diffusion region is provided, as described later). The gate trenches 7 extend in a stripe shape in the second direction Y. The length (longitudinal length) of each gate trench 7 is set so that the short-side end of the gate trench 7 terminates near the boundary between the active region 10 and the edge termination region 20.

[0061] Therefore, the gate trenches 7 terminating at the corners of the active region 10 are progressively shorter in length as they are positioned further outward in the first direction X, depending on the curvature of the corners of the active region 10 (Figures 5-7). The portion of the gate trench 7 terminating at the corners of the active region 10 that is not adjacent to any other gate trenches 7 outward in the first direction X becomes the outermost gate trench 7a. Outside the outermost gate trench 7a, n + A type source region 5 is not provided. A gate electrode 9 is provided inside the gate trench 7 via a gate insulating film 8.

[0062] Between the p-type base region 4 and the parallel pn layer 3 in the active region 10, n is greater than the bottom surface of the gate trench 7. + In a deep position on the drain region 1 side (back side of the semiconductor substrate 30), p + Type regions (second conductivity type high concentration regions) 11 and 12 are selectively provided. + Type regions 11 and 12 extend in a stripe-like manner in the second direction Y. + The JFET (Junction FET) portion between type regions 11 and 12 contains n + An n-type column region 31 (or an n-type current diffusion region, described later) is interposed to extend from the type drain region 1 to the p-type base region 4.

[0063] p +The n-type regions 11 and 12 have a fixed potential at the source electrode 18 and function to deplete (or deplete the JFET portion, or both) when the MOSFET is off, thereby mitigating the electric field applied to the gate insulating film 8 at the bottom of the gate trench 7. The JFET portion is the adjacent p-type regions of the n-type column region 31 (or the n-type current diffusion region described later). + This is the portion between type regions 11 and 12, adjacent to the channel formed in the current path of the drift current flowing between the drain and source when the MOSFET is on.

[0064] p + The type region 12 is formed on the surface region of the n-type epitaxial layer 42. Specifically, p + The type region 12 is formed by epitaxially growing an n-type epitaxial layer 42, which will be a drift layer (parallel pn layer 3), in two stages (twice), and implanting p-type impurities into each layer each time. The lower part adjacent to the depth Z (n + Type drain region 1 side portion: 1st part) 13 and upper (n + The part on the source region 5 side (the front side of the semiconductor substrate 30): the second part) 14 is a diffusion region. + Type region (first part) 11 is p + It is formed simultaneously with the lower part 13 of the mold region 12.

[0065] Specifically, p + The mold region 11 is positioned separately from the p-type base region 4 and faces the bottom surface and bottom corner of the gate trench 7 in the depth direction Z. The bottom corner of the gate trench 7 is the boundary between the side wall and the bottom surface of the gate trench 7. + The type region 11 is adjacent to the n-type column region 31 in the depth direction Z. + The mold region 11 may be in contact with the gate insulating film 8 at the bottom surface of the gate trench 7. + The width of the mold area 11 is set to be wider by a predetermined width W11 than the width of the gate trench 7, extending from the side walls of the gate trench 7 (both sides in the short direction (first direction X) and both ends in the long direction (second direction Y)) (see Figure 4(a)).

[0066] Directly below gate trench 7 (n + p (on the drain region 1 side) + All type regions 11 are set to the same width. Therefore, p + The mold region 11 terminates outward by a predetermined width W11 in the second direction Y from the longitudinal end of the gate trench 7 and does not come into contact with the JTE structure 21. + Of the type region 11, p directly below the outermost gate trench 7a + The mold region 11a also terminates outward by a width W11 in the first direction X from the side wall of the gate trench 7 and does not come into contact with the JTE structure 21 (see Figures 3, 4(a)).

[0067] p + The width of the mold region 11 is, for example, wider in both the short direction (first direction X) and the long direction (second direction Y) from the side walls of the gate trench 7 (both sides in the short direction and both ends in the long direction) by approximately the same width W11. Specifically, for example, if the width W10 of the gate trench 7 in the short direction is about 0.8 μm, then p + The width of the mold region 11 may be set to widen by a width W11 of approximately 0.35 μm or less in the first direction X and the second direction Y, respectively, from both sides of the gate trench 7 in the short direction and from both ends in the long direction.

[0068] Thus, p + The mold regions 11 and 11a extend slightly outward from the outermost side wall adjacent to the edge end region 20 of the gate trench 7, enclosing the boundary between the side wall and the bottom surface (bottom corner). The outermost side wall adjacent to the edge end region 20 of the gate trench 7 refers to the outer side wall of the outermost gate trench 7a, and the side walls at both ends in the longitudinal direction of the gate trench 7. p directly below the outermost gate trench 7a + The type region 11a surrounds the active region 10, and n in the active region 10 + All p located at the deepest position on the drain region 1 side + Type region 11 and p + The lower part 13 of the type region 12 is connected.

[0069] In this way p +Type regions 11, 11a and p + The lower part 13 of the mold region 12 terminates near the boundary between the edge termination region 20 and the active region 10, surrounding the boundary between the outermost side wall adjacent to the edge termination region 20 of the gate trench 7 and the bottom surface, and is almost not present in the edge termination region 20. + The outer periphery 24c of the mold region 11a may be curved at a predetermined distance from the inner periphery 24a of the JTE structure 21 at the corner of the semiconductor substrate 40 (see Figure 5), or it may be stepped at a predetermined distance from the outermost periphery of the cell (see Figure 6).

[0070] p + The outer periphery 24c of the mold region 11a is a straight line in the straight portion of the semiconductor substrate 40, maintaining a predetermined distance from the outermost periphery of the cell. The outermost periphery of the cell is the boundary between the outermost unit cell among the multiple unit cells arranged adjacent to each other in the active region 10 and the edge termination region 20, and is approximately the same as the outer periphery of the active region 10. Maintaining a predetermined distance from the outermost periphery of the cell means making it wider by a width W11 from the outermost side wall adjacent to the edge termination region 20 of the gate trench 7.

[0071] p + By making the outer circumference 24c of the mold region 11a curved while maintaining a predetermined distance from the inner circumference 24a of the JTE structure 21, p at the corner of the semiconductor substrate 40 + The radius of curvature of the corners of the outer circumference 24c of the type region 11a can be increased. This allows p to be generated when the MOSFET is off. + Since the electric field is less likely to concentrate on the gate insulating film 8 at the bottom of the gate trench 7 near the corner of the outer circumference 24c of the mold region 11a, the breakdown voltage of the edge termination region 20 can be improved.

[0072] p + By making the outer periphery 24c of the mold region 11a a stepped shape that maintains a predetermined distance from the outermost periphery of the cell, p + Between the outer circumference 24c of the mold region 11a and the inner circumference 24a of the JTE structure 21, the p described later +The number of p-type column regions 32 in contact with the mold extension portion 14a can be increased. As a result, in the edge-terminal region 20, the number of p-type column regions 32 with a length in the depth direction Z is longer than that of the p-type column regions 32 in the active region 10, so the effects of this embodiment 1 (improved fracture resistance), which will be described later, can be obtained more effectively.

[0073] Also, p + The width of the type region 11 in the short direction is narrower than the width Wn1 of the n-type column region 31 in the short direction. + Type region 11 is, for example, p + Partially extending toward type region 12, or other p + type area (hereinafter p + (This is a type connecting part) via p + It is connected to type region 12. Figures 5 and 6 show p + Type region 11 and p + The lower part 13 of type region 12 is p + Figure 7 shows the state in which the lower part 15 of the type connecting section connects them in a grid pattern. + Upper part 14 and p of type region 12 + This shows the state in which the upper part 16 of the mold connecting section is arranged in a grid pattern.

[0074] p + The type region 12 is in contact with the p-type base region 4 between adjacent gate trenches 7, and p + It is located away from the mold region 11 and the gate trench 7. + The type region 12 is adjacent to the p-type column region 32 in the depth direction Z. + The width of the type region 12 in the short direction is made approximately the same as the width Wp1 of the p-type column region 32, p + The type region 12 may be in contact with the n-type column region 31. + The lower part 13 of the type region 12 is formed by ion implantation of p-type impurities into the p-type column region 32 and is provided overlapping the p-type column region 32.

[0075] p + The lower part 13 of the type region 12 overlaps with the p-type column region 32, +The impurity concentration in the lower part 13 of type region 12 is p + The impurity concentration becomes higher than that of the upper part 14 of the type region 12. As a result, when a positive voltage (forward voltage) is applied to the drain electrode 19 relative to the source electrode 18, p + Type region 11 and p + The JFET portion between the lower part 13 and the type region 12 becomes more prone to depletion. As a result, the time until the drain-source current is interrupted is shortened, and the short-circuit withstand capability can be improved.

[0076] Also, p + Because the lower part 13 of the p-type region 12 overlaps with the p-type column region 32, when a positive voltage is applied to the drain electrode 19 relative to the source electrode 18, the depletion layer is less likely to spread within the p-type column region 32. Therefore, p + Compared to the case where the lower part 13 of the type region 12 does not overlap with the p-type column region 32, the effective length of the p-type column region 32 in the depth direction Z becomes shorter. Therefore, p + Compared to the case where the lower part 13 of the type region 12 does not overlap with the p-type column region 32, the pressure resistance of the active region 10 can be intentionally reduced.

[0077] Between adjacent gate trenches 7, p + An n-type current diffusion region (not shown) may be provided between the type regions 11, 12, the p-type base region 4, and the n-type column region 31, in contact with these regions and reaching the side wall of the gate trench 7 in the first direction X. The n-type current diffusion region is a so-called current spreading layer (CSL) that reduces the carrier spreading resistance. The impurity concentration of the n-type current diffusion region is equal to or greater than the impurity concentration of the n-type column region 31.

[0078] The interlayer insulating film 17 is provided over the entire surface of the front surface of the semiconductor substrate 40 and covers the gate electrode 9. The source electrode 18 makes ohmic contact with the first surface 40a of the front surface of the semiconductor substrate 40 at the contact hole of the interlayer insulating film 17, and the p-type base region 4, n + Type source region 5 and p ++It is electrically connected to the contact area 6. The drain electrode (second electrode) 19 is on the back surface (n) of the semiconductor substrate 40. + Provided on the entire surface of the back surface of the mold starting substrate 41, n + It is electrically connected to the drain region 1.

[0079] The p-type epitaxial layer 43 is removed by etching from the outer portion of the edge termination region 20, and remains in a mesa-like (convex) shape in the center of the front surface of the semiconductor substrate 40. The mesa-like retention of the p-type epitaxial layer 43 in the center of the front surface of the semiconductor substrate 40 creates a step 44 on the front surface of the semiconductor substrate 40. Due to this step 44, the front surface of the semiconductor substrate 40 is recessed towards the drain electrode 19 on the second surface 40b, which is outside the first surface 40a on the chip center side, with the step 44 as the boundary.

[0080] The first surface 40a of the front surface of the semiconductor substrate 40 is formed of a p-type epitaxial layer 43. The second surface 40b of the front surface of the semiconductor substrate 40 is the exposed surface of the n-type epitaxial layer 42, which is exposed when the p-type epitaxial layer 43 is removed from the outer portion of the edge termination region 20. Outside the step 44, a JTE structure 21 is provided between the second surface 40b of the front surface of the semiconductor substrate 40 and the parallel pn layer 3 as a breakdown structure, composed of multiple p-type regions with different impurity concentrations.

[0081] The JTE structure 21 is separated from the active region 10 by a third surface (mesa edge of a step) 40c that connects the first surface 40a and the second surface 40b of the front surface of the semiconductor substrate 40. The JTE structure 21 is made up of multiple p-type regions (second conductivity type breakdown voltage regions) with different impurity concentrations, arranged concentrically adjacent to each other surrounding the active region 10, such that the p-type regions with lower impurity concentrations are arranged further outward from the active region 10. Figure 2 shows the JTE structure 21, with two p-type regions (p - Type region 22 and p -- This shows a double-zone JTE structure composed of type region 23).

[0082] p-type region (p- Type region 22 and p -- Lower surface (n + The side of the drain region 1 is p + The lower surface of the type region 11 and p + n + It is located at a shallow position on the type source area 5 side, and p + The lower surface of the upper part 14 of the mold region 12 and the p described later + n is lower than the lower surface of the mold extension portion 14a. + It is located deep on the side of the type drain region 1. The upper surface (n + The side of the type source region 5 is p + The lower surface of the upper part 14 of the mold region 12 and p + n is lower than the lower surface of the mold extension portion 14a. + It is located at a shallow position on the type source area 5 side.

[0083] The upper surface of the p-type region constituting the JTE structure 21 is exposed to the second surface 40b of the front surface of the semiconductor substrate 40. The second and third surfaces 40b and 40c of the front surface of the semiconductor substrate 40 are covered with an insulating layer (either a single-layer structure of interlayer insulating film 17, or a laminated structure in which a field oxide film (not shown) and interlayer insulating film 17 are sequentially stacked). Exposure to the second and third surfaces 40b and 40c of the front surface of the semiconductor substrate 40 means contact with the insulating layer on the second and third surfaces 40b and 40c of the front surface of the semiconductor substrate 40.

[0084] The parallel pn layer 3 extends beyond the JTE structure 21. The parallel pn layer 3 has the p-type column region 32 positioned furthest out in the first direction X. The portion between the edge of the semiconductor substrate 40 and the parallel pn layer 3 is a normal n-type drift region 33, which is not an SJ structure. The impurity concentration in the normal n-type drift region 33 is less than or equal to the impurity concentration in the n-type column region 31 of the parallel pn layer 3. The parallel pn layer 3 is exposed on the second surface 40b of the front surface of the semiconductor substrate 40, between the JTE structure 21 and the normal n-type drift region 33.

[0085] Between the front surface of the semiconductor substrate 40 and the normal n-type drift region 33, there is a parallel pn layer 3 and an n +A channel stopper region 25 is selectively provided. The normal n-type drift region 33 and n + The n-type channel stopper region 25 is provided along the outer periphery of the semiconductor substrate 40 and surrounds the parallel pn layer 3. + The channel stopper region 25 is exposed on the side surface of the semiconductor substrate 40. + Instead of the channel stopper region 25, p + A channel stopper region may be provided.

[0086] Inside the step 44 of the edge termination region 20, a p-type base extension 4a is provided between the first surface 40a of the front surface of the semiconductor substrate 40 and the parallel pn layer 3. Between the p-type base extension 4a and the parallel pn layer 3, in contact with the p-type base extension 4a and the parallel pn layer 3 (n-type column region 31 and p-type column region 32), + A type-extended portion (second conductive type high-concentration region) 14a is provided. + The type extension portion 14a and the p-type base extension portion 4a are, respectively, p + This is the upper part 14 of the mold region 12 and the extended portion of the p-type base region 4.

[0087] p + The mold extension portion 14a and the p-type base extension portion 4a extend inward in the first direction X to the outermost gate trench 7a, and in the second direction Y to the longitudinal ends of all gate trenches 7, and extend outward to the third surface 40c of the front surface of the semiconductor substrate 40. + The type extension portion 14a and the p-type base extension portion 4a are provided over the entire area from the active region 10 to the step 44, surrounding the active region 10 (Figure 7). + In the mold extension portion 14a, all p + Type region 12 is p + The upper part 14 of the mold region 12 is connected at the end in the second direction Y.

[0088] p + The lower surface of the mold extension portion 14a is n greater than the second surface 40b of the front surface of the semiconductor substrate 40. + It is located deep on the drain region 1 side.+ The mold extension portion 14a extends outward beyond the step 44 and is exposed on the second surface 40b of the front surface of the semiconductor substrate 40. + The mold extension portion 14a is the innermost p of the JTE structure 21 - It overlaps the inner edge of the mold region 22 (Figures 2 and 6). The JTE structure 21 is p + In contact with the mold extension portion 14a, p + The potential of the source electrode 18 is fixed via the type extension portion 14a and the p-type base extension portion 4a.

[0089] The p-type column region 32 inside the JTE structure 21 of the edge-terminal region 20 is p + In contact with the mold extension portion 14a, p + The p-type column region 32 is fixed to the potential of the source electrode 18 via the p-type extension portion 14a and the p-type base extension portion 4a. The p-type column region 32 in contact with the JTE structure 21 is fixed to the potential of the source electrode 18 via the JTE structure 21. The p-type column region 32 outside the JTE structure 21 is exposed to the second surface 40b of the front surface of the semiconductor substrate 40. The p-type column region 32 outside the JTE structure 21 is electrically floating.

[0090] In the edge termination region 20, p + The lower surface of the mold extension portion 14a, the p-type region (p) constituting the JTE structure 21 - Type region 22 and p -- The lower surface of the type region 23) and the second surface 40b of the front surface of the semiconductor substrate 40 are the p of the active region 10. + Lower surface of type region 12 (p + n (lower surface of the lower part 13 of type region 12) + It is located at a shallow position on the source region 5 side. Therefore, the length in the depth direction Z of the p-type column region 32 in the edge termination region 20 is longer than the length in the depth direction Z of the p-type column region 32 in the active region 10.

[0091] By making the length in the depth direction Z of the p-type column region 32 of the edge termination region 20 longer than the length in the depth direction Z of the p-type column region 32 of the active region 10, the breakdown voltage of the edge termination region 20 becomes higher than that of the active region 10. This makes it possible to create a structure in which the SiC-MOSFET (silicon carbide semiconductor device 50) undergoes avalanche yield in the large active region 10, which occupies most of the surface area of ​​the semiconductor substrate 40. As a result, the breakdown withstand voltage can be improved.

[0092] Instead of the JTE structure 21, a floating p-type region called a Field Limiting Ring (FLR) may be provided. In this case as well, p + The lower surface of the type extension portion 14a and the lower surface of the FLR are p + Type regions 11, 11a and p + n + By positioning it at a shallower depth on the source region 5 side, the length in the depth direction Z of the p-type column region 32 in the edge termination region 20 becomes longer than the length in the depth direction Z of the p-type column region 32 in the active region 10, thereby improving fracture resistance.

[0093] A gate runner 45 (see Figure 1) is provided between the active region 10 and the JTE structure 21. The gate runner 45 includes, for example, a gate polysilicon wiring layer provided on the first surface 40a of the front surface of the semiconductor substrate 40 via a field oxide film (not shown). This gate polysilicon wiring layer is covered with an interlayer insulating film 17. All gate electrodes 9 of the active region 10 are connected to the gate polysilicon wiring layer. The gate runner electrically connects the gate electrodes 9 to the gate pads 46 (electrode pads: see Figure 1).

[0094] The operation of the silicon carbide semiconductor device 50 according to this embodiment will now be described. When a positive voltage (forward voltage) is applied to the drain electrode 19 relative to the source electrode 18, and a voltage greater than or equal to the gate threshold voltage is applied to the gate electrode 9, a channel (n-type inversion layer) is formed in the portion of the p-type base region 4 along the side wall of the gate trench 7. As a result, n+ From type drain region 1 through channel n + The main current (drift current) flows towards the source region 5, and the SiC-MOSFET (silicon carbide semiconductor device 50) turns on.

[0095] On the other hand, when a forward voltage is applied between the source and drain, and a voltage less than the gate threshold voltage is applied to the gate electrode 9, p + When the pn junction (main junction of the active region 10) between the p-type regions 11 and 12 and the n-type column region 31 of the parallel pn layer 3 with the p-type base region 4 is reverse-biased, the main current stops flowing, and the SiC-MOSFET remains in the off state. When the main junction (pn junction) of the active region 10 is reverse-biased, the depletion layer expands from the pn junction, and the predetermined breakdown voltage of the active region 10 is ensured.

[0096] Furthermore, when the SiC-MOSFET is off, the pn junction between the p-type column region 32 and the n-type column region 31 is reverse-biased, and the depletion layer expands from this pn junction, so that the breakdown voltage is borne by the parallel pn layer 3. This ensures a predetermined breakdown voltage that exceeds the breakdown voltage achievable with the impurity concentration of the drift layer (n-type column region 31). In addition, since the length in the depth direction Z of the p-type column region 32 is longer in the edge-terminal region 20 than in the active region 10, avalanche yielding is more likely to occur in the active region 10.

[0097] A method for manufacturing the silicon carbide semiconductor device 50 according to Embodiment 1 will be described. First, n + n becomes type drain region 1 + A drift layer including parallel pn layers 3 is formed on the front surface of a starting substrate (semiconductor wafer) 41. At this time, for example, using a multi-stage epitaxial method, the n-type epitaxial layer 42 that will become the drift layer is grown epitaxially in multiple stages (multiple times), and each time p-type impurities such as aluminum (Al) are ion-implanted into the n-type epitaxial layer, the portion that will become the p-type column region 32 of the parallel pn layer 3 is selectively formed.

[0098] The portion of the n-type epitaxial layer 42 that remains n-type without ion implantation between adjacent p-type column regions 32 becomes the n-type column region 31 of the parallel pn layer 3. + The entire area between the starting substrate 41 and the parallel pn layer may be left as an n-type buffer region 2 without ion implantation. The following explanation will use the case where an n-type buffer region 2 is provided as an example. The portion between the parallel pn layer 3 and the chip edge (the edge of the part that will become a semiconductor chip) that is not ion implanted and remains n-type becomes a normal n-type drift region 33.

[0099] The n-type column region 31 may be formed by ion implantation of n-type impurities. In this case, instead of the n-type epitaxial layer 42, an undoped epitaxial layer or n - The n-type epitaxial layer is divided into multiple stages and epitaxially grown in multiple stages. In this case, the n-type buffer region 2 and the normal n-type drift region 33 can be appropriately implanted with n-type impurities according to the impurity concentration. For this reason, for example, it is possible to form an n-type buffer region 2 and a normal n-type drift region 33 with a lower impurity concentration than the n-type column region 31.

[0100] Next, by ion implantation of p-type impurities, p-type impurities are implanted in the surface region of the parallel pn layer 3, adjacent to the n-type column region 31 and the p-type column region 32 of the parallel pn layer 3 in the depth direction Z. + Type region 11 and p + The lower part 13 of the mold region 12 is selectively formed. + The lower part 13 of the p-type region 12 is formed to overlap with the p-type column region 32 by ion implantation of p-type impurities into the surface region of the p-type column region 32. + Simultaneously with type region 11, p + Type region 11 and p + p between the lower part 13 of type region 12 + The lower part 15 of the mold connection is selectively formed.

[0101] Furthermore, the n-type epitaxial layer 42 is thickened to a predetermined thickness by epitaxial growth. Next, p-type impurities are ion-implanted into the increased thickness of the n-type epitaxial layer 42 in the depth direction Z. + Lower part 13 and p of type region 12 + Adjacent to the lower part 15 of the type connecting section, p + Upper part 14 and p of type region 12 + The upper part 16 of the mold connecting section is selectively formed. Also, p + Simultaneously with the upper part 14 of the type region 12, in the inner portion 20a of the edge termination region 20, a parallel pn layer 3 adjacent to the p in the depth direction Z is formed. + A mold extension portion 14a is formed.

[0102] Next, a p-type epitaxial layer 43, which will become the p-type base region 4, is epitaxially grown on the n-type epitaxial layer 42. + Epitaxial layers 42 and 43 are sequentially stacked on a starting substrate 41 to fabricate a semiconductor substrate (semiconductor wafer) 40 containing a parallel pn layer 3 within the n-type epitaxial layer 42. Next, the p-type epitaxial layer 43 (or the surface region of the n-type epitaxial layer 42) is removed by etching in the outer portion of the edge termination region 20 to expose the parallel pn layer 3 in the outer portion of the edge termination region 20.

[0103] As a result, a step 44 is formed on the front surface of the semiconductor substrate 40, and the p-type epitaxial layer 43 remains in a mesa-like manner in the inner portion 20a of the edge termination region 20 and in the active region 10. The parallel pn layer 3 is exposed on the second surface 40b, which has become the new front surface of the semiconductor substrate 40 in the outer portion of the edge termination region 20. The mesa edge (third surface 40c) of the step 44 on the front surface of the semiconductor substrate 40 may be obtuse (inclined surface) or approximately right (vertical surface) with respect to the second surface 40b of the front surface of the semiconductor substrate 40, for example.

[0104] Next, by ion implantation, n + Type source area 5, p ++ Type contact area 6, JTE structure 21(p -type region 22, p -- Type region 23) and n + Each type channel stopper region 25 is selectively formed. + Type source region 5 and p ++ The type contact regions 6 are selectively formed on the surface regions of the p-type epitaxial layer 43. ++ Simultaneously with the contact area 6, p is present in the inner portion 20a of the edge termination area 20. ++ A contact region (not shown) on the outer circumference of the mold may be formed.

[0105] JTE structure 21 and n + The type channel stopper region 25 is selectively formed on the surface region of the parallel pn layer 3 exposed on the second surface 40b of the front surface of the semiconductor substrate 40. The JTE structure 21 is p + Type regions 11, 12 and p + It is formed at a different timing than the mold extension portion 14a. The innermost p of the JTE structure 21 - The inner edge of the mold region 22 is near the step 44 on the front surface of the semiconductor substrate 40, p + It is formed so as to overlap the mold extension portion 14a. + The channel stopper region 25 is n + The p-type source region 5 may be formed simultaneously with the p-type epitaxial layer 43. The portion of the p-type epitaxial layer 43 that remains at the same impurity concentration as during epitaxial growth without ion implantation becomes the p-type base region 4 and the p-type base extension 4a.

[0106] Next, heat treatment is performed to activate the ion-implanted impurities in the epitaxial layers 42 and 43. Then, from the front surface of the semiconductor substrate 40, n + The source region 5 and the base region 4 of type p penetrate through, + A gate trench 7 is formed opposite the mold region 11. Next, a gate insulating film 8, gate electrode 9, interlayer insulating film 17, source electrode 18, and drain electrode 19 are formed by a general method. After that, the semiconductor wafer (semiconductor substrate 40) is diced (cut) into individual chips to complete the silicon carbide semiconductor device 50 shown in Figures 1-7.

[0107] In the manufacturing method of the silicon carbide semiconductor device 50 according to Embodiment 1 described above, the parallel pn layer 3 may be formed using a trench-embedded epitaxial method instead of the multi-stage epitaxial method. When using the trench-embedded epitaxial method, trenches (SJ trenches) with the same depth as the length Z in the depth direction of the p-type column region 32 are formed in the n-type epitaxial layer 42, leaving a portion that becomes the n-type column region 31, and these SJ trenches are filled with p-type epitaxial layers that become the p-type column region 32 to form the parallel pn layer 3.

[0108] As described above, according to Embodiment 1, the JTE structure provided in the edge termination region is fixed to the potential of the source electrode. + The lower surface of the type extension is n in the active region. + The deepest position on the drain region side is p + Type region (p directly below the gate trench) + n below the bottom surface of the type region + It is located at a shallow position on the source region side. As a result, the length in the depth direction of the p-type column region in the edge-terminal region becomes longer than the length in the depth direction of the p-type column region in the active region, improving the breakdown voltage of the edge-terminal region, and thus the breakdown voltage of the edge-terminal region can be made higher than that of the active region. Therefore, the location where avalanche yield occurs becomes a large active region that occupies most of the surface area of ​​the semiconductor substrate, improving the breakdown tolerance.

[0109] (Embodiment 2) Next, the structure of the silicon carbide semiconductor device according to Embodiment 2 will be described. Figure 8 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 2. The layout of the silicon carbide semiconductor device 60 according to Embodiment 2, as seen from the front side of the semiconductor substrate 40, is the same as in Figure 1. Figure 8 shows the cross-sectional structure along the cutting line A-A' in Figure 1. Figure 9 is a plan view showing an enlarged view of the area within the rectangular frame C1-C1' in Figure 1. Figure 9 shows the p of Figure 8 + This shows the layout of the mold extension portion 64a at the corner of the semiconductor substrate 40.

[0110] In Figure 8, the p-type column region 32 is shown by hatching. In Figure 8, the inner circumference 24a of the JTE structure 21 is p + The portion overlapping with the extended part 64a is shown with a dashed line, and the gate runner 45 is omitted from the illustration. In Figure 8, the number of n-type column regions 31 and p-type column regions 32 is simplified and differs from Figure 9. In the upper part of Figure 9, the gate trench 7 is shown with a thick line, and the inner circumference 24a and outer circumference 24b of the JTE structure 21 are shown with dashed lines. In Figure 9, p + Upper part 14 of type region 12, p + mold extension portion 64a and p + The upper part 16 of the mold connection section is shown with the same hatching.

[0111] The difference between the silicon carbide semiconductor device 60 according to Embodiment 2 and the silicon carbide semiconductor device 50 according to Embodiment 1 (see Figures 2 and 7) is that in the inner portion 20a of the edge termination region 20, p + The mold extension portion 64a is selectively provided. + The mold extension portion 64a is p + The upper part 14 of the mold region 12 was formed simultaneously with p + This is the extension of the upper part 14 of the mold region 12. For example, p + The type extension portion 64a may be provided only between the p-type base extension portion 4a and the p-type column region 32, and not between the p-type base extension portion 4a and the n-type column region 31.

[0112] In this case, the adjacent p + Between the extended sections 64a, the n-type column region 31 extends to the p-type base extended section 4a. Therefore, between the active region 10 and the step 44, the length of the n-type column region 31 in the depth direction Z is longer than the length of the p-type column region 32 in the depth direction Z. + The width of the type extension portion 64a in the short direction may be narrower than the width Wp1 of the p-type column region 32 in the short direction (not shown). + The type extension portion 64a may extend linearly in the second direction Y between the p-type base extension portion 4a and the p-type column region 32 (Figure 9), or it may be scattered in the second direction Y (not shown).

[0113] p +When the mold extension portion 64a extends linearly in the second direction Y, p + The end of the mold extension portion 64a in the longitudinal direction (second direction Y) is the p of the JTE structure 21. - It overlaps with the inner edge of type region 22. + The longitudinal end of the type extension portion 64a terminates inward from the end of the p-type column region 32 in the second direction Y. + When the mold extension portion 64a is scattered in the second direction Y, p + The mold extension portion 64a is provided in a matrix shape between the active region 10 and the step 44 when viewed from the front side of the semiconductor substrate 30. The outermost p in the second direction Y + The mold extension portion 64a is the p of the JTE structure 21 - It overlaps with the inner edge of type region 22. The outermost p in the second direction Y + The type extension portion 64a is located inside the end of the p-type column region 32 in the second direction Y.

[0114] p + Regardless of the layout of the mold extension portion 64a, the outermost p in the first direction X + The mold extension portion 64a is the innermost p of the JTE structure 21 - It overlaps with the inner edge of mold region 22 (Figure 8). + The portion of the mold extension 64a adjacent to the outermost gate trench 7a is p + The upper part 16 of the type connecting section, and p + The lower part 15 of the mold connection (not shown in Figures 8 and 9), and the p directly below the outermost gate trench 7a. + It may be connected to the mold region 11a. The outermost gate trench 7a is the outermost gate trench 7 in the first direction X and the portion of the gate trench 7 that terminates at a corner of the active region 10 that is not adjacent to any other gate trenches 7 in the first direction X.

[0115] The method for manufacturing the silicon carbide semiconductor device 60 according to Embodiment 2 is the same as the method for manufacturing the silicon carbide semiconductor device 50 according to Embodiment 1, p + The layout of the mold extension portion 64a can be changed.

[0116] As described above, according to Embodiment 2, in the inner portion of the edge termination region, p is present only between the p-type base extension and the p-type column region. + By providing the mold extension portion, the same effects as in Embodiment 1 can be obtained, and these effects can be further improved.

[0117] (Examples) The breakdown voltage of the silicon carbide semiconductor devices 50 and 60 according to the above-described embodiments 1 and 2 was verified. Figure 10 is a characteristic diagram showing the breakdown voltage characteristics of embodiments 1 and 2. The horizontal axis of Figure 10 shows the sample names (embodiments 1 and 2, conventional example, and comparative example), and the vertical axis shows the breakdown voltage BVdss. The numerical values ​​on the bar graph are the breakdown voltage values ​​of each sample. Figure 10 shows the simulation results of the breakdown voltage of the edge termination region 20 and the breakdown voltage of the active region 10 (hereinafter referred to as the comparative example) of the silicon carbide semiconductor devices 50 and 60 according to embodiments 1 and 2 (hereinafter referred to as embodiments 1 and 2).

[0118] For comparison, Figure 10 also shows the simulation results of the breakdown voltage of the edge termination region 120 of a conventional silicon carbide semiconductor device 150 (hereinafter referred to as the conventional example). The difference between the conventional example and Examples 1 and 2 is that the inner portion 120a of the edge termination region 120 is provided in contact with the JTE structure 121. + The boundary between the p-type extended portion 111a and the p-type column region 132 is the active region 110. + The boundary between the type region 112 and the p-type column region 132 is at the same depth. The pressure resistance of the active region 110 in the conventional example is the same as the pressure resistance of the active region 10 in Examples 1 and 2.

[0119] As shown in Figure 10, in the conventional example, it was confirmed that the withstand voltage of the edge termination region 120 was lower than that of the active region 110. On the other hand, in Examples 1 and 2, it was confirmed that the withstand voltage of the edge termination region 20 could be made higher than that of the active region 10. Furthermore, in Example 2, it was confirmed that the withstand voltage of the edge termination region 20 could be increased by approximately 50V compared to Example 1.

[0120] Therefore, as in Examples 1 and 2, the JTE structure 21 is fixed to the potential of the source electrode 18 in the edge termination region 20. + The depth position of the bottom surface of the mold extension portion 14a is n + It was confirmed that the pressure resistance of the edge-terminal region 20 can be improved by making the source region 5 shallower and making the length in the depth direction Z of the p-type column region 32 of the edge-terminal region 20 longer than the length in the depth direction Z of the p-type column region 32 of the active region 10.

[0121] Furthermore, as in Example 2, the JTE structure 21 is fixed to the potential of the source electrode 18 in the edge termination region 20. + By providing the p-type extension portion 64a only between the p-type base extension portion 4a and the p-type column region 32 of the parallel pn layer 3, the JTE structure 21 is fixed to the potential of the source electrode 18. + It was confirmed that the pressure resistance of the edge termination region 20 can be further increased compared to the case where the mold extension portion 14a is provided over the entire inner portion 20a of the edge termination region 20.

[0122] In summary, the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit of the invention. For example, it is sufficient to make the length in the depth direction of the p-type column region of the edge-terminal region longer than the length in the depth direction of the p-type column region of the active region, thereby making the pressure resistance of the edge-terminal region higher than that of the active region, and the p between adjacent gate trenches + The lower part of the type region and the p-type column region of the parallel pn layer do not necessarily have to overlap. Furthermore, the present invention is not limited to MOSFETs, but can be applied to silicon carbide semiconductor devices with various SJ structures in which the drift layer is a parallel pn layer.In addition, although the first conductivity type was set to n-type and the second conductivity type to p-type in the embodiments described above, the present invention also holds true even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial applicability]

[0123] As described above, the silicon carbide semiconductor device according to the present invention is useful as a power semiconductor device used in power conversion devices, power supply devices for various industrial machines, and the like. [Explanation of symbols]

[0124] 1 n + Type drain region 2 n-type buffer area 3 parallel pn layers 4 p-type base region 4a p type base extension 5 n + Type source area 6 p ++ Type Contact Area 7 Gate Trench 7a Outermost gate trench 8 gate insulating film 9. Postal Service 10 Active area 11 p for electric field relaxation directly below the gate trench + type area 11a p for electric field relaxation directly below the outermost gate trench + type area 12 p for electric field relaxation between adjacent gate trenches + type area 13 p for electric field relaxation between adjacent gate trenches + Lower part of the type domain 14 p for electric field relaxation between adjacent gate trenches + Top of the type region 14a,64a p + Mold extension 15 p + Lower part of the mold connection section 16 pages + Upper part of the mold connection section 17 Interlayer insulating film 18 Source electrodes 19 Drain electrode 20 Edge Termination Region 20a Inner portion of the edge termination region 21 JTE structure 22 p of JTE structure - type area 23 p of JTE structure -- type area 24a Inner circumference of JTE structure 24b Outer periphery of the JTE structure 24c p for electric field relaxation directly below the outermost gate trench + Outer perimeter of the type region 25 n + Type channel stopper region 31 n-type column region 32 p-type column regions 33 Normal n-type drift region 40 Semiconductor substrates 40a~40c Front side of semiconductor substrate 41 n + Mold starting substrate 42 n-type epitaxial layer 43 p-type epitaxial layer 44 Steps on the front surface of the semiconductor substrate 45 Gate Runner 46 Gate Pad 50,60 Silicon Carbide Semiconductor Devices Wn1 n-type column region width in the short direction Wp1 p-type column region width in the short direction X First direction parallel to the front surface of the semiconductor substrate Y: A second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction. Z-direction (depth)

Claims

1. An active region provided on a semiconductor substrate made of silicon carbide, A terminal region surrounding the active region, A parallel pn layer is provided inside the semiconductor substrate extending from the active region to the termination region, in which a first conductivity type column region and a second conductivity type column region are alternately and repeatedly arranged adjacent to each other in a first direction parallel to the front surface of the semiconductor substrate, A first semiconductor region of a second conductivity type is provided between the first main surface of the semiconductor substrate and the parallel pn layer, and extends from the active region to the termination region. A second semiconductor region of a first conductivity type is selectively provided between the first main surface and the first semiconductor region in the active region, A trench that penetrates the second semiconductor region and the first semiconductor region in the depth direction and reaches the first conductivity type column region, A gate electrode is provided inside the trench via a gate insulating film, A second conductivity type high-concentration region, having a higher impurity concentration than the second semiconductor region, is selectively provided between the first semiconductor region and the parallel pn layer in the active region and the termination region. A breakdown structure comprising one or more second conductivity type breakdown regions selectively provided between the first main surface and the parallel pn layer outside the first semiconductor region and the second conductivity type high-concentration region, and concentrically surrounding the periphery of the active region, A first electrode electrically connected to the second semiconductor region, the first semiconductor region, and the second conductivity type high concentration region, A second electrode electrically connected to the second main surface of the semiconductor substrate, Equipped with, The second conductivity type high concentration region is, In the active region, the position reaches a depth deeper than the bottom surface of the trench, on the second main surface side. A silicon carbide semiconductor device characterized in that the surface on the second main surface side is located shallower toward the first main surface side in the terminal region than in the active region.

2. The portion of the active region in the second conductivity type high concentration region is, A first portion that is deeper on the second main surface side than the bottom surface of the trench, It has a second portion that is shallower on the first main surface side than the bottom surface of the trench, The silicon carbide semiconductor device according to claim 1, characterized in that the portion of the termination region of the second conductivity type high concentration region is such that the second portion extends to the termination region.

3. The silicon carbide semiconductor device according to claim 2, characterized in that the first portion of the second conductivity type high concentration region surrounds the active region while maintaining a predetermined distance from the outermost side wall adjacent to the termination region of the trench.

4. The silicon carbide semiconductor device according to claim 2, characterized in that the first portion of the second conductivity type high concentration region is terminated outward by a predetermined width of 0.35 μm or less from the outermost side wall adjacent to the termination region of the trench.

5. The silicon carbide semiconductor device according to claim 2, characterized in that the first portion of the second conductivity type high concentration region surrounds the active region while maintaining a predetermined distance from the inner circumference of the pressure-resistant structure.

6. The silicon carbide semiconductor device according to claim 1, characterized in that the portion of the termination region of the second conductivity type high concentration region is provided over the entire area between the active region and the breakdown structure.

7. The silicon carbide semiconductor device according to claim 1, characterized in that the portion of the termination region of the second conductivity type high concentration region is selectively provided.

8. The silicon carbide semiconductor device according to claim 7, characterized in that the portion of the terminal region of the second conductivity type high concentration region is provided only between the first semiconductor region and the second conductivity type column region.

9. The first conductivity type column region and the second conductivity type column region extend in a stripe shape in a second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction. The silicon carbide semiconductor device according to claim 8, characterized in that the portion of the termination region of the second conductivity type high concentration region is provided in a stripe shape in the second direction.

10. The first conductivity type column region and the second conductivity type column region extend in a stripe shape in a second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction. The silicon carbide semiconductor device according to claim 8, characterized in that the portion of the termination region of the second conductivity type high concentration region is scattered in the second direction and arranged in a matrix between the active region and the breakdown structure.

11. The silicon carbide semiconductor device according to claim 7, characterized in that the width in the first direction of the portion of the terminal region of the second conductivity type high concentration region is narrower than the width in the first direction of the second conductivity type column region.

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