Method for manufacturing semiconductor devices

Abstract

Provided is a semiconductor device that enables greater refinement or a higher degree of integration. In the invention, a first electroconductor is formed on a substrate, a ferroelectric layer is formed on the first electroconductor, and a second electroconductor is formed on the ferroelectric layer while substrate heating is being performed. The ferroelectric layer comprises hafnium oxide and zirconium oxide. After the second electroconductor has been formed, no heating treatment at 500°C or higher is performed.

Description

[Technical Field]

[0001] One aspect of the present invention relates to metal oxides, capacitive elements utilizing metal oxides, and methods for manufacturing them. Alternatively, one aspect of the present invention relates to transistors, semiconductor devices, and electronic devices. Alternatively, one aspect of the present invention relates to methods for manufacturing semiconductor devices. Alternatively, one aspect of the present invention relates to semiconductor wafers and modules.

[0002] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Semiconductor elements such as transistors, as well as semiconductor circuits, computing devices, and memory devices, are all forms of semiconductor devices. Display devices (such as liquid crystal displays and light-emitting displays), projection devices, lighting devices, electro-optical devices, energy storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices may also be considered to have semiconductor devices.

[0003] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the invention disclosed herein relates to a product, a method, or a method of manufacture. Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] In recent years, the development of semiconductor devices has progressed, with LSIs, CPUs, and memory being the main components used in them. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memory) formed on chips by processing semiconductor wafers, and electrodes that serve as connection terminals are formed on them.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memory are mounted on circuit boards, such as printed circuit boards, and used as components in various electronic devices.

[0006] Furthermore, the technology of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials.

[0007] Furthermore, transistors using oxide semiconductors are known to have extremely low leakage current in the non-conductive state. For example, Patent Document 1 discloses a low-power CPU that takes advantage of the low leakage current characteristic of transistors using oxide semiconductors. Also, for example, Patent Document 2 discloses a memory device that can retain its contents for a long period of time by taking advantage of the low leakage current characteristic of transistors using oxide semiconductors.

[0008] Furthermore, in recent years, with the miniaturization and weight reduction of electronic devices, there has been an increasing demand for even higher density integrated circuits. There is also a need to improve the productivity of semiconductor devices, including integrated circuits. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 2012-257187 [Patent Document 2] Japanese Patent Publication No. 2011-151383 [Overview of the project] [Problems that the invention aims to solve]

[0010] One aspect of the present invention aims to provide a semiconductor device with less variation in the electrical characteristics of transistors. Alternatively, one aspect of the present invention aims to provide a semiconductor device with good reliability. Alternatively, one aspect of the present invention aims to provide a semiconductor device with good electrical characteristics. Alternatively, one aspect of the present invention aims to provide a semiconductor device with a large on-current. Alternatively, one aspect of the present invention aims to provide a semiconductor device that can be miniaturized or highly integrated. Alternatively, one aspect of the present invention aims to provide a semiconductor device with low power consumption.

[0011] One aspect of the present invention aims to provide a capacitive element containing a material that may have ferroelectric properties. Alternatively, one aspect of the present invention aims to provide the above-mentioned capacitive element with good productivity. Alternatively, one aspect of the present invention aims to provide a semiconductor device having the above-mentioned capacitive element and a transistor. Alternatively, one aspect of the present invention aims to provide the above-mentioned semiconductor device that can be miniaturized or highly integrated.

[0012] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other problems from the description in the specification, drawings, and claims. [Means for solving the problem]

[0013] One aspect of the present invention is a method for manufacturing a capacitive element, comprising forming a first conductor on a substrate, forming a ferroelectric layer on the first conductor, and forming a second conductor on the ferroelectric layer while heating the substrate, wherein the ferroelectric layer contains hafnium oxide and zirconium oxide.

[0014] In the above configuration, the ferroelectric layer may be formed by thermal ALD, and no heat treatment above 500°C may be performed after the formation of the second conductor. Furthermore, in the above configuration, it is preferable that the precursor used in forming the ferroelectric layer does not contain hydrocarbons.

[0015] In the above, it is preferable that the second conductor is deposited by thermal ALD method. Furthermore, in the above, it is preferable that the precursor used in the deposition of the second conductor does not contain hydrocarbons. Furthermore, in the above, it is preferable that the substrate heating temperature is 350°C or higher and 450°C or lower.

[0016] Another aspect of the present invention is a semiconductor device comprising a capacitive element and a transistor electrically connected to the capacitive element, wherein the capacitive element comprises a first conductor, a second conductor, and a ferroelectric layer, the ferroelectric layer being provided between the first conductor and the second conductor, the ferroelectric layer comprising hafnium oxide and zirconium oxide, and the transistor having an oxide semiconductor in its channel-forming region.

[0017] In the above, the concentration of hydrogen and at least one of carbon contained in the ferroelectric layer is 5 × 10 20 atoms / cm 3 The following is preferable:

[0018] Furthermore, in the above, the concentration of hydrogen and at least one of carbon contained in the ferroelectric layer is 1 × 10⁻⁶. 20 atoms / cm 3 The following is preferable:

[0019] In the above configuration, the first conductor may be electrically connected to either the source or the drain of the transistor. Furthermore, in the above configuration, it is preferable that the thickness of the ferroelectric layer is 10 nm or less.

[0020] Furthermore, in the above configuration, the capacitive element may be placed above the transistor.

[0021] In the above configuration, a first insulator may be placed below the capacitive element, a second insulator may be placed covering the capacitive element, the first insulator may be in contact with the upper surface of the second insulator in a region that does not overlap with the capacitive element, and both the first and second insulators may contain silicon nitride.

[0022] In the above configuration, a first insulator may be placed below the transistor, a second insulator may be placed covering the capacitive element, the first insulator may be in contact with the upper surface of the second insulator in a region that does not overlap with the transistor and the capacitive element, and both the first and second insulators may contain silicon nitride.

[0023] In the above, it is preferable that the second insulator has a first layer and a second layer on top of the first layer.

[0024] In the above configuration, an interlayer insulating film may be placed above the transistor, the interlayer insulating film having an opening that reaches either the source or the drain of the transistor, a first conductor placed in contact with the side and bottom surfaces of the opening, a ferroelectric layer placed over the first conductor, and a second conductor placed on top of the ferroelectric layer. [Effects of the Invention]

[0025] According to one aspect of the present invention, a semiconductor device with less variation in the electrical characteristics of transistors can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with a large on-current can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided.

[0026] According to one aspect of the present invention, a capacitive element containing a material capable of ferroelectricity can be provided. Alternatively, according to one aspect of the present invention, the above-mentioned capacitive element can be provided with good productivity. Alternatively, according to one aspect of the present invention, a semiconductor device having the above-mentioned capacitive element and a transistor can be provided. Alternatively, according to one aspect of the present invention, the above-mentioned semiconductor device that can be miniaturized or highly integrated can be provided.

[0027] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one embodiment of the present invention does not need to possess all of these effects. Other effects will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other effects from the description in the specification, drawings, and claims. [Brief explanation of the drawing]

[0028] Figures 1A to 1C are cross-sectional views showing a method for manufacturing a capacitive element according to one aspect of the present invention. Figure 2 is a model diagram illustrating the crystal structure of hafnium oxide according to one aspect of the present invention. Figure 3A is a top view of a semiconductor device according to one embodiment of the present invention. Figures 3B to 3D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. Figures 4A and 4B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. Figure 5A illustrates the classification of IGZO crystal structures. Figure 5B illustrates the XRD spectrum of a CAAC-IGZO film. Figure 5C illustrates the micro-electron diffraction pattern of a CAAC-IGZO film. Figure 6A is a top view of a semiconductor device according to one embodiment of the present invention. Figure 6B is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. Figure 7A is a top view of a semiconductor device according to one embodiment of the present invention. Figure 7B is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. Figure 8A is a top view of a semiconductor device according to one embodiment of the present invention. Figure 8B is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. Figure 9A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 9B to 9D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 10A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 10B to 10D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 11A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 11B to 11D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 12A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 12B to 12D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 13A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 13B to 13D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 14A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 14B to 14D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 15A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 15B to 15D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 16A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 16B to 16D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 17A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 17B to 17D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 18A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 18B to 18D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 19A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 19B to 19D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 20A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 20B to 20D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 21A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 21B to 21D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 22A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 22B to 22D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 23A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 23B to 23D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 24A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 24B to 24D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 25 is a top view illustrating a microwave processing apparatus according to one aspect of the present invention. Figure 26 is a cross-sectional view illustrating a microwave processing apparatus according to one aspect of the present invention. Figure 27 is a cross-sectional view illustrating a microwave processing apparatus according to one aspect of the present invention. Figure 28 is a cross-sectional view illustrating a microwave processing apparatus according to one aspect of the present invention. Figure 29A is a plan view of a semiconductor device according to one aspect of the present invention. Figures 29B and 29C are cross-sectional views of a semiconductor device according to one aspect of the present invention. Figure 30 is a cross-sectional view showing the configuration of a storage device according to one aspect of the present invention. Figure 31 is a cross-sectional view showing the configuration of a storage device according to one aspect of the present invention. Figure 32 is a cross-sectional view showing the configuration of a storage device according to one aspect of the present invention. Figure 33 is a cross-sectional view showing the configuration of a storage device according to one aspect of the present invention. Figures 34A and 34B are cross-sectional views showing the configuration of a storage device according to one aspect of the present invention. Figures 35A to 35C are cross-sectional views of a semiconductor device according to one embodiment of the present invention. Figure 36A is a block diagram showing an example of the configuration of a storage device according to one aspect of the present invention. Figure 36B is a perspective view showing an example of the configuration of a storage device according to one aspect of the present invention. Figure 37A is a circuit diagram showing an example of a memory cell configuration. Figure 37B is a graph showing an example of the hysteresis characteristics of a ferroelectric layer. Figure 37C is a timing chart showing an example of a memory cell driving method. Figures 38A to 38E are schematic diagrams of a storage device according to one embodiment of the present invention. Figures 39A to 39H show an electronic device according to one aspect of the present invention. Figure 40A is an optical microscope image showing the appearance of the sample. Figure 40B is a schematic cross-sectional view of the sample. Figure 40C shows the input voltage waveform. Figure 41A shows the measurement results for PE characteristics. Figure 41B shows the GIXD measurement results. Figure 42 shows the SIMS analysis results. Figure 43 shows the SIMS analysis results. Figures 44A and 44B show the measurement results of fatigue characteristics. Figure 45 shows the PE characteristics for each voltage amplitude of a triangular wave. [Modes for carrying out the invention]

[0029] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope. Therefore, the present invention is not to be construed as being limited to the following embodiments.

[0030] Furthermore, in drawings, size, layer thickness, or area may be exaggerated for clarity. Therefore, they are not necessarily limited to that scale. Also, the drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers, resist masks, etc., may be unintentionally reduced due to processes such as etching, but this may not be reflected in the drawings for ease of understanding. In addition, in drawings, the same reference numerals may be used in common across different drawings for the same part or parts with similar functions, and repeated explanations may be omitted. Also, when referring to similar functions, the hatch pattern may be the same, and no specific reference numeral may be assigned.

[0031] Furthermore, in particular, in top views (also called "plan views"), perspective views, etc., descriptions of some components may be omitted to facilitate understanding of the invention. In addition, descriptions of some hidden lines may be omitted.

[0032] Furthermore, the ordinal numbers used in this specification, such as "first," "second," etc., are for convenience only and do not indicate the order of processes or stacking. Therefore, for example, "first" can be replaced with "second" or "third," etc., as appropriate in the explanation. Also, the ordinal numbers described in this specification may not be the same as the ordinal numbers used to specify an aspect of the present invention.

[0033] Furthermore, in this specification, terms indicating placement, such as "above" and "below," are used for convenience to explain the positional relationships between components with reference to the drawings. The positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms used are not limited to those described in the specification and can be appropriately rephrased depending on the situation.

[0034] For example, if it is explicitly stated in this specification that X and Y are connected, then the disclosure in this specification includes cases where X and Y are electrically connected, where X and Y are functionally connected, and where X and Y are directly connected. Therefore, it is not limited to predetermined connection relationships, such as those shown in the figures or text, but also includes connection relationships other than those shown in the figures or text. Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0035] Furthermore, in this specification, a transistor is defined as an element having at least three terminals, including a gate, a drain, and a source. It also has a region where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) (hereinafter also referred to as the channel-forming region), and current can flow between the source and the drain through the channel-forming region. In this specification, the channel-forming region refers to the region through which current primarily flows.

[0036] Furthermore, the functions of the source or drain may be reversed when transistors of different polarities are used, or when the direction of current changes during circuit operation. For this reason, the terms source and drain may be used interchangeably in this specification.

[0037] The channel length refers to the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or in the channel formation region, as seen in a top view of a transistor. It should be noted that the channel length is not necessarily the same in all regions of a single transistor. That is, the channel length of a single transistor may not be a single fixed value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0038] Channel width refers to the length of the channel formation region perpendicular to the channel length direction, for example, in a top view of a transistor, where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or within the channel formation region. Note that the channel width is not necessarily the same across all regions in a single transistor. That is, the channel width of a single transistor may not be a single fixed value. Therefore, in this specification, the channel width is defined as any one value, maximum value, minimum value, or average value within the channel formation region.

[0039] In this specification, depending on the transistor structure, the channel width in the region where the channel is actually formed (hereinafter also referred to as the "effective channel width") may differ from the channel width shown in the top view of the transistor (hereinafter also referred to as the "apparent channel width"). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may become larger than the apparent channel width, and this effect may not be negligible. For example, in a miniature transistor where the gate electrode covers the side surface of the semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width will be larger than the apparent channel width.

[0040] In such cases, it can be difficult to estimate the effective channel width through actual measurements. For example, estimating the effective channel width from design values ​​requires the assumption that the semiconductor shape is known. Therefore, if the semiconductor shape is not precisely known, it is difficult to accurately measure the effective channel width.

[0041] In this specification, when simply referred to as "channel width," it may refer to the apparent channel width. Alternatively, when simply referred to as "channel width," it may refer to the effective channel width. Note that channel length, channel width, effective channel width, apparent channel width, etc., can be determined by analyzing cross-sectional TEM images, etc.

[0042] Impurities in semiconductors refer to elements other than the main components that make up the semiconductor. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities. The presence of impurities can cause problems such as an increase in the defect level density of the semiconductor or a decrease in crystallinity. In the case of oxide semiconductors, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of oxide semiconductors, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water can also function as an impurity. Furthermore, for example, the inclusion of impurities can cause oxygen vacancies (V) in oxide semiconductors. O (Also known as an oxygen vacancy) may form.

[0043] In this specification, silicon oxide nitride refers to a material whose composition contains more oxygen than nitrogen. Similarly, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0044] Furthermore, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." Similarly, the term "conductor" may be replaced with "conductive film" or "conductive layer." Finally, the term "semiconductor" may be replaced with "semiconductor film" or "semiconductor layer."

[0045] Furthermore, in this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Also, "approximately parallel" means a state in which two lines are positioned at an angle of -30 degrees or more and 30 degrees or less. Also, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Also, "approximately perpendicular" means a state in which two lines are positioned at an angle of 60 degrees or more and 120 degrees or less.

[0046] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, when a metal oxide is used in the semiconductor layer of a transistor, that metal oxide may be referred to as an oxide semiconductor. In other words, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or oxide semiconductor.

[0047] Furthermore, in this specification, normally off means that when no potential is applied to the gate, or when the gate is given a ground potential, the drain current flowing through the transistor per 1 μm of channel width is 1 × 10⁻¹⁶ at room temperature. -20 A or less, 1 × 10 at 85℃ -18 A or less, or 1 × 10 at 125°C -16 This means being less than or equal to A.

[0048] (Embodiment 1) In this embodiment, an example of a semiconductor device having a transistor 200 and a capacitive element 100, and a method for manufacturing the same, will be described using Figures 3A to 20D.

[0049] <Example of semiconductor device configuration> Figures 3A to 3D are top and cross-sectional views of a semiconductor device having a transistor 200 and a capacitive element 100. Figure 3A is a top view of the semiconductor device. Figures 3B to 3D are cross-sectional views of the same semiconductor device. Here, Figure 3B is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 3A, and is also a cross-sectional view of the transistor 200 in the channel length direction. Figure 3C is a cross-sectional view of the area indicated by the dashed line A3-A4 in Figure 3A, and is also a cross-sectional view of the transistor 200 in the channel width direction. Figure 3D is a cross-sectional view of the area indicated by the dashed line A5-A6 in Figure 3A. Note that some elements have been omitted from the top view of Figure 3A for clarity.

[0050] A semiconductor device according to one aspect of the present invention includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, a transistor 200 on the insulator 214, an insulator 280 on an insulator 275 provided on the transistor 200, an insulator 282 on the insulator 280, an insulator 283 on the insulator 282, an insulator 274 on the insulator 283, and an insulator 285 on the insulator 283 and the insulator 274. The insulators 212, 214, 216, 275, 280, 282, 283, 285, and 274 function as interlayer films. Furthermore, the insulator 283 is in contact with a portion of the upper surface of the insulator 214, the side surface of the insulator 216, the side surface of the insulator 222, the side surface of the insulator 275, the side surface of the insulator 280, and the side surface and upper surface of the insulator 282.

[0051] Here, the transistor 200 has a semiconductor layer, a first gate, a second gate, a source, and a drain. One of the source and drain of the transistor 200 is in contact with one of the electrodes of the capacitive element 100 above the semiconductor layer. An insulator 271 (insulator 271a and insulator 271b) is provided in contact with the source and drain of the transistor 200. Note that insulators 271a and 271b are sometimes collectively referred to as insulator 271.

[0052] The capacitive element 100 is provided in an opening formed in insulators 271, 275, 280, 282, 283, and 285 that reaches one of the source and drain of the transistor 200. The capacitive element 100 has a conductor 110 that contacts the upper surface of one of the source and drain of the transistor 200 at the opening, an insulator 130 disposed on the conductor 110 and the insulator 285, and a conductor 120 (conductor 120a and conductor 120b) disposed on the insulator 130. Here, it is preferable that the conductor 110 is disposed along the side and bottom surfaces of the opening.

[0053] Furthermore, it is preferable that an insulator 245 is provided between the conductor 110 and the insulator 280. It is preferable that the insulator 245 has the function of suppressing the diffusion of hydrogen (for example, at least one such as a hydrogen atom or hydrogen molecule). It is also preferable that the insulator 245 has the function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom or oxygen molecule). For example, it is preferable that the insulator 245 has lower permeability to one or both oxygen and hydrogen than the insulator 280.

[0054] [Transistor 200] As shown in Figures 3A to 3D, the transistor 200 comprises an insulator 216 on an insulator 214, a conductor 205 (conductor 205a and conductor 205b) arranged to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, a conductor 242a on the oxide 230b, an insulator 271a on the conductor 242a, and an oxide 230b The device comprises a conductor 242b, an insulator 271b on the conductor 242b, an insulator 252 on the oxide 230b, an insulator 250 on the insulator 252, an insulator 254 on the insulator 250, a conductor 260 (conductors 260a and 260b) located on the insulator 254 and overlapping with a portion of the oxide 230b, and an insulator 275 arranged on the insulators 222, 224, oxide 230a, oxide 230b, conductor 242a, conductor 242b, insulator 271a, and insulator 271b. Here, as shown in Figures 3B and 3C, insulator 252 is in contact with the top surface of insulator 222, the side surface of insulator 224, the side surface of oxide 230a, the side surface and top surface of oxide 230b, the side surface of conductor 242, the side surface of insulator 271, the side surface of insulator 275, the side surface of insulator 280, and the bottom surface of insulator 250. The top surface of conductor 260 is positioned so as to be roughly the same height as the top of insulator 254, the top of insulator 250, the top of insulator 252, and the top surface of insulator 280. Insulator 282 is in contact with at least a portion of the top surfaces of conductor 260, insulator 252, insulator 250, insulator 254, and insulator 280.

[0055] In the following, oxides 230a and 230b may be collectively referred to as oxide 230. Similarly, conductors 242a and 242b may be collectively referred to as conductor 242.

[0056] Insulators 280 and 275 are provided with openings that reach oxide 230b. Insulators 252, 250, 254, and 260 are arranged within these openings. In addition, in the channel length direction of transistor 200, conductors 260, 252, 250, and 254 are provided between insulators 271a and conductor 242a, and between insulators 271b and conductor 242b. Insulator 254 has a region in contact with the side surface of conductor 260 and a region in contact with the bottom surface of conductor 260.

[0057] Preferably, the oxide 230 has an oxide 230a disposed on the insulator 224 and an oxide 230b disposed on top of the oxide 230a. By having oxide 230a below oxide 230b, the diffusion of impurities from structures formed below oxide 230a to oxide 230b can be suppressed.

[0058] In the transistor 200, the oxide 230 is shown as having a configuration in which two layers of oxide 230a and oxide 230b are stacked, but the present invention is not limited to this. For example, a single layer of oxide 230b or a stacked structure of three or more layers may be provided, or oxide 230a and oxide 230b may each have a stacked structure.

[0059] Conductor 260 functions as the first gate (also called the top gate) electrode, and conductor 205 functions as the second gate (also called the back gate) electrode. Insulators 252, 250, and 254 function as the first gate insulators, and insulators 222 and 224 function as the second gate insulators. Note that gate insulators are sometimes called gate insulating layers or gate insulating films. Conductor 242a functions as either the source or the drain, and conductor 242b functions as either the source or the drain. At least a portion of the region of oxide 230 that overlaps with conductor 260 functions as a channel-forming region.

[0060] Here, an enlarged view of the vicinity of the channel formation region in FIG. 3B is shown in FIG. 4A. In the oxide 230b, a channel formation region is formed in the region between the conductor 242a and the conductor 242b. Therefore, as shown in FIG. 4A, the oxide 230b has a region 230bc that functions as the channel formation region of the transistor 200, and regions 230ba and 230bb that are provided so as to sandwich the region 230bc and function as a source region or a drain region. At least a part of the region 230bc overlaps with the conductor 260. In other words, the region 230bc is provided in the region between the conductor 242a and the conductor 242b. The region 230ba is provided to overlap with the conductor 242a, and the region 230bb is provided to overlap with the conductor 242b.

[0061] The region 230bc that functions as the channel formation region is a high-resistance region with a low carrier concentration because it has less oxygen deficiency or a lower impurity concentration than the regions 230ba and 230bb. Therefore, the region 230bc can be said to be of i-type (intrinsic) or substantially i-type. Here, it is preferable that oxygen is supplied to the region 230bc to reduce the oxygen deficiency.

[0062] In addition, the regions 230ba and 230bb that function as a source region or a drain region are regions where the carrier concentration is increased and the resistance is reduced due to a large amount of oxygen deficiency and / or a high impurity concentration such as hydrogen, nitrogen, and metal elements. That is, the regions 230ba and 230bb are n-type regions with a high carrier concentration and a low resistance compared to the region 230bc.

[0063] Here, the carrier concentration of the region 230bc that functions as the channel formation region is preferably 18 cm -3 or less, more preferably 17 cm -3 less than, and even more preferably 16 cm -3 less than, and most preferably 13 cm -3It is even more preferable that it be less than 1 × 10 12 cm -3 It is even more preferable that it be less than . There are no particular limitations on the lower limit of the carrier concentration in the region 230bc that functions as a channel-forming region, but for example, 1 × 10 -9 cm -3 It can be done this way.

[0064] Furthermore, a region may be formed between region 230bc and region 230ba or region 230bb, where the carrier concentration is equal to or lower than that of regions 230ba and 230bb, and equal to or higher than that of region 230bc. In other words, this region functions as a junction region between region 230bc and region 230ba or region 230bb. The hydrogen concentration in this junction region may be equal to or lower than that of regions 230ba and 230bb, and equal to or higher than that of region 230bc. Also, the oxygen deficiency in this junction region may be equal to or less than that of regions 230ba and 230bb, and equal to or greater than that of region 230bc.

[0065] Although Figure 4A shows an example in which regions 230ba, 230bb, and 230bc are formed in oxide 230b, the present invention is not limited to this. For example, each of the above regions may be formed not only in oxide 230b but also in oxide 230a.

[0066] Furthermore, in oxide 230, it can be difficult to clearly detect the boundaries between each region. The concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen, detected within each region may not be limited to stepwise changes between regions, but may also change continuously within each region. In other words, the closer a region is to the channel-forming region, the lower the concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen should be.

[0067] In transistor 200, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor for the oxide 230 (oxide 230a and oxide 230b) which includes the channel formation region.

[0068] Furthermore, it is preferable to use a metal oxide that functions as a semiconductor and has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large band gap in this way, the off-current of the transistor can be reduced.

[0069] As oxide 230, for example, a metal oxide such as In-M-Zn oxide having indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) may be used. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 230.

[0070] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a.

[0071] In this way, by placing oxide 230a below oxide 230b, the diffusion of impurities and oxygen from structures formed below oxide 230a to oxide 230b can be suppressed.

[0072] Furthermore, because oxides 230a and 230b share a common element other than oxygen (as a main component), the defect level density at the interface between oxide 230a and oxide 230b can be reduced. Because the defect level density at the interface between oxide 230a and oxide 230b can be reduced, the influence of interfacial scattering on carrier conduction is small, resulting in a high on-current.

[0073] It is preferable that oxide 230b is crystalline. In particular, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) as oxide 230b.

[0074] CAAC-OS has a highly crystalline, dense structure and is free from impurities and defects (e.g., oxygen deficiency V). O It is a metal oxide with few impurities (such as). In particular, by heat-treating the metal oxide after its formation at a temperature that does not cause polycrystallization of the metal oxide (for example, between 400°C and 600°C), the CAAC-OS can be made to have a more crystalline and dense structure. By increasing the density of the CAAC-OS in this way, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0075] On the other hand, because it is difficult to identify clear grain boundaries in CAAC-OS, the decrease in electron mobility caused by grain boundaries is less likely to occur. Therefore, metal oxides containing CAAC-OS have stable physical properties. As a result, metal oxides containing CAAC-OS are heat resistant and highly reliable.

[0076] In transistors using oxide semiconductors, the electrical properties tend to fluctuate and reliability may be poor if impurities and oxygen vacancies are present in the region where the channel is formed in the oxide semiconductor. Furthermore, hydrogen near the oxygen vacancy can fill the oxygen vacancy, creating a defect (hereinafter referred to as V). O Sometimes called H, it forms a channel and generates electrons that become carriers. For this reason, if the region where the channel is formed in the oxide semiconductor contains oxygen vacancies, the transistor is likely to exhibit normally-on characteristics (a characteristic in which the channel exists and current flows through the transistor even without applying voltage to the gate electrode). Therefore, in the region where the channel is formed in the oxide semiconductor, impurities, oxygen vacancies, and V are likely to be present. OIt is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where the channel is formed has a reduced carrier concentration and is type i (intrinsed) or substantially type i.

[0077] In contrast, by placing an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen is supplied from the insulator to the oxide semiconductor, eliminating oxygen deficiencies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source or drain region, it may cause a decrease in the on-current of transistor 200 or a decrease in the field-effect mobility. Furthermore, variations in the amount of oxygen supplied to the source or drain region within the substrate surface will result in variations in the characteristics of the semiconductor device containing the transistor.

[0078] Therefore, in an oxide semiconductor, the region 230bc, which functions as a channel-forming region, preferably has a reduced carrier concentration and is i-type or substantially i-type, while the regions 230ba and 230bb, which function as a source region or drain region, preferably have a high carrier concentration and are n-type. In other words, oxygen vacancies in region 230bc of the oxide semiconductor, and V O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to regions 230ba and 230bb.

[0079] Therefore, in this embodiment, with the conductor 242a and conductor 242b placed on the oxide 230b, microwave treatment is performed in an oxygen-containing atmosphere to eliminate oxygen deficiencies in region 230bc, and V O The aim is to reduce H. Here, microwave processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example.

[0080] By performing microwave treatment in an oxygen-containing atmosphere, oxygen gas can be plasmaized using microwaves or high-frequency waves such as RF (Radio Frequency), and this oxygen plasma can be applied. At this time, microwaves or high-frequency waves such as RF can also be irradiated into region 230bc. Due to the action of plasma, microwaves, etc., the V of region 230bc O By cleaving H, hydrogen H is removed from region 230bc, and oxygen is lost V. O It can be supplemented with oxygen. In other words, in region 230bc, "V O H → H + V O The following reaction occurs, which reduces the hydrogen concentration in region 230bc. Therefore, the oxygen deficiency in region 230bc, and V O This can reduce H and lower the carrier concentration.

[0081] Furthermore, when performing microwave processing in an oxygen-containing atmosphere, the effects of microwaves, high frequencies such as RF, and oxygen plasma are shielded by conductors 242a and 242b and do not reach regions 230ba and 230bb. In addition, the effects of oxygen plasma can be reduced by insulators 271 and 280, which are provided covering oxide 230b and conductor 242. As a result, during microwave processing, V O This prevents a decrease in H and avoids excessive oxygen supply, thus preventing a drop in carrier concentration.

[0082] Furthermore, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after the deposition of the insulating film that will become the insulator 252, or after the deposition of the insulating film that will become the insulator 250. By performing microwave treatment in an oxygen-containing atmosphere via the insulator 252 or insulator 250 in this way, oxygen can be efficiently injected into region 230bc. In addition, by arranging the insulator 252 in contact with the side surface of the conductor 242 and the surface of region 230bc, the injection of more oxygen than necessary into region 230bc can be suppressed, thereby suppressing oxidation of the side surface of the conductor 242. Furthermore, oxidation of the side surface of the conductor 242 can be suppressed when the insulating film that will become the insulator 250 is deposited.

[0083] Furthermore, the oxygen injected into region 230bc can take various forms, including oxygen atoms, oxygen molecules, and oxygen radicals (also called O radicals, which are atoms or molecules with unpaired electrons, or ions). Note that the oxygen injected into region 230bc may be one or more of the above forms, and oxygen radicals are particularly preferred. Additionally, the film quality of insulators 252 and 250 can be improved, thereby enhancing the reliability of transistor 200.

[0084] In this way, oxygen vacancies are selectively created in the oxide semiconductor region 230bc, and V O By removing H, region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to regions 230ba and 230bb, which function as source or drain regions, can be suppressed, thereby maintaining the n-type configuration. This suppresses variations in the electrical properties of transistor 200 and prevents variations in the electrical properties of transistor 200 within the substrate plane.

[0085] Furthermore, as shown in Figure 3C, in a cross-sectional view of the transistor 200 in the channel width direction, there may be a curved surface between the side surface and the top surface of the oxide 230b. In other words, the ends of the side surface and the ends of the top surface may be curved (hereinafter also referred to as rounded).

[0086] The radius of curvature of the curved surface is preferably greater than 0 nm and less than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or less than half the length of the region without the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and 20 nm or less, preferably 1 nm to 15 nm, and more preferably 2 nm to 10 nm. By adopting such a shape, the coverage of the oxide 230b by the insulator 252, insulator 250, insulator 254, and conductor 260 can be improved.

[0087] It is preferable that oxide 230 has a layered structure of multiple oxide layers with different chemical compositions. Specifically, it is preferable that the atomic ratio of element M to the main metal element in the metal oxide used in oxide 230a is greater than the atomic ratio of element M to the main metal element in the metal oxide used in oxide 230b. Furthermore, it is preferable that the atomic ratio of element M to In in the metal oxide used in oxide 230a is greater than the atomic ratio of element M to In in the metal oxide used in oxide 230b. Furthermore, it is preferable that the atomic ratio of In to element M in the metal oxide used in oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used in oxide 230a.

[0088] Furthermore, it is preferable that the oxide 230b is a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen deficiencies), and possess a dense structure with high crystallinity. Therefore, the extraction of oxygen from the oxide 230b by the source electrode or drain electrode can be suppressed. As a result, even when heat treatment is performed, the extraction of oxygen from the oxide 230b can be reduced, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0089] Here, at the junction of oxide 230a and oxide 230b, the lower end of the conduction band changes smoothly. In other words, the lower end of the conduction band at the junction of oxide 230a and oxide 230b can be said to change continuously or be a continuous junction. To achieve this, it is desirable to lower the defect level density of the mixed layer formed at the interface between oxide 230a and oxide 230b.

[0090] Specifically, by having oxides 230a and 230b share a common element other than oxygen as a main component, a mixed layer with a low defect level density can be formed. For example, if oxide 230b is In-M-Zn oxide, oxide 230a may be In-M-Zn oxide, M-Zn oxide, an oxide of element M, In-Zn oxide, indium oxide, etc.

[0091] Specifically, for oxide 230a, a metal oxide with a composition of In:M:Zn = 1:3:4 [atomic ratio] or close to it, or In:M:Zn = 1:1:0.5 [atomic ratio] or close to it may be used. For oxide 230b, a metal oxide with a composition of In:M:Zn = 1:1:1 [atomic ratio] or close to it, In:M:Zn = 1:1:2 [atomic ratio] or close to it, or In:M:Zn = 4:2:3 [atomic ratio] or close to it may be used. Note that "close to it" includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use gallium as element M.

[0092] Furthermore, when depositing metal oxide films by sputtering, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide film, but may also be the atomic ratio of the sputtering target used for depositing the metal oxide film.

[0093] Furthermore, as shown in Figure 3C and other figures, by providing an insulator 252 made of aluminum oxide or the like in contact with the top and side surfaces of the oxide 230, the indium contained in the oxide 230 may be unevenly distributed at and near the interface between the oxide 230 and the insulator 252. As a result, the atomic ratio near the surface of the oxide 230 becomes similar to that of indium oxide, or similar to that of In-Zn oxide. By increasing the atomic ratio of indium near the surface of the oxide 230, particularly oxide 230b, the field-effect mobility of the transistor 200 can be improved.

[0094] By configuring oxides 230a and 230b as described above, the defect level density at the interface between oxide 230a and oxide 230b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and transistor 200 can obtain a large on-current and high frequency characteristics.

[0095] It is preferable that at least one of insulators 212, 214, 271, 275, 282, 283, and 285 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 into the transistor 200. Therefore, it is preferable that at least one of insulators 212, 214, 271, 275, 282, 283, and 285 is an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (i.e., the above impurities do not easily permeate it). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (e.g., at least one such as oxygen atoms or oxygen molecules) (i.e., the above oxygen does not easily permeate it).

[0096] In this specification, a barrier insulating film refers to an insulating film that has barrier properties. In this specification, barrier properties refer to the function of suppressing the diffusion of the corresponding substance (also called low permeability), or the function of capturing and fixing the corresponding substance (also called gettering).

[0097] For insulators 212, 214, 271, 275, 282, 283, and 285, it is preferable to use insulators that have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, for insulators 212, 275, and 283, it is preferable to use silicon nitride, which has higher hydrogen barrier properties. Also, for example, for insulators 214, 271, 282, and 285, it is preferable to use aluminum oxide or magnesium oxide, which have high hydrogen capture and hydrogen fixation functions. This makes it possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side via insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of impurities such as water and hydrogen from the interlayer insulating film located outside the insulator 285 towards the transistor 200. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 224, etc., towards the substrate side via the insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 280, etc., upward from the transistor 200 via the insulator 282, etc. Thus, it is preferable to have a structure in which the transistor 200 is surrounded by insulators 212, 214, 271, 275, 282, 283, and 285, which have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0098] Here, it is preferable to use oxides having an amorphous structure as insulators 212, 214, 271, 275, 282, 283, and 285. For example, AlO x (x is any number greater than 0), or MgO y It is preferable to use a metal oxide such as (y is any number greater than 0). In such an amorphous metal oxide, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. By using such an amorphous metal oxide as a component of the transistor 200, or by providing it around the transistor 200, hydrogen contained in the transistor 200, or hydrogen present around the transistor 200, can be captured or fixed. It is particularly preferable to capture or fix hydrogen contained in the channel formation region of the transistor 200. By using an amorphous metal oxide as a component of the transistor 200, or by providing it around the transistor 200, it is possible to manufacture a transistor 200 and a semiconductor device that have good characteristics and are highly reliable.

[0099] Furthermore, while insulators 212, 214, 271, 275, 282, 283, and 285 are preferably amorphous, they may also have regions of polycrystalline structure. In addition, insulators 212, 214, 271, 275, 282, 283, and 285 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, a stacked structure in which a polycrystalline layer is formed on top of an amorphous layer is also possible.

[0100] The insulators 212, 214, 271, 275, 282, 283, and 285 may be deposited using, for example, a sputtering method. Since the sputtering method does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration of insulators 212, 214, 271, 275, 282, 283, and 285 can be reduced. Note that the deposition method is not limited to sputtering, and chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), atomic layer deposition (ALD), etc. may be used as appropriate.

[0101] Furthermore, it may be preferable to lower the resistivity of insulators 212, 275, and 283. For example, the resistivity of insulators 212, 275, and 283 may be approximately 1 × 10⁻⁶. 13 By setting the resistivity to Ωcm, insulators 212, 275, and 283 may be able to mitigate charge-up of conductors 205, 242, 260, or 110 in processes using plasma or the like during semiconductor device manufacturing. The resistivity of insulators 212, 275, and 283 is preferably 1 × 10⁻⁶. 10 Ωcm or more, 1 × 10 15 The density should be less than or equal to Ωcm.

[0102] Furthermore, it is preferable that insulators 216, 274, 280, and 285 have a lower dielectric constant than insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and porous silicon oxide may be used as insulators 216, 274, 280, and 285 as appropriate.

[0103] The conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Here, it is preferable that the conductor 205 is embedded in an opening formed in the insulator 216. In some cases, a portion of the conductor 205 may be embedded in the insulator 214.

[0104] The conductor 205 comprises a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and side wall of the opening. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the height of the upper surface of the conductor 205b is approximately equal to the height of the upper surface of the conductor 205a and the height of the upper surface of the insulator 216.

[0105] Here, it is preferable to use a conductive material for the conductor 205a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0106] By using a conductive material that has the function of reducing hydrogen diffusion for the conductor 205a, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulator 224, etc. Furthermore, by using a conductive material that has the function of suppressing oxygen diffusion for the conductor 205a, it is possible to suppress the oxidation of the conductor 205b and the decrease in conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. Therefore, the conductive material can be used as a single layer or in a laminate for the conductor 205a. For example, titanium nitride can be used for the conductor 205a.

[0107] Furthermore, it is preferable to use a conductive material whose main component is tungsten, copper, or aluminum for the conductor 205b. For example, tungsten may be used for the conductor 205b.

[0108] Conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of transistor 200 can be controlled by changing the potential applied to conductor 205 independently of the potential applied to conductor 260, without linking it to the potential applied to conductor 260. In particular, by applying a negative potential to conductor 205, it is possible to increase the Vth of transistor 200 and reduce the off-current. Therefore, applying a negative potential to conductor 205 reduces the drain current when the potential applied to conductor 260 is 0V compared to not applying a negative potential.

[0109] Furthermore, the electrical resistivity of the conductor 205 is designed considering the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 as thin as possible within the limits permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thereby reducing the diffusion of these impurities into the oxide 230.

[0110] Furthermore, as shown in Figure 3A, the conductor 205 should be larger than the size of the region that does not overlap with the conductors 242a and 242b of the oxide 230. In particular, as shown in Figure 3C, it is preferable that the conductor 205 extends to the region outside the ends of the oxide 230a and oxide 230b in the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 are superimposed on the outside of the side surface of the oxide 230 in the channel width direction, with an insulator in between. With this configuration, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 which functions as the first gate electrode and the electric field of the conductor 205 which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is called a surrounded channel (S-channel) structure.

[0111] In this specification, an S-channel transistor refers to a transistor structure in which the channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. Furthermore, the S-channel structure disclosed in this specification is different from the Fin-type structure and the Planar-type structure. By adopting an S-channel structure, it is possible to create a transistor that has improved resistance to short-channel effects, or in other words, a transistor in which short-channel effects are less likely to occur.

[0112] Furthermore, as shown in Figure 3C, the conductor 205 is extended to function as wiring. However, the configuration is not limited to this, and a conductor that functions as wiring may be provided beneath the conductor 205. Also, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0113] In the transistor 200, the conductor 205 is shown as a stacked structure of conductor 205a and conductor 205b, but the present invention is not limited to this. For example, the conductor 205 may be provided as a single layer or as a stacked structure of three or more layers.

[0114] Insulators 222 and 224 function as gate insulators.

[0115] Preferably, the insulator 222 has the function of suppressing the diffusion of hydrogen (for example, at least one such as a hydrogen atom or a hydrogen molecule). Furthermore, preferably, the insulator 222 has the function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom or an oxygen molecule). For example, it is preferable that the insulator 222 has the function of suppressing the diffusion of one or both hydrogen and oxygen more effectively than the insulator 224.

[0116] The insulator 222 may be an insulator containing an oxide of one or both of the insulating materials aluminum and hafnium. Preferably, the insulator is an oxide containing aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Alternatively, an oxide containing hafnium and zirconium, such as hafnium-zirconium oxide, is preferred. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, by providing the insulator 222, it is possible to suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and to suppress the generation of oxygen vacancies in the oxide 230. In addition, it is possible to suppress the reaction of the conductor 205 with the oxygen contained in the insulator 224 and the oxide 230.

[0117] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above-mentioned insulator. Alternatively, these insulators may be subjected to nitriding treatment. Furthermore, insulator 222 may be used by laminating silicon oxide, silicon oxide nitride, or silicon nitride onto these insulators.

[0118] Furthermore, the insulator 222 may be a single-layer or multi-layer insulator containing so-called high-k materials, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium-zirconium oxide. As transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, materials with high dielectric constants, such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), and (Ba,Sr)TiO3 (BST), may also be used as the insulator 222.

[0119] The insulator 224 in contact with the oxide 230 can be, for example, silicon oxide, silicon oxide nitride, or the like, as appropriate.

[0120] Furthermore, during the manufacturing process of the transistor 200, it is preferable to perform a heat treatment while the surface of the oxide 230 is exposed. This heat treatment may be performed at, for example, 100°C to 600°C, more preferably 350°C to 550°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing an oxidizing gas (e.g., oxygen gas) at a flow rate ratio of 10 ppm or more, 1% or more, or 10% or more. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This supplies oxygen to the oxide 230, thereby preventing oxygen deficiency (V OThis can reduce the amount of oxygen released. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the oxygen that has been removed. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then continuously in an atmosphere of nitrogen gas or an inert gas.

[0121] Furthermore, by performing an oxygenation treatment on oxide 230, oxygen deficiencies in oxide 230 are repaired by the supplied oxygen, or in other words, "V O This can accelerate the reaction "+O→null". Furthermore, the oxygen supplied reacts with the hydrogen remaining in oxide 230, removing the hydrogen as H2O (dehydration). As a result, the hydrogen remaining in oxide 230 recombines with the oxygen vacancy and V O This can suppress the formation of H.

[0122] Furthermore, the insulators 222 and 224 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to being made of the same material, but may be made of different materials. Also, the insulator 224 may be formed in an island shape by being superimposed with the oxide 230a. In this case, the insulator 275 will be in contact with the side surface of the insulator 224 and the upper surface of the insulator 222.

[0123] Conductors 242a and 242b are provided in contact with the upper surface of oxide 230b. Conductors 242a and 242b function as the source electrode or drain electrode of transistor 200, respectively.

[0124] As the conductor 242 (conductor 242a and conductor 242b), it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0125] Furthermore, hydrogen contained in oxide 230b, etc., may diffuse into conductor 242a or conductor 242b. In particular, by using tantalum-containing nitrides for conductor 242a and conductor 242b, hydrogen contained in oxide 230b, etc., is more likely to diffuse into conductor 242a or conductor 242b, and the diffused hydrogen may combine with nitrogen present in conductor 242a or conductor 242b. In other words, hydrogen contained in oxide 230b, etc., may be absorbed by conductor 242a or conductor 242b.

[0126] Furthermore, it is preferable that no curved surface is formed between the side surface of the conductor 242 and the top surface of the conductor 242. By using a conductor 242 without such a curved surface, the cross-sectional area of ​​the conductor 242 in the channel width direction can be increased, as shown in Figure 3D. This increases the conductivity of the conductor 242 and increases the on-current of the transistor 200.

[0127] The insulator 271a is provided in contact with the upper surface of the conductor 242a, and the insulator 271b is provided in contact with the upper surface of the conductor 242b. It is preferable that the insulator 271 functions as at least a barrier insulating film against oxygen. Therefore, it is preferable that the insulator 271 has a function to suppress the diffusion of oxygen. For example, it is preferable that the insulator 271 has a function to suppress the diffusion of oxygen more than the insulator 280. As the insulator 271, for example, an insulator such as aluminum oxide or magnesium oxide may be used.

[0128] The insulator 275 is provided so as to cover the insulator 224, oxide 230a, oxide 230b, conductor 242, and insulator 271. Preferably, the insulator 275 has the function of capturing and fixing hydrogen. In that case, it is preferable that the insulator 275 includes silicon nitride or an insulator such as an amorphous metal oxide, for example, aluminum oxide or magnesium oxide. Alternatively, for example, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 275.

[0129] By providing the insulators 271 and 275 described above, the conductor 242 can be surrounded by an insulator that has barrier properties against oxygen. In other words, the oxygen contained in the insulators 224 and 280 can be prevented from diffusing into the conductor 242. This prevents the conductor 242 from being directly oxidized by the oxygen contained in the insulators 224 and 280, which would increase its resistivity and reduce the on-current.

[0130] The insulator 252 functions as part of the gate insulator. Preferably, the insulator 252 is a barrier insulating film against oxygen. The insulator 252 can be any insulator that can be used for the insulator 282 described above. The insulator 252 may be an insulator containing an oxide of either or both aluminum and hafnium. Examples of such insulators include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, aluminum oxide is used as the insulator 252. In this case, the insulator 252 is an insulator containing at least oxygen and aluminum.

[0131] As shown in Figure 3C, the insulator 252 is provided in contact with the top and side surfaces of oxide 230b, the side surface of oxide 230a, the side surface of insulator 224, and the top surface of insulator 222. In other words, the regions of oxide 230a, oxide 230b, and insulator 224 that overlap with the conductor 260 are covered by the insulator 252 in the cross-section in the channel width direction. This prevents oxygen from being released from oxide 230a and oxide 230b during heat treatment, etc., as the insulator 252 has an oxygen barrier property. Therefore, oxygen deficiency (V) in oxide 230a and oxide 230b is prevented. O This reduces the formation of oxygen deficiencies (V) in region 230bc. O ), and V O H can be reduced. Therefore, the electrical characteristics of transistor 200 can be improved, and its reliability can be enhanced.

[0132] Conversely, even if an excess amount of oxygen is present in the insulator 280 and insulator 250, it is possible to suppress the excessive supply of such oxygen to oxides 230a and 230b. Therefore, it is possible to suppress the excessive oxidation of regions 230ba and 230bb via region 230bc, which would otherwise cause a decrease in the on-current of transistor 200 or a decrease in field-effect mobility.

[0133] Furthermore, as shown in Figure 3B, the insulator 252 is provided in contact with the sides of the conductor 242, insulator 271, insulator 275, and insulator 280. Therefore, oxidation of the side surface of the conductor 242 and the formation of an oxide film on that side surface can be reduced. This makes it possible to suppress a decrease in the on-current of the transistor 200 or a decrease in the field-effect mobility.

[0134] Furthermore, the insulator 252, along with the insulator 254, the insulator 250, and the conductor 260, must be provided in an opening formed in the insulator 280 or the like. In order to miniaturize the transistor 200, it is preferable that the film thickness of the insulator 252 be thin. The film thickness of the insulator 252 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, it is sufficient that the insulator 252 has a region with the above-mentioned film thickness in at least a part of it. Also, it is preferable that the film thickness of the insulator 252 is thinner than the film thickness of the insulator 250. In this case, it is sufficient that the insulator 252 has a region with a thinner film thickness than the insulator 250 in at least a part of it.

[0135] To deposit the insulator 252 with a thin film thickness as described above, it is preferable to use the ALD method. ALD methods include thermal ALD, which uses only thermal energy for the reaction between the precursor and reactant, and plasma-enhanced ALD (PEALD), which uses plasma-excited reactants. The PEALD method is preferable in some cases because the use of plasma allows for film deposition at lower temperatures.

[0136] The ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer, resulting in several advantages: ultra-thin film deposition is possible, deposition on structures with high aspect ratios is possible, film deposition with fewer defects such as pinholes is possible, film deposition with excellent coverage is possible, and film deposition is possible at low temperatures. Therefore, the insulator 252 can be deposited with good coverage on the sides of openings formed in the insulator 280, etc., with the thin film thickness described above.

[0137] Note that precursors used in the ALD method may contain carbon and other impurities. Therefore, films formed by the ALD method may contain more carbon and other impurities compared to films formed by other film deposition methods. The quantity of impurities can be quantified using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0138] The insulator 250 functions as part of the gate insulator. It is preferable that the insulator 250 is placed in contact with the upper surface of the insulator 252. The insulator 250 can be silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or porous silicon oxide. Silicon oxide and silicon oxynitride are particularly preferred because they are stable with respect to heat. In this case, the insulator 250 will be an insulator having at least oxygen and silicon.

[0139] Similar to the insulator 224, it is preferable that the insulator 250 has a reduced concentration of impurities such as water and hydrogen. The film thickness of the insulator 250 is preferably 1 nm to 20 nm, and more preferably 0.5 nm to 15.0 nm. In this case, it is sufficient that the insulator 250 has a region with the above-mentioned film thickness in at least a portion of it.

[0140] Figures 3A to 3D show a configuration in which the insulator 250 is a single layer, but the present invention is not limited to this, and a laminated structure of two or more layers is also possible. For example, as shown in Figure 4B, the insulator 250 may be a laminated structure of two layers: an insulator 250a and an insulator 250b on top of the insulator 250a.

[0141] As shown in Figure 4B, when the insulator 250 has a two-layer laminated structure, it is preferable that the lower insulator 250a is formed using an insulator that is permeable to oxygen, and the upper insulator 250b is formed using an insulator that has the function of suppressing the diffusion of oxygen. With this configuration, it is possible to suppress the diffusion of oxygen contained in the insulator 250a to the conductor 260. In other words, it is possible to suppress the decrease in the amount of oxygen supplied to the oxide 230. In addition, it is possible to suppress the oxidation of the conductor 260 by the oxygen contained in the insulator 250a. For example, the insulator 250a may be made using a material that can be used for the insulator 250 described above, and the insulator 250b may be an insulator containing an oxide of aluminum and / or hafnium. As such an insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), etc., can be used. In this embodiment, hafnium oxide is used as the insulator 250b. In this case, the insulator 250b is an insulator having at least oxygen and hafnium. The film thickness of the insulator 250b is 0.5 nm or more and 5.0 nm or less, preferably 1.0 nm or more and 5.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, it is sufficient that the insulator 250b has at least a portion of the above-mentioned film thickness region.

[0142] Furthermore, when silicon oxide or silicon oxynitride is used for insulator 250a, insulator 250b may be an insulating material that is a high-k material with a high dielectric constant. By making the gate insulator a laminated structure of insulator 250a and insulator 250b, a laminated structure that is stable against heat and has a high dielectric constant can be made. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it is possible to make the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator thinner. Thus, the dielectric breakdown voltage of insulator 250 can be increased.

[0143] The insulator 254 functions as part of the gate insulator. Preferably, a barrier insulating film against hydrogen is used as the insulator 254. This prevents impurities such as hydrogen contained in the conductor 260 from diffusing into the insulator 250 and oxide 230b. The insulator 254 can be any insulator that can be used for the insulator 283 described above. For example, silicon nitride deposited by the PEALD method can be used as the insulator 254. In this case, the insulator 254 will be an insulator containing at least nitrogen and silicon.

[0144] Furthermore, the insulator 254 may also have barrier properties against oxygen. This can suppress the diffusion of oxygen contained in the insulator 250 into the conductor 260.

[0145] Furthermore, the insulator 254, along with the insulator 252, the insulator 250, and the conductor 260, must be provided in an opening formed in the insulator 280 or the like. In order to miniaturize the transistor 200, it is preferable that the film thickness of the insulator 254 be thin. The film thickness of the insulator 254 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, it is sufficient that the insulator 254 has a region with the above-mentioned film thickness in at least a part of it. Also, it is preferable that the film thickness of the insulator 254 is thinner than the film thickness of the insulator 250. In this case, it is sufficient that the insulator 254 has a region with a thinner film thickness than the insulator 250 in at least a part of it.

[0146] The conductor 260 functions as the first gate electrode of the transistor 200. Preferably, the conductor 260 has a conductor 260a and a conductor 260b disposed on top of the conductor 260a. For example, it is preferable that the conductor 260a is arranged to enclose the bottom and sides of the conductor 260b. Also, as shown in Figures 3B and 3C, the top surface of the conductor 260 is roughly coincided with the top surface of the insulator 250. In Figures 3B and 3C, the conductor 260 is shown as a two-layer structure of conductor 260a and conductor 260b, but it may also be a single-layer structure or a stacked structure of three or more layers.

[0147] It is preferable to use a conductive material for the conductor 260a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0148] Furthermore, because the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress the oxidation of the conductor 260b by the oxygen contained in the insulator 250, which would otherwise reduce its conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

[0149] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 260b may also be in a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0150] Furthermore, in transistor 200, the conductor 260 is formed self-aligningly to fill the openings formed in the insulator 280 and the like. By forming the conductor 260 in this way, the conductor 260 can be reliably positioned in the region between the conductors 242a and 242b without the need for alignment.

[0151] Furthermore, as shown in Figure 3C, in the channel width direction of the transistor 200, with reference to the bottom surface of the insulator 222, the height of the bottom surface of the conductor 260 in the region where the conductor 260 and the oxide 230b do not overlap is preferably lower than the height of the bottom surface of the oxide 230b. By configuring the conductor 260, which functions as a gate electrode, to cover the side and top surfaces of the channel formation region of the oxide 230b via the insulator 250 or the like, it becomes easier to apply the electric field of the conductor 260 to the entire channel formation region of the oxide 230b. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved. With reference to the bottom surface of the insulator 222, the difference between the height of the bottom surface of the conductor 260 in the region where the oxide 230a and oxide 230b and the conductor 260 do not overlap and the height of the bottom surface of the oxide 230b is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0152] The insulator 280 is provided on the insulator 275, and openings are formed in the regions where the insulator 250 and the conductor 260 are provided. The upper surface of the insulator 280 may also be flattened.

[0153] The insulator 280, which functions as an interlayer film, preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between the wiring can be reduced. The insulator 280 is preferably made of the same material as the insulator 216, for example. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are particularly preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0154] Preferably, the insulator 280 has a reduced concentration of impurities such as water and hydrogen. For example, the insulator 280 may be made of silicon oxide such as silicon oxide or silicon oxynitride.

[0155] The insulator 282 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the insulator 280 from above, and preferably has the function of capturing impurities such as hydrogen. Furthermore, the insulator 282 preferably functions as a barrier insulating film that suppresses the permeation of oxygen. As the insulator 282, an amorphous metal oxide, such as aluminum oxide, may be used. In this case, the insulator 282 will be an insulator having at least oxygen and aluminum. By providing an insulator 282 that is in contact with the insulator 280 in the region sandwiched between the insulator 212 and the insulator 283 and has the function of capturing impurities such as hydrogen, impurities such as hydrogen contained in the insulator 280 can be captured, and the amount of hydrogen in that region can be kept constant. In particular, using aluminum oxide with an amorphous structure as the insulator 282 is preferable because it may be possible to capture or fix hydrogen more effectively. This makes it possible to manufacture a transistor 200 and a semiconductor device that have good characteristics and are highly reliable.

[0156] The insulator 283 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the insulator 280 from above. The insulator 283 is placed on top of the insulator 282. Preferably, the insulator 283 is a silicon-containing nitride such as silicon nitride or silicon nitride oxide. For example, silicon nitride deposited by sputtering may be used as the insulator 283. By depositing the insulator 283 by sputtering, a high-density silicon nitride film can be formed. Alternatively, as the insulator 283, silicon nitride deposited by PEALD or CVD may be further laminated on top of the silicon nitride deposited by sputtering.

[0157] [Capacitive element 100] The capacitive element 100 is arranged in openings formed in insulators 271, 275, 280, 282, 283, and 285 and includes a conductor 110 in contact with the upper surface of the conductor 242b, an insulator 130 on the conductor 110 and insulator 283, and a conductor 120 on the insulator 130. The conductor 120 has a laminated structure of conductor 120a on insulator 130 and conductor 120b on conductor 120a. Here, at least a portion of the conductor 110, insulator 130, and conductor 120 are arranged in openings formed in insulators 271, 275, 280, 282, 283, and 285.

[0158] The conductor 110 functions as the lower electrode of the capacitive element 100, the conductor 120 functions as the upper electrode of the capacitive element 100, and the insulator 130 functions as the dielectric of the capacitive element 100. In the openings of the insulators 271, 275, 280, 282, 283, and 285 of the capacitive element 100, the upper electrode and the lower electrode face each other with the dielectric in between, not only on the bottom surface but also on the sides, which allows for a large capacitance per unit area. Therefore, the deeper the opening, the larger the capacitance of the capacitive element 100 can be. By increasing the capacitance per unit area of ​​the capacitive element 100 in this way, miniaturization or high integration of semiconductor devices can be promoted.

[0159] The shape of the openings formed in insulators 271, 275, 280, 282, 283, and 285 when viewed from above may be a rectangle, a polygon other than a rectangle, a polygon with curved corners, or a circle including an ellipse. Here, it is preferable that the area overlapping between the opening and the transistor 200 is large when viewed from above. For example, as shown in Figure 3A, it is preferable to provide the capacitive element 100 such that it fits within the range of the conductor 242b when viewed from above. In this case, the length of the conductor 110 in the channel width direction is smaller than the length of the conductor 242b in the channel width direction. By adopting such a configuration, the occupied area of ​​the semiconductor device having the capacitive element 100 and the transistor 200 can be reduced. However, it is not limited to this, and a configuration in which the length of the conductor 110 in the channel width direction is larger than the length of the conductor 242b in the channel width direction is also possible.

[0160] The conductor 110 is arranged along the openings formed in the insulators 271, 275, 280, 282, 283, and 285. Here, it is preferable that the side and bottom surfaces of the openings are joined by curved surfaces. With this configuration, the conductor 110 can be formed in the openings with good coverage.

[0161] Furthermore, it is preferable that the height of a portion of the upper surface of the conductor 110 roughly coincides with the height of the upper surface of the insulator 285. Also, the upper surface of the conductor 242b is in contact with the lower surface of the conductor 110. The conductor 110 is preferably formed using the ALD method or the CVD method, and any conductor that can be used for the conductor 205 may be used. For example, titanium nitride formed using the thermal ALD method can be used as the conductor 110.

[0162] The insulator 130 is positioned to cover the conductor 110, the insulator 245, and a portion of the insulator 285. Here, in the insulator 285, the height of the upper surface of the region overlapping with the insulator 130 may be higher than the height of the upper surface of the region not overlapping with the insulator 130. The insulator 130 is preferably formed using the ALD method or the CVD method. It is preferable to use a material that can have ferroelectric properties for the insulator 130.

[0163] Materials that can possess ferroelectric properties include hafnium oxide, zirconium oxide, and HfZrO x Examples include materials obtained by adding element J1 (where element J1 is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to hafnium oxide, and materials obtained by adding element J2 (where element J2 is hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to zirconium oxide. In addition, PbTiO is an example of a material that may possess ferroelectric properties. x Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may be used. Furthermore, as a material capable of ferroelectricity, for example, a mixture or compound containing multiple materials selected from the materials listed above can be used. Alternatively, the insulator 130 can be a laminated structure made of multiple materials selected from the materials listed above. Incidentally, hafnium oxide, zirconium oxide, HfZrO x Materials such as hafnium oxide with added element J1 may exhibit changes in their crystal structure (properties) depending not only on the film deposition conditions but also on various processes. Therefore, in this specification, materials that exhibit ferroelectricity are not only called ferroelectrics, but also materials that may possess ferroelectricity.

[0164] Among the materials that can possess ferroelectric properties, hafnium oxide, or materials containing both hafnium oxide and zirconium oxide, are preferred because they can exhibit ferroelectric properties even when processed into thin films of a few nanometers. Here, the film thickness of the insulator 130 can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less. By creating a ferroelectric layer that can be made into a thin film, the capacitive element 100 can be combined with a miniaturized transistor 200 to form a semiconductor device. In this specification, a layer of material that can possess ferroelectric properties may be referred to as a ferroelectric layer.

[0165] A material capable of ferroelectricity is an insulator that exhibits internal polarization when an external electric field is applied, and retains this polarization even when the electric field is removed. Therefore, a non-volatile memory element can be formed using a capacitive element (sometimes referred to as a ferroelectric capacitor) made of this material as a dielectric. A non-volatile memory element using a ferroelectric capacitor is sometimes called FeRAM (Ferroelectric Random Access Memory) or ferroelectric memory. For example, a ferroelectric memory can have a transistor and a ferroelectric capacitor, with one of the transistor's sources and drains electrically connected to one terminal of the ferroelectric capacitor. Thus, the semiconductor device having a capacitive element 100 and a transistor 200, as shown in this embodiment, can function as a ferroelectric memory.

[0166] Furthermore, the insulator 130 may be made of a laminated structure of a material that may have the above-mentioned ferroelectric properties and a material with high dielectric strength. Materials with high dielectric strength include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and porous silicon oxide or resin. By using such insulators with high dielectric strength in a laminated structure, the dielectric strength can be improved and the leakage current of the capacitive element 100 can be suppressed.

[0167] The conductor 120 is positioned to fill the openings formed in the insulators 271, 275, 280, 282, 283, and 285. Here, it is preferable that the conductor 120 has a region that overlaps with the insulator 285 via the insulator 130. With this configuration, the conductor 120 can be insulated from the conductor 110 via the insulator 130. In addition, the portion of the conductor 120 above the insulator 283 may be routed and formed into a wiring-like structure.

[0168] As shown in Figure 3B, it is preferable that the conductor 120 has a conductor 120a and a conductor 120b on the conductor 120a. In this case, the conductor 120a can be provided as a thin conductive film with good coverage on the insulator 130. The conductor 120b can be arranged to fill the opening on the conductor 120a. It is preferable that the conductor 120a be formed using the ALD method or CVD method, and any conductor that can be used for the conductor 205 may be used. For example, titanium nitride formed using the ALD method can be used as the conductor 120a. It is preferable that the conductor 120b be formed using the ALD method, CVD method, or sputtering method, and any conductor that can be used for the conductor 205 may be used. Tungsten formed using the sputtering method can be used as the conductor 120b. However, the conductor 120 is not limited to a two-layer structure, but can also be a single-layer structure or a laminated structure of three or more layers.

[0169] Furthermore, a conductor that functions as wiring may be placed in contact with the upper surface of the conductor 120. It is preferable that the conductor be made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductor may also be in a laminated structure, for example, a laminate of titanium or titanium nitride with the conductive material. The conductor may also be formed to be embedded in an opening provided in the insulator.

[0170] Furthermore, it is preferable that the insulator 245 is positioned in contact with the side surfaces of the openings formed in the insulators 271, 275, 280, 282, 283, and 285. The conductor 110 is provided in contact with the inner side surface of the insulator 245, the insulator 130 is provided in contact with the inner side surface of the conductor 110, and the conductor 120 is provided in contact with the inner side surface of the insulator 130.

[0171] As the insulator 245, any barrier insulating film that can be used for insulator 275, etc., may be used. For example, as the insulator 245, an insulator such as silicon nitride, aluminum oxide, or silicon oxide nitride may be used. Since the insulator 245 is provided in contact with insulators 283, 282, 275, and 271, it is possible to suppress the mixing of impurities such as water and hydrogen contained in insulator 280 or insulator 285, etc., into the oxide 230 through the conductor 110. In particular, silicon nitride is preferred because it has high blocking properties for hydrogen. In addition, it is possible to prevent oxygen contained in insulator 280 from being absorbed by the conductor 110.

[0172] When the insulator 245 is made into a laminated structure as shown in Figure 3B, it is preferable to use a combination of an oxygen barrier insulating film and a hydrogen barrier insulating film for the first insulator in contact with the inner wall of the opening such as the insulator 280 and the second insulator inside it. For example, aluminum oxide deposited by the ALD method may be used as the first insulator, and silicon nitride deposited by the PEALD method may be used as the second insulator. By using such a configuration, oxidation of the conductor 110 can be suppressed, and furthermore, the contamination of the conductor 110 with hydrogen can be reduced.

[0173] Although the insulator 245 is shown in a configuration in which a first insulator and a second insulator are laminated, the present invention is not limited to this. For example, the insulator 245 may be provided as a single layer or as a laminated structure of three or more layers.

[0174] <Component materials for semiconductor devices> The following describes the constituent materials that can be used in semiconductor devices.

[0175] <<Substrate>> As the substrate for forming transistor 200, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon and germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides or metal oxides. Furthermore, there are substrates on which a conductor or semiconductor is provided on an insulating substrate, substrates on which a conductor or insulator is provided on a semiconductor substrate, and substrates on which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates with elements mounted on them may be used. Examples of elements mounted on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0176] <<Insulator>> Insulators include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0177] For example, as transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0178] Furthermore, examples of insulators with high dielectric constants include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0179] Insulators with low dielectric constants include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with vacancies, or resins.

[0180] Furthermore, the electrical properties of transistors using metal oxides can be stabilized by surrounding them with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxide nitride, and silicon nitride can be used.

[0181] Furthermore, the insulator that functions as a gate insulator is preferably an insulator having a region containing oxygen that is desorbed by heating. For example, by having silicon oxide or silicon oxynitride having a region containing oxygen that is desorbed by heating in a structure that is in contact with the oxide 230, the oxygen deficiency in the oxide 230 can be compensated for.

[0182] <<Conductive material>> As the conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metallic elements, or an alloy combining the above metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0183] Furthermore, multiple conductive layers formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with a nitrogen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0184] Furthermore, when using an oxide in the channel formation region of a transistor, it is preferable to use a laminated structure for the conductor functioning as the gate electrode, which combines a material containing the aforementioned metal element with a conductive material containing oxygen. In this case, it is preferable to place the conductive material containing oxygen on the channel formation region side. By placing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is more easily supplied to the channel formation region.

[0185] In particular, it is preferable to use a conductive material containing metal elements and oxygen contained in the metal oxide in which the channel is formed as the conductor that functions as the gate electrode. Alternatively, conductive materials containing the aforementioned metal elements and nitrogen may be used. For example, conductive materials containing nitrogen such as titanium nitride and tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-doped indium tin oxide may be used. In addition, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may be possible to capture hydrogen that is mixed in from an external insulator or the like.

[0186] <<Metal Oxides>> It is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor as oxide 230. Below, metal oxides applicable to oxide 230 according to the present invention will be described.

[0187] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that it contains indium and zinc. In addition, it is preferable that it contains aluminum, gallium, yttrium, tin, etc. It may also contain one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0188] Here, we consider the case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. Element M can be aluminum, gallium, yttrium, or tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, it is sometimes permissible to use a combination of multiple of the aforementioned elements as element M.

[0189] In this specification, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be called metal oxynitrides.

[0190] <Classification of crystal structures> First, we will explain the classification of crystal structures in oxide semiconductors using Figure 5A. Figure 5A is a diagram illustrating the classification of crystal structures in oxide semiconductors, specifically IGZO (a metal oxide containing In, Ga, and Zn).

[0191] As shown in Figure 5A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." "Amorphous" includes completely amorphous materials. "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite) (excluding single crystal and polycrystal). Note that single crystal, polycrystal, and completely amorphous materials are excluded from the "Crystalline" classification. "Crystal" includes single crystal and polycrystal materials.

[0192] The structure within the thick frame shown in Figure 5A represents an intermediate state between "Amorphous" and "Crystal," and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as being completely different from the energetically unstable "Amorphous" and "Crystal" states.

[0193] The crystal structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 5B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or Seemann-Bohlin method. Hereafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 5B may simply be referred to as the XRD spectrum in this specification. The composition of the CAAC-IGZO film shown in Figure 5B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 5B is 500 nm.

[0194] In Figure 5B, the horizontal axis represents 2θ [deg.] and the vertical axis represents intensity [au]. As shown in Figure 5B, the XRD spectrum of the CAAC-IGZO film shows a peak indicating clear crystallinity. Specifically, the XRD spectrum of the CAAC-IGZO film shows a peak indicating c-axis orientation near 2θ = 31°. As shown in Figure 5B, the peak near 2θ = 31° is asymmetrical with respect to the angle at which the peak intensity was detected.

[0195] Furthermore, the crystal structure of a film or substrate can be evaluated by the diffraction pattern (also called the nano-beam electron diffraction pattern) observed by nano-beam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 5C. Figure 5C shows the diffraction pattern observed by NBED with the electron beam incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 5C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In nano-beam electron diffraction, electron diffraction is performed with a probe diameter of 1 nm.

[0196] As shown in Figure 5C, the diffraction pattern of the CAAC-IGZO film shows multiple spots indicating c-axis orientation.

[0197] <<Oxide semiconductor structure>> Note that when focusing on the crystal structure, oxide semiconductors may be classified differently from those shown in Figure 5A. For example, oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the aforementioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors also include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0198] Here, we will explain the details of the CAAC-OS, nc-OS, and a-like OS mentioned above.

[0199] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, the c-axis of which is oriented in a specific direction. This specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If we consider the atomic arrangement as a lattice arrangement, then a crystalline region is also a region with a aligned lattice arrangement. Furthermore, CAAC-OS has regions where multiple crystalline regions are connected in the ab-plane direction, and these regions may exhibit distortion. Distortion refers to a point in the connected region where the orientation of the lattice arrangement changes between a region with a aligned lattice arrangement and another region with a aligned lattice arrangement. In short, CAAC-OS is an oxide semiconductor that is c-axis oriented and does not exhibit clear orientation in the ab-plane direction.

[0200] Each of the multiple crystalline regions described above is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of a single minute crystal, the maximum diameter of that crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of that crystalline region may be around several tens of nanometers.

[0201] Furthermore, in In-M-Zn oxides (where element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystalline structure (also called a layered structure) consisting of layers containing indium (In) and oxygen (hereinafter referred to as the In layer) and layers containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer). Note that indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Also, the In layer may contain Zn. This layered structure can be observed, for example, as a lattice image in high-resolution TEM images.

[0202] When structural analysis of a CAAC-OS film is performed using an XRD instrument, for example, out-of-plane XRD measurements using θ / 2θ scanning show a peak indicating c-axis orientation at 2θ = 31° or nearby. Note that the position of the c-axis orientation peak (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0203] Furthermore, for example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film. These spots are observed at point-symmetric positions with respect to the incident electron beam spot (also called the direct spot) that passed through the sample.

[0204] When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the strain may have lattice arrangements such as pentagons or heptagons. Moreover, in CAAC-OS, clear grain boundaries cannot be observed even near the strain. In other words, it can be seen that the formation of grain boundaries is suppressed by the strain in the lattice arrangement. This is thought to be because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction, and the bond distance between atoms changes due to the substitution of metal atoms.

[0205] A crystal structure in which clear grain boundaries are observed is called a polycrystal. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in transistor on-current and field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides with a suitable crystal structure for the semiconductor layer of a transistor. In addition, a structure containing Zn is preferred for the composition of CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are preferred because they suppress the generation of grain boundaries more than In oxide.

[0206] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. Furthermore, since the crystallinity of oxide semiconductors can decrease due to the inclusion of impurities and the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in OS transistors allows for greater flexibility in the manufacturing process.

[0207] [nc-OS] nc-OS exhibits periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). In other words, nc-OS contains minute crystals. These minute crystals are also called nanocrystals because their size is, for example, between 1 nm and 10 nm, particularly between 1 nm and 3 nm. Furthermore, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductors. For example, when structural analysis of an nc-OS film is performed using an XRD instrument, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the nanocrystals (e.g., 50 nm or larger), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystal (for example, 1 nm to 30 nm), an electron diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on a direct spot.

[0208] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Also, a-like OS has a higher hydrogen concentration in the film compared to nc-OS and CAAC-OS.

[0209] <<Oxide Semiconductor Composition>> Next, we will explain the details of CAC-OS mentioned above. Note that CAC-OS refers to the material composition.

[0210] [CAC-OS] CAC-OS is, for example, a component of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. In the following, in the metal oxide, a state in which one or more metal elements are unevenly distributed and the regions having the metal elements are mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof is also referred to as a mosaic state or a patch state.

[0211] Furthermore, CAC-OS is a composite metal oxide having a structure in which the material is separated into a first region and a second region to form a mosaic state, and the first region is distributed in the film (hereinafter, also referred to as a cloud state). That is, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0212] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0213] Specifically, the first region is a region mainly composed of indium oxide, indium zinc oxide, etc. The second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. That is, the first region can be rephrased as a region mainly composed of In. The second region can be rephrased as a region mainly composed of Ga.

[0214] Furthermore, a clear boundary may not be observed between the first region and the second region described above.

[0215] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) confirms that it has a structure in which regions mainly composed of In (first region) and regions mainly composed of Ga (second region) are unevenly distributed and mixed.

[0216] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulation due to the second region work complementaryly to give CAC-OS a switching function (on / off function). In other words, CAC-OS has conductive function in part of the material, insulating function in part of the material, and semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I) can be achieved. on This enables high field-effect mobility (μ) and good switching operation.

[0217] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention may include two or more of the following: amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0218] <Transistors containing oxide semiconductors> Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0219] By using the above-mentioned oxide semiconductor in transistors, it is possible to realize transistors with high field-effect mobility. Furthermore, it is possible to realize highly reliable transistors.

[0220] It is preferable to use an oxide semiconductor with a low carrier concentration in the channel formation region of a transistor. For example, the carrier concentration in the channel formation region of an oxide semiconductor is 1 × 10⁻⁶. 17 cm -3 The following is preferably 1 × 10 15 cm -3 More preferably 1 × 10 13 cm -3 More preferably 1 × 10 11 cm -3 More preferably 1 × 10 10 cm -3 It is less than 1 × 10 -9 cm -3 This concludes the explanation. Furthermore, when lowering the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film should be lowered to reduce the defect level density. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that oxide semiconductors with low carrier concentrations are sometimes referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors.

[0221] Furthermore, oxide semiconductor films that are highly pure or substantially highly pure have a low defect level density, which may result in a low trap level density.

[0222] Furthermore, charges trapped in the trap levels of oxide semiconductors can take a long time to disappear, sometimes behaving like fixed charges. Therefore, transistors in which channel formation regions are formed in oxide semiconductors with a high trap level density may exhibit unstable electrical properties.

[0223] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0224] <Impurities> Here, we will explain the effects of various impurities in oxide semiconductors.

[0225] In oxide semiconductors, the presence of silicon or carbon, which are Group 14 elements, leads to the formation of defect levels in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the channel formation region of the oxide semiconductor and the concentrations of silicon or carbon near the interface with the channel formation region of the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry) are measured at 2 × 10⁻¹⁶. 18 atoms / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0226] Furthermore, if an oxide semiconductor contains alkali metals or alkaline earth metals, it may form defect levels and generate carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit normally-on characteristics. For this reason, the concentration of alkali metals or alkaline earth metals in the channel formation region of the oxide semiconductor obtained by SIMS should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0227] Furthermore, in oxide semiconductors, the presence of nitrogen generates electrons, which act as carriers, increasing the carrier concentration and making it easier for the semiconductor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Alternatively, the presence of nitrogen in oxide semiconductors can lead to the formation of trap levels. As a result, the electrical properties of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of oxide semiconductors obtained by SIMS should be set to 5 × 10⁻⁶. 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 1018 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 Do the following:

[0228] Furthermore, hydrogen contained in oxide semiconductors can react with oxygen bonded to metal atoms to form water, potentially creating oxygen vacancies. When hydrogen fills these oxygen vacancies, electrons, which act as carriers, may be generated. Additionally, some of the hydrogen can combine with oxygen bonded to metal atoms to generate electrons. Therefore, transistors using oxide semiconductors containing hydrogen tend to exhibit normally-on characteristics. For this reason, it is preferable to minimize the amount of hydrogen in the channel formation region of the oxide semiconductor. Specifically, in the channel formation region of the oxide semiconductor, the hydrogen concentration obtained by SIMS should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 5 × 10 19 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Make it less than.

[0229] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0230] <<Other Semiconductor Materials>> The semiconductor material that can be used for oxide 230 is not limited to the metal oxides described above. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used as oxide 230. For example, it is preferable to use semiconductors of elemental elements such as silicon, compound semiconductors such as gallium arsenide, or layered materials that function as semiconductors (also called atomic layer materials, two-dimensional materials, etc.) as the semiconductor material. In particular, it is preferable to use layered materials that function as semiconductors as the semiconductor material.

[0231] In this specification, the term "layered material" refers to a group of materials having a layered crystalline structure. A layered crystalline structure is a structure in which layers formed by covalent or ionic bonds are stacked via weaker bonds than covalent or ionic bonds, such as van der Waals forces. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, it is possible to provide a transistor with a large on-current.

[0232] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens. Chalcogens are a general term for elements belonging to Group 16, and include oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0233] As the oxide 230, it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor. Specific examples of the transition metal chalcogenide applicable as the oxide 230 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), and the like.

[0234] <Method for fabricating a semiconductor device> Next, a method for fabricating a semiconductor device, which is an aspect of the present invention shown in FIGS. 3A to 3D, will be described using FIGS. 9A to 20D.

[0235] A in each figure shows a top view. Also, B in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A1 - A2 shown in A of each figure, and is also a cross-sectional view in the channel length direction of the transistor 200. Further, C in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A3 - A4 in A of each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. Additionally, D in each figure is a cross-sectional view of the portion indicated by the dashed line A5 - A6 in A of each figure. Note that in the top view of A in each figure, some elements are omitted for clarity of the figure.

[0236] Hereinafter, an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor can be formed into a film by appropriately using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0237] Sputtering methods include RF sputtering, which uses a high-frequency power supply; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrodes in pulses. RF sputtering is mainly used for depositing insulating films, while DC sputtering is mainly used for depositing conductive metal films. Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0238] Furthermore, CVD methods can be classified into plasma CVD (PECVD), which utilizes plasma; thermal CVD (TCVD), which utilizes heat; and photo CVD (Photo CVD), which utilizes light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD) depending on the source gas used.

[0239] Plasma CVD allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing plasma damage to the workpiece. For example, wiring, electrodes, and elements (transistors, capacitive elements, etc.) contained in semiconductor devices can be charged up by receiving charge from the plasma. In this case, the accumulated charge can destroy the wiring, electrodes, and elements contained in the semiconductor device. In contrast, thermal CVD, which does not use plasma, does not cause such plasma damage, thus increasing the yield of semiconductor devices. Furthermore, because thermal CVD does not cause plasma damage during film formation, films with fewer defects can be obtained.

[0240] Furthermore, ALD methods that can be used include thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and PEALD, which uses plasma-excited reactants.

[0241] CVD and ALD methods differ from sputtering, where particles emitted from a target or other source are deposited. Therefore, they are less affected by the shape of the workpiece and provide good step-level coating. In particular, the ALD method is suitable for coating the surface of openings with high aspect ratios due to its excellent step-level coating and uniform thickness. However, because the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other deposition methods that have a faster deposition rate, such as the CVD method.

[0242] Furthermore, the CVD method allows for the deposition of films with any desired composition by changing the flow rate ratio of the raw material gases. For example, in the CVD method, films with continuously changing compositions can be deposited by changing the flow rate ratio of the raw material gases while the film is being deposited. When depositing films while changing the flow rate ratio of the raw material gases, the time required for film deposition can be shortened compared to depositing films using multiple deposition chambers, because time spent on transport or pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0243] Furthermore, the ALD method allows for the deposition of films of any composition by simultaneously introducing multiple different types of precursors, or by controlling the number of cycles for each precursor.

[0244] First, a substrate (not shown) is prepared, and an insulator 212 is deposited on the substrate (see Figures 9A to 9D). The deposition of the insulator 212 is preferably carried out using a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 212 can be reduced. However, the deposition of the insulator 212 is not limited to the sputtering method; CVD, MBE, PLD, ALD, etc., may be used as appropriate.

[0245] In this embodiment, silicon nitride is deposited as the insulator 212 using a silicon target in a nitrogen gas-containing atmosphere by pulsed DC sputtering. By using pulsed DC sputtering, the generation of particles due to arcing on the target surface can be suppressed, resulting in a more uniform film thickness distribution. Furthermore, by using a pulsed voltage, the rise and fall of the discharge can be made steeper than with a high-frequency voltage. This allows for more efficient power supply to the electrode, improving the sputtering rate and film quality.

[0246] By using an insulator that is impermeable to impurities such as water and hydrogen, such as silicon nitride, the diffusion of impurities such as water and hydrogen contained in the layer below the insulator 212 can be suppressed. Furthermore, by using an insulator that is impermeable to copper, such as silicon nitride, as the insulator 212, even if a diffusive metal such as copper is used in the conductor layer below the insulator 212 (not shown), the diffusion of that metal upward through the insulator 212 can be suppressed.

[0247] Next, an insulator 214 is deposited on the insulator 212 (see Figures 9A to 9D). The deposition of the insulator 214 is preferably carried out using a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 214 can be reduced. However, the deposition of the insulator 214 is not limited to the sputtering method; CVD, MBE, PLD, ALD, etc., may be used as appropriate.

[0248] In this embodiment, aluminum oxide is deposited as the insulator 214 using a pulsed DC sputtering method with an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. Here, RF power may be applied to the substrate. The amount of oxygen injected into the layer below the insulator 214 can be controlled by the magnitude of the RF power applied to the substrate. The RF power is 0 W / cm². 2 The above is 1.86 W / cm².2 The following applies: In other words, the amount of oxygen injected can be varied to suit the characteristics of the transistor by changing the RF power used during the formation of the insulator 214. Therefore, an amount of oxygen suitable for improving the reliability of the transistor can be injected. Furthermore, the RF frequency is preferably 10 MHz or higher. Typically, it is 13.56 MHz. The higher the RF frequency, the less damage can be inflicted on the substrate.

[0249] It is preferable to use an amorphous metal oxide, such as aluminum oxide, as the insulator 214, which has a high ability to capture and fix hydrogen. This allows for the capture or fixation of hydrogen contained in the insulator 216, etc., preventing the hydrogen from diffusing into the oxide 230. In particular, it is preferable to use amorphous aluminum oxide, or aluminum oxide with an amorphous structure, as the insulator 214, as this may allow for more effective capture or fixation of hydrogen. This makes it possible to manufacture a transistor 200 and semiconductor device with good properties and high reliability.

[0250] Next, an insulator 216 is deposited on the insulator 214. The deposition of the insulator 216 is preferably carried out using a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 216 can be reduced. However, the deposition of the insulator 216 is not limited to the sputtering method; CVD, MBE, PLD, ALD, etc., may be used as appropriate.

[0251] In this embodiment, silicon oxide is deposited as the insulator 216 using a silicon target in an atmosphere containing oxygen gas by pulsed DC sputtering. By using pulsed DC sputtering, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0252] It is preferable to continuously deposit insulators 212, 214, and 216 without exposure to the atmosphere. For example, a multi-chamber type deposition apparatus can be used. This allows for the deposition of insulators 212, 214, and 216 with reduced hydrogen content in the films, and further reduces the incorporation of hydrogen into the films between each deposition process.

[0253] Next, an opening is formed in the insulator 216 that reaches the insulator 214. The opening includes, for example, grooves and slits. In some cases, the term "opening" refers to the region in which the opening is formed. The opening may be formed using wet etching, but dry etching is preferable for microfabrication. Furthermore, it is preferable to select an insulator 214 that functions as an etching stopper film when etching the insulator 216 to form grooves. For example, if silicon oxide or silicon oxynitride is used for the insulator 216 in which grooves are formed, silicon nitride, aluminum oxide, or hafnium oxide may be used for the insulator 214.

[0254] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one electrode of the parallel plate electrodes. Alternatively, it may be configured to apply multiple different high-frequency voltages to one electrode of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. A dry etching apparatus having a high-density plasma source may be, for example, an inductively coupled plasma (ICP) etching apparatus.

[0255] After the opening is formed, a conductive film that will become the conductor 205a is deposited. It is desirable that the conductive film that will become the conductor 205a contains a conductor that has the function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc., can be used. Alternatively, a laminated film can be formed of a conductor that has the function of suppressing oxygen permeation and a tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum-tungsten alloy. The conductive film that will become the conductor 205a can be deposited using sputtering, CVD, MBE, PLD, ALD, etc.

[0256] In this embodiment, titanium nitride is deposited as a conductive film that forms the conductor 205a. By using such a metal nitride as a layer beneath the conductor 205b, oxidation of the conductor 205b by the insulator 216 and the like can be suppressed. Furthermore, even if a highly diffusive metal such as copper is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205a.

[0257] Next, a conductive film to become the conductor 205b is deposited. As the conductive film to become the conductor 205b, tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum-tungsten alloy, etc., can be used. The conductive film can be deposited using methods such as plating, sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, tungsten is deposited as the conductive film to become the conductor 205b.

[0258] Next, by performing a CMP treatment, a portion of the conductive film that will become conductor 205a and the conductive film that will become conductor 205b is removed, exposing the insulator 216 (see Figures 9A to 9D). As a result, conductor 205a and conductor 205b remain only in the opening. Note that a portion of the insulator 216 may be removed by this CMP treatment.

[0259] Next, an insulator 222 is deposited on the insulator 216 and the conductor 205 (see Figures 10A to 10D). It is preferable to deposit an insulator 222 containing an oxide of either or both aluminum and hafnium. Preferably, the insulator containing an oxide of either or both aluminum and hafnium is an aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Alternatively, hafnium zirconium oxide is preferred. An insulator containing an oxide of either or both aluminum and hafnium has barrier properties against oxygen, hydrogen, and water. Because the insulator 222 has barrier properties against hydrogen and water, the diffusion of hydrogen and water contained in the structure surrounding the transistor 200 into the transistor 200 through the insulator 222 is suppressed, thereby suppressing the formation of oxygen vacancies in the oxide 230.

[0260] The insulator 222 can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD. In this embodiment, hafnium oxide is deposited as the insulator 222 using the ALD method.

[0261] Next, it is preferable to perform a heat treatment. The heat treatment should be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas should be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then further in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen.

[0262] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from moisture or other substances being incorporated into the insulator 222 and the like.

[0263] In this embodiment, as a heat treatment, after the insulator 222 is formed, a nitrogen gas to oxygen gas flow rate ratio of 4 slm:1 slm is used, and the treatment is performed at a temperature of 400°C for 1 hour. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. Furthermore, when an oxide containing hafnium is used as the insulator 222, a portion of the insulator 222 may crystallize as a result of this heat treatment. The heat treatment can also be performed at a later time, such as after the insulator 224 is formed.

[0264] Next, an insulating film 224A is deposited on the insulator 222 (see Figures 10A to 10D). The insulating film 224A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, silicon oxide is deposited as the insulating film 224A using the sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating film 224A can be reduced. Since the insulating film 224A will come into contact with the oxide 230a in a later step, it is preferable that the hydrogen concentration is reduced in this way.

[0265] Next, oxide films 230A and 230B are sequentially deposited on the insulating film 224A (see Figures 10A to 10D). It is preferable to deposit oxide films 230A and 230B continuously without exposing them to the atmosphere. By depositing the films without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmosphere from adhering to oxide films 230A and 230B, and to keep the vicinity of the interface between oxide films 230A and 230B clean.

[0266] The oxide films 230A and 230B can be deposited using sputtering, CVD, MBE, PLD, ALD, and the like. The ALD method is preferred for depositing oxide films 230A and 230B because it allows for the formation of films with uniform thickness even in grooves or openings with large aspect ratios. The PEALD method is also preferred because it allows for the formation of oxide films 230A and 230B at lower temperatures compared to the thermal ALD method. In this embodiment, the oxide films 230A and 230B are deposited using sputtering.

[0267] For example, when depositing oxide films 230A and 230B by sputtering, oxygen or a mixture of oxygen and a noble gas is used as the sputtering gas. By increasing the proportion of oxygen in the sputtering gas, the excess oxygen in the deposited oxide film can be increased. Furthermore, when depositing the above oxide films by sputtering, the above-mentioned In-M-Zn oxide target can be used.

[0268] In particular, during the formation of the oxide film 230A, some of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas should be 70% or more, preferably 80% or more, and more preferably 100%.

[0269] Furthermore, when the oxide film 230B is formed by sputtering, if the proportion of oxygen in the sputtering gas is set to be more than 30% but 100% or less, preferably 70% or more but 100%, an oxygen-rich oxide semiconductor is formed. Transistors using an oxygen-rich oxide semiconductor in the channel formation region can achieve relatively high reliability. However, the present invention is not limited to this. When the oxide film 230B is formed by sputtering, if the proportion of oxygen in the sputtering gas is set to be 1% or more but 30% or less, preferably 5% or more but 20%, an oxygen-deficient oxide semiconductor is formed. Transistors using an oxygen-deficient oxide semiconductor in the channel formation region can achieve relatively high field-effect mobility. In addition, the crystallinity of the oxide film can be improved by performing film formation while heating the substrate.

[0270] In this embodiment, oxide film 230A is formed by sputtering using an oxide target with an In:Ga:Zn ratio of 1:3:4. Oxide film 230B is formed by sputtering using an oxide target with an In:Ga:Zn ratio of 4:2:4.1, an In:Ga:Zn ratio of 1:1:1, or an In:Ga:Zn ratio of 1:1:2. Each oxide film can be formed according to the desired properties of oxide 230a and oxide 230b by appropriately selecting the deposition conditions and atomic ratios.

[0271] Furthermore, it is preferable to deposit the insulating film 224A, oxide film 230A, and oxide film 230B by sputtering without exposure to the atmosphere. For example, a multi-chamber type deposition apparatus can be used. This reduces the incorporation of hydrogen into the films between each deposition process for the insulating film 224A, oxide film 230A, and oxide film 230B.

[0272] Next, it is preferable to perform a heat treatment. The heat treatment should be performed within a temperature range in which the oxide films 230A and 230B do not undergo polycrystallization, and should be performed between 250°C and 650°C, preferably between 400°C and 600°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas should be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen.

[0273] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from the incorporation of water and other substances into the oxide film 230A and oxide film 230B.

[0274] In this embodiment, the heat treatment involves a nitrogen gas to oxygen gas flow rate ratio of 4 slm:1 slm, performed at a temperature of 400°C for 1 hour. This heat treatment including oxygen gas can reduce impurities such as carbon, water, and hydrogen in oxide films 230A and 230B. By reducing impurities in the films in this way, the crystallinity of oxide film 230B can be improved, resulting in a denser, more compact structure. This increases the crystalline region in oxide films 230A and 230B, reducing in-plane variation of the crystalline region within oxide films 230A and 230B. Therefore, in-plane variation in the electrical characteristics of transistor 200 can be reduced.

[0275] Furthermore, by performing the heat treatment, hydrogen in the insulator 216, insulating film 224A, oxide film 230A, and oxide film 230B moves to the insulator 222 and is absorbed into the insulator 222. In other words, it can be said that hydrogen in the insulator 216, insulating film 224A, oxide film 230A, and oxide film 230B diffuses into the insulator 222. Therefore, the hydrogen concentration in the insulator 222 increases, but the hydrogen concentrations in the insulator 216, insulating film 224A, oxide film 230A, and oxide film 230B decrease.

[0276] In particular, the insulating film 224A functions as a gate insulator for the transistor 200, and the oxide films 230A and 230B function as channel formation regions for the transistor 200. Therefore, a transistor 200 having insulating films 224A, oxide films 230A, and oxide films 230B with reduced hydrogen concentrations is preferred because it has good reliability.

[0277] Next, a conductive film 242A is deposited on the oxide film 230B (see Figures 10A to 10D). The conductive film 242A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. For example, tantalum nitride can be deposited as the conductive film 242A using sputtering. Before depositing the conductive film 242A, a heat treatment may be performed. This heat treatment may be performed under reduced pressure, and the conductive film 242A may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230B can be removed, and the moisture and hydrogen concentrations in the oxide film 230A and the oxide film 230B can be further reduced. The temperature of the heat treatment is preferably between 100°C and 400°C. In this embodiment, the temperature of the heat treatment is set to 200°C.

[0278] Next, an insulating film 271A is deposited on the conductive film 242A (see Figures 10A to 10D). The insulating film 271A can be deposited using sputtering, CVD, MBE, PLD, or ALD. It is preferable to use an insulating film 271A that has the function of suppressing oxygen permeation. For example, aluminum oxide or silicon nitride can be deposited as the insulating film 271A by sputtering.

[0279] Furthermore, it is preferable to deposit the conductive film 242A and the insulating film 271A by sputtering without exposure to the atmosphere. For example, a multi-chamber type deposition apparatus may be used. This reduces the amount of hydrogen in the films when depositing the conductive film 242A and the insulating film 271A, and also reduces the amount of hydrogen introduced into the films between each deposition process. In addition, if a hard mask is provided on the insulating film 271A, the hard mask film may also be deposited continuously without exposure to the atmosphere.

[0280] Next, the insulating film 224A, oxide film 230A, oxide film 230B, conductive film 242A, and insulating film 271A are processed into island-like structures using lithography to form the insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B (see Figures 11A to 11D). Here, the insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B are formed so that at least a portion of them overlaps with the conductor 205. The above processing can be performed using either dry etching or wet etching. Dry etching is suitable for microfabrication. Furthermore, the processing of the insulating film 224A, oxide film 230A, oxide film 230B, conductive film 242A, and insulating film 271A may be carried out under different conditions.

[0281] In lithography, the resist is first exposed through a mask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Then, the conductor, semiconductor, or insulator can be processed into a desired shape by etching through the resist mask. For example, the resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. Alternatively, immersion technology can be used, where a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. In addition, an electron beam or ion beam may be used instead of the aforementioned light. When using an electron beam or ion beam, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0282] Furthermore, a hard mask made of an insulator or conductor may be used beneath the resist mask. When using a hard mask, an insulating film or conductive film that serves as the hard mask material is formed on the conductive film 242A, a resist mask is formed on top of it, and a hard mask of the desired shape can be formed by etching the hard mask material. Etching of the conductive film 242A, etc., may be performed after removing the resist mask, or it may be performed while the resist mask remains. In the latter case, the resist mask may disappear during etching. The hard mask may also be removed by etching after etching of the conductive film 242A, etc. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not always necessary to remove the hard mask. In this embodiment, an insulating layer 271B is used as the hard mask.

[0283] Here, the insulating layer 271B functions as a mask for the conductive layer 242B, so as shown in Figures 11B to 11D, the conductive layer 242B does not have a curved surface between its side and top surfaces. As a result, the conductors 242a and 242b shown in Figures 3B and 3D have angular ends where their side and top surfaces intersect. The angular shape of the ends where the side and top surfaces of the conductor 242 intersect increases the cross-sectional area of ​​the conductor 242 compared to when the ends have a curved surface. This reduces the resistance of the conductor 242, allowing the on-current of the transistor 200 to be increased.

[0284] Furthermore, as shown in Figures 11B to 11D, the cross-sections of the insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B may be tapered. In this specification, a tapered shape refers to a shape in which at least a part of the side surface of the structure is inclined with respect to the substrate surface. For example, it is preferable that the angle between the inclined side surface and the substrate surface (hereinafter sometimes referred to as the taper angle) is less than 90°. For example, the insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B may have a taper angle of 60° or more and less than 90°. By making the cross-section tapered in this way, the coverage of the insulator 275 and other components can be improved in subsequent processes, and defects such as porosity can be reduced.

[0285] However, the above is not limited to the above, and the sides of the insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B may be configured to be approximately perpendicular to the upper surface of the insulator 222. Such a configuration makes it possible to reduce the area and increase the density when providing multiple transistors 200.

[0286] Furthermore, by-products generated during the etching process may form in layers on the sides of the insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B. In this case, the layered by-products will be formed between the insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B and the insulator 275. Therefore, it is preferable to remove the layered by-products formed in contact with the upper surface of the insulator 222.

[0287] Next, an insulator 275 is formed by covering the insulator 224, oxide 230a, oxide 230b, conductive layer 242B, and insulating layer 271B (see Figures 12A to 12D). Here, it is preferable that the insulator 275 is in close contact with the upper surface of the insulator 222 and the side surface of the insulator 224. The insulator 275 can be formed using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable that the insulator 275 is an insulating film that has the function of suppressing oxygen permeation. For example, as the insulator 275, aluminum oxide can be formed using the sputtering method, and silicon nitride can be formed on top of it using the PEALD method. By making the insulator 275 such a layered structure, the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen may be improved.

[0288] In this way, oxide 230a, oxide 230b, and conductive layer 242B can be covered with insulator 275 and insulating layer 271B, which have the function of suppressing oxygen diffusion. This reduces the direct diffusion of oxygen from insulator 280, etc., to insulator 224, oxide 230a, oxide 230b, and conductive layer 242B in subsequent processes.

[0289] Next, an insulating film, which will become an insulator 280, is deposited on the insulator 275. This insulating film can be deposited using sputtering, CVD, MBE, PLD, ALD, or the like. For example, a silicon oxide film can be deposited as the insulating film using sputtering. By depositing the insulating film that will become the insulator 280 using sputtering in an oxygen-containing atmosphere, an insulator 280 containing excess oxygen can be formed. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 280 can be reduced. Note that a heat treatment may be performed before depositing the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 275 can be removed, and the moisture and hydrogen concentrations in the oxide 230a, oxide 230b, and insulator 224 can be further reduced. The heat treatment conditions described above can be used for this heat treatment.

[0290] Next, the insulating film that will become the insulator 280 is subjected to CMP treatment to form an insulator 280 with a flat upper surface (see Figures 12A to 12D). Alternatively, silicon nitride may be deposited on the insulator 280 by, for example, a sputtering method, and the silicon nitride may be subjected to CMP treatment until it reaches the insulator 280.

[0291] Next, a portion of the insulator 280, a portion of the insulator 275, a portion of the insulating layer 271B, and a portion of the conductive layer 242B are processed to form an opening that reaches the oxide 230b. Preferably, the opening is formed so as to overlap with the conductor 205. The formation of the opening creates the insulator 271a, the insulator 271b, the conductor 242a, and the conductor 242b (see Figures 13A to 13D).

[0292] Here, as shown in Figures 13B and 13C, the sides of the insulators 280, 275, 271, and conductor 242 may be tapered. Also, the taper angle of the insulator 280 may be larger than the taper angle of the conductor 242. In addition, although not shown in Figures 13A to 13C, the upper part of the oxide 230b may be removed when forming the above-mentioned opening.

[0293] Furthermore, the processing of a portion of the insulator 280, a portion of the insulator 275, a portion of the insulating layer 271B, and a portion of the conductive layer 242B can be carried out using either a dry etching method or a wet etching method. Dry etching is suitable for microfabrication. Moreover, these processing methods may be carried out under different conditions. For example, a portion of the insulator 280 may be processed by dry etching, a portion of the insulator 275 and a portion of the insulating layer 271B may be processed by wet etching, and a portion of the conductive layer 242B may be processed by dry etching.

[0294] Here, impurities may adhere to the sides of oxide 230a, the top and sides of oxide 230b, the sides of conductor 242, the sides of insulator 280, etc., or diffuse into these surfaces. A step to remove such impurities may be performed. In addition, a damaged area may be formed on the surface of oxide 230b during the dry etching process. Such a damaged area may be removed. Examples of such impurities include those resulting from components contained in insulator 280, insulator 275, a part of insulating layer 271B, and conductive layer 242B, components contained in materials used in the apparatus used to form the opening, and components contained in the gas or liquid used for etching. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.

[0295] In particular, impurities such as aluminum or silicon inhibit the CAAC-OS conversion of oxide 230b. Therefore, it is preferable that impurity elements that inhibit CAAC-OS conversion, such as aluminum or silicon, are reduced or removed. For example, the concentration of aluminum atoms in oxide 230b and its vicinity should be 5.0 atomic% or less, preferably 2.0 atomic% or less, more preferably 1.5 atomic% or less, even more preferably 1.0 atomic% or less, and even more preferably less than 0.3 atomic%.

[0296] Furthermore, the region of a metal oxide where CAAC-OS formation is inhibited by impurities such as aluminum or silicon, resulting in a pseudo-amorphous-like oxide semiconductor (a-like OS), is sometimes called the non-CAAC region. In the non-CAAC region, the density of the crystal structure is reduced, therefore V O A large amount of H is formed, making it easier for the transistor to become normally-on. Therefore, it is preferable that the non-CAAC region of oxide 230b is reduced or removed.

[0297] In contrast, it is preferable that the oxide 230b has a layered CAAC structure. In particular, it is preferable that the CAAC structure extends to the lower end of the drain of the oxide 230b. Here, in the transistor 200, the conductor 242a or conductor 242b, and its vicinity, function as a drain. That is, it is preferable that the oxide 230b near the lower end of the conductor 242a (conductor 242b) has a CAAC structure. In this way, even at the drain end, which significantly affects the drain breakdown voltage, the damaged region of the oxide 230b is removed and a CAAC structure is present, which further suppresses fluctuations in the electrical characteristics of the transistor 200. Furthermore, the reliability of the transistor 200 can be improved.

[0298] In order to remove impurities and other contaminants adhering to the oxide 230b surface during the etching process described above, a cleaning treatment is performed. Cleaning methods include wet cleaning using a cleaning solution (which can also be called wet etching), plasma treatment using plasma, and cleaning by heat treatment. These cleaning methods may be combined as appropriate. Note that this cleaning treatment may deepen the grooves.

[0299] For wet cleaning, cleaning may be performed using aqueous solutions of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, etc., diluted with carbonated water or distilled water, distilled water, carbonated water, etc. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, distilled water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0300] In this specification, an aqueous solution obtained by diluting hydrofluoric acid with pure water is sometimes referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting ammonia water with pure water is sometimes referred to as diluted ammonia water. The concentration and temperature of the aqueous solution may be adjusted as appropriate depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water should be 0.01% to 5%, preferably 0.1% to 0.5%. The hydrogen fluoride concentration of the diluted hydrofluoric acid should be 0.01 ppm to 100 ppm, preferably 0.1 ppm to 10 ppm.

[0301] Furthermore, it is preferable to use a frequency of 200 kHz or higher for ultrasonic cleaning, and more preferably a frequency of 900 kHz or higher. Using these frequencies can reduce damage to oxides such as 230b.

[0302] Furthermore, the above cleaning process may be performed multiple times, and the cleaning solution may be changed each time. For example, the first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and the second cleaning process may be performed using pure water or carbonated water.

[0303] As the above cleaning treatment, in the present embodiment, wet cleaning is performed using diluted aqueous ammonia. By performing this cleaning treatment, impurities adhering to the surface or diffused inside the oxides 230a, 230b, etc. can be removed. Furthermore, the crystallinity of the oxide 230b can be enhanced.

[0304] After the above etching or after the above cleaning, a heat treatment may be performed. The heat treatment may be performed at 100°C or higher and 450°C or lower, preferably 350°C or higher and 400°C or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. Thereby, oxygen can be supplied to the oxides 230a and 230b to reduce the oxygen vacancy V O . Also, by performing such a heat treatment, the crystallinity of the oxide 230b can be improved. Also, the heat treatment may be performed under reduced pressure. Or, after performing the heat treatment in an oxygen atmosphere, the heat treatment may be continuously performed in a nitrogen atmosphere without being exposed to the atmosphere.

[0305] Next, the insulating film 252A is deposited (see Figures 14A to 14D). The insulating film 252A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable to deposit the insulating film 252A using the ALD method. As mentioned above, it is preferable to deposit the insulating film 252A with a thin film thickness, and it is necessary to minimize variations in film thickness. In contrast, the ALD method is a film deposition method that alternately introduces a precursor and a reactant (e.g., an oxidizing agent), and the film thickness can be adjusted by the number of times this cycle is repeated, thus enabling precise film thickness adjustment. Also, as shown in Figures 14B and 14C, the insulating film 252A needs to be deposited with good coverage on the bottom and side surfaces of openings formed in the insulator 280, etc. In particular, it is preferable to deposit it with good coverage on the top and side surfaces of the oxide 230 and the side surfaces of the conductor 242. Since atomic layers can be deposited one by one on the bottom and side surfaces of the opening, the insulating film 252A can be formed on the opening with good coverage.

[0306] Furthermore, when the insulating film 252A is deposited by the ALD method, ozone (O3), oxygen (O2), water (H2O), etc., can be used as oxidizing agents. By using hydrogen-free oxidizing agents such as ozone (O3) and oxygen (O2), the amount of hydrogen diffusing into the oxide 230b can be reduced.

[0307] In this embodiment, aluminum oxide is deposited as the insulating film 252A by thermal ALD method.

[0308] Next, it is preferable to perform microwave processing in an oxygen-containing atmosphere (see Figures 14A to 14D). Here, microwave processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example. In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0309] As shown in Figures 14B to 14D, the dotted lines represent microwaves, high frequencies such as RF, oxygen plasma, or oxygen radicals. For microwave processing, it is preferable to use a microwave processing apparatus that has a power supply for generating high-density plasma using microwaves. Here, the frequency of the microwave processing apparatus should be 300 MHz or more and 300 GHz or less, preferably 2.4 GHz or more and 2.5 GHz or less, for example, 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. The power of the power supply for applying microwaves to the microwave processing apparatus should be 1000 W or more and 10000 W or less, preferably 2000 W or more and 5000 W or less. The microwave processing apparatus may also have a power supply for applying RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently guided into the oxide 230b.

[0310] Furthermore, the above microwave treatment is preferably carried out under reduced pressure, with a pressure of 10 Pa to 1000 Pa, preferably 300 Pa to 700 Pa. The treatment temperature should be 750°C or lower, preferably 500°C or lower, for example, around 400°C. Alternatively, after oxygen plasma treatment, heat treatment may be carried out continuously without exposure to the outside air. For example, heat treatment may be carried out at 100°C to 750°C, preferably 300°C to 500°C.

[0311] Furthermore, for example, the above microwave treatment may be carried out using oxygen gas and argon gas. Here, the oxygen flow rate ratio (O2 / (O2+Ar)) should be greater than 0% and 100% or less. Preferably, the oxygen flow rate ratio (O2 / (O2+Ar)) should be greater than 0% and 50% or less. More preferably, the oxygen flow rate ratio (O2 / (O2+Ar)) should be 10% or more and 40% or less. Even more preferably, the oxygen flow rate ratio (O2 / (O2+Ar)) should be 10% or more and 30% or less. In this way, by performing microwave treatment in an oxygen-containing atmosphere, the carrier concentration in region 230bc can be reduced. In addition, by preventing an excessive amount of oxygen from being introduced into the chamber during microwave treatment, it is possible to prevent an excessive decrease in carrier concentration in regions 230ba and 230bb.

[0312] As shown in Figures 14B to 14D, by performing microwave treatment in an oxygen-containing atmosphere, the oxygen gas can be plasma-generated using microwaves or high-frequency waves such as RF, and this oxygen plasma can be applied to the region between the conductors 242a and 242b of the oxide 230b. At this time, microwaves or high-frequency waves such as RF can also be irradiated onto region 230bc. In other words, microwaves or high-frequency waves such as RF, oxygen plasma, etc., can be applied to region 230bc shown in Figure 4A. Due to the action of plasma, microwaves, etc., the V of region 230bc O By cleaving H, hydrogen H can be removed from region 230bc. In other words, in region 230bc, "V O H → H + V O The following reaction occurs, and V is included in region 230bc. O H can be reduced. Therefore, oxygen deficiency in region 230bc, and V O By reducing H, the carrier concentration can be lowered. Furthermore, by supplying oxygen radicals generated in the oxygen plasma or oxygen contained in the insulator 250 to the oxygen vacancy formed in region 230bc, the oxygen vacancy in region 230bc can be further reduced, and the carrier concentration can be lowered.

[0313] On one hand, conductors 242a and 242b are provided on regions 230ba and 230bb shown in FIG. 4A. Here, when microwave treatment is performed in an oxygen-containing atmosphere, the conductor 242 preferably functions as a shielding film against the actions of microwaves, high frequencies such as RF, and oxygen plasma. For this reason, the conductor 242 preferably has a function of shielding electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.

[0314] As shown in FIGS. 14B to 14D, since the conductors 242a and 242b shield the actions of microwaves, high frequencies such as RF, and oxygen plasma, these actions do not reach the regions 230ba and 230bb. As a result, by microwave treatment, in regions 230ba and 230bb, O the reduction of VH and the supply of an excessive amount of oxygen do not occur, so that a decrease in carrier concentration can be prevented.

[0315] In addition, an insulator 252 having a barrier property against oxygen is provided in contact with the side surfaces of the conductors 242a and 242b. Thereby, formation of an oxide film on the side surfaces of the conductors 242a and 242b by microwave treatment can be suppressed.

[0316] As described above, oxygen deficiency and O VH can be selectively removed in the region 230bc of the oxide semiconductor, and the region 230bc can be made i-type or substantially i-type. Further, the supply of excessive oxygen to the regions 230ba and 230bb that function as source regions or drain regions can be suppressed, and n-type conversion can be maintained. Thereby, fluctuations in the electrical characteristics of the transistor 200 can be suppressed, and variations in the electrical characteristics of the transistor 200 within the substrate surface can be suppressed.

[0317] In microwave processing, electromagnetic interaction between microwaves and molecules in oxide 230b can directly transfer thermal energy to oxide 230b. This thermal energy can cause oxide 230b to heat up. This type of heat treatment is sometimes called microwave annealing. Performing microwave processing in an oxygen-containing atmosphere can sometimes achieve effects equivalent to oxygen annealing. Furthermore, if oxide 230b contains hydrogen, this thermal energy may be transferred to the hydrogen in oxide 230b, causing activated hydrogen to be released from oxide 230b.

[0318] Next, an insulating film 250A is deposited (see Figures 15A to 15D). A heat treatment may be performed before depositing the insulating film 250A, and this heat treatment may be carried out under reduced pressure, allowing for continuous deposition of the insulating film 250A without exposure to the atmosphere. Furthermore, it is preferable to carry out this heat treatment in an atmosphere containing oxygen. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulating film 252A can be removed, and the moisture and hydrogen concentrations in oxides 230a and 230b can be further reduced. The temperature of the heat treatment is preferably between 100°C and 400°C.

[0319] The insulating film 250A can be deposited using methods such as sputtering, CVD, PECVD, MBE, PLD, and ALD. Furthermore, it is preferable to deposit the insulating film 250A using a deposition method that utilizes a gas with reduced or removed hydrogen atoms. This allows for a reduction in the hydrogen concentration of the insulating film 250A. Since the insulating film 250A will later become an insulator 250 facing the oxide 230b via a thin insulating film 252, such a reduction in hydrogen concentration is preferable.

[0320] In this embodiment, silicon oxidnitride is used as the insulating film 250A and deposited by the PECVD method.

[0321] Furthermore, when the insulator 250 is made into a two-layer laminated structure as shown in Figure 4B, the insulating film that will become the insulator 250b can be deposited after the insulating film 250A has been deposited. The insulating film that will become the insulator 250b can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable that the insulating film that will become the insulator 250b be formed using an insulator that has the function of suppressing the diffusion of oxygen. With this configuration, the diffusion of oxygen contained in the insulator 250a to the conductor 260 can be suppressed. In other words, the decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 by oxygen contained in the insulator 250a can be suppressed. The insulating film that will become the insulator 250b can be made using the same material as the insulator 222. For example, hafnium oxide can be deposited as the insulating film that will become the insulator 250b by thermal ALD.

[0322] Microwave treatment may be performed after the deposition of the insulating film 250A (see Figures 15A to 15D). The microwave treatment may use the same microwave treatment conditions as those used after the deposition of the insulating film 252A. Alternatively, microwave treatment may be performed after the deposition of the insulating film 250A without performing the microwave treatment after the deposition of the insulating film 252A. Furthermore, when an insulating film that will become the insulator 250b is provided as described above, microwave treatment may be performed after deposition. The microwave treatment may use the same microwave treatment conditions as those used after the deposition of the insulating film 252A. Alternatively, microwave treatment may be performed after the deposition of the insulating film that will become the insulator 250b without performing the microwave treatment after the deposition of either the insulating film 252A or the insulating film 250A.

[0323] Furthermore, after the deposition of insulating film 252A and insulating film 250A, and after the deposition of the insulating film that will become insulator 250b, a heat treatment may be performed while maintaining a reduced pressure state. By performing such a treatment, hydrogen can be efficiently removed from insulating film 252A, insulating film 250A, insulating film that will become insulator 250b, oxide 230b, and oxide 230a. In addition, some of the hydrogen may be gettered into the conductor 242 (conductor 242a and conductor 242b). Alternatively, the step of performing a heat treatment while maintaining a reduced pressure state after microwave treatment may be repeated multiple times. By repeating the heat treatment, hydrogen can be removed even more efficiently from insulating film 252A, insulating film 250A, insulating film that will become insulator 250b, oxide 230b, and oxide 230a. The heat treatment temperature is preferably 300°C to 500°C. Furthermore, the above-mentioned microwave treatment, i.e., microwave annealing, may also serve as the heat treatment. If the oxide 230b, etc., is sufficiently heated by microwave annealing, the heat treatment may not be necessary.

[0324] Furthermore, by performing microwave treatment to modify the film quality of the insulating film 252A, insulating film 250A, and insulating film 250b, the diffusion of hydrogen, water, impurities, etc. can be suppressed. Therefore, in subsequent processes such as deposition of a conductive film that becomes the conductor 260, or post-treatment such as heat treatment, the diffusion of hydrogen, water, impurities, etc., to oxides 230b, oxides 230a, etc., via the insulating film 252 can be suppressed.

[0325] Next, the insulating film 254A is deposited (see Figures 16A to 16D). The insulating film 254A can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable to deposit the insulating film 254A using the ALD method, similar to the insulating film 252A. By depositing the film using the ALD method, the insulating film 254A can be deposited with a thin film thickness and good coverage. In this embodiment, silicon nitride is deposited as the insulating film 254A using the PEALD method.

[0326] Next, a conductive film to become conductor 260a and a conductive film to become conductor 260b are deposited in sequence. The conductive films to become conductor 260a and conductor 260b can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, titanium nitride is deposited as the conductive film to become conductor 260a using the ALD method, and tungsten is deposited as the conductive film to become conductor 260b using the CVD method.

[0327] Next, by CMP treatment, insulating films 252A, 250A, 254A, the conductive film that will become conductor 260a, and the conductive film that will become conductor 260b are polished until the insulator 280 is exposed, thereby forming insulators 252, 250, 254, and conductor 260 (conductor 260a and conductor 260b) (see Figures 17A to 17D). As a result, insulator 252 is positioned to cover the opening that reaches oxide 230b. Conductor 260 is positioned to fill the opening via insulators 252 and 250.

[0328] Next, a heat treatment may be performed under the same conditions as the heat treatment described above. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400°C for 1 hour. This heat treatment can reduce the moisture concentration and hydrogen concentration in the insulator 250 and insulator 280. After the heat treatment, the insulator 282 may be deposited continuously without exposure to the atmosphere.

[0329] Next, an insulator 282 is formed on the insulator 252, the insulator 250, the conductor 260, and the insulator 280 (see Figures 17A to 17D). The insulator 282 can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. It is preferable to deposit the insulator 282 using sputtering. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 282 can be reduced.

[0330] In this embodiment, aluminum oxide is deposited as the insulator 282 using a pulsed DC sputtering method with an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0331] Furthermore, by using the sputtering method to deposit the insulator 282 in an oxygen-containing atmosphere, oxygen can be added to the insulator 280 during film formation. This allows the insulator 280 to contain excess oxygen. In this case, it is preferable to deposit the insulator 282 while heating the substrate.

[0332] Next, an etching mask is formed on the insulator 282 by lithography, and a portion of the insulator 282, a portion of the insulator 280, a portion of the insulator 275, a portion of the insulator 222, and a portion of the insulator 216 are processed until the upper surface of the insulator 214 is exposed (see Figures 18A to 18D). This processing may be done using wet etching, but dry etching is preferable for fine processing.

[0333] Next, a heat treatment may be performed. The heat treatment should be performed at a temperature of 250°C to 650°C, preferably 350°C to 600°C. Furthermore, it is preferable that this heat treatment temperature is lower than the heat treatment temperature performed after the formation of the oxide film 230B. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas. By performing this heat treatment, some of the oxygen added to the insulator 280 diffuses into the oxide 230 via the insulator 250, etc.

[0334] Furthermore, by performing this heat treatment, oxygen contained in insulator 280 and hydrogen combined with that oxygen can be released to the outside from the side surface of insulator 280, which was formed by processing insulators 282, 280, 275, 222, and 216. The hydrogen combined with oxygen is released as water. Therefore, the amount of unwanted oxygen and hydrogen contained in insulator 280 can be reduced.

[0335] Furthermore, an insulator 252 is provided in contact with the upper and side surfaces of the oxide 230 in the region where the oxide 230 overlaps with the conductor 260. Since the insulator 252 has an oxygen barrier property, it can reduce the diffusion of excess oxygen into the oxide 230. This allows oxygen to be supplied in such a way that excess oxygen is not supplied to region 230bc and its vicinity. This suppresses oxidation of the side surfaces of the conductor 242 by excess oxygen, while preventing oxygen deficiencies and V2 formation in region 230bc. O H can be reduced. Therefore, the electrical characteristics of transistor 200 can be improved, and its reliability can be enhanced.

[0336] On the other hand, when transistors 200 are densely integrated, the volume of insulator 280 per transistor 200 may become excessively small. In this case, the amount of oxygen diffused into the oxide 230 during the heat treatment described above becomes significantly smaller. When the oxide 230 is heated while in contact with an oxide insulator that does not contain sufficient oxygen (for example, insulator 250), there is a risk that the oxygen constituting the oxide 230 will be desorbed. However, in the transistor 200 shown in this embodiment, an insulator 252 is provided in contact with the upper and side surfaces of the oxide 230 in the region overlapping with the conductor 260 of the oxide 230. Since the insulator 252 has barrier properties against oxygen, the desorption of oxygen from the oxide 230 can be reduced even during the heat treatment described above. As a result, oxygen deficiencies and V are formed in region 230bc. O H can be reduced. Therefore, the electrical characteristics of transistor 200 can be improved, and its reliability can be enhanced.

[0337] As described above, in the semiconductor device according to this embodiment, a transistor with good electrical characteristics and good reliability can be formed whether the amount of oxygen supplied from the insulator 280 is high or low. Therefore, a semiconductor device can be provided that suppresses variations in the electrical characteristics of the transistor 200 within the substrate surface.

[0338] Next, an insulator 283 is formed on the insulator 282 (see Figures 19A to 19D). The insulator 283 can be deposited using sputtering, CVD, MBE, PLD, or ALD. It is preferable to deposit the insulator 283 using sputtering. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 283 can be reduced. The insulator 283 may also be multilayered. For example, silicon nitride may be deposited using sputtering, and then silicon nitride may be deposited on the silicon nitride using the ALD method. By encasing the transistor 200 with the highly barrier insulators 283 and 214, moisture and hydrogen can be prevented from entering from the outside.

[0339] Next, an insulator 274 is formed on the insulator 283. The insulator 274 can be deposited using sputtering, CVD, MBE, PLD, or ALD. In this embodiment, silicon oxide is deposited as the insulator 274 by the CVD method.

[0340] Next, the upper surface of the insulator 274 is flattened by CMP treatment, which involves polishing the insulator 274 until the insulator 283 is exposed (see Figures 19A to 19D). This CMP treatment may remove a portion of the upper surface of the insulator 283.

[0341] Next, an insulator 285 is formed on the insulator 274 and the insulator 283 (see Figures 20A to 20D). The insulator 285 can be deposited using sputtering, CVD, MBE, PLD, or ALD. It is preferable to deposit the insulator 285 using sputtering. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 285 can be reduced.

[0342] In this embodiment, silicon oxide is deposited as the insulator 285 by sputtering.

[0343] Next, openings 290 reaching the conductor 242b are formed in insulators 271b, 275, 280, 282, 283, and 285 (see Figures 20A to 20D). The openings 290 can be formed using lithography. Since the openings 290 have a large aspect ratio, anisotropic etching is preferred, for example, by dry etching. For this dry etching, for example, C4F6 gas, C5F6 gas, C4F8 gas, CF4 gas, SF6 gas, CHF3 gas, Cl2 gas, BCl3 gas, or SiCl4 gas can be used individually or in a mixture of two or more gases. Alternatively, oxygen gas, helium gas, argon gas, or hydrogen gas can be added to the above gases as appropriate. These etching gases can be switched and used as appropriate depending on the material to be etched (insulator 271b, insulator 275, insulator 280, insulator 282, insulator 283, and insulator 285).

[0344] In Figure 20A, the shape of the opening 290 is shown as circular in a top view, but it is not limited to this. For example, the opening 290 may be a roughly circular shape such as an ellipse, a polygon such as a quadrilateral, or a polygon with rounded corners, when viewed from above.

[0345] In this configuration, it is preferable that the side and bottom surfaces of the opening 290 are joined by curved surfaces. This configuration allows for good coverage of the conductive material 110 in the opening 290.

[0346] Next, an insulating film that will become the insulator 245 is deposited. At this time, the insulating film is deposited in contact with at least the side surface of the opening 290. For example, the insulating film may be deposited along the side surface and bottom surface of the opening 290. The insulating film can be deposited using sputtering, CVD, MBE, PLD, or ALD. As the insulating film that will become the insulator 245, it is preferable to use an insulating film that has the function of suppressing the permeation of impurities such as water and hydrogen or oxygen. For example, it is preferable to deposit aluminum oxide using the ALD method and then deposit silicon nitride on top of it using the PEALD method. Silicon nitride is preferred because it has high blocking properties for hydrogen.

[0347] Next, the insulating film is anisotropically etched to form an insulator 245 in contact with the side surface of the opening 290 (see Figures 20A to 20D). At this point, at least a portion of the insulating film is removed, and at least a portion of the upper surface of the conductor 242b is exposed. In this case, as shown in Figure 20B, a portion of the upper surface of the conductor 242b may be removed. Anisotropic etching can be performed by, for example, a dry etching method. By configuring the side wall of the opening 290 in this way, the permeation of oxygen from the outside can be suppressed, and oxidation of the conductor 110 to be formed next can be prevented. In addition, impurities such as water and hydrogen contained in the insulator 280 can be prevented from diffusing into the conductor 110.

[0348] Next, a conductive film 110A is formed to cover the insulator 285 and the opening 290 (see Figures 21A to 21D). At this time, it is preferable that the conductive film 110A is formed in contact with the side and bottom surfaces of the opening 290, which have a large aspect ratio. For this reason, it is preferable to form the conductive film 110A using a film formation method that provides good coverage, such as the ALD method or the CVD method. For example, titanium nitride can be formed using the ALD method.

[0349] Next, a filler 135 is deposited on the conductive film 110A (see Figures 21A to 21D). The filler 135 only needs to fill the opening 290 to the extent that the subsequent CMP treatment can be performed. Therefore, cavities or other structures may be formed within the opening 290. The filler 135 may be an insulator or a conductor. For example, silicon oxide can be deposited as the filler 135 using the APCVD method.

[0350] Next, a CMP (Chemical Polishing) treatment is performed to remove the layer above the insulator 285 and form the conductor 110 (see Figures 22A to 22D). Here, it is preferable that the insulator 285 functions as a stopper for the CMP treatment of the conductive film 110A. Note that a portion of the insulator 285 may be removed by this CMP treatment.

[0351] Next, etching is performed to remove the filler material 135 from the opening 290 (see Figures 23A to 23D). Either wet etching or dry etching can be used for the etching process, but in some cases, wet etching is easier for removing the filler material 135 from the opening 290. When using wet etching, a hydrofluoric acid-based solution or the like can be used as the etchant.

[0352] Next, an insulating film 130A is formed on the conductor 110 and the insulator 285 (see Figures 24A to 24D). Preferably, the insulating film 130A is formed in contact with the conductor 110, which is located inside the opening 290 with a large aspect ratio. For this reason, it is preferable to form the insulating film 130A using a film formation method with good coverage, such as the ALD method or the CVD method. Preferably, the insulating film 130A is made of a material capable of having the ferroelectric properties described above. For example, HfZrO x The film should be deposited with (x being a real number greater than 0).

[0353] Furthermore, by forming an insulating film 130A using a film deposition method such as the ALD method, and covering the conductor 110 with good coverage, it is possible to prevent short circuits between the upper and lower electrodes of the capacitive element 100.

[0354] Next, a conductive film 120A is deposited on the insulating film 130A (see Figures 24A to 24D). Preferably, at least the conductive film 120A is formed in contact with the insulating film 130A located inside the aperture 290 with a large aspect ratio. For this reason, the conductive film 120A is preferably deposited using a deposition method with good embedding properties, such as the ALD method or the CVD method. For example, titanium nitride can be deposited using the thermal ALD method.

[0355] Here, the deposition of the conductive film 120A is preferably carried out by a method that heats the substrate, such as the thermal ALD method. For example, the film may be deposited when the substrate temperature is above room temperature, preferably above 300°C, more preferably above 325°C, and even more preferably above 350°C. Alternatively, the film may be deposited when the substrate temperature is below 500°C, preferably below 450°C. For example, the substrate temperature may be set to around 400°C.

[0356] By forming the conductive film 120A within the temperature range described above, the ferroelectricity of the insulator 130 can be increased without performing a high-temperature bake treatment after the formation of the capacitive element 100. This makes it possible to easily manufacture ferroelectric capacitors and improve the productivity of semiconductor devices.

[0357] Next, a conductive film 120B is deposited on the conductive film 120A (see Figures 24A to 24D). Preferably, the conductive film 120B is deposited so as to fill the opening 290. For this reason, it is preferable to deposit the conductive film 120B using a deposition method that provides good filling properties, such as the ALD method or the CVD method. For example, tungsten can be deposited using the metal CVD method.

[0358] In this way, by forming conductive films 120A and 120B, the upper electrode of the capacitive element 100 can be provided in the opening 290 with good embedding properties, thereby increasing the capacitance of the capacitive element 100.

[0359] Next, the conductive film 120A, the conductive film 120B, and the insulating film 130A are processed by lithography to form the conductor 120a, the conductor 120b, and the insulator 130 (see Figures 3A to 3D). Alternatively, the insulating film 130A may be left as is without being processed into the insulator 130. Furthermore, the conductor 120 may be formed so that the portion above the insulator 285 functions as wiring, or a conductor functioning as wiring may be formed in a layer above the conductor 120. Also, in the lithography method described above, the height of the upper surface of the region of the insulator 285 that overlaps with the insulator 130 may be higher than the height of the upper surface of the region that does not overlap with the insulator 130.

[0360] Based on the above, a semiconductor device having the transistor 200 and the capacitive element 100 shown in Figures 3A to 3D can be fabricated.

[0361] As shown in Figures 9A to 20D, a transistor 200 can be fabricated using the semiconductor device fabrication method described in this embodiment.

[0362] <Microwave Processing Equipment> The following describes a microwave processing apparatus that can be used in the manufacturing method of the semiconductor device described above.

[0363] First, we will explain the configuration of a manufacturing equipment that minimizes the inclusion of impurities during the manufacturing of semiconductor devices and other equipment, using Figures 25 to 28.

[0364] Figure 25 schematically shows a top view of a single-wafer multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 includes an atmospheric substrate supply chamber 2701 equipped with a cassette port 2761 for housing substrates and an alignment port 2762 for aligning substrates; an atmospheric substrate transport chamber 2702 for transporting substrates from the atmospheric substrate supply chamber 2701; a load lock chamber 2703a for loading substrates and switching the pressure inside the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure; an unload lock chamber 2703b for unloading substrates and switching the pressure inside the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure; a transport chamber 2704 for transporting substrates in a vacuum; and chambers 2706a, 2706b, 2706c, and 2706d.

[0365] Furthermore, the atmospheric substrate transport chamber 2702 is connected to the load lock chamber 2703a and the unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to the transport chamber 2704, and the transport chamber 2704 is connected to chambers 2706a, 2706b, 2706c, and 2706d.

[0366] Furthermore, gate valves GV are provided at the connection points of each chamber, and each chamber can be independently maintained in a vacuum state, except for the atmospheric substrate supply chamber 2701 and the atmospheric substrate transport chamber 2702. In addition, a transport robot 2763a is provided in the atmospheric substrate transport chamber 2702, and a transport robot 2763b is provided in the transport chamber 2704. Transport robots 2763a and 2763b can transport substrates within the manufacturing apparatus 2700.

[0367] The back pressure (total pressure) in the transport chamber 2704 and each chamber is, for example, 1 × 10⁻⁶ -4 Pa or less, preferably 3 × 10 -5 Pa or less, more preferably 1 × 10⁻⁶ -5 The pressure shall be less than or equal to Pa. Furthermore, the partial pressure of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 18 in the transport chamber 2704 and each chamber shall be, for example, 3 × 10⁻⁶. -5Pa or less, preferably 1 × 10⁻⁶ -5 Pa or less, more preferably 3 × 10 -6 The pressure shall be less than or equal to Pa. Furthermore, the partial pressure of gas molecules (atoms) with an m / z of 28 in the transport chamber 2704 and each chamber shall be, for example, 3 × 10⁻⁶. -5 Pa or less, preferably 1 × 10⁻⁶ -5 Pa or less, more preferably 3 × 10 -6 The pressure shall be less than or equal to Pa. Furthermore, the partial pressure of gas molecules (atoms) with an m / z of 44 in the transport chamber 2704 and each chamber shall be, for example, 3 × 10⁻⁶. -5 Pa or less, preferably 1 × 10⁻⁶ -5 Pa or less, more preferably 3 × 10 -6 It should be Pa or less.

[0368] The total pressure and partial pressure in the transport chamber 2704 and each chamber can be measured using a mass spectrometer. For example, a quadrupole mass spectrometer (also known as Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc. can be used.

[0369] Furthermore, it is desirable that the transport chamber 2704 and each chamber be configured to minimize external or internal leaks. For example, the leak rate of the transport chamber 2704 and each chamber should be 3 × 10⁻⁶. -6 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 The rate should be less than or equal to / s. Also, for example, the leak rate of a gas molecule (atom) with m / z 18 is 1 × 10⁻⁶. -7 Pa·m 3 / s or less, preferably 3 × 10 -8 Pa·m 3 The rate should be less than or equal to / s. Also, for example, the leak rate of a gas molecule (atom) with m / z 28 is 1 × 10⁻⁶. -5 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 The rate should be less than or equal to / s. Also, for example, the leak rate of a gas molecule (atom) with m / z 44 is 3 × 10⁻⁶. -6 Pa·m 3 / s or less, preferably 1 × 10 -6Pa·m 3 Set to / s or less.

[0370] The leak rate can be derived from the total pressure and partial pressure measured using the mass spectrometer mentioned above. The leak rate depends on both external and internal leaks. External leaks are caused by gas flowing in from outside the vacuum system through tiny holes, faulty seals, etc. Internal leaks are caused by leakage from valves or other partitions within the vacuum system, or by gas release from internal components. To keep the leak rate below the values ​​mentioned above, countermeasures must be taken from both external and internal leaks.

[0371] For example, the opening and closing parts of the conveying chamber 2704 and each chamber may be sealed with metal gaskets. Preferably, the metal gaskets are made of metal coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets offer better adhesion than O-rings, reducing external leakage. Furthermore, using a passivated metal coated with iron fluoride, aluminum oxide, or chromium oxide suppresses the release of impurity-containing gases from the metal gasket, thereby reducing internal leakage.

[0372] Furthermore, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which emit less impurity-containing gas, are used as components of the manufacturing apparatus 2700. Alternatively, the aforementioned metals that emit less impurity-containing gas may be used as a coating on an alloy containing iron, chromium, and nickel. Alloys containing iron, chromium, and nickel are rigid, heat-resistant, and suitable for processing. Here, reducing the surface area by reducing surface irregularities of the components through polishing or other means can reduce the emission of gas.

[0373] Alternatively, the components of the aforementioned manufacturing apparatus 2700 may be coated with iron fluoride, aluminum oxide, chromium oxide, or the like.

[0374] The components of the manufacturing apparatus 2700 are preferably made of metal as much as possible. For example, when installing viewing windows made of quartz or the like, it is advisable to thinly coat the surface with iron fluoride, aluminum oxide, chromium oxide, etc., to suppress the release of gases.

[0375] The adsorbed substances present in the transport chamber 2704 and each chamber do not affect the pressure in the transport chamber 2704 and each chamber because they are adsorbed onto the inner walls, but they cause gas release when the transport chamber 2704 and each chamber are evacuated. Therefore, although there is no correlation between the leak rate and the exhaust rate, it is important to use a pump with high exhaust capacity to desorb as much of the adsorbed substances present in the transport chamber 2704 and each chamber as possible and evacuate them in advance. In addition, the transport chamber 2704 and each chamber may be baked to promote the desorption of adsorbed substances. Baking can increase the desorption rate of adsorbed substances by about 10 times. Baking should be performed at a temperature between 100°C and 450°C. At this time, if the adsorbed substances are removed while introducing an inert gas into the transport chamber 2704 and each chamber, the desorption rate of water and other substances that are difficult to desorb by exhaust alone can be further increased. In addition, the desorption rate of adsorbed substances can be further increased by heating the introduced inert gas to approximately the same temperature as the baking temperature. It is preferable to use a noble gas as the inert gas here.

[0376] Alternatively, it is preferable to increase the pressure in the transport chamber 2704 and each chamber by introducing an inert gas such as a heated noble gas or oxygen, and then exhaust the transport chamber 2704 and each chamber again after a certain period of time. By introducing a heated gas, adsorbed substances can be removed from the transport chamber 2704 and each chamber, thereby reducing the amount of impurities present in the transport chamber 2704 and each chamber. This process is most effective when repeated 2 to 30 times, preferably 5 to 15 times. Specifically, the pressure in the transport chamber 2704 and each chamber can be increased to 0.1 Pa to 10 kPa, preferably 1 Pa to 1 kPa, and more preferably 5 Pa to 100 Pa by introducing an inert gas or oxygen with a temperature of 40°C to 400°C, preferably 50°C to 200°C, and the pressure can be maintained for 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. Subsequently, the transport chamber 2704 and each chamber are evacuated for a period of 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes.

[0377] Next, chambers 2706b and 2706c will be described using the schematic cross-sectional diagrams shown in Figure 26.

[0378] Chambers 2706b and 2706c are chambers capable of performing microwave processing on an object to be processed. The only difference between chambers 2706b and 2706c is the atmosphere used during microwave processing. Other configurations are common to both chambers, and will therefore be described together below.

[0379] Chambers 2706b and 2706c each have a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. Outside of chambers 2706b and 2706c, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high-frequency power supply 2816, a vacuum pump 2817, and a valve 2818.

[0380] The high-frequency generator 2803 is connected to the mode converter 2805 via a waveguide 2804. The mode converter 2805 is connected to the slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 is positioned in contact with the dielectric plate 2809. The gas supply source 2801 is connected to the mode converter 2805 via a valve 2802. Gas is then supplied to chambers 2706b and 2706c through a gas pipe 2806 that passes through the mode converter 2805, waveguide 2807, and dielectric plate 2809. The vacuum pump 2817 has the function of exhausting gas and other substances from chambers 2706b and 2706c via a valve 2818 and an exhaust port 2819. The high-frequency power supply 2816 is connected to the substrate holder 2812 via a matching box 2815.

[0381] The substrate holder 2812 has the function of holding the substrate 2811. For example, it has the function of electrostatically or mechanically chucking the substrate 2811. It also functions as an electrode to which power is supplied from the high-frequency power supply 2816. It also has an internal heating mechanism 2813 and has the function of heating the substrate 2811.

[0382] As the vacuum pump 2817, for example, a dry pump, mechanical booster pump, ion pump, titanium sublimation pump, cryopump, or turbomolecular pump can be used. In addition to the vacuum pump 2817, a cryotrap may also be used. Using a cryopump and cryotrap is particularly preferable because it allows for efficient water removal.

[0383] Furthermore, the heating mechanism 2813 may be, for example, a heating mechanism that uses a resistance heating element. Alternatively, it may be a heating mechanism that heats by heat conduction or thermal radiation from a heated medium such as a gas. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA performs heat treatment using a high-temperature gas. An inert gas is used as the gas.

[0384] Furthermore, the gas supply source 2801 may be connected to the purifier via a mass flow controller. It is preferable to use a gas with a dew point of -80°C or lower, preferably -100°C or lower. For example, oxygen gas, nitrogen gas, and noble gases (such as argon gas) may be used.

[0385] For example, silicon oxide (quartz), aluminum oxide (alumina), or yttrium oxide (yttria) may be used as the dielectric plate 2809. Furthermore, another protective layer may be formed on the surface of the dielectric plate 2809. The protective layer may be made of magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide. Since the dielectric plate 2809 will be exposed to particularly high-density regions of the high-density plasma 2810 described later, providing a protective layer can mitigate damage. As a result, an increase in particles during processing can be suppressed.

[0386] The high-frequency generator 2803 has the function of generating microwaves in frequencies such as 0.3 GHz to 3.0 GHz, 0.7 GHz to 1.1 GHz, or 2.2 GHz to 2.8 GHz. The microwaves generated by the high-frequency generator 2803 are transmitted to the mode converter 2805 via the waveguide 2804. In the mode converter 2805, the microwaves transmitted as TE mode are converted to TEM mode. The microwaves are then transmitted to the slot antenna plate 2808 via the waveguide 2807. The slot antenna plate 2808 is provided with multiple slot holes, and the microwaves pass through these slot holes and the dielectric plate 2809. This generates an electric field below the dielectric plate 2809, thereby generating a high-density plasma 2810. The high-density plasma 2810 contains ions and radicals depending on the type of gas supplied from the gas supply source 2801. For example, oxygen radicals are present.

[0387] At this time, the substrate 2811 can be modified by ions and radicals generated in the high-density plasma 2810, which can alter films and other structures on the substrate 2811. It is preferable to apply a bias to the substrate 2811 using a high-frequency power supply 2816. For example, an RF (Radio Frequency) power supply with frequencies such as 13.56 MHz or 27.12 MHz can be used as the high-frequency power supply 2816. By applying a bias to the substrate, ions in the high-density plasma 2810 can efficiently reach deep into the openings of films and other structures on the substrate 2811.

[0388] For example, oxygen radical treatment using high-density plasma 2810 can be performed by introducing oxygen from gas supply source 2801 in chamber 2706b or chamber 2706c.

[0389] Next, chambers 2706a and 2706d will be described using the schematic cross-sectional diagrams shown in Figure 27.

[0390] Chambers 2706a and 2706d are chambers capable of irradiating the workpiece with electromagnetic waves, for example. The only difference between chambers 2706a and 2706d is the type of electromagnetic wave they emit. Since many other components are common to both, they will be described together below.

[0391] Chambers 2706a and 2706d each have one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust port 2830. Outside of chambers 2706a and 2706d, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided.

[0392] The gas supply source 2821 is connected to the gas inlet 2823 via valve 2822. The vacuum pump 2828 is connected to the exhaust port 2830 via valve 2829. The lamp 2820 is positioned opposite the substrate holder 2825. The substrate holder 2825 has the function of holding the substrate 2824. The substrate holder 2825 also has an internal heating mechanism 2826 that has the function of heating the substrate 2824.

[0393] For lamp 2820, for example, a light source having the function of emitting electromagnetic waves such as visible light or ultraviolet light may be used. For example, a light source having the function of emitting electromagnetic waves with peaks in wavelengths of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm may be used.

[0394] For example, lamp 2820 can be a light source such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp.

[0395] For example, electromagnetic waves emitted from the lamp 2820 can be partially or entirely absorbed by the substrate 2824, thereby modifying the film on the substrate 2824. For example, defects can be created or reduced, or impurities can be removed. Furthermore, if the substrate 2824 is heated during the process, the creation or reduction of defects or the removal of impurities can be performed more efficiently.

[0396] Alternatively, for example, the substrate holder 2825 may be heated by electromagnetic waves emitted from the lamp 2820, thereby heating the substrate 2824. In this case, the substrate holder 2825 does not need to have a heating mechanism 2826 inside.

[0397] For vacuum pump 2828, refer to the description for vacuum pump 2817. For heating mechanism 2826, refer to the description for heating mechanism 2813. For gas supply source 2821, refer to the description for gas supply source 2801.

[0398] The microwave processing apparatus that can be used in this embodiment is not limited to the one described above. The microwave processing apparatus 2900 shown in Figure 28 can be used. The microwave processing apparatus 2900 has a quartz tube 2901, an exhaust port 2819, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a gas pipe 2806, a vacuum pump 2817, and a valve 2818. The microwave processing apparatus 2900 also has a substrate holder 2902 inside the quartz tube 2901 that holds a plurality of substrates 2811 (2811_1 to 2811_n, where n is an integer of 2 or more). The microwave processing apparatus 2900 may also have a heating means 2903 on the outside of the quartz tube 2901.

[0399] Microwaves generated by the high-frequency generator 2803 are irradiated onto a substrate placed inside the quartz tube 2901 via the waveguide 2804. The vacuum pump 2817 is connected to the exhaust port 2819 via the valve 2818, and can adjust the pressure inside the quartz tube 2901. The gas supply source 2801 is connected to the gas pipe 2806 via the valve 2802, and can introduce a desired gas into the quartz tube 2901. The heating means 2903 can heat the substrate 2811 inside the quartz tube 2901 to a desired temperature. Alternatively, the heating means 2903 may heat the gas supplied from the gas supply source 2801. The microwave processing device 2900 can perform heating and microwave processing on the substrate 2811 simultaneously. Alternatively, the substrate 2811 can be heated first, followed by microwave processing, or the substrate 2811 can be microwaved first, followed by heating.

[0400] Substrates 2811_1 to 2811_n may all be processing substrates forming semiconductor devices or memory devices, or some of the substrates may be dummy substrates. For example, substrates 2811_1 and 2811_n may be dummy substrates, and substrates 2811_2 to 2811_n-1 may be processing substrates. Alternatively, substrates 2811_1, 2811_2, 2811_n-1, and 2811_n may be dummy substrates, and substrates 2811_3 to 2811_n-2 may be processing substrates. Using dummy substrates is preferable because it allows multiple processing substrates to be processed uniformly during microwave processing or heat processing, reducing variations between processing substrates. For example, it is preferable to place dummy substrates on the processing substrates closest to the high-frequency generator 2803 and waveguide 2804, as this suppresses direct exposure of the processing substrates to microwaves.

[0401] By using the above manufacturing equipment, it becomes possible to modify the film while suppressing the inclusion of impurities in the processed material.

[0402] <Modified examples of semiconductor devices> In the following section, an example of a semiconductor device according to one aspect of the present invention will be described using Figures 6A to 8B.

[0403] Figure A shows a top view of a semiconductor device. Figure B shows a cross-sectional view corresponding to the area indicated by the dashed line A1-A2 in Figure A. Some elements have been omitted from the top view of Figure A for clarity.

[0404] In the semiconductor devices shown in Figures A and B, the same reference numerals are used to denote structures that have the same function as those shown in <Examples of Semiconductor Device Configurations>. Furthermore, the materials used for the semiconductor devices in this section may be those described in detail in <Examples of Semiconductor Device Configurations>.

[0405] <Example 1 of a semiconductor device> The semiconductor devices shown in Figures 6A and 6B are modified versions of the semiconductor devices shown in Figures 3A to 3D. The semiconductor devices shown in Figures 6A and 6B differ from those shown in Figures 3A to 3D in that they are provided with conductors 240 and 246. Here, conductor 240 functions as a plug electrically connected to either the source or drain of transistor 200, and conductor 246 functions as wiring connected to said plug.

[0406] The conductor 240 is provided to fill the openings formed in the insulators 271, 275, 280, 282, 283, and 285. The lower surface of the conductor 240 is in contact with the upper surface of the conductor 242a. It is preferable that the conductor 240 be made of a conductive material mainly composed of tungsten, copper, or aluminum. Alternatively, the conductor 240 may have a laminated structure consisting of a thin first conductor provided along the side and bottom surfaces of the openings and a second conductor on the first conductor.

[0407] When the conductor 240 has a laminated structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the first conductor placed near the insulators 285 and 280. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminate. In addition, it is possible to suppress the mixing of impurities such as water and hydrogen contained in the layer above the insulator 283 into the oxide 230 through the conductor 240. As for the second conductor, conductive materials mainly composed of tungsten, copper, or aluminum as described above may be used.

[0408] Although Figure 6B shows a configuration in which the conductor 240 consists of a first conductor and a second conductor stacked together, the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or as a stacked structure of three or more layers.

[0409] Furthermore, the conductor 246 may be placed in contact with the upper surface of the conductor 240. It is preferable that the conductor 246 be made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 246 may also be in a laminated structure, for example, a laminate of titanium or titanium nitride and the above conductive material. As shown in Figure 6B, in the insulator 285, the height of the upper surface of the region overlapping with the conductor 246 may be higher than the height of the upper surface of the region not overlapping with the conductor 246. The conductor 246 may also be formed to be embedded in an opening provided in the insulator.

[0410] Furthermore, it is preferable that an insulator 241, which functions as a barrier insulating film, is provided between the conductor 240 and the insulator 280. It is preferable that the insulator 245 is positioned in contact with the sides of the openings formed in insulators 271, 275, 280, 282, 283, and 285. It is preferable that the insulator 241 has the same structure as the insulator 245 described above.

[0411] In this modified example, an insulator 286 is provided covering the conductor 246 and the insulator 285. The insulator 286 may be formed using an insulating material that can be used for the insulator 285.

[0412] This modified configuration involves forming the conductor 240, conductor 246, and insulator 286, and then forming the capacitive element 100. Therefore, unlike the semiconductor devices shown in Figures 3A to 3D, a portion of the lower surface of the insulator 130 and a portion of the side surface of the insulator 245 are in contact with the insulator 286. In other words, the opening into which the capacitive element 100 is embedded is deeper, corresponding to the thickness of the insulator 286. This allows for an increase in the capacitance of the capacitive element 100 without increasing the occupied area of ​​the semiconductor device.

[0413] <Modified example of a semiconductor device 2> The semiconductor device shown in Figures 7A and 7B is a modified version of the semiconductor device shown in Figures 6A and 6B. Similar to the semiconductor device shown in Figures 6A and 6B, the semiconductor device shown in Figures 7A and 7B has an insulator 241a, a conductor 240a, and a conductor 246a on the conductor 242a. Furthermore, the conductor 120 has an insulator 241b, a conductor 240b, and a conductor 246b. Here, the conductor 240b functions as a plug electrically connected to one of the terminals of the capacitive element 100, and the conductor 246b functions as wiring connected to the plug.

[0414] Furthermore, the same conductive material as the above-described insulator 241 can be used for insulators 241a and 241b. Also, the same conductive material as the above-described conductor 240 can be used for conductors 240a and 240b. In addition, the same conductive material as the above-described conductor 246b can be used for conductors 246a and 246b.

[0415] However, unlike the semiconductor devices shown in Figures 6A and 6B, the semiconductor devices shown in Figures 7A and 7B are configured such that the conductors 240a and 240b are formed after the capacitive element 100 has been formed. As a result, the lower surfaces of the conductors 246a and 246b are in contact with the upper surface of the insulator 285 that is formed covering the conductor 120.

[0416] Unlike the semiconductor devices shown in Figures 3A to 3D, the semiconductor devices shown in Figures 7A and 7B do not have an interlayer insulating film between the insulator 283 and the insulator 130, and the lower surface of the insulator 130 and the upper surface of the insulator 283 are in contact.

[0417] <Modified example of semiconductor device 3> The semiconductor device shown in Figures 8A and 8B is a modified version of the semiconductor device shown in Figures 7A and 7B. The semiconductor device shown in Figures 8A and 8B differs from the semiconductor device shown in Figures 7A and 7B in that the insulator 283 is in contact with a part of the upper surface of the insulator 212. Therefore, the transistor 200 is placed within the region sealed by the insulator 283 and the insulator 212. This configuration makes it possible to suppress the mixing of hydrogen contained outside the sealed region into the sealed region. Furthermore, although the transistor 200 shown in Figures 8A and 8B shows a configuration in which the insulator 212 and the insulator 283 are provided as single layers, the present invention is not limited to this. For example, the insulator 212 and the insulator 283 may each be provided as a stacked structure of two or more layers.

[0418] <Examples of semiconductor device applications> Below, an example of a semiconductor device according to one aspect of the present invention will be described using Figure 29.

[0419] Figure 29A shows a top view of the semiconductor device 500. In Figure 29A, the x-axis is taken parallel to the channel length direction of the transistor 200, and the y-axis is taken perpendicular to the x-axis. Figure 29B is a cross-sectional view corresponding to the area indicated by the dashed line A1-A2 in Figure 29A, and is also a cross-sectional view of the transistor 200 in the channel length direction. Figure 29C is a cross-sectional view corresponding to the area indicated by the dashed line A3-A4 in Figure 29A, and is also a cross-sectional view of the aperture region 400 and its vicinity. Note that some elements have been omitted from the top view of Figure 29A for clarity.

[0420] In the semiconductor devices shown in Figures 29A to 29C, structures having the same function as those constituting the semiconductor devices shown in <Example of Semiconductor Device Configuration> are denoted by the same reference numerals. Furthermore, in this section as well, the materials used for the semiconductor devices are those described in detail in <Example of Semiconductor Device Configuration>.

[0421] The semiconductor device 500 shown in Figures 29A to 29C is a modified example of the semiconductor device shown in Figures 3A to 3D. The semiconductor device 500 shown in Figures 29A to 29C differs from the semiconductor device shown in Figures 3A to 3D in that an opening region 400 is formed in the insulator 282 and the insulator 280. It also differs from the semiconductor device shown in Figures 3A to 3D in that a sealing portion 265 is formed to surround the plurality of transistors 200 and capacitive elements 100.

[0422] The semiconductor device 500 has a plurality of transistors 200, a plurality of capacitive elements 100, and a plurality of aperture regions 400 arranged in a matrix. A plurality of conductors 260, which function as gate electrodes for the transistors 200, are provided extending in the y-axis direction. The aperture regions 400 are formed in areas that do not overlap with the oxide 230 and the conductors 260. Furthermore, a sealing portion 265 is formed to surround the plurality of transistors 200, a plurality of capacitive elements 100, a plurality of conductors 260, and a plurality of aperture regions 400. Note that the number, arrangement, and size of the transistors 200, capacitive elements 100, conductors 260, and aperture regions 400 are not limited to the structure shown in Figure 29, but can be appropriately set according to the design of the semiconductor device 500.

[0423] As shown in Figures 29B and 29C, the sealing portion 265 is provided so as to surround the multiple transistors 200, insulators 216, 222, 275, 280, and 282. In other words, insulator 283 is provided so as to cover insulators 216, 222, 275, 280, and 282. In the sealing portion 265, insulator 283 is in contact with the upper surface of insulator 214. Also in the sealing portion 265, insulator 274 is provided between insulator 283 and insulator 285. The upper surface of insulator 274 is approximately the same height as the uppermost surface of insulator 283. Furthermore, the same type of insulator as insulator 280 can be used for insulator 274.

[0424] This structure allows multiple transistors 200 to be enclosed by insulators 283, 214, and 212. Here, it is preferable that one or more of insulators 283, 214, and 212 function as a barrier insulating film against hydrogen. This prevents hydrogen contained outside the sealing portion 265 from mixing into the sealing portion 265.

[0425] As shown in Figure 29C, the insulator 282 has an opening in the opening region 400. In addition, the insulator 280 may have a groove that overlaps the opening of the insulator 282 in the opening region 400. The depth of the groove in the insulator 280 should not be too deep, except to the point where the upper surface of the insulator 275 is exposed. For example, it should be about 1 / 4 to 1 / 2 of the maximum film thickness of the insulator 280.

[0426] Furthermore, as shown in Figure 29C, the insulator 283 is in contact with the side surface of the insulator 282, the side surface of the insulator 280, and the upper surface of the insulator 280 inside the opening region 400. In addition, a portion of the insulator 274 may be formed within the opening region 400 to fill in the recess formed in the insulator 283. In this case, the height of the upper surface of the insulator 274 formed within the opening region 400 and the uppermost surface of the insulator 283 may be approximately the same.

[0427] With such an opening region 400 formed and the insulator 280 exposed through the opening in the insulator 282, heat treatment can be performed to supply oxygen to the oxide 230 while diffusing some of the oxygen contained in the insulator 280 outward from the opening region 400. This ensures that sufficient oxygen is supplied from the insulator 280 containing oxygen that is released by heating to the region in the oxide semiconductor that functions as a channel-forming region and its vicinity, while preventing the supply of an excessive amount of oxygen.

[0428] At this time, the hydrogen contained in the insulator 280 can combine with oxygen and be released to the outside through the opening region 400. The hydrogen combined with oxygen is released as water. Therefore, the amount of hydrogen contained in the insulator 280 can be reduced, and the mixing of hydrogen contained in the insulator 280 into the oxide 230 can be reduced.

[0429] Furthermore, although the shape of the aperture region 400 in a top view in Figure 29A is approximately rectangular, the present invention is not limited to this. For example, the shape of the aperture region 400 in a top view may be rectangular, elliptical, circular, rhombus, or a combination thereof. In addition, the area and spacing of the aperture region 400 can be appropriately set according to the design of the semiconductor device including the transistors 200. For example, in areas where the density of transistors 200 is low, the area of ​​the aperture region 400 can be increased or the spacing of the aperture region 400 can be decreased. Conversely, in areas where the density of transistors 200 is high, the area of ​​the aperture region 400 can be decreased or the spacing of the aperture region 400 can be increased.

[0430] According to one aspect of the present invention, a novel transistor can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with less variation in transistor characteristics can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with high on-current can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with high field-effect mobility can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with good frequency characteristics can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided.

[0431] Furthermore, according to one aspect of the present invention, a capacitive element containing a material that may have ferroelectric properties can be provided. Alternatively, according to one aspect of the present invention, the above-mentioned capacitive element can be provided with good productivity. Alternatively, according to one aspect of the present invention, a semiconductor device having the above-mentioned capacitive element and a transistor can be provided. Alternatively, according to one aspect of the present invention, the above-mentioned semiconductor device that can be miniaturized or highly integrated can be provided.

[0432] The configurations and methods described in this embodiment can be implemented by appropriately combining at least a part thereof with other embodiments and examples described herein.

[0433] (Embodiment 2) In this embodiment, a method for manufacturing a capacitive element according to one aspect of the present invention will be described with reference to Figures 1A to 1C.

[0434] As shown in Figure 1A, a conductive film 110 is deposited on a substrate (not shown). The conductive film 110 can be deposited using sputtering, CVD, MBE, PLD, ALD, etc. By depositing the conductive film 110 using the ALD method, it is sometimes possible to deposit a conductive film with good flatness relatively easily. For example, titanium nitride can be deposited using thermal ALD. The conductive film 110 can also be patterned as appropriate using lithography or the like.

[0435] Next, as shown in Figure 1B, an insulator 130 is deposited on the conductor 110. The insulator 130 can be deposited using sputtering, CVD, ALD, or other methods. For example, by depositing the film using the ALD method, the insulator 130 can be deposited on the conductor 110 with good coverage. This makes it possible to suppress the generation of leakage current between the upper and lower electrodes of the capacitive element 100.

[0436] It is preferable to use a material that can exhibit ferroelectric properties for the insulator 130. Examples of materials that can exhibit ferroelectric properties include hafnium oxide, zirconium oxide, and HfZrO xExamples include materials obtained by adding element J1 (where element J1 is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to hafnium oxide, and materials obtained by adding element J2 (where element J2 is hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to zirconium oxide. In addition, PbTiO is an example of a material that may possess ferroelectric properties. x Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may be used. Furthermore, as a material capable of ferroelectricity, for example, a mixture or compound containing multiple materials selected from the materials listed above can be used. Alternatively, the insulator 130 can be a laminated structure composed of multiple materials selected from the materials listed above.

[0437] Among the materials that can possess ferroelectric properties, hafnium oxide, or materials containing both hafnium oxide and zirconium oxide, are preferred because they can exhibit ferroelectric properties even when processed into thin films of a few nanometers. Here, the film thickness of the insulator 130 can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less (typically 2 nm to 9 nm). By thinning the insulator 130, the capacitive element 100 can be combined with the miniaturized transistor 200 to form a semiconductor device.

[0438] Here, we will explain the crystal structure of hafnium oxide, one of the materials that can be used for the insulator 130, using Figure 2. Figure 2 is a model diagram illustrating the crystal structure of hafnium oxide (HfO2 in this embodiment). Hafnium oxide is known to take on a variety of crystal structures, for example, it can take on crystal structures such as cubic (space group: Fm-3m), tetragonal (space group: P42 / nmc), orthorhombic (space group: Pbc22), and monoclinic (space group: P21 / c), as shown in Figure 2. Furthermore, as shown in Figure 2, each of the above crystal structures can undergo a phase change. For example, by doping hafnium oxide with zirconium to create a composite material, the monoclinic crystal structure of hafnium oxide can be changed to an orthorhombic crystal structure.

[0439] When the above-mentioned composite material is formed by alternately depositing hafnium oxide and zirconium oxide in a 1:1 composition using the ALD method, the composite material has an orthorhombic crystal structure. Alternatively, the composite material has an amorphous structure. Subsequently, by applying heat treatment or the like to the composite material, the amorphous structure can be converted into an orthorhombic crystal structure. Note that the orthorhombic crystal structure may change to a monoclinic crystal structure. When imparting ferroelectricity to the above-mentioned composite material, an orthorhombic crystal structure is preferred over a monoclinic crystal structure.

[0440] The crystal structure of the insulator 130 is not particularly limited. The crystal structure of the insulator 130 may be one or more selected from cubic, tetragonal, orthorhombic, and monoclinic systems. In particular, an orthorhombic crystal structure is preferred for the insulator 130 because it exhibits ferroelectric properties. Alternatively, the crystal structure of the insulator 130 may be amorphous. Or, the insulator 130 may have a composite structure having both an amorphous structure and a crystalline structure.

[0441] As insulator 130, a material having hafnium oxide and zirconium oxide (HfZrO xWhen using ), it is preferable to deposit the film using the thermal ALD method.

[0442] Furthermore, when forming the insulator 130 using the thermal ALD method, it is preferable to use a material that does not contain hydrocarbons (also called Hydrocarbon, HC) as a precursor. If the insulator 130 contains either hydrogen or carbon, or both, it may inhibit the crystallization of the insulator 130. For this reason, as described above, it is preferable to reduce the concentration of either hydrogen or carbon, or both, in the insulator 130 by using a hydrocarbon-free precursor. For example, chlorine-based materials can be used as hydrocarbon-free precursors. Note that the insulator 130 may be a material having hafnium oxide and zirconium oxide (HfZrO x When using ), HfCl4 and / or ZrCl4 can be used as precursors.

[0443] Furthermore, when forming the insulator 130 using the thermal ALD method, H2O or O3 can be used as the oxidizing agent. In the thermal ALD method, using O3 is preferable to using H2O because it reduces the hydrogen concentration in the film. However, the oxidizing agent for the thermal ALD method is not limited to these. For example, the oxidizing agent for the thermal ALD method may include one or more selected from O2, O3, N2O, NO2, H2O, and H2O2.

[0444] Next, as shown in Figure 1C, a conductive film 120 is formed on the insulator 130. Here, the conductive film 120 is arranged at a distance from the conductive film 110 via the insulator 130. As shown in the previous embodiment, the conductive film 120 may have a laminated structure consisting of a conductive film 120a provided in contact with the insulator 130 and a conductive film 120b provided in contact with the conductive film 120a.

[0445] The conductor 120a can be deposited using methods such as ALD or CVD. For example, titanium nitride can be deposited using the thermal ALD method. Here, the deposition of the conductor 120a is preferably carried out by heating the substrate, as in the thermal ALD method. For example, the substrate temperature can be set to room temperature or higher, preferably 300°C or higher, more preferably 325°C or higher, and even more preferably 350°C or higher for deposition. Alternatively, the substrate temperature can be set to 500°C or lower, preferably 450°C or lower for deposition. For example, the substrate temperature can be set to around 400°C.

[0446] By forming the conductor 120a within the temperature range described above, ferroelectric properties can be imparted to the insulator 130 without performing a high-temperature bake treatment (for example, a bake treatment at a heat treatment temperature of 400°C or higher or 500°C or higher) after the formation of the conductor 120a.

[0447] Furthermore, by depositing the conductor 120a using the ALD method, which causes relatively little damage to the substrate as described above, it is possible to suppress excessive destruction of the crystal structure of the insulator 130, thereby increasing the ferroelectric properties of the insulator 130.

[0448] For example, when forming the conductor 120a by a sputtering method, there is a possibility that the underlying film, in this case the insulator 130, may be damaged. For example, if the insulator 130 is a material having hafnium oxide and zirconium oxide (HfZrO x When forming the conductor 120a by sputtering using ), the underlayer HfZrO x Damage is dealt to HfZrO x The crystal structure (typically orthorhombic crystal structure, etc.) may be disrupted. Therefore, it is preferable to deposit the conductive film 120a using the ALD method, which causes relatively little damage to the substrate.

[0449] Furthermore, after depositing the conductive film 120a by sputtering, heat treatment is performed to obtain HfZrO x It can also repair damage to the crystal structure.

[0450] Here, HfZrO x The dangling bond inside (for example, O * ) and HfZrO x It combines with the hydrogen contained within, HfZrO x Damage in the crystal structure of HfZrO may not be repairable. x The dangling bond inside is formed, for example, by damage caused by the sputtering method used to deposit the conductive material 120a.

[0451] Therefore, insulator 130, in this case HfZrO x It is preferable to use materials that do not contain hydrogen or have an extremely low hydrogen content. For example, the hydrogen concentration in the insulator 130 is 5 × 10⁻⁶. 20 atoms / cm 3 The following is preferable: 1 × 10 20 atoms / cm 3 The following are preferable.

[0452] Furthermore, as described above, in order to reduce the hydrogen concentration in the insulator 130, it is preferable to use a hydrocarbon-free material as a precursor. As a result, the insulator 130 may be a film that does not contain hydrocarbons as its main component, or has an extremely low hydrocarbon content. For example, the concentration of carbon constituting the hydrocarbons contained in the insulator 130 is preferably 5 × 10⁻⁶. 20 atoms / cm 3 More preferably 1 × 10 20 atoms / cm 3 The following applies.

[0453] Furthermore, when a hydrocarbon-free material is used as a precursor for forming the insulator 130, the insulator 130 may be a film that does not contain carbon as its main component, or has an extremely low carbon content. For example, the carbon concentration in the insulator 130 is preferably 5 × 10⁻¹⁶. 20 atoms / cm 3 More preferably 1 × 10 20 atoms / cm 3 The following applies.

[0454] Furthermore, it is preferable to use a material for the insulator 130 that has an extremely low content of at least one of hydrogen, hydrocarbons, and carbon, but it is especially important to drastically reduce the content of hydrocarbons and carbon. Since hydrocarbons and carbon are heavier molecules or atoms than hydrogen, they are difficult to remove in subsequent processes. Therefore, it is preferable to thoroughly eliminate hydrocarbons and carbon during the film formation of the insulator 130.

[0455] As described above, by using a material for the insulator 130 that does not contain at least one of hydrogen, hydrocarbons, and carbon, or has an extremely low content of at least one of hydrogen, hydrocarbons, and carbon, it is possible to improve the crystallinity of the insulator 130 and create a structure with high ferroelectricity.

[0456] As described above, by thoroughly removing impurities in the insulator 130 film, specifically at least one of hydrogen, hydrocarbons, and carbon, a film with high purity intrinsic ferroelectricity, or in this case, a high purity intrinsic capacitive element, can be formed. Furthermore, the manufacturing process of the high purity intrinsic ferroelectric capacitive element and the high purity intrinsic oxide semiconductor shown in Embodiment 1 are highly compatible. Therefore, a method for manufacturing semiconductor devices with high productivity can be provided.

[0457] As described above, in one embodiment of the present invention, for example, a ferroelectric material is formed as an insulator 130 using a thermal ALD method with a hydrocarbon-free precursor (typically a chlorine-based precursor) and an oxidizing agent (typically O3). Subsequently, a conductor 120a is formed by film deposition using the thermal ALD method (typically at a temperature of 400°C or higher), thereby improving the crystallinity or ferroelectricity of the insulator 130 without post-deposition annealing, or in other words, by utilizing the temperature at which the conductor 120a was deposited. Note that improving the crystallinity or ferroelectricity of the insulator 130 by utilizing the temperature at which the conductor 120a was deposited, without performing post-deposition annealing of the conductor 120a, is sometimes referred to as self-annealing.

[0458] The conductive material 120b can be deposited using methods such as sputtering, ALD, or CVD. For example, tungsten can be deposited using the metal CVD method.

[0459] As described above, a capacitive element 100 having an insulator 130 between a conductor 110 and a conductor 120, as shown in Figure 1C, can be manufactured. As described above, the capacitive element 100 according to this embodiment can enhance the ferroelectricity of the insulator 130 without performing a high-temperature bake treatment after the formation of the conductor 120a. This reduces the manufacturing process for ferroelectric capacitors, thereby improving the productivity of ferroelectric capacitors and semiconductor devices containing them.

[0460] According to one aspect of the present invention, a capacitive element containing a material capable of ferroelectricity can be provided. Alternatively, according to one aspect of the present invention, the above-mentioned capacitive element can be provided with good productivity. Alternatively, according to one aspect of the present invention, a capacitive element that can be miniaturized or highly integrated can be provided.

[0461] The configurations and methods described in this embodiment can be implemented by appropriately combining at least a part thereof with other embodiments and examples described herein.

[0462] (Embodiment 3) In this embodiment, one form of a semiconductor device will be described with reference to Figure 30.

[0463] [Example of a storage device configuration] Figure 30 shows an example of a semiconductor device (memory device) according to one aspect of the present invention. In the semiconductor device according to one aspect of the present invention, the transistor 200 is provided above the transistor 300, and the capacitive element 100 is provided above both the transistor 300 and the transistor 200. The transistor 200 can be the same as the transistor 200 described in the previous embodiment. Similarly, the capacitive element 100 can be the same as the capacitive element 100 described in the previous embodiment. Although Figure 30 shows an example using the capacitive element 100 and transistor 200 shown in Figure 6, the present invention is not limited thereto, and the capacitive element 100 and transistor 200 can be appropriately selected.

[0464] The capacitive element 100 is made of a ferroelectric material that exhibits properties such as polarization occurring internally when an external electric field is applied, and the polarization remaining even when the electric field is removed. This allows for the formation of a non-volatile memory element using the capacitive element 100. In other words, a 1-transistor, 1-capacitor type ferroelectric memory can be formed using a capacitive element that functions as a ferroelectric capacitor and a transistor 200.

[0465] Transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Transistor 200 has the characteristic of high voltage resistance. Therefore, by using an oxide semiconductor in transistor 200, a high voltage can be applied to transistor 200 even when transistor 200 is miniaturized. By miniaturizing transistor 200, the occupied area of ​​the semiconductor device can be reduced.

[0466] In the semiconductor device shown in Figure 30, wire 1001 is electrically connected to the source of transistor 300, and wire 1002 is electrically connected to the drain of transistor 300. Additionally, wire 1003 is electrically connected to either the source or drain of transistor 200, wire 1004 is electrically connected to the first gate of transistor 200, wire 1005 is electrically connected to one of the electrodes of capacitive element 100, wire 1006 is electrically connected to the second gate of transistor 200, and wire 1007 is electrically connected to the gate of transistor 300.

[0467] Furthermore, the memory devices shown in Figure 30 can be arranged in a matrix to form a memory cell array.

[0468] <Transistor 300> The transistor 300 is provided on a substrate 311 and has a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or drain region. The transistor 300 may be either a p-channel type or an n-channel type.

[0469] In Figure 30, the transistor 300 has a convex shape in the semiconductor region 313 (part of the substrate 311) where the channel is formed. Furthermore, the sides and top surface of the semiconductor region 313 are covered by a conductor 316 via an insulator 315. The conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. It may also have an insulator in contact with the top of the convex portion, functioning as a mask for forming the convex portion. While this example shows the formation of the convex portion by processing a part of the semiconductor substrate, a semiconductor film with a convex shape may also be formed by processing an SOI substrate.

[0470] Note that the transistor 300 shown in Figure 30 is just one example, and its structure is not limited to that; any appropriate transistor can be used depending on the circuit configuration or driving method.

[0471] <Wiring layer> A wiring layer containing interlayer films, wiring, and plugs may be provided between each structure. Furthermore, multiple wiring layers may be provided depending on the design. Here, a conductor functioning as a plug or wiring may be grouped together and assigned the same reference numeral. Also, in this specification, the wiring and the plug that electrically connects to the wiring may be an integrated unit. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug.

[0472] For example, on the transistor 300, insulators 320, 322, 324, and 326 are sequentially stacked as interlayer films. Insulators 320, 322, 324, and 326 also have embedded conductive elements such as conductors 328 and 330 that are electrically connected to the capacitive element 100 or the transistor 200. Conductors 328 and 330 function as plugs or wiring.

[0473] Furthermore, the insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape beneath it. For example, the upper surface of the insulator 322 may be planarized by a planarizing treatment such as chemical mechanical polishing (CMP) to improve its flatness.

[0474] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Figure 30, insulators 350, 352, and 354 are stacked in order. Conductors 356 are formed on insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring.

[0475] Similarly, insulators 210, 212, 214, and 216 have conductors 218 and conductors constituting the transistor 200 (back gate of transistor 200) embedded within them. Conductor 218 functions as a plug or wiring that electrically connects to the capacitive element 100 or the transistor 300.

[0476] Here, similar to the insulator 241 shown in the above embodiment, an insulator 217 is provided in contact with the side surface of the conductor 218, which functions as a plug. The insulator 217 is provided in contact with the inner wall of the opening formed in the insulators 210, 212, 214, and 216. In other words, the insulator 217 is provided between the conductor 218 and the insulators 210, 212, 214, and 216. Note that the conductor 205 can be formed in parallel with the conductor 218, so the insulator 217 may also be formed in contact with the side surface of the conductor 205.

[0477] As the insulator 217, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used. Since the insulator 217 is provided in contact with insulators 210, 212, 214, and 222, it is possible to suppress the mixing of impurities such as water or hydrogen from insulators 210 or 216 into the oxide 230 through the conductor 218. Silicon nitride is particularly suitable because it has high blocking properties for hydrogen. In addition, it is possible to prevent oxygen contained in insulators 210 or 216 from being absorbed by the conductor 218.

[0478] The insulator 217 can be formed in the same manner as the insulator 241. For example, silicon nitride can be deposited using the PEALD method, and an opening reaching the conductor 356 can be formed using anisotropic etching.

[0479] Furthermore, on the transistor 200, a conductor 112 is provided on top of the insulator 285 and the conductor 240. The conductor 112 functions as a plug or wiring that electrically connects to the transistor 200 or the transistor 300. An insulator 286 is provided covering the insulator 285 and the conductor 112. An insulator 150 is provided covering the insulator 286 and the capacitive element 100.

[0480] Alternatively, a barrier insulating film against hydrogen may be provided by covering the insulator 285 and the conductor 112. As shown in Figure 30, it is preferable to provide an insulator 152a covering the insulator 285 and the conductor 112, and an insulator 152b on the insulator 152a as the barrier insulating film against hydrogen. As the insulator 152a and insulator 152b, any barrier insulating film that can be used for the insulator 283 etc. described above may be used. By providing such insulators 152a and insulators 152b, it is possible to reduce the diffusion of impurities such as hydrogen contained in the insulator 286 etc. into the transistor 200 via the conductor 112 and the conductor 240.

[0481] The insulator 152a can be deposited using the sputtering method. For example, silicon nitride deposited by the sputtering method can be used as the insulator 152a. Since the sputtering method does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration of the insulator 152a can be reduced. In this way, by reducing the hydrogen concentration of the insulator 152a in contact with the conductor 112 and the insulator 285, the diffusion of hydrogen from the insulator 152a to the conductor 112 and the insulator 285 can be suppressed.

[0482] The insulator 152b is preferably deposited using the ALD method, particularly the PEALD method. For example, silicon nitride deposited by the PEALD method can be used as the insulator 152b. This allows the insulator 152b to be deposited with good coverage, so even if pinholes or stepped defects are formed in the insulator 152a due to irregularities in the substrate, covering them with the insulator 152b reduces the diffusion of hydrogen into the conductor 112 and the insulator 285.

[0483] However, the film deposition method for insulators 152a and 152b is not limited to sputtering and ALD; CVD, MBE, PLD, etc., can also be used as appropriate. Furthermore, although a two-layer structure of insulators 152a and 152b is shown above, the present invention is not limited to this, and a single-layer structure or a laminated structure of three or more layers may also be used.

[0484] Furthermore, insulators 283 and 212 may also be multilayer barrier insulating films, similar to insulators 152a and 152b.

[0485] Alternatively, a similar configuration may be used to provide a barrier insulating film against hydrogen by covering the insulator 286 and the capacitive element 100. As shown in Figure 30, it is preferable to provide an insulator 154a covering the insulator 286 and the capacitive element 100, and an insulator 154b on the insulator 154a as the barrier insulating film against hydrogen. The insulator 154a can be made of the same barrier insulating film as the insulator 152a, and the insulator 154b can be made of the same barrier insulating film as the insulator 152b. By providing such insulators 154a and 154b, it is possible to reduce the diffusion of impurities such as hydrogen contained in the insulator 150, etc., into the transistor 200 via the capacitive element 100.

[0486] Insulators that can be used as interlayer films include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0487] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0488] For example, it is preferable that insulators 150, 210, 352, and 354 have an insulator with a low dielectric constant. For example, it is preferable that the insulator has fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, porous silicon oxide, or a resin. Alternatively, it is preferable that the insulator has a laminated structure of silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide, and a resin. Since silicon oxide and silicon oxynitride are thermally stable, combining them with a resin can create a thermally stable laminated structure with a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, or acrylic.

[0489] Furthermore, the electrical characteristics of a transistor using an oxide semiconductor can be stabilized by surrounding it with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, insulators 214, 212, and 350 should be insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen.

[0490] As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon nitride or silicon nitride, etc., can be used.

[0491] Conductors that can be used for wiring and plugs may include materials containing one or more metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0492] For example, conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials can be used as conductors 328, 330, 356, 218, and 112, either in a single layer or in a laminated form. It is preferable to use high-melting-point materials such as tungsten or molybdenum that provide both heat resistance and conductivity, and tungsten is preferable. Alternatively, it is preferable to form them with low-resistance conductive materials such as aluminum or copper. Using low-resistance conductive materials can reduce wiring resistance. Furthermore, as shown in the above embodiment, the ferroelectricity of the insulator 130 can be increased without performing high-temperature baking after formation by forming the conductor 120a using a method involving substrate heating, such as thermal ALD. Therefore, semiconductor devices can be manufactured without high-temperature baking, and low-resistance conductive materials such as copper with a low melting point can be used.

[0493] <Wiring or plugs in layers containing oxide semiconductors> Furthermore, when an oxide semiconductor is used in the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, it is preferable to provide a barrier insulator between the insulator having the excess oxygen region and the conductor provided on the insulator having the excess oxygen region.

[0494] For example, in Figure 30, an insulator 241 may be provided between the insulators 224 and 280, which have excess oxygen, and the conductor 240. By providing the insulator 241 in contact with the insulators 222, 282, and 283, the insulator 224 and the transistor 200 can be sealed by the barrier insulator.

[0495] In other words, by providing the insulator 241, it is possible to suppress the absorption of excess oxygen present in the insulators 224 and 280 into the conductor 240. Furthermore, by having the insulator 241, it is possible to suppress the diffusion of hydrogen, which is an impurity, into the transistor 200 via the conductor 240.

[0496] Furthermore, as the insulator 241, an insulating material having the function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen, is preferable. For example, silicon nitride, silicon oxide nitride, aluminum oxide, or hafnium oxide are preferred. Silicon nitride is particularly preferred because of its high blocking properties for hydrogen. In addition, other materials such as metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide can also be used.

[0497] Furthermore, as shown in the above embodiment, the transistor 200 may be configured to be sealed with insulators 212, 214, 282, and 283. With such a configuration, it is possible to reduce the amount of hydrogen contained in insulators 274, 285, 150, etc., that mixes into insulator 280, etc.

[0498] Here, the conductor 240 penetrates insulators 283 and 282, and the conductor 218 penetrates insulators 214 and 212. However, as described above, insulator 241 is provided in contact with conductor 240, and insulator 217 is provided in contact with conductor 218. This reduces the amount of hydrogen that enters the inside of insulators 212, 214, 282, and 283 via conductors 240 and 218. In this way, the transistor 200 is sealed with insulators 212, 214, 282, 283, 241, and 217, reducing the amount of impurities such as hydrogen contained in insulator 274, etc., that enter from the outside. In Figure 30, one transistor 200 is shown within the region sealed by the insulator 212 and the insulator 283, but the design is not limited to this, and multiple transistors 200 can be provided within the sealed region.

[0499] <Dicing line> The following describes dicing lines (sometimes called scribe lines, division lines, or cutting lines) that are provided when extracting multiple semiconductor devices as chips by dividing a large-area substrate into individual semiconductor elements. One method of division is to first form grooves (dicing lines) in the substrate to divide the semiconductor elements, and then cut along the dicing lines to divide (divide) the substrate into multiple semiconductor devices.

[0500] Here, for example, as shown in Figure 30, it is preferable to design the region where insulator 283 and insulator 214 are in contact to overlap with the dicing line. In other words, openings are provided in insulators 282, 280, 275, 222, and 216 near the region that will become the dicing line provided on the outer edge of the memory cell having multiple transistors 200.

[0501] In other words, in the openings provided in insulators 282, 280, 275, 222, and 216, insulator 214 and insulator 283 are in contact.

[0502] Furthermore, for example, openings may be provided in insulators 282, 280, 275, 222, 216, and 214. With this configuration, insulator 212 and insulator 283 come into contact at the openings provided in insulators 282, 280, 275, 222, 216, and 214. In this case, insulators 212 and 283 may be formed using the same material and method. By forming insulators 212 and 283 using the same material and method, adhesion can be improved. For example, silicon nitride is preferable.

[0503] This structure allows the transistor 200 to be enclosed by insulators 212, 214, 282, and 283. Since at least one of insulators 212, 214, 282, and 283 has the function of suppressing the diffusion of oxygen, hydrogen, and water, even if the substrate is divided into multiple chips for each circuit region on which the semiconductor element shown in this embodiment is formed, it is possible to prevent impurities such as hydrogen or water from entering from the side of the divided substrate and diffusing into the transistor 200.

[0504] Furthermore, this structure prevents excess oxygen from insulators 280 and 224 from diffusing to the outside. Therefore, excess oxygen from insulators 280 and 224 is efficiently supplied to the oxide in which the channel in transistor 200 is formed. This oxygen reduces oxygen deficiencies in the oxide in which the channel in transistor 200 is formed. As a result, the oxide in which the channel in transistor 200 is formed can be made into an oxide semiconductor with a low defect level density and stable properties. In other words, fluctuations in the electrical properties of transistor 200 can be suppressed and reliability can be improved.

[0505] <Example 1 of a memory device> In the memory device shown in Figure 30, the capacitive element 100 is formed so as to be embedded in the insulator 285 and the insulator 280, but the present invention is not limited to this. As shown in Figure 31, the planar type capacitive element 100 may be provided on top of the insulator 285.

[0506] The capacitive element 100 includes a conductor 110, an insulator 130 covering the conductor 110, and a conductor 120 (conductor 120a and conductor 120b) covering the insulator 130. Here, it is preferable that the insulator 130 covers the top and side surfaces of the conductor 110 and separates the conductor 110 and the conductor 120. Details of the conductor 110, the insulator 130, and the conductor 120 can be found in the [Example of Memory Device Configuration] and the description of the previous embodiment.

[0507] The conductor 110 is formed in the same layer as the conductor 112 and is in contact with the upper surface of the conductor 240. The conductor 110 is electrically connected to either the source or the drain of the transistor 200 via the conductor 240.

[0508] Furthermore, it is preferable that an insulator 155 is provided covering the conductor 120, the insulator 130, and the conductor 112. It is preferable that the insulator 155 is an insulator having the function of capturing and fixing hydrogen, which can be used for insulators 214 or 282, etc. For example, it is preferable to use aluminum oxide. By providing such an insulator 155 so as to cover the capacitive element 100, hydrogen contained in the insulator 130 of the capacitive element 100 can be captured and fixed, and the hydrogen concentration in the insulator 130 can be reduced. This can increase the ferroelectricity of the insulator 130. In addition, the leakage current between the conductor 110 and the conductor 120 can be reduced. However, the configuration is not limited to this, and a configuration without an insulator 155 may also be used.

[0509] Furthermore, similar to the memory device shown in Figure 30, it is preferable to provide insulators 152a and 152b on the conductor 112 and conductor 120, which function as barrier insulating films against hydrogen. Insulators 152a and 152b are provided on insulator 155. By providing such insulators 152a and 152b, it is possible to reduce the diffusion of impurities such as hydrogen contained in the insulator 286 on insulator 152b to the transistor 200 via the capacitive element 100, conductor 112, and conductor 240.

[0510] Furthermore, as shown in Figure 31, it is preferable to provide an insulator 287 on top of the insulator 285, which functions as a barrier insulating film against hydrogen. Conductors 112, 110, and 155 are provided in contact with the insulator 287. Here, the insulator 287 can be a barrier insulating film similar to that of the insulator 283.

[0511] With this configuration, insulator 155 and insulator 287 are in contact in the region that does not overlap with the capacitive element 100. In other words, the capacitive element 100 is sealed by insulator 155, insulator 152a and insulator 152b and insulator 287. If insulator 155 is not used, insulator 287 and insulator 152a are in contact in the region that does not overlap with the capacitive element 100, and the capacitive element 100 is sealed by insulator 152a and insulator 152b and insulator 287. This suppresses the diffusion of hydrogen from outside insulator 152b and insulator 287 to the capacitive element 100, and the hydrogen concentration of the capacitive element 100 can be reduced. Thus, the ferroelectricity of insulator 130 can be increased.

[0512] Furthermore, as shown in Figure 31, the transistor 200 is also sealed with insulators 283, 214, and 212, which function as barrier insulating films against hydrogen. This suppresses the diffusion of hydrogen from outside insulators 283 and 212 into the transistor 200, thereby reducing the hydrogen concentration in the oxide semiconductor film of the transistor 200. Thus, the electrical characteristics and reliability of the transistor 200 can be improved.

[0513] <Modified Memory Device 2> In the memory device shown in Figure 31, the transistor 200 and the capacitive element 100 are individually sealed with a hydrogen barrier insulating film, but the present invention is not limited to this. As shown in Figure 32, the transistor 200 and the capacitive element 100 may be sealed together with a hydrogen barrier insulating film (insulator 212, insulator 152a, and insulator 152b).

[0514] In the storage device shown in Figure 32, insulators 214, 216, 222, 275, 280, 282, 283, 285, and 155 have openings that reach insulator 212. Insulators 152a and 152b on insulator 155 are formed along the side and bottom surfaces of the opening. Insulator 152a contacts the top surface of insulator 212 at the bottom surface of the opening.

[0515] This configuration allows the transistor 200 and the capacitive element 100 to be sealed together with insulators 212, 152a, and 152b. This suppresses the diffusion of hydrogen from outside insulators 212 and 152b to the capacitive element 100 and the transistor 200, thereby reducing the hydrogen concentration in the insulator 130 of the capacitive element 100 and the oxide semiconductor film of the transistor 200. As a result, the ferroelectricity of insulator 130 is increased, improving the electrical characteristics and reliability of the transistor 200.

[0516] <Modification example 3 of the memory device> The memory device shown in Figure 32 has a capacitive element 100 placed on top of a transistor 200, but the present invention is not limited to this. As shown in Figure 33, the capacitive element 100 may be placed on the same layer as the transistor 200.

[0517] As shown in Figure 33, it is preferable that the conductor 110, which functions as the lower electrode of the capacitive element 100, is formed of the same layer of conductor as the conductor 205, which functions as the back gate of the transistor 200. An insulator 130 is placed on top of the conductor 110, and a conductor 120 (conductor 120a and conductor 120b) is placed on top of the insulator 130. Here, it is preferable that the insulator 130 covers the upper surface of the conductor 110 and separates the conductor 110 and the conductor 120. The insulator 130 and the conductor 120 may have the same configuration as shown in Figure 31, etc., and details can be found in the [Example of Memory Device Configuration] and the previous embodiments. An insulator 222 is placed over the insulator 130 and the conductor 120.

[0518] A conductor 240 is provided in contact with the upper surface of conductor 120b, and a conductor 112 is provided in contact with the upper surface of conductor 240. Conductor 112 is in contact with conductor 240, which is electrically connected to one of the source and drain of transistor 200. In other words, conductor 120, which functions as the upper electrode of the capacitive element 100 shown in Figure 33, is electrically connected to one of the source and drain of transistor 200. Conductor 110, which functions as the lower electrode of the capacitive element 100, is electrically connected to wiring 1005.

[0519] Furthermore, similar to the memory device shown in Figure 32, the transistor 200 and the capacitive element 100 can be sealed together with insulators 212, 152a, and 152b. This suppresses the diffusion of hydrogen from outside insulators 212 and 152b to the capacitive element 100 and the transistor 200, thereby reducing the hydrogen concentration in the insulator 130 of the capacitive element 100 and the oxide semiconductor film of the transistor 200. As a result, the ferroelectricity of insulator 130 can be increased, improving the electrical characteristics and reliability of the transistor 200.

[0520] <Modification of memory device 4> The memory device shown in Figure 31 and other figures has a configuration in which a transistor 200 is placed on a transistor 300 and a capacitive element 100 is connected to the transistor 200, but the present invention is not limited to this. As shown in Figure 34A, the device may be configured in which the capacitive element 100 is connected to the transistor 300 without providing a transistor 200.

[0521] As shown in Figure 34A, openings are formed in insulators 320, 322, and 287 that reach the low-resistance region 314a of the transistor 300, and a conductor 357 is formed to fill these openings. Conductors 357 can be the same type of conductor as conductor 328, etc. The upper surface of the conductor 357 is in contact with the lower surface of the conductor 110 of the capacitive element 100. In this way, the conductor 110, which functions as the lower electrode of the capacitive element 100, and the low-resistance region 314a, which functions as one of the source and drain of the transistor 300, are connected via the conductor 357. The configuration of the transistor 300, the capacitive element 100, and the layers containing them is the same as the configuration shown in Figure 31, and the description relating to the configuration shown in Figure 31 can be referenced.

[0522] Furthermore, in the memory device shown in Figure 34A, similar to the memory device shown in Figure 31, the capacitive element 100 can be sealed with insulators 287, 152a, and 152b. This suppresses the diffusion of hydrogen from outside insulators 287 and 152b into the capacitive element 100, and reduces the hydrogen concentration of the oxide semiconductor film of the insulator 130 of the capacitive element 100. Thus, the ferroelectricity of the insulator 130 can be increased.

[0523] Furthermore, in the configuration shown in Figure 34A, the low-resistance region 314a of the transistor 300 and the conductor 110 of the capacitive element 100 are directly connected by a conductor 357, but the present invention is not limited to this. Multiple wiring layers, as shown in Figure 31 and others, may be provided between the capacitive element 100 and the transistor 300. For example, as shown in Figure 34B, a conductor 328 may be formed on the transistor 300, a conductor 330 on the conductor 328, a conductor 356 on the conductor 330, and a conductor 357 on the conductor 356. The low-resistance region 314a of the transistor 300 and the conductor 110 of the capacitive element 100 are electrically connected by conductors 328, 330, 356, and 357. Note that the conductors 328, 330, 356, and the wiring layers including them can be referenced from the description in [Example of Memory Device Configuration].

[0524] Figure 31 and others show a configuration in which the transistor 200 is connected to a capacitive element 100 containing a material that may have ferroelectric properties, but the present invention is not limited to this. For example, the transistor 200 and the insulator provided around it may be made of a material that may have ferroelectric properties. A transistor with such a configuration will be explained using Figures 35A to 35C. Note that the transistor 200 shown in Figures 35A to 35C is the same as the transistor 200 shown in Figure 3, but instead of the capacitive element 100, it is provided with conductors 240a, conductors 240b, conductors 246a, conductors 246b, insulators 241a, and insulators 241b.

[0525] The transistor 200 shown in Figure 35A uses insulator 130a instead of insulator 222. Insulator 130a can be made of a material that has the same ferroelectric properties as insulator 130. In other words, the transistor 200 shown in Figure 35A uses a material that has ferroelectric properties as the second gate insulator.

[0526] The transistor 200 shown in Figure 35B uses insulator 130b instead of insulators 252, 250, and 254. Insulator 130b can be made of a material that has ferroelectric properties similar to insulator 130. In other words, the transistor 200 shown in Figure 35B uses a material that can have ferroelectric properties as the first gate insulator. Note that in Figure 35B, all of the first gate insulators are made of ferroelectric materials, but the present invention is not limited to this. For example, the configuration shown in Figure 4B may use a material that can have ferroelectric properties for one or more of the insulators 252, 250a, 250b, and 254.

[0527] In the transistor 200 shown in Figure 35C, an insulator 130c is provided on a conductor 260, and a conductor 262 is provided on the insulator 130c. The insulator 130c can be made of a material that has the same ferroelectric properties as the insulator 130. The conductor 262 can be made of a conductive material that can be used for the conductor 260. An insulator 282 is provided covering the insulator 130c and the conductor 262. The semiconductor device shown in Figure 35C can also be viewed as having one terminal of a ferroelectric capacitor provided on the gate electrode of the transistor 200.

[0528] The configurations and methods described in this embodiment can be implemented by appropriately combining at least a part thereof with other embodiments and examples described herein.

[0529] (Embodiment 4) In this embodiment, a memory device to which an oxide-based transistor (hereinafter sometimes referred to as an OS transistor) and a ferroelectric capacitor are applied, according to one aspect of the present invention, will be described with reference to Figures 36A and 36B. The device according to this embodiment is a memory device having at least a capacitive element and an OS transistor that controls the charging and discharging of the capacitive element. The device according to this embodiment functions as a one-transistor, one-capacitor type ferroelectric memory using a ferroelectric capacitor.

[0530] <Example of storage device configuration> Figure 36A shows an example of the configuration of a storage device. The storage device 1400 has peripheral circuits 1411 and a memory cell array 1470. The peripheral circuits 1411 have row circuits 1420, column circuits 1430, output circuits 1440, and control logic circuits 1460.

[0531] The column circuit 1430 includes, for example, a column decoder, a bit line driver circuit, a precharge circuit, a sense amplifier, a write circuit, etc. The precharge circuit has the function of precharging the wiring. The sense amplifier has the function of amplifying the data signal read from the memory cell. The above wiring is the wiring connected to the memory cells of the memory cell array 1470, which will be described in more detail later. The amplified data signal is output to the outside of the storage device 1400 as the data signal RDATA via the output circuit 1440. The row circuit 1420 includes, for example, a row decoder, a word line driver circuit, etc., and can select the row to access.

[0532] The memory device 1400 is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 from an external source. The memory device 1400 also receives control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA from an external source. The address signal ADDR is input to the row decoder and column decoder, and the data signal WDATA is input to the write circuit.

[0533] The control logic circuit 1460 processes externally input control signals (CE, WE, RE) to generate control signals for the row decoder and column decoder. Control signal CE is the chip enable signal, control signal WE is the write enable signal, and control signal RE is the read enable signal. The signals processed by the control logic circuit 1460 are not limited to these; other control signals may be input as needed.

[0534] The memory cell array 1470 has multiple memory cells MC arranged in a matrix and multiple wirings. The number of wirings connecting the memory cell array 1470 to the row circuit 1420 is determined by the configuration of the memory cells MC and the number of memory cells MC in each row. Similarly, the number of wirings connecting the memory cell array 1470 to the column circuit 1430 is determined by the configuration of the memory cells MC and the number of memory cells MC in each row.

[0535] Although Figure 36A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, this embodiment is not limited to this. For example, as shown in Figure 36B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470.

[0536] The configuration of the peripheral circuit 1411, memory cell array 1470, etc., as shown in this embodiment is not limited to the above. The arrangement or function of these circuits, and the wiring, circuit elements, etc. connected to them, may be changed, deleted, or added as necessary. A storage device according to one aspect of the present invention has a high operating speed and can retain data for a long period of time.

[0537] <Example of memory cell configuration> Figure 37A shows an example of the configuration of the memory cell MC described above. The memory cell MC has a transistor Tr and a capacitor Fe. Here, as the memory cell MC, a semiconductor device having a transistor 200 and a capacitor element 100 as shown in the previous embodiment can be used. In this case, transistor Tr corresponds to transistor 200, and capacitor Fe corresponds to capacitor element 100. Note that transistor Tr may or may not have a back gate in addition to a gate. Also, although transistor Tr is shown as an n-channel transistor in Figure 37A, it may also be a p-channel transistor.

[0538] One of the sources or drains of transistor Tr is electrically connected to wiring BL. The other of the sources or drains of transistor Tr is electrically connected to one electrode of capacitor Fe. The gate of transistor Tr is electrically connected to wiring WL. The other electrode of capacitor Fe is electrically connected to wiring PL.

[0539] Wiring WL functions as a word line, and the on / off state of transistor Tr can be controlled by controlling the potential of wiring WL. For example, by setting the potential of wiring WL to a high potential, transistor Tr can be turned on, and by setting the potential of wiring WL to a low potential, transistor Tr can be turned off. Wiring WL is electrically connected to the word line driver circuit of row circuit 1420, and the potential of wiring WL can be controlled by the word line driver circuit.

[0540] Wiring BL functions as a bit line, and when transistor Tr is ON, a potential corresponding to the potential of wiring BL is supplied to one electrode of capacitor Fe. Wiring BL is electrically connected to the bit line driver circuit of column circuit 1430. The bit line driver circuit has the function of generating data to be written to memory cell MC. The bit line driver circuit also has the function of reading data output from memory cell MC. Specifically, a sense amplifier is provided in the bit line driver circuit, and data output from memory cell MC can be read using the sense amplifier.

[0541] The wiring PL functions as a plate wire, and the potential of the wiring PL can be set to the potential of the other electrode of the capacitance Fe.

[0542] It is preferable to use an OS transistor as the transistor Tr. OS transistors have the characteristic of high voltage resistance. Therefore, by using an OS transistor as the transistor Tr, a high voltage can be applied to the transistor Tr even when the transistor Tr is miniaturized. By miniaturizing the transistor Tr, the occupied area of ​​the memory cell MC can be reduced. For example, the occupied area of ​​one memory cell MC shown in Figure 37A can be 1 / 3 to 1 / 6 of the occupied area of ​​one SRAM cell. Therefore, memory cells MC can be arranged at high density. As a result, the memory device according to one aspect of the present invention can be a memory device with a large storage capacity.

[0543] Capacitive Fe has a dielectric layer between its two electrodes, which is made of a material that can exhibit ferroelectric properties. Hereafter, the dielectric layer of capacitive Fe will be referred to as the ferroelectric layer.

[0544] As a material capable of ferroelectricity, any material that can be used for the insulator 130 described above may be used. Among these, hafnium oxide, or materials containing both hafnium oxide and zirconium oxide, are pre...

Claims

1. A transistor is formed on a first insulator, A second insulator is formed having a region located above a first conductor that functions as one of the source and drain of the transistor, and a region located above a second conductor that functions as the other of the source and drain of the transistor. A third insulator is formed having a region that contacts the upper surface of a third conductor that functions as the gate of the transistor, and a region that contacts the upper surface of the second insulator. A fourth insulator is formed having a region in contact with the upper surface of the third insulator, a region in contact with the side surface of the third insulator, a region in contact with the side surface of the second insulator, and a region in contact with the upper surface of the first insulator. An opening is formed in the second to fourth insulators that reaches the first conductor. Using the ALD method, a fifth insulator having a region in contact with the inner wall of the opening is formed. A fourth conductor is formed using the ALD method, having a region in contact with the fifth insulator and a region in contact with the upper surface of the first conductor. A ferroelectric layer is formed on the fourth conductor. While heating, a fifth conductor is formed on the ferroelectric layer. A sixth conductor is formed on the fifth conductor, The fourth insulator has silicon nitride, The ferroelectric layer comprises hafnium oxide and zirconium oxide. The precursor used in forming the ferroelectric layer does not contain hydrocarbons. The ferroelectric layer has a region located above the fourth insulator, a region facing the inner wall of the opening via the fourth conductor and the fifth insulator, and a region facing the upper surface of the first conductor via the fourth conductor. A method for manufacturing a semiconductor device, wherein each of the fifth conductor and the sixth conductor has a region located above the fourth insulator via the ferroelectric layer, a region facing the inner wall of the opening via the ferroelectric layer, the fourth conductor and the fifth insulator, and a region facing the upper surface of the first conductor via the ferroelectric layer and the fourth conductor.

2. In claim 1, The ferroelectric layer is formed using the thermal ALD method. A method for manufacturing a semiconductor device, wherein no heat treatment of 500°C or higher is performed after the formation of the fifth conductor.

3. In claim 1 or 2, A method for fabricating a semiconductor device, wherein the fifth conductor is formed using a thermal ALD method.

4. In claim 3, The precursor used in the formation of the fifth conductor is a method for manufacturing a semiconductor device that does not contain hydrocarbons.

5. In any one of claims 1 to 4, A method for manufacturing a semiconductor device, wherein the temperature at which the substrate is heated is 350°C or higher and 450°C or lower.

6. In any one of claims 1 to 5, A method for fabricating a semiconductor device, wherein the channel formation region of the transistor has an oxide semiconductor containing In, Ga, and Zn.

7. In any one of claims 1 to 5, A method for fabricating a semiconductor device, wherein the channel formation region of the transistor has indium oxide.

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