Semiconductor equipment

Abstract

This semiconductor device is provided with: a cell region in which a plurality of cells are formed; and an outer peripheral region which surrounds the cell region. The cell region is provided with: an insulating film which covers the plurality of cells; and an electrode part which has a superposition part that is superposed on the insulating film. The outer peripheral region is provided with a first semiconductor layer, a second semiconductor region, an outer peripheral insulating film, an outer peripheral electrode part, a barrier layer and a passivation film. The outer peripheral insulating film covers the surface of the first semiconductor layer and the surface of the second semiconductor region, while having an opening part from which a part of the surface of the second semiconductor region is exposed. The outer peripheral electrode part has a projection part which is superposed on the outer peripheral insulating film, while being in contact with a part of the surface of the second semiconductor region, said part being exposed from the opening part. The barrier layer covers both the outer peripheral insulating film and the outer peripheral electrode part, while having a smaller diffusion coefficient than the outer peripheral insulating film. The passivation film is superposed on the barrier layer, while having a larger diffusion coefficient than the barrier layer. The thickness of the projection part is thinner than the thickness of the superposition part.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices.

Background Art

[0002] For example, in semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) used in in - vehicle inverter devices, it is known to form a protective film on an electrode (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, when an organic protective film such as polyimide is used as the protective film, there is a risk that external ions may pass through the protective film.

Means for Solving the Problems

[0005] The semiconductor device that solves the above problems includes a cell region in which a plurality of cells are formed, and an outer peripheral region provided outside the cell region so as to surround the cell region. The cell region includes an insulating film that covers the plurality of cells, and an electrode portion having a stacked portion stacked on the insulating film. The outer peripheral region includes a first semiconductor layer of a first conductivity type, a second semiconductor region of a second conductivity type partially formed in the first semiconductor layer, an outer peripheral insulating film that covers the surface of the first semiconductor layer and the surface of the second semiconductor region and has an opening that exposes a part of the surface of the second semiconductor region, a protruding portion that protrudes laterally from the opening and is stacked on the outer peripheral insulating film, an outer peripheral electrode portion that contacts a portion of the surface of the second semiconductor region exposed by the opening, a barrier layer that covers both the outer peripheral insulating film and the outer peripheral electrode portion and has a diffusion coefficient smaller than that of the outer peripheral insulating film, and a passivation film that is stacked on the barrier layer and has a diffusion coefficient larger than that of the barrier layer. The thickness of the protruding portion is thinner than the thickness of the stacked portion.

[0006] The semiconductor device that solves the above problems includes a cell region in which a plurality of cells are formed, and an outer peripheral region provided outside the cell region so as to surround the cell region. The cell region includes an insulating film that covers the plurality of cells, and an electrode portion having a stacked portion stacked on the insulating film. The outer peripheral region includes a first semiconductor layer of a first conductivity type, a second semiconductor region of a second conductivity type partially formed in the first semiconductor layer, an outer peripheral insulating film that covers the surface of the first semiconductor layer and the surface of the second semiconductor region and has an opening formed of a silicon oxide film that exposes a part of the surface of the second semiconductor region, a protruding portion that protrudes laterally from the opening and is stacked on the outer peripheral insulating film, an outer peripheral electrode portion that contacts a portion of the surface of the second semiconductor region exposed by the opening, a barrier layer that covers both the outer peripheral insulating film and the outer peripheral electrode portion and is formed of a silicon nitride film, and a passivation film that is stacked on the barrier layer and is formed of an organic insulating film. The thickness of the protruding portion is thinner than the thickness of the stacked portion.

Effect of the Invention

[0007] According to the above semiconductor device, the intrusion of external ions into the semiconductor layer can be suppressed. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a plan view of a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a plan view of the semiconductor device shown in Figure 1 with the protective film removed. [Figure 3] Figure 3 is a cross-sectional view showing an example of the cross-sectional structure of a cell region. [Figure 4] Figure 4 is a cross-sectional view showing the cross-sectional structure of the semiconductor device shown in Figure 1, as indicated by line 4-4. [Figure 5] Figure 5 is an enlarged view of a portion of the FLR section in the outer peripheral region of Figure 4. [Figure 6] Figure 6 is an enlarged view of the gate finger and emitter routing in the outer peripheral region of Figure 4. [Figure 7] Figure 7 is an enlarged view of the equipotential ring in the outer region of Figure 4. [Figure 8] Figure 8 is an explanatory diagram illustrating an example of the manufacturing process for the semiconductor device according to the first embodiment. [Figure 9] Figure 9 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 10] Figure 10 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 11] Figure 11 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 12] Figure 12 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 13] Figure 13 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 14] Figure 14 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 15] Figure 15 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 16] Figure 16 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 17] Figure 17 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 18] Figure 18 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 19] Figure 19 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 20] Figure 20 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 21] Figure 21 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 22] Figure 22 is a cross-sectional view showing the cell region structure of the semiconductor device according to the second embodiment. [Figure 23] Figure 23 is a cross-sectional view showing an example of a partial cross-sectional structure of the FLR portion in the outer peripheral region. [Figure 24] Figure 24 is an explanatory diagram illustrating an example of the manufacturing process for a semiconductor device according to the second embodiment. [Figure 25] Figure 25 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 26] Figure 26 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 27] Figure 27 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 28] Figure 28 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 29] Figure 29 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 30] Figure 30 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 31] Figure 31 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 32] Figure 32 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 33] Figure 33 is an explanatory diagram illustrating an example of a manufacturing process for semiconductor devices. [Figure 34] Figure 34 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 35] Figure 35 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 36] Figure 36 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Figure 37] Figure 37 is an explanatory diagram illustrating an example of a manufacturing process for a semiconductor device. [Modes for carrying out the invention]

[0009] The embodiments of the semiconductor device will be described below with reference to the drawings. The embodiments shown below are examples of configurations and methods for realizing the technical concept, and the materials, shapes, structures, arrangements, dimensions, etc. of each component are not limited to those described below.

[0010] [First Embodiment] The semiconductor device 10 of the first embodiment will be described with reference to Figures 1 to 21. Figures 1 to 7 show an example of the configuration of the semiconductor device 10, and Figures 8 to 21 show an example of the manufacturing process of the semiconductor device 10.

[0011] (Configuration of a semiconductor device) The configuration of the semiconductor device 10 of this embodiment will be described with reference to Figures 1 to 7. As shown in Figure 1, the semiconductor device 10 in this embodiment is a trench-gate type IGBT (Insulated Gate Bipolar Transistor). This semiconductor device 10 is used, for example, as a switching element in an in-vehicle inverter device. In this case, a current of, for example, 5A to 1000A flows through the semiconductor device 10.

[0012] As shown in Figure 1, the semiconductor device 10 is formed in the shape of a rectangular plate, for example. In this embodiment, the main surface 10s of the semiconductor device 10 is formed in the shape of a square, for example. In this embodiment, the length of one side of the main surface 10s is about 11 mm. That is, the chip size of the semiconductor device 10 in this embodiment is 11 mm square. The semiconductor device 10 has a back surface 10r (see Figure 3) facing away from the main surface 10s, and four side surfaces 10a to 10d formed between the main surface 10s and the back surface 10r. The side surfaces 10a to 10d are, for example, surfaces that connect the main surface 10s and the back surface 10r, and are perpendicular to both the main surface 10s and the back surface 10r.

[0013] In the following description, the direction in which the main surface 10s and the back surface 10r of the device face is referred to as the "z-direction." The z-direction can also be said to be the height direction of the semiconductor device 10. Two mutually orthogonal directions that are perpendicular to the z-direction are referred to as the "x-direction" and the "y-direction." In this embodiment, the side surfaces 10a and 10b of the device constitute both end surfaces in the x-direction of the semiconductor device 10, and the side surfaces 10c and 10d of the device constitute both end surfaces in the y-direction of the semiconductor device 10. For convenience, the direction from the back surface 10r of the device toward the main surface 10s of the device is referred to as "upward," and the direction from the main surface 10s of the device toward the back surface 10r of the device is referred to as "downward."

[0014] As shown in Figure 2, the semiconductor device 10 is equipped with an emitter electrode 21, a gate electrode 22, and a collector electrode 29 (see Figure 3) as external electrodes for connecting to the outside of the semiconductor device 10.

[0015] The emitter electrode 21 is an electrode that constitutes the emitter of the IGBT and is the electrode through which the main current of the semiconductor device 10 flows. The emitter electrode 21 has a recessed area 21a that is recessed in the y-direction. The recessed area 21a opens toward the side surface 10c of the device. The emitter electrode 21 is formed on the main surface 10s of the device.

[0016] The gate electrode 22 is an electrode that constitutes the gate of the IGBT, and is the electrode to which a drive voltage signal for driving the semiconductor device 10 is supplied from outside the semiconductor device 10. The gate electrode 22 is located adjacent to the emitter electrode 21 in the y-direction. The gate electrode 22 fits into the housing recess 21a of the emitter electrode 21. The gate electrode 22 is formed on the main surface 10s of the device.

[0017] The collector electrode 29 is an electrode that constitutes the collector of the IGBT, and is the electrode through which the main current of the semiconductor device 10 flows. In other words, in the semiconductor device 10, the main current flows from the collector electrode 29 to the emitter electrode 21. The collector electrode 29 is formed on the back surface 10r of the device. More specifically, the collector electrode 29 is formed over the entire back surface 10r of the device.

[0018] As shown by the dashed line in Figure 2, the semiconductor device 10 comprises a cell region 11 in which multiple cells are formed, and an outer peripheral region 12 provided outside the cell region 11 so as to surround the cell region 11. Here, "cell" refers to a main cell in which a transistor is formed. In other words, the cell region 11 includes the region in which the transistor is formed. The outer peripheral region 12 is formed on the outer periphery of the main surface 10s of the device when viewed from the z direction.

[0019] The cell region 11 includes an emitter electrode 21. The emitter electrode 21 is formed over most of the cell region 11. Viewed from the z direction, the emitter electrode 21 has a shape that conforms to the shape of the cell region 11. In this embodiment, the emitter electrode 21 corresponds to the "electrode portion".

[0020] The outer peripheral region 12 is a region where a termination structure to improve the dielectric breakdown voltage of the semiconductor device 10 is provided. The outer peripheral region 12 is the region surrounding the emitter electrode 21, excluding the region where the gate electrode 22 is formed. The gate electrode 22 is provided in the region enclosed by the cell region 11 and the outer peripheral region 12.

[0021] The outer peripheral region 12 includes a pair of gate fingers 23A, 23B, an emitter routing portion 24, an FLR (Field Limiting Ring) portion 25, and an equipotential ring 26. The emitter electrode 21, gate electrode 22, gate fingers 23A, 23B, emitter routing portion 24, FLR portion 25, and equipotential ring 26 all contain a common metal film. This metal film is formed from a material containing, for example, AlCu (an alloy of aluminum and copper). In this embodiment, the gate fingers 23A, 23B, emitter routing portion 24, FLR portion 25, and equipotential ring 26 correspond to the "outer peripheral electrode portion".

[0022] The pair of gate fingers 23A and 23B are configured to quickly supply the current supplied to the gate electrode 22 to cells in the portion of the emitter electrode 21 that is far from the gate electrode 22. The pair of gate fingers 23A and 23B are integrated with the gate electrode 22. The pair of gate fingers 23A and 23B are connected to the end of the gate electrode 22 in the y-direction that is closer to the side surface 10c of the device.

[0023] The gate finger 23A extends from the gate electrode 22 toward the device side 10a and is formed to surround the emitter electrode 21 from the device side 10c, device side 10a, and device side 10d. The gate finger 23B extends from the gate electrode 22 toward the device side 10b and is formed to surround the emitter electrode 21 from the device side 10c, device side 10b, and device side 10d. The tip of the gate finger 23A and the tip of the gate finger 23B face each other with a gap in the x direction in the portion closer to the device side 10d than the emitter electrode 21.

[0024] The emitter routing portion 24 is a part integrated with the emitter electrode 21 and is formed in an annular shape to surround the pair of gate fingers 23A and 23B. The FLR section 25 is a termination structure for improving the breakdown voltage of the semiconductor device 10 and is provided outside the emitter routing section 24. The FLR section 25 is formed in an annular shape surrounding the emitter electrode 21 and the gate electrode 22. In this embodiment, the FLR section 25 is formed to be a closed annular shape. The FLR section 25 has the function of improving the breakdown voltage of the semiconductor device 10 by mitigating the electric field in the outer peripheral region 12 and suppressing the influence of external ions.

[0025] The equipotential ring 26 is a termination structure for improving the breakdown voltage of the semiconductor device 10, and is formed in an annular shape to surround the FLR portion 25. As shown in Figure 1, the equipotential ring 26 is formed on the outermost periphery of the main surface 10s of the device. In this embodiment, the equipotential ring 26 is formed to be a closed annular shape. The equipotential ring 26 has the function of improving the breakdown voltage of the semiconductor device 10.

[0026] As shown in Figure 1, the semiconductor device 10 includes a passivation film 13 covering the emitter electrode 21, gate electrode 22, a pair of gate fingers 23A, 23B, emitter routing portion 24, FLR portion 25, and equipotential ring 26. The passivation film 13 is a protective film that protects the semiconductor device 10 from the outside. The passivation film 13 is an organic insulating film formed from a material including, for example, polyimide (PI). Since the passivation film 13 covers the pair of gate fingers 23A, 23B, emitter routing portion 24, FLR portion 25, and equipotential ring 26, it can also be said that the outer peripheral region 12 is equipped with the passivation film 13.

[0027] The passivation film 13 has a first opening 14 and a second opening 15. The first opening 14 exposes a portion of the emitter electrode 21, thereby forming an emitter electrode pad 16. The second opening 15 exposes most of the gate electrode 22, thereby forming a gate electrode pad 17. In this way, the openings 14 and 15 form pads for conductive members (not shown) from outside the semiconductor device 10 to join.

[0028] Figure 3 schematically shows an example of a cross-sectional structure of a part of the cell region 11. For convenience, in Figure 3, some hatching of components of the semiconductor device 10 in the cell region 11 has been omitted.

[0029] As shown in Figure 3, the semiconductor device 10 includes a semiconductor substrate 30. The semiconductor substrate 30 is, for example, n - It is formed from a material containing silicon (Si) of a specific type. The semiconductor substrate 30 has a thickness of, for example, 50 μm to 200 μm.

[0030] The semiconductor substrate 30 has a substrate surface 30s and a substrate back surface 30r that face opposite each other in the z-direction. In other words, the z-direction can also be said to be the thickness direction of the semiconductor substrate 30. The semiconductor substrate 30 is arranged in order from the back surface 30r of the substrate toward the front surface 30s of the substrate, p + A collector layer 31 of type n, a buffer layer 32 of type n, and n - The substrate has a structure in which a drift layer 33 of a certain type is stacked. A collector electrode 29 is formed on the back surface 30r of the substrate. The collector electrode 29 is formed over almost the entire surface of the back surface 30r of the substrate. The side of the collector electrode 29 opposite to the back surface 30r of the substrate constitutes the back surface 10r of the semiconductor device 10.

[0031] In this embodiment, the z-direction corresponds to the thickness direction of the drift layer 33. In other words, "viewed from the z-direction" can also be said as "viewed from the thickness direction of the drift layer 33." Since the drift layer 33 corresponds to the first semiconductor layer, "viewed from the z-direction" can also be said as "viewed from the first semiconductor layer."

[0032] For the p-type dopant in the collector layer 31, for example, boron (B) and aluminum (Al) are used. The impurity concentration in the collector layer 31 is, for example, 1 × 10⁻⁶. 15 cm -3 The above 2 x 10 19 cm -3 The following applies:

[0033] As examples of the n-type dopant for the buffer layer 32 and the drift layer 33, N (nitrogen), P (phosphorus), As (arsenic), etc. are used. The impurity concentration of the buffer layer 32 is, for example, 1 × 10 15 cm -3 or more and 5 × 10 17 cm -3 or less. The impurity concentration of the drift layer 33 is lower than that of the buffer layer 32, for example, 1 × 10 13 cm -3 or more and 5 × 10 14 cm -3 or less.

[0034] On the surface of the drift layer 33, that is, the substrate surface 30s, a p-type base region 34 is formed. The base region 34 is formed over substantially the entire surface of the substrate surface 30s. The impurity concentration of the base region 34 is higher than that of the drift layer 33, for example, 1 × 10 16 cm -3 or more and 1 × 10 18 cm -3 or less. The depth of the base region 34 from the substrate surface 30s is, for example, 1.0 μm or more and 4.0 μm or less.

[0035] On the surface of the base region 34 (substrate surface 30s) in the cell region 11, a plurality of trenches 35 are arranged side by side. Each trench 35 extends, for example, along the y direction and is arranged at intervals in the x direction. As a result, it is partitioned into a stripe-shaped main cell 11A. The interval between adjacent trenches 35 in the x direction (the center-to-center distance of the trenches 35) is, for example, 1.5 μm or more and 7.0 μm or less. The width of each trench 35 (the dimension of the trench 35 in the x direction) is, for example, 0.5 μm or more and 3.0 μm or less. Each trench 35 penetrates the base region 34 in the z direction and extends to the middle of the drift layer 33. Each trench 35 may be formed in a grid pattern so as to partition the main cell 11A in a matrix shape.

[0036] On the surface of the base region 34 (substrate surface 30s) in the cell region 11, n +An emitter region 36 of type 1 is formed. The emitter region 36 is located on both sides of the trench 35 in the x-direction. In other words, the emitter region 36 can be said to be located on both sides of the trench 35 in the direction of the trench 35 arrangement within the base region 34. Therefore, between adjacent trenches 35 in the x-direction, two emitter regions 36 are arranged with a gap between them in the x-direction. The depth of each emitter region 36 is, for example, 0.2 μm to 0.6 μm. Also, the impurity concentration of each emitter region 36 is higher than that of the base region 34, for example, 1 × 10⁻¹⁶. 19 cm -3 The above 5 x 10 20 cm -3 The following applies:

[0037] On the surface of the base region 34 in the cell region 11 (substrate surface 30s), p + A base contact region 37 of type 1 is formed. The base contact region 37 is located adjacent to the emitter region 36 in the x-direction. That is, the base contact region 37 is located between the x-direction of two emitter regions 36 that are located between adjacent trenches 35 in the x-direction. Each base contact region 37 may be formed deeper than the emitter region 36. The depth of each base contact region 37 is, for example, 0.2 μm or more and 1.6 μm or less. Also, the impurity concentration of each base contact region 37 is higher than that of the base region 34, for example, 5 × 10⁻¹⁶ 18 cm -3 The above 1 x 10 20 cm -3 The following applies:

[0038] An insulating film 38 is integrally formed on both the inner surface of each trench 35 and the substrate surface 30s. Therefore, it can also be said that the insulating film 38 is formed on the surface of the drift layer 33. The insulating film 38 has, for example, silicon oxide (SiO2). The thickness of the insulating film 38 is, for example, 1100 Å to 1300 Å. The insulating film 38 in the cell region 11 can also be said to constitute the gate insulating film.

[0039] An electrode material, such as polysilicon, is embedded in each trench 35 via an insulating film 38. The electrode material embedded in each trench 35 is electrically connected to either the gate electrode 22 (gate fingers 23A, 23B) or the emitter electrode 21. In other words, the electrode material embedded in each trench 35 forms a gate trench 22A and an emitter trench 21A. In this embodiment, gate trenches 22A and emitter trenches 21A are alternately provided in the arrangement direction of the multiple trenches 35. In this embodiment, both the gate trenches 22A and emitter trenches 21A are embedded up to the open end of each trench 35.

[0040] An intermediate insulating film 39 is formed on the surface 38s of the insulating film 38 provided on the substrate surface 30s. The intermediate insulating film 39 has, for example, SiO2. The thickness of the intermediate insulating film 39 is thicker than that of the insulating film 38, for example, 3000 Å or more and 15000 Å or less.

[0041] The emitter electrode 21 is formed on the intermediate insulating film 39. In other words, the intermediate insulating film 39 is an interlayer insulating film that fills both the space between the emitter electrode 21 and the gate trench 22A, and the space between the emitter electrode 21 and the emitter trench 21A.

[0042] In both the intermediate insulating film 39 and the insulating film 38, an inner circumferential opening 51 is formed at a position that overlaps with the base contact region 37 when viewed from the z direction, and penetrates both the intermediate insulating film 39 and the insulating film 38. The inner circumferential opening 51 exposes the base contact region 37 from the intermediate insulating film 39 and the insulating film 38. The inner circumferential opening 51 constitutes a contact hole for bringing the emitter electrode 21 into contact with the base contact region 37. Multiple inner circumferential openings 51 are provided.

[0043] The emitter electrode 21 has an electrode body portion 21c formed on the surface 39s of the intermediate insulating film 39, and a plurality of embedded electrode portions 21b individually embedded in a plurality of inner circumferential openings 51. In this embodiment, the electrode body portion 21c and each embedded electrode portion 21b are integrated. The electrode body portion 21c is provided on each embedded electrode portion 21b. The electrode body portion 21c protrudes above the intermediate insulating film 39. Here, in this embodiment, the emitter electrode 21 corresponds to the "electrode portion", and the electrode body portion 21c corresponds to the "laminated portion".

[0044] More specifically, the emitter electrode 21 has a barrier metal layer 21e. The barrier metal layer 21e is formed on the surface 39s of the intermediate insulating film 39, the inner surface 51a that constitutes the inner peripheral opening 51, and the surface (substrate surface 30s) of the drift layer 33 opened by the inner peripheral opening 51. The barrier metal layer 21e is formed by a laminated structure of Ti (titanium) and TiN (titanium nitride), for example. Therefore, the barrier metal layer 21e constitutes the portion of each embedded electrode portion 21b that is in contact with each inner surface 51a and the substrate surface 30s, and the portion of the electrode body portion 21c that is in contact with the surface 39s of the intermediate insulating film 39. An electrode layer 21f made of a material containing AlCu is provided on the barrier metal layer 21e. In other words, the emitter electrode 21 is formed by a laminated structure of the barrier metal layer 21e and the electrode layer 21f. Therefore, in this embodiment, it can be said that the embedded electrode portion 21b and the electrode body portion 21c are formed integrally.

[0045] A barrier layer 40 is formed on the emitter electrode 21. The barrier layer 40 has the function of suppressing the penetration of external ions from the passivation film 13 to the substrate surface 30s of the semiconductor substrate 30. Specifically, the barrier layer 40 has a material with a smaller external ion diffusion coefficient than the passivation film 13. In this embodiment, the barrier layer 40 has a material with a smaller external ion diffusion coefficient than the intermediate insulating film 39. Furthermore, the barrier layer 40 has a material with a smaller external ion diffusion coefficient than the insulating film 38. In summary, the barrier layer 40 has a material with a smaller external ion diffusion coefficient than the passivation film 13, the intermediate insulating film 39, and the insulating film 38. In other words, the passivation film 13 has a material with a larger external ion diffusion coefficient than the barrier layer 40. The barrier layer 40 is formed from a material containing, for example, silicon nitride. In this embodiment, the barrier layer 40 has SiN as silicon nitride. The thickness of the barrier layer 40 is thinner than the thickness of the intermediate insulating film 39. Furthermore, the barrier layer 40 is thinner than the passivation film 13. The barrier layer 40 is formed in a shape that follows the surface of the electrode body portion 21c of the emitter electrode 21. The barrier layer 40 has a front surface 40s and a back surface 40r. The front surface 40s is in contact with the passivation film 13 (see Figure 1), and the back surface 40r is in contact with the surface of the electrode body portion 21c of the emitter electrode 21. Here, the barrier layer 40 is formed on the portion of the emitter electrode 21 covered by the passivation film 13, and is not formed on the emitter electrode pad 16 (see Figure 1).

[0046] Viewed from the z-direction, the insulating film 38, the intermediate insulating film 39, and the barrier layer 40 are formed over substantially the entire surface of the main surface 10s of the apparatus. In other words, the insulating film 38, the intermediate insulating film 39, and the barrier layer 40 are formed in both the cell region 11 and the outer peripheral region 12 when viewed from the z-direction. Although not shown in the figures, the barrier layer 40 is not formed on the gate electrode pad 17.

[0047] The detailed configuration of the outer region 12 will be described with reference to Figures 4 to 7. Figure 4 shows a cross-sectional structure of a part of the outer peripheral region 12. Figure 5 shows a magnified structure of a part of the FLR portion 25 and its surroundings within the outer peripheral region 12 of Figure 4. Figure 6 shows a magnified structure of the gate finger 23A and the emitter routing portion 24 within the outer peripheral region 12 of Figure 4. Figure 7 shows the various structures of a part of the equipotential ring 26 and its surroundings within the outer peripheral region 12 of Figure 4. Note that, for convenience, the hatching of the components of the semiconductor device 10 is omitted in Figures 4 to 7.

[0048] As shown in Figures 4 to 7, a drift layer 33 is also formed in the outer peripheral region 12. Both the insulating film 38A and the intermediate insulating film 39 are formed on the substrate surface 30s of the semiconductor substrate 30 in the outer peripheral region 12. In other words, the insulating film 38A and the intermediate insulating film 39 can be said to cover the surface of the drift layer 33 in the outer peripheral region 12. The intermediate insulating film 39 is formed on the surface of the insulating film 38A. The insulating film 38A of the outer peripheral region 12 includes the insulating film 38. The insulating film 38A is formed separately from the insulating film 38 of the cell region 11. Furthermore, a barrier layer 40 is formed on the surface 39s of the intermediate insulating film 39 in the outer peripheral region 12. Here, in this embodiment, the outer peripheral region 12 can be said to consist of the insulating film 38A, the intermediate insulating film 39, and the barrier layer 40. Here, in this embodiment, the insulating film 38A and the intermediate insulating film 39 correspond to the "outer peripheral insulating film". Here, in this embodiment, the insulating film 38A corresponds to the "first insulating film", and the intermediate insulating film 39 corresponds to the "second insulating film".

[0049] As shown in Figure 6, the insulating film 38A has a substrate-side insulating film 38B formed on the substrate surface 30s of the semiconductor substrate 30, and an insulating film 38 as an anti-substrate-side insulating film formed on the surface 38Bs of the substrate-side insulating film 38B. In other words, the insulating film 38A in this embodiment has a two-layer laminated structure of the substrate-side insulating film 38B and the insulating film 38. The substrate-side insulating film 38B is an oxide film formed by thermal oxidation of the semiconductor substrate 30. For this reason, the intermediate insulating film 39 laminated on the insulating film 38A can also be said to be formed on the surface 38s of the insulating film 38. The thickness of the substrate-side insulating film 38B is, for example, about 18,000 Å.

[0050] As shown in Figure 4, a p-type well region 34A is formed in the region of the outer peripheral region 12 adjacent to the cell region 11. The well region 34A is formed on the substrate surface 30s of the semiconductor substrate 30, similar to the base region 34. The well region 34A is partially formed in the drift layer 33. Therefore, the surface of the well region 34A is covered by the insulating film 38A and the intermediate insulating film 39. Thus, it can be said that the insulating film 38A and the intermediate insulating film 39 (both seen in Figure 5) cover the surface of the drift layer 33 and the surface of the well region 34A. In this embodiment, the well region 34A is formed to surround the emitter electrode 21. The impurity concentration of the well region 34A is, for example, 1 × 10⁻⁶. 16 cm -3 The above 1 x 10 18 cm -3 The following applies:

[0051] The depth of the well region 34A in the outer peripheral region 12 is greater than the depth of the base region 34 (see Figure 3) in the cell region 11. More specifically, the depth of the well region 34A in the outer peripheral region 12 is greater than the depth of the trench 35. In this embodiment, the well region 34A extends to a position that overlaps with the outer peripheral portion of the emitter electrode 21 when viewed from the z direction. In other words, the well region 34A is also formed on the outer peripheral portion of the cell region 11. The barrier layer 40 (see Figure 5) is provided at a position that overlaps with the well region 34A when viewed from the z direction. The barrier layer 40 covers the well region 34A when viewed from the z direction. In this embodiment, the barrier layer 40 is formed to extend beyond the outer edge of the well region 34A when viewed from the z direction. Here, in this embodiment, the well region 34A corresponds to the "second semiconductor region of the second conductivity type".

[0052] As shown in Figure 4, an FLR portion 25 is formed outside the well region 34A. The FLR portion 25 is composed of a plurality (four in this embodiment) of annular conductive and semiconductor regions that are spaced apart from each other.

[0053] Multiple (four in this embodiment) annular guard rings 25a to 25d are formed on the substrate surface 30s of the semiconductor substrate 30. In this embodiment, the guard rings 25a to 25d are formed in a closed annular shape. The guard rings 25a to 25d are partially formed in the drift layer 33. The guard rings 25a to 25d are semiconductor regions of the second conductivity type (p-type in this embodiment) and are spaced apart from each other in a direction perpendicular to the z-direction. The guard rings 25a to 25d are arranged in the order of guard ring 25a, guard ring 25b, guard ring 25c, and guard ring 25d as you move away from the emitter electrode 21. The width Wge of the outermost guard ring 25d is greater than the width Wg of the other guard rings 25a to 25c. For example, B, Al, etc., are used as the p-type dopant for each guard ring 25a to 25d. The impurity concentration in each guard ring 25a to 25d is the same as, for example, the impurity concentration in well region 34A, for example, 1 × 10⁻⁶ 16 cm -3 The above 1 x 10 18 cm -3 The following applies. In this case, the guard rings 25a to 25d and the well region 34A may be formed in the same process. Here, in this embodiment, the guard rings 25a to 25d correspond to the "second semiconductor region of the second conductivity type". The width Wge of the guard ring 25d can be arbitrarily changed. For example, the width Wge of the guard ring 25d may be equal to the width Wg of the guard rings 25a to 25c.

[0054] The FLR section 25 has field plates 25e to 25h that correspond to the guard rings 25a to 25d. Viewed from the z direction, field plate 25e is positioned to overlap with guard ring 25a, field plate 25f is positioned to overlap with guard ring 25b, field plate 25g is positioned to overlap with guard ring 25c, and field plate 25h is positioned to overlap with guard ring 25d. Field plate 25e is in contact with guard ring 25a, field plate 25f is in contact with guard ring 25b, field plate 25g is in contact with guard ring 25c, and field plate 25h is in contact with guard ring 25d. In this embodiment, field plates 25e to 25h correspond to the "outer peripheral electrode section".

[0055] Figure 5 is an enlarged view of the guard rings 25a, 25b and field plates 25e, 25f and their surroundings within the FLR section 25. The configuration of guard ring 25a and field plate 25e is the same as that of guard rings 25b, 25c and field plates 25f, 25g. Also, the configuration of guard ring 25d and field plate 25h is the same as that of guard ring 25a and field plate 25e, except that field plate 25h extends outward. For this reason, the configuration of guard ring 25a and field plate 25e will be described below, and the descriptions of the configurations of guard rings 25b-25d and field plates 25f-25h will be omitted.

[0056] In the barrier layer 40, the intermediate insulating film 39, and the insulating film 38A, at positions that overlap with the guard ring 25a when viewed from the z direction, an outer peripheral opening 52 is formed that penetrates both the intermediate insulating film 39 and the insulating film 38A. When viewed from the z direction, the opening area of ​​the outer peripheral opening 52 is smaller than the surface area of ​​the guard ring 25a. In other words, the outer peripheral opening 52 forms a contact hole that exposes a portion of the surface of the guard ring 25a to make contact with the field plate 25e.

[0057] As shown in Figure 5, the portion of the insulating film 38A that constitutes the outer peripheral opening 52 is inclined toward the drift layer 33 as it approaches the inner surface 52a of the outer peripheral opening 52. In this embodiment, the opening end of the insulating film 38A has a curved portion 38j. The curved portion 38j is curved toward the drift layer 33 as it approaches the opening center of the outer peripheral opening 52. The intermediate insulating film 39 covers the curved portion 38j.

[0058] The field plate 25e is in contact with the guard ring 25a by fitting into the outer peripheral opening 52. The field plate 25e includes an embedded electrode portion 27 provided within the outer peripheral opening 52, and a plate body portion 28 having a protruding portion 28a that protrudes laterally from the outer peripheral opening 52 and is laminated on the intermediate insulating film 39. In this embodiment, the protruding portion 28a is formed on the surface 39s of the intermediate insulating film 39.

[0059] More specifically, the field plate 25e has a barrier metal layer 25m. The barrier metal layer 25m is formed on the surface 39s of the intermediate insulating film 39, the inner surface 52a that constitutes the outer peripheral opening 52, and the surface (substrate surface 30s) of the drift layer 33 opened by the outer peripheral opening 52. The barrier metal layer 25m is formed by a laminated structure of Ti and TiN, for example. Therefore, the barrier metal layer 25m constitutes the portion of the embedded electrode portion 27 that is in contact with the inner surface 52a and the surface of the drift layer 33, and the portion of the plate body portion 28 that is in contact with the surface 39s of the intermediate insulating film 39. An electrode layer 25n made of a material containing AlCu is provided on the barrier metal layer 25m. In other words, the field plate 25e is formed by a laminated structure of the barrier metal layer 25m and the electrode layer 25n. Therefore, in this embodiment, it can be said that the embedded electrode portion 27 and the plate body portion 28 are formed integrally.

[0060] The plate body portion 28 is provided on the embedded electrode portion 27. The plate body portion 28 protrudes from the intermediate insulating film 39 on the side opposite to the drift layer 33. In other words, the plate body portion 28 protrudes above the intermediate insulating film 39. The protruding portion 28a constitutes the portion of the plate body portion 28 that extends outward from the outer peripheral opening 52. More specifically, viewed from the z direction, the protruding portion 28a constitutes the portion that extends outward from the outer peripheral opening 52 in a direction perpendicular to the direction in which the field plate 25e extends, that is, the portion that extends outward from the outer peripheral opening 52 in the width direction of the field plate 25e. In this embodiment, viewed from the z direction, the protruding portion 28a covers the entire guard ring 25a. Viewed from the z direction, the protruding portion 28a has a portion that extends beyond the outer edge of the guard ring 25a.

[0061] The plate body portion 28 has an inclined surface 28b that curves toward the surface 39s of the intermediate insulating film 39 as it approaches the outer edge in the width direction of the field plate 25e. In this embodiment, the plate body portion 28 is formed by wet etching. Therefore, it can be said that the shape of the plate body portion 28 is a shape processed by wet etching.

[0062] More specifically, the field plate 25e has a surface 25s that is furthest from the intermediate insulating film 39 and a curved surface 28c that connects the surface 25s and the inclined surface 28b. The surface 25s is, for example, the surface facing the same side as the surface 39s of the intermediate insulating film 39, and is formed in a position that overlaps with the outer peripheral opening 52 when viewed from the z direction. The curved surface 28c has a curved surface that is convex upward and smoothly connects the surface 25s and the inclined surface 28b.

[0063] As shown in Figures 3 and 5, the thickness TB of the field plate 25e is thinner than the thickness TA of the emitter electrode 21. Here, the thickness TB of the field plate 25e is the distance in the z-direction between the tip surface of the embedded electrode portion 27 that is in contact with the contact region 25p and the surface 25s of the field plate 25e. In other words, the thickness TB is the thickness of the thickest part of the field plate 25e. In this embodiment, the thickness TB of the field plate 25e is the average thickness when the thickness of the field plate 25e is measured at multiple locations on the field plate 25e.

[0064] Furthermore, the thickness TA of the emitter electrode 21 (see Figure 3) is the distance in the z-direction between the tip surface of the embedded electrode portion 21b that is in contact with the base contact region 37 and the surface 21s of the emitter electrode 21. In other words, the thickness TA is the thickness of the thickest part of the emitter electrode 21. In this embodiment, the thickness TA of the emitter electrode 21 is the average thickness when the thickness of the emitter electrode 21 is measured at multiple locations on the emitter electrode 21.

[0065] Furthermore, the definition of the thickness TB of the field plate 25e is not limited to the average thickness described above, but may be changed as follows: The thickness TB of the field plate 25e may be the maximum thickness when the thickness of the field plate 25e is measured at multiple locations on the field plate 25e, or it may be the minimum thickness when the thickness of the field plate 25e is measured at multiple locations on the field plate 25e.

[0066] Similarly, the definition of the thickness TA of the emitter electrode 21 may also be changed as follows: The thickness TA of the emitter electrode 21 may be the maximum thickness when the thickness of the emitter electrode 21 is measured at multiple locations on the emitter electrode 21, or it may be the minimum thickness when the thickness of the emitter electrode 21 is measured at multiple locations on the emitter electrode 21.

[0067] The thickness T1 of the protrusion 28a of the field plate 25e is thinner than the thickness T2 of the electrode body portion 21c of the emitter electrode 21. The thickness T1 of the protrusion 28a is, for example, 3 μm or less, preferably 2 μm or less. More preferably, the thickness T1 of the protrusion 28a is about 1 μm.

[0068] Here, the thickness T1 of the protrusion 28a is the distance in the z-direction between the surface 39s of the intermediate insulating film 39 and the surface 25s of the field plate 25e. In other words, the thickness T1 is the thickness of the thickest part of the protrusion 28a. In this embodiment, the thickness T1 of the protrusion 28a is the average thickness when the thickness of the protrusion 28a is measured at multiple locations on the field plate 25e.

[0069] Furthermore, the thickness T2 of the electrode body portion 21c is the distance in the z-direction between the surface 39s of the intermediate insulating film 39 and the surface 21s of the emitter electrode 21. The surface 21s is the surface of the emitter electrode 21 that faces the same side as the surface 39s of the intermediate insulating film 39. In this embodiment, the thickness T2 of the electrode body portion 21c is the average thickness when the thickness of the electrode body portion 21c is measured at multiple locations on the emitter electrode 21.

[0070] Furthermore, the definition of the thickness T1 of the protrusion 28a is not limited to the average thickness described above, but may be changed as follows: The thickness T1 of the protrusion 28a may be the maximum thickness when the thickness of the protrusion 28a is measured at multiple locations on the field plate 25e, or it may be the minimum thickness when the thickness of the protrusion 28a is measured at multiple locations on the field plate 25e.

[0071] Similarly, the definition of the thickness T2 of the electrode body portion 21c may also be changed as follows: The thickness T2 of the electrode body portion 21c may be the maximum thickness when the thickness of the electrode body portion 21c is measured at multiple locations on the emitter electrode 21, or it may be the minimum thickness when the thickness of the electrode body portion 21c is measured at multiple locations on the emitter electrode 21.

[0072] Here, even if the thickness T1 of the protruding portion 28a is defined as the maximum thickness when the thickness of the protruding portion 28a is measured at multiple locations on the field plate 25e, and the thickness T2 of the electrode body portion 21c is defined as the minimum thickness when the thickness of the electrode body portion 21c is measured at multiple locations on the emitter electrode 21, it is preferable that the thickness T1 of the protruding portion 28a is thinner than the thickness T2 of the electrode body portion 21c.

[0073] As shown in Figure 5, the thickness T1 of the protrusion 28a is thinner than the thickness T3 of the laminated structure of the intermediate insulating film 39 and the insulating film 38A. On the other hand, the thickness T1 of the protrusion 28a is thicker than the thickness T4 of the intermediate insulating film 39. The thickness T1 of the protrusion 28a may also be equal to the thickness T4 of the intermediate insulating film 39.

[0074] Here, the thickness T3 of the laminated structure of the intermediate insulating film 39 and the insulating film 38A is the distance in the z-direction between the substrate surface 30s of the semiconductor substrate 30 and the surface 39s of the intermediate insulating film 39. In this embodiment, the thickness T3 of the laminated structure of the intermediate insulating film 39 and the insulating film 38A is the average thickness when the thickness of the laminated structure of the intermediate insulating film 39 and the insulating film 38A is measured at multiple locations.

[0075] Furthermore, the thickness T4 of the intermediate insulating film 39 is the distance in the z-direction between the surface 38s of the insulating film 38 and the surface 39s of the intermediate insulating film 39. In this embodiment, the thickness T4 of the intermediate insulating film 39 is the average thickness when the thickness of the intermediate insulating film 39 is measured at multiple locations.

[0076] Furthermore, the thickness T3 of the laminated structure of the intermediate insulating film 39 and the insulating film 38A is not limited to the average thickness mentioned above, but may be changed as follows: The thickness T3 of the laminated structure of the intermediate insulating film 39 and the insulating film 38A may be the maximum thickness when the thickness of the laminated structure of the intermediate insulating film 39 and the insulating film 38A is measured at multiple locations in the outer peripheral region 12, or the thickness T3 of the laminated structure of the intermediate insulating film 39 and the insulating film 38A may be the minimum thickness when the thickness of the laminated structure of the intermediate insulating film 39 and the insulating film 38A is measured at multiple locations in the outer peripheral region 12.

[0077] Furthermore, the thickness T4 of the intermediate insulating film 39 may also be changed in the same way as the thickness T3, as follows: The thickness T4 of the intermediate insulating film 39 may be the maximum thickness when the thickness of the intermediate insulating film 39 is measured at multiple locations in the outer peripheral region 12, or it may be the minimum thickness when the thickness of the intermediate insulating film 39 is measured at multiple locations in the outer peripheral region 12.

[0078] Here, even if the thickness T1 of the protruding portion 28a is defined as the maximum thickness when the thickness of the protruding portion 28a is measured at multiple locations on the field plate 25e, and the thickness T3 of the laminated structure of the intermediate insulating film 39 and the insulating film 38A is defined as the minimum thickness when the thickness of the laminated structure of the intermediate insulating film 39 and the insulating film 38A is measured at multiple locations on the outer peripheral region 12, it is preferable that the thickness T1 of the protruding portion 28a is thinner than the thickness T3 of the laminated structure of the intermediate insulating film 39 and the insulating film 38A.

[0079] In this embodiment, the thickness T1 of the protrusion 28a is greater than the thickness T5 of the barrier layer 40. In other words, the thickness T5 of the barrier layer 40 is less than the thickness T1 of the protrusion 28a. Also, the thickness T1 of the protrusion 28a is greater than the thickness T6 of the insulating film 38A. However, the thickness T1 of the protrusion 28a may be less than or equal to the thickness T6 of the insulating film 38A.

[0080] Here, the thickness T5 of the barrier layer 40 is the distance in the z-direction between the surface 39s of the intermediate insulating film 39 and the surface 40s of the barrier layer 40. In this embodiment, the thickness T5 of the barrier layer 40 is the average thickness when the thickness of the barrier layer 40 is measured at multiple locations.

[0081] Furthermore, the thickness T6 of the insulating film 38 is the distance in the z-direction between the substrate surface 30s of the semiconductor substrate 30 and the surface 38s of the insulating film 38. In this embodiment, the thickness T6 of the insulating film 38A is the average thickness when the thickness of the insulating film 38A is measured at multiple locations.

[0082] Furthermore, the thickness T5 of the barrier layer 40 is not limited to the average thickness mentioned above, but may be changed as follows: The thickness T5 of the barrier layer 40 may be the maximum thickness when the thickness of the barrier layer 40 is measured at multiple locations in the outer peripheral region 12, or it may be the minimum thickness when the thickness of the barrier layer 40 is measured at multiple locations in the outer peripheral region 12.

[0083] Furthermore, the thickness T6 of the insulating film 38A may also be changed in the same way as the thickness T5, as follows: The thickness T6 of the insulating film 38 may be the maximum thickness when the thickness of the insulating film 38A is measured at multiple locations in the outer peripheral region 12, or it may be the minimum thickness when the thickness of the insulating film 38A is measured at multiple locations in the outer peripheral region 12.

[0084] The lower end of the embedded electrode portion 27 is embedded in the upper part of the guard ring 25a. In the part of the guard ring 25a corresponding to the embedded electrode portion 27, p + A type p-type contact region 25p is formed. For example, B, Al, etc., are used as the p-type dopant for the contact region 25p. The impurity concentration of the contact region 25p is higher than that of the guard ring 25a, for example, 5 × 10⁻⁶. 18 cm -3 The above 1 x 10 20 cm -3 The following applies:

[0085] The barrier layer 40 is a stepped layer formed by covering both the intermediate insulating film 39 and the field plate 25e. The barrier layer 40 has a plate cover portion 41 that covers the plate body portion 28. Stepped portions 42 are formed in the portion of the plate cover portion 41 that covers both ends of the field plate 25e in the width direction. Here, the width direction of the field plate 25e is the direction perpendicular to the direction in which the field plate 25e extends when viewed from the z direction. Since the protruding portion 28a extends beyond the outer edge of the guard ring 25a when viewed from the z direction, the stepped portion 42 is located outward from the outer edge of the guard ring 25a. Here, if the tip of the stepped portion 42 in the width direction of the field plate 25e is located outward from the outer edge of the guard ring 25a, then it can be said that the stepped portion 42 is located outward from the outer edge of the guard ring 25a. In this embodiment, when viewed from the z direction, the entire stepped portion 42 is located outward from the outer edge of the guard ring 25a.

[0086] The plate cover portion 41 of the barrier layer 40 has a shape that conforms to the surface shape of the plate body portion 28. That is, the plate cover portion 41 has an inclined surface 41a that covers the inclined surface 28b of the plate body portion 28, a curved portion 41b that covers the curved surface 28c of the plate body portion 28, and a surface portion 41c that covers the surface of the plate body portion 28 (for example, the surface 25s of the field plate 25e). In this way, the plate cover portion 41 of the barrier layer 40 has a smooth curved shape that conforms to the surface shape of the plate body portion 28. The passivation film 13 is laminated on the barrier layer 40.

[0087] As shown in Figure 4, the field plate 25h has a projection 28a that extends on the opposite side from the field plate 25g which is longer than the projection 28a of the field plate 25e. The portion of the projection 28a of the field plate 25h that extends on the opposite side from the field plate 25g protrudes from the guard ring 25d when viewed from the z direction.

[0088] As shown in Figure 4, when viewed from the z direction, a gate finger 23A (23B) and an emitter routing portion 24 are formed at a position overlapping with the well region 34A. The gate finger 23A (23B) is formed at a position spaced outward from the emitter electrode 21.

[0089] As shown in Figure 6, the gate finger 23A has a gate layer 23a formed on the surface 38s of the insulating film 38 and a gate wiring 23b formed on the surface 40s of the barrier layer 40.

[0090] The gate layer 23a is made of, for example, polysilicon and is formed to surround the emitter electrode 21 from the apparatus side 10c, apparatus side 10a, and apparatus side 10d (see Figure 1). The gate layer 23a is covered by an intermediate insulating film 39. An oxide film 23c is formed on the gate layer 23a.

[0091] The gate wiring 23b is positioned so as to overlap with the gate layer 23a when viewed from the z direction. The gate wiring 23b is integrated with the gate electrode 22. An outer peripheral opening 53 is provided in the intermediate insulating film 39 and the oxide film 23c at a position corresponding to the gate finger 23A, penetrating both the intermediate insulating film 39 and the oxide film 23c. As a result, the gate layer 23a is exposed through the outer peripheral opening 53. The gate wiring 23b enters the outer peripheral opening 53 and contacts the gate layer 23a. In other words, the outer peripheral opening 53 constitutes a contact hole for the gate wiring 23b to contact the gate layer 23a.

[0092] The gate wiring 23b includes an embedded electrode portion 23ba provided within the outer peripheral opening 53, and a wiring body portion 23bb having a protruding portion 23bc that protrudes laterally from the embedded electrode portion 23ba and covers the intermediate insulating film 39.

[0093] More specifically, the gate wiring 23b has a barrier metal layer 23m. The barrier metal layer 23m is formed on the surface 39s of the intermediate insulating film 39, the inner surface 53a that constitutes the outer peripheral opening 53, and the surface (substrate surface 30s) of the drift layer 33 opened by the outer peripheral opening 53. The barrier metal layer 23m is formed by a laminated structure of Ti and TiN, for example. Therefore, the barrier metal layer 23m constitutes the portion of the embedded electrode portion 23ba that is in contact with the inner surface 53a and the surface of the drift layer 33, and the portion of the wiring body portion 23bb that is in contact with the surface 39s of the intermediate insulating film 39. An electrode layer 23n made of a material containing AlCu is provided on the barrier metal layer 23m. In other words, the gate wiring 23b is formed by a laminated structure of the barrier metal layer 23m and the electrode layer 23n. Therefore, in this embodiment, it can be said that the embedded electrode portion 23ba and the wiring body portion 23bb are formed integrally.

[0094] The thickness T7 of the protrusion 23bc is equal to the thickness T1 of the protrusion 28a of the field plate 25e (see Figure 5). Here, if the difference between thickness T7 and thickness T1 is, for example, within 20% of thickness T7, then thickness T7 and thickness T1 can be said to be equal.

[0095] In the gate layer 23a, in the portion where the embedded electrode portion 23ba is embedded, p + A contact region 23d, which is a type of semiconductor region, is formed. For example, B, Al, etc., are used as p-type dopants in the contact region 23d. The impurity concentration in the contact region 23d is higher than that of the well region 34A, for example, 5 × 10⁻⁶ 18 cm -3 The above 1 x 10 20 cm -3 The following applies:

[0096] The wiring body portion 23bb is provided on the embedded electrode portion 23ba. The wiring body portion 23bb protrudes from the intermediate insulating film 39 on the side opposite to the well region 34A. In other words, the wiring body portion 23bb protrudes above the intermediate insulating film 39. The protruding portion 23bc constitutes the portion of the wiring body portion 23bb that extends outward from the outer peripheral opening 53. More specifically, viewed from the z direction, the protruding portion 23bc constitutes the portion that extends outward from the outer peripheral opening 53 in a direction perpendicular to the direction in which the gate wiring 23b extends, that is, the portion that extends outward from the outer peripheral opening 53 in the width direction of the gate wiring 23b. The wiring body portion 23bb is curved and inclined toward the surface 39s of the intermediate insulating film 39 as it extends outward in the width direction of the gate wiring 23b. The wiring body portion 23bb is formed by wet etching. The shape of the wiring body portion 23bb can also be said to be the shape processed by wet etching. In this embodiment, the shape of the wiring body portion 23bb is the same as the shape of the plate body portion 28 of the field plate 25e.

[0097] The barrier layer 40 is a stepped layer formed by covering both the intermediate insulating film 39 and the gate finger 23A. The wiring cover portion 43 of the barrier layer 40 that covers the wiring body portion 23bb has a shape that conforms to the surface shape of the wiring body portion 23bb. The wiring cover portion 43 of the barrier layer 40 has a smooth curved shape that conforms to the surface shape of the wiring body portion 23bb. The passivation film 13 is laminated on the barrier layer 40.

[0098] The emitter routing portion 24 is made of a metal film and is formed on the surface 40s of the barrier layer 40. The emitter routing portion 24 is formed on the outer periphery of the well region 34A. An outer peripheral opening 54 is provided in the intermediate insulating film 39 and the insulating film 38 at a position corresponding to the emitter routing portion 24, penetrating the entirety of the intermediate insulating film 39 and the insulating film 38. As a result, the well region 34A is exposed through the outer peripheral opening 54. The emitter routing portion 24 enters the outer peripheral opening 54 and contacts the well region 34A. In other words, the outer peripheral opening 54 constitutes a contact hole for the emitter routing portion 24 to contact the well region 34A.

[0099] The emitter routing section 24 includes an embedded electrode section 24a embedded within the outer peripheral opening 54, and a wiring body section 24b having a protruding section 24c that protrudes laterally from the embedded electrode section 24a and covers the intermediate insulating film 39.

[0100] More specifically, the emitter routing section 24 has a barrier metal layer 24m. The barrier metal layer 24m is formed on the surface 39s of the intermediate insulating film 39, the inner surface 54a that constitutes the outer peripheral opening 54, and the surface (substrate surface 30s) of the drift layer 33 opened by the outer peripheral opening 54. The barrier metal layer 24m is formed by a laminated structure of Ti and TiN, for example. Therefore, the barrier metal layer 24m constitutes the portion of the embedded electrode section 24a that is in contact with the inner surface 54a and the surface of the drift layer 33, and the portion of the wiring body section 24b that is in contact with the surface 39s of the intermediate insulating film 39. An electrode layer 24n made of a material containing AlCu is provided on the barrier metal layer 24m. In other words, the emitter routing section 24 is formed by a laminated structure of the barrier metal layer 24m and the electrode layer 24n. Therefore, in this embodiment, it can be said that the embedded electrode section 24a and the wiring body section 24b are formed integrally.

[0101] The protrusion 24c is located within the well region 34A when viewed from the z direction. The thickness T8 of the protrusion 24c is equal to the thickness T1 of the protrusion 28a of the field plate 25e (see Figure 5). Here, if the difference between thickness T8 and thickness T1 is, for example, within 20% of thickness T8, then thickness T8 and thickness T1 can be said to be equal.

[0102] The lower end of the embedded electrode portion 24a is embedded in the upper part of the well region 34A. In the well region 34A, the portion corresponding to the embedded electrode portion 24a is p + A type-1 contact region 34B is formed. For example, B, Al, etc., are used as the p-type dopant in the contact region 34B. The impurity concentration in the contact region 34B is higher than that of the well region 34A, for example, 5 × 10⁻⁶ 18 cm -3 The above 1 x 10 20 cm -3 The following applies:

[0103] The wiring body portion 24b is provided on the embedded electrode portion 24a. The wiring body portion 24b protrudes from the intermediate insulating film 39 on the side opposite to the well region 34A. In other words, the wiring body portion 24b protrudes above the intermediate insulating film 39. The protruding portion 24c constitutes the portion of the wiring body portion 24b that extends outward from the outer peripheral opening 54. More specifically, viewed from the z direction, the protruding portion 24c constitutes the portion that extends outward from the outer peripheral opening 54 in a direction perpendicular to the direction in which the emitter routing portion 24 extends, that is, the portion that extends outward from the outer peripheral opening 54 in the width direction of the emitter routing portion 24. The wiring body portion 24b is curved and inclined toward the surface 39s of the intermediate insulating film 39 as it extends outward in the width direction of the emitter routing portion 24. The wiring body portion 24b is formed by wet etching. The shape of the wiring body portion 24b can also be said to be the shape processed by wet etching. In this embodiment, the shape of the wiring body portion 24b is the same as the shape of the plate body portion 28 of the field plate 25e.

[0104] The barrier layer 40 is a stepped layer that covers both the intermediate insulating film 39 and the emitter routing portion 24. The wiring cover portion 44 of the barrier layer 40 that covers the wiring body portion 24b has a shape that conforms to the surface shape of the wiring body portion 24b. The wiring cover portion 44 of the barrier layer 40 has a smooth curved shape that conforms to the surface shape of the wiring body portion 24b. The passivation film 13 is laminated on the barrier layer 40.

[0105] As shown in Figure 4, an equipotential ring 26 is formed at a position outside the FLR portion 25. As shown in Figure 7, the equipotential ring 26 is formed on the surface of the drift layer 33 (substrate surface 30s) with a first conductivity type (n + It has a channel stop region 26a of type (type), internal wiring 26b provided within the insulating film 38 and the intermediate insulating film 39, and surface-side wiring 26c provided on the surface 39s of the intermediate insulating film 39.

[0106] The channel stop region 26a is formed from a position overlapping with the surface wiring 26c when viewed from the z direction to the side surface 10a of the device. The channel stop region 26a is positioned outward (closer to the side surface 10a) relative to the internal wiring 26b. The impurity concentration in the channel stop region 26a is the same as, for example, the impurity concentration in the emitter region 36 (see Figure 3), which is 1 × 10⁻⁶. 19 cm -3 The above 5 x 10 20 cm -3 The following applies. In this case, for example, the channel stop region 26a is formed in the same process as the emitter region 36.

[0107] The internal wiring 26b is provided on the surface 38s of the insulating film 38 and is covered by the intermediate insulating film 39. The internal wiring 26b is formed of an electrode material such as polysilicon. The internal wiring 26b is formed in the same process as the gate layer 23a of the gate finger 23A (see Figure 5). An oxide film 26d is formed on the surface of the internal wiring 26b.

[0108] Outer peripheral openings 55 are provided in the barrier layer 40, the intermediate insulating film 39, and the oxide film 23c at positions corresponding to the channel stop region 26a. The outer peripheral openings 55 penetrate the intermediate insulating film 39, the insulating film 38, and the substrate-side insulating film 38B in the z-direction. As a result, the channel stop region 26a is exposed through the outer peripheral openings 55. The surface-side wiring 26c enters the outer peripheral openings 55 and contacts the channel stop region 26a. In other words, these outer peripheral openings 55 constitute contact holes for the surface-side wiring 26c to contact the channel stop region 26a.

[0109] Outer peripheral openings 56 are provided in the barrier layer 40, the intermediate insulating film 39, and the oxide film 26d at positions corresponding to the internal wiring 26b. The internal wiring 26b penetrates both the intermediate insulating film 39 and the oxide film 26d in the z direction through the outer peripheral openings 56. As a result, the internal wiring 26b is exposed through the outer peripheral openings 56. The surface-side wiring 26c enters the outer peripheral openings 56 and contacts the internal wiring 26b. In other words, the outer peripheral openings 56 constitute contact holes for the surface-side wiring 26c to contact the internal wiring 26b.

[0110] The surface wiring 26c includes two embedded electrode portions 26f and 26g, and a wiring body portion 26i having a protruding portion 26h that protrudes laterally from each embedded electrode portion 26f and 26g and overlaps with the intermediate insulating film 39.

[0111] More specifically, the surface wiring 26c has a barrier metal layer 26m. The barrier metal layer 26m is formed on the surface 39s of the intermediate insulating film 39, the inner surface 55a that constitutes the outer peripheral opening 55, the surface of the drift layer 33 (substrate surface 30s) opened by the outer peripheral opening 55, the inner surface 56a that constitutes the outer peripheral opening 56, and the surface of the internal wiring 26b opened by the outer peripheral opening 56. Therefore, the barrier metal layer 26m constitutes the portion of the embedded electrode portion 26f that is in contact with the inner surface 55a and the portion that is in contact with the surface of the channel stop region 26a. Furthermore, the barrier metal layer 26m constitutes the portion of the embedded electrode portion 26g that is in contact with the inner surface 56a and the portion that is in contact with the surface of the internal wiring 26b. Furthermore, the barrier metal layer 26m constitutes the portion of the wiring body portion 26i that is in contact with the surface 39s of the intermediate insulating film 39. The barrier metal layer 26m is formed, for example, by a laminated structure of Ti and TiN. An electrode layer 26n, made of a material containing AlCu, is provided on the barrier metal layer 26m. In other words, the surface wiring 26c is formed by a laminated structure of the barrier metal layer 26m and the electrode layer 26n. For this reason, in this embodiment, it can be said that the embedded electrode portions 26f, 26g and the wiring body portion 26i are formed integrally.

[0112] The embedded electrode portion 26f is positioned so as to overlap with both the channel stop region 26a and the wiring body portion 26i when viewed from the z direction. The embedded electrode portion 26f penetrates all of the insulating films 38, 38B on the channel stop region 26a and the intermediate insulating film 39 on the insulating film 38 in the z direction.

[0113] The embedded electrode portion 26g is positioned so as to overlap with both the internal wiring 26b and the wiring body portion 26i when viewed from the z direction. The embedded electrode portion 26g is located inward from the embedded electrode portion 26f. The embedded electrode portion 26g penetrates both the oxide film 26d and the intermediate insulating film 39 on the internal wiring 26b in the z direction. In this embodiment, the embedded electrode portion 26g is embedded in the upper portion of the internal wiring 26b.

[0114] The wiring body portion 26i is provided on the embedded electrode portions 26f and 26g. The wiring body portion 26i protrudes from the intermediate insulating film 39 on the side opposite to the drift layer 33. In other words, the wiring body portion 26i protrudes above the intermediate insulating film 39. The protruding portion 26h constitutes the end of the wiring body portion 26i and the portion of the wiring body portion 26i between the embedded electrode portion 26f and the embedded electrode portion 26g when viewed from the z direction. More specifically, when viewed from the z direction, the protruding portion 26h constitutes both ends in the direction perpendicular to the direction in which the surface wiring 26c extends, that is, both ends in the width direction of the surface wiring 26c and the portion between the embedded electrode portion 26f and the embedded electrode portion 26g in the direction in which the surface wiring 26c extends.

[0115] The thickness T9 of the protrusion 26h is equal to the thickness T1 of the protrusion 28a of the field plate 25e (see Figure 5). Here, if the difference between thickness T9 and thickness T1 is, for example, within 20% of thickness T8, then thickness T9 and thickness T1 can be said to be equal.

[0116] The barrier layer 40 is a stepped layer formed by covering both the intermediate insulating film 39 and the surface wiring 26c. The wiring cover portion 45 of the barrier layer 40 that covers the wiring body portion 26i has a shape that conforms to the surface shape of the wiring body portion 26i. The wiring cover portion 45 of the barrier layer 40 has a smooth curved shape that conforms to the surface shape of the wiring body portion 26i. The passivation film 13 is laminated on the barrier layer 40.

[0117] As shown in Figures 4 to 7, the outer peripheral region 12 is covered by the passivation film 13. In other words, the barrier layer 40 can also be said to be covered by the passivation film 13 when viewed from the z direction. For this reason, the barrier layer 40 can also be said to be provided between the passivation film 13 and the drift layer 33. Furthermore, the passivation film 13 is located above the intermediate insulating film 39 and overlaps with the intermediate insulating film 39 when viewed from the z direction. In other words, the passivation film 13 can also be said to cover the intermediate insulating film 39.

[0118] (Method of manufacturing semiconductor devices) The manufacturing method of the semiconductor device 10 of this embodiment will be described with reference to Figures 8 to 21. For convenience, Figures 8 to 21 show a simplified representation of the semiconductor device 10 during the manufacturing process. Therefore, the shape and size of the components of the semiconductor device 10 in Figures 8 to 21 may differ from those of the components of the semiconductor device 10 in Figures 1 to 7. Figures 8 to 21 show the manufacturing processes for a part of the cell region 11 and a part of the FLR section 25. Furthermore, for convenience, Figures 8 to 21 will be used to describe the manufacturing method of one semiconductor device 10. Hereinafter, the manufacturing method of the semiconductor device 10 of this embodiment is not limited to the manufacturing of one semiconductor device 10, but may also be used to manufacture multiple semiconductor devices 10.

[0119] The manufacturing method of the semiconductor device 10 of this embodiment includes a step of preparing a semiconductor substrate 830 formed from a material containing Si. The semiconductor substrate 830 has n as a first conductivity type semiconductor layer -The semiconductor substrate 830 has a drift layer 33 of type 1. The drift layer 33 is formed over the entire semiconductor substrate 830. The semiconductor substrate 830 has a substrate surface 830s and a substrate back surface (not shown) that face opposite each other in the thickness direction (z direction). For this reason, the substrate surface 830s can also be said to be the surface of the drift layer 33. The drift layer 33 is formed over the entire semiconductor substrate 830. For this reason, the drift layer 33 is formed over both the cell region 11 and the peripheral region 12. In this embodiment, the step of preparing the semiconductor substrate 830 corresponds to the "step of forming a first semiconductor layer of the first conductivity type on the peripheral region".

[0120] As shown in Figure 8, the manufacturing method of the semiconductor device 10 in this embodiment includes a step of forming a substrate-side insulating film 838B on the portion of the substrate surface 830s of the semiconductor substrate 830 that corresponds to the outer peripheral region 12. The substrate-side insulating film 838B is an insulating film that corresponds to the substrate-side insulating film 38B of the semiconductor device 10.

[0121] The step of forming the substrate-side insulating film 838B includes a step of thermally oxidizing the semiconductor substrate 830 to form a first insulating layer on the substrate surface 830s, a step of wet etching the first insulating layer, and a step of dry etching the first insulating layer.

[0122] Specifically, first, an oxide film is formed on the entire surface of the semiconductor substrate 830 by thermal oxidation. In this case, the oxide film is formed of silicon oxide (SiO2). Next, the portion of the oxide film other than the outer peripheral region 12 of the substrate surface 830s of the semiconductor substrate 830 is removed. More specifically, the thickness of the oxide film is first reduced by wet etching. Meanwhile, in the outer peripheral region 12, the thickness of the oxide film is partially reduced using a mask. Next, the oxide film is removed by dry etching. In the outer peripheral region 12, the portion exposed by the mask is removed by dry etching. After these steps, the substrate-side insulating film 838B is formed on the substrate surface 830s of the semiconductor substrate 830. Here, in this embodiment, the step of forming the substrate-side insulating film 838B includes the step of forming a first insulating layer (oxide film) by thermal oxidation of both the surface of the first semiconductor layer and the surface of the second semiconductor region, and the step of wet etching the first insulating layer followed by dry etching.

[0123] As shown in Figure 9, the manufacturing method of the semiconductor device 10 of this embodiment includes a step of forming a p-type well region 834 as a second conductivity type semiconductor region on a semiconductor substrate 830. Specifically, p-type impurities are selectively implanted into the substrate surface 830s of the semiconductor substrate 830. Subsequently, the p-type impurities are diffused by heat treatment of the semiconductor substrate 830. Through these steps, the well region 834 is formed. The well region 834 is partially formed in the drift layer 33. The surface of the well region 834 constitutes the substrate surface 830s and is therefore a continuous surface with the surface of the drift layer 33. Here, the well region 834 includes the well region 34A and guard rings 25a to 25d (guard ring 25d is not shown in Figure 9). Here, the step of forming the well region 834 on the semiconductor substrate 830 corresponds to the "step of partially forming a second semiconductor region of the second conductivity type in the first semiconductor layer". It can also be said that the well region 834 is covered by the substrate-side insulating film 838B.

[0124] As shown in Figure 10, the manufacturing method of the semiconductor device 10 in this embodiment includes a step of forming a plurality of trenches 835 in the portion of the semiconductor substrate 830 corresponding to the cell region 11. Specifically, first, a trench mask (not shown) is formed on the substrate surface 830s of the semiconductor substrate 830. Next, the trench mask is selectively etched. That is, the region of the trench mask in which the trenches 835 are to be formed is etched when viewed from the z direction. As a result, the region of the substrate surface 830s of the semiconductor substrate 830 in which the trenches 835 are to be formed is exposed on the trench mask. Next, the region of the substrate surface 830s of the semiconductor substrate 830 in which the trenches 835 are to be formed is etched. As a result, trenches 835 are formed in the semiconductor substrate 830.

[0125] As shown in Figure 11, the manufacturing method of the semiconductor device 10 of this embodiment includes the steps of forming an insulating film 838 and forming electrodes. In the process of forming the insulating film 838, first, the semiconductor substrate 830 is thermally oxidized, forming an oxide film over the entire surface of the semiconductor substrate 830, including the inner surfaces of each trench 835. In other words, the insulating film 838 is formed of silicon oxide (SiO2). As a result, the insulating film 838 is formed on the cell region 11 of the substrate surface 830s of the semiconductor substrate 830. The insulating film 838 is the insulating film corresponding to the insulating film 38. The insulating film 838 in the cell region 11 is a gate insulating film and is also formed on the inner surfaces of each trench 835. Furthermore, in the outer peripheral region 12 of the semiconductor substrate 830, the insulating film 838 is laminated on the surface 838Bs of the substrate-side insulating film 838B. In this embodiment, the process of forming the substrate-side insulating film 838B and the insulating film 838 corresponds to the "process of forming the first insulating film".

[0126] Next, in the electrode formation process, electrode material PS such as polysilicon is embedded in each trench 835 and formed on the substrate surface 830s of the semiconductor substrate 830. This forms the gate trench 22A and the emitter trench 21A.

[0127] As shown in Figure 12, the manufacturing method of the semiconductor device 10 of this embodiment comprises the steps of etching the electrode material PS and forming an insulating film 838 on the electrode material PS. In the process of etching the electrode material PS, the electrode material PS on the substrate surface 830s of the semiconductor substrate 830 is removed by etching. Although not shown in the figure, the electrode material PS of the gate fingers 23A, 23B and gate electrode 22 in the outer peripheral region 12, and the electrode material PS of the internal wiring 26b of the equipotential ring 26 are not etched.

[0128] Next, in the step of forming an insulating film 838 on the electrode material PS, the electrode material PS embedded in each trench 835, the electrode material PS forming the gate fingers 23A, 23B and the gate electrode 22, and the electrode material PS forming the internal wiring 26b of the equipotential ring 26 are oxidized. As a result, an insulating film 838 is formed on each electrode material PS. Here, the electrode material PS of the gate fingers 23A, 23B corresponds to the gate layer 23a, and the insulating film 838 on the electrode material PS corresponds to the oxide film 23c of the gate fingers 23A, 23B and the oxide film 26d of the internal wiring 26b of the equipotential ring 26.

[0129] As shown in Figure 13, the manufacturing method of the semiconductor device 10 of this embodiment includes a step of forming a base region 34, an emitter region 36, and a channel stop region 26a (see Figure 7). Specifically, n-type and p-type dopants are selectively ion-implanted and diffused into the portion of the substrate surface 830s of the semiconductor substrate 830 corresponding to the cell region 11, thereby forming a p-type base region 34 and an n-type dopant. + The emitter region 36 and channel stop region 26a are formed sequentially. In other words, the emitter region 36 and channel stop region 26a are formed in the same process.

[0130] As shown in Figure 14, the manufacturing method of the semiconductor device 10 in this embodiment includes a step of forming an intermediate insulating film 839. The intermediate insulating film 839 is formed of silicon oxide (SiO2) and is formed over the entire substrate surface 830s of the semiconductor substrate 830, for example, by chemical vapor deposition (CVD). The intermediate insulating film 839 is an insulating film corresponding to the intermediate insulating film 39. The intermediate insulating film 839 is laminated on the insulating film 838. In this case, in the cell region 11, the insulating film has a two-layer structure consisting of the insulating film 838 formed on the substrate surface 830s of the semiconductor substrate 830 and the intermediate insulating film 839. On the other hand, in the peripheral region 12, the insulating film has a three-layer structure consisting of the substrate-side insulating film 838B formed on the substrate surface 830s of the semiconductor substrate 830, the insulating film 838, and the intermediate insulating film 839. Thus, in this embodiment, the steps for forming the substrate-side insulating film 838B, insulating film 838, and intermediate insulating film 839 correspond to both "the step of forming an insulating film covering multiple cells in the cell region" and "the step of forming an outer peripheral insulating film covering the surface of the first semiconductor layer and the surface of the second semiconductor region." Furthermore, in this embodiment, the steps for forming the substrate-side insulating film 838B, insulating film 838, and intermediate insulating film 839 correspond to "the step of forming an outer peripheral insulating film formed of a silicon oxide film covering the surface of the first semiconductor layer and the surface of the second semiconductor region."

[0131] As shown in Figure 15, the manufacturing method of the semiconductor device 10 of this embodiment includes a step of forming an opening. In the cell region 11, openings 861 are formed by etching, penetrating the intermediate insulating film 839 and the insulating film 838, respectively. The openings 861 in the cell region 11 expose the base region 34. These openings 861 form recesses 831 on the substrate surface 830s of the semiconductor substrate 830 corresponding to the base region 34.

[0132] In the outer peripheral region 12, openings 862 are formed by etching so as to penetrate the intermediate insulating film 839, the insulating film 838, and the substrate-side insulating film 838B, respectively. The openings 862 in the outer peripheral region 12 individually expose, for example, the guard rings 25a to 25d. The openings 862 form recesses 832 on the substrate surface 830s of the semiconductor substrate 830 corresponding to the guard rings 25a to 25d. Another opening 862 may expose the well region 34A corresponding to the gate fingers 23A and 23B, or the well region 34A corresponding to the emitter routing portion 24. Here, the step of forming the openings corresponds to the "step of forming openings in the outer peripheral insulating film that expose a part of the surface of the second semiconductor region."

[0133] As shown in Figure 16, the manufacturing method of the semiconductor device 10 of this embodiment includes a step of forming the base contact region 37 and the contact region 25p. Specifically, a p-type dopant is ion-implanted and diffused into the substrate surface 830s of the semiconductor substrate 830 through an opening, thereby forming the base contact region 37 and the contact region 25p. + The base contact region 37 and contact region 25p are formed, respectively. Although not shown in the figures, the manufacturing method of the semiconductor device 10 in this embodiment includes a step of forming a contact region 34B in the portion of the well region 34A exposed from the opening 862 that corresponds to the emitter routing portion 24. This step is carried out, for example, in the same way as the step of forming the base contact region 37 and contact region 25p.

[0134] As shown in Figures 17 and 18, the manufacturing method of the semiconductor device 10 in this embodiment includes the steps of forming the emitter electrode 21, gate electrode 22, gate fingers 23A, 23B, emitter routing portion 24, field plates 25e to 25h, and equipotential ring 26. In this embodiment, the steps of forming the emitter electrode 21, gate electrode 22, gate fingers 23A, 23B, emitter routing portion 24, field plates 25e to 25h, and equipotential ring 26 correspond to both the "step of forming the electrode portion" and the "step of forming the outer peripheral electrode portion". Note that Figures 17 and 18 show the emitter electrode 21 and field plates 25e to 25g.

[0135] As shown in Figure 17, first, a first metal layer is formed on the surface 39s of the intermediate insulating film 39 and on the inner surfaces of each opening 861, 862 by sputtering, for example, titanium (Ti). Subsequently, a second metal layer is formed on the first metal layer by sputtering, using titanium nitride (TiN). This forms a barrier metal layer 823. Here, the barrier metal layer 823 corresponds to the barrier metal layer 21e of the emitter electrode 21, the barrier metal layer 23m of the gate finger 23A (23B), the barrier metal layer 24m of the emitter routing section 24, the barrier metal layer 25m of the field plates 25e~25h, and the barrier metal layer 26m of the equipotential ring 26. In other words, in this embodiment, the barrier metal layers 21e, 23m, 24m, 25m, and 26m are formed by the same process.

[0136] Next, the embedded electrode portion 821 and the electrode layer 822 are integrally formed by sputtering using AlCu. The embedded electrode portion 821 is the portion embedded in the openings 861 and 862. The electrode layer 822 is formed over the entire intermediate insulating film 39 when viewed from the z direction.

[0137] Next, as shown in Figure 18, the electrode layer 822 is etched to form the electrode layer 822 corresponding to the electrode layer 21f of the emitter electrode 21, the electrode layer 23n of the gate electrode 22 and gate fingers 23A, 23B, the electrode layer 24n of the emitter routing section 24, the electrode layer 24n of the field plates 25e~25h, and the electrode layer 26n of the equipotential ring 26. In other words, in this embodiment, the electrode layers 21f, 23n, 24n, 25n, and 26n are formed by the same process. In addition, the embedded electrode portion 21b and electrode body portion 21c of the emitter electrode 21, the embedded electrode portion 23ba and wiring body portion 23bb of the gate electrode 22 and gate fingers 23A and 23B, the embedded electrode portion 24a and wiring body portion 24b of the emitter routing portion 24, the embedded electrode portion 27 and plate body portion 28 of the field plates 25e to 25h, and the embedded electrode portions 26f, 26g and wiring body portion 26i of the equipotential ring 26 are formed by the same process. Figure 18 shows the emitter electrode 21 and the electrode layers 822 corresponding to the field plates 25e to 25g.

[0138] Next, as shown in Figure 19, the thickness of the electrode layers 822 corresponding to the emitter electrode 21, gate electrode 22, gate fingers 23A, 23B, emitter routing portion 24, field plates 25e to 25h, and equipotential ring 26 is reduced by etching, for example. In this embodiment, for example, the electrode layer 822 is etched to a thickness of 2 μm or less. This forms the emitter routing portion 24, field plates 25e to 25h, and equipotential ring 26. Note that in Figure 19, field plates 25e to 25g are shown. Thus, the process of forming the outer periphery electrode portion includes a step of making the thickness of the electrode layers 822 corresponding to the insulating film 38A and intermediate insulating film 39 thinner than the thickness of the electrode layers 822 corresponding to the insulating film 38 and intermediate insulating film 39.

[0139] As shown in Figure 20, the manufacturing method of the semiconductor device 10 in this embodiment includes a step of forming a barrier layer 840. The barrier layer 840 is an insulating layer corresponding to the barrier layer 40 of the semiconductor device 10. The barrier layer 840 is formed of a material with a smaller diffusion coefficient than the intermediate insulating film 839 and insulating films 838, 838B. In this embodiment, in the outer peripheral region 12, the barrier layer 840 is made of a material containing silicon nitride (SiN) and is formed, for example, by CVD over the entire surface 39s of the intermediate insulating film 39, the gate fingers 23A, 23B, the emitter routing portion 24, the field plates 25e to 25h, and the equipotential ring 26. As a result, the barrier layer 840 is formed in a stepped manner. Here, in this embodiment, the step of forming the barrier layer 840 corresponds to "the step of forming a barrier layer with a smaller diffusion locking number than the outer peripheral insulating film in a stepped manner so as to cover both the outer peripheral insulating film and the protruding portion." Furthermore, the process of forming the barrier layer 840 corresponds to "the process of forming a barrier layer made of silicon nitride film in a stepped manner so as to cover both the outer insulating film and the protruding portion."

[0140] As shown in Figure 21, the manufacturing method of the semiconductor device 10 in this embodiment includes a step of forming a passivation film 13. Specifically, a passivation layer made of a material with a diffusion coefficient greater than that of the barrier layer 840, such as an organic material like polyimide, is formed over the entire substrate surface 830s of the semiconductor substrate 830 when viewed from the z direction, so as to cover the emitter electrode 21, gate electrode 22, gate fingers 23A, 23B, field plates 25e~25h, and equipotential ring 26. Subsequently, openings are formed by etching to expose the emitter electrode 21 and gate electrode 22. This forms the passivation film 13, the emitter electrode pad 16, and the gate electrode pad 17. The passivation film 13 covers the barrier layer 40. In this embodiment, the step of forming the passivation film 13 corresponds to the "step of laminating a passivation film with a diffusion coefficient greater than that of the barrier layer onto the barrier layer." Furthermore, the step of forming the passivation film 13 corresponds to the "step of laminating the passivation film formed by the organic insulating film onto the barrier layer."

[0141] Although not shown in the figures, the manufacturing method of the semiconductor device 10 in this embodiment includes the steps of forming a buffer layer 32, a collector layer 31, and a collector electrode 29. Specifically, the buffer layer 32 and the collector layer 31 are sequentially formed by selective ion implantation and diffusion of n-type and p-type dopants into the back surface of the semiconductor substrate 830. Subsequently, the collector electrode 29 is formed on the surface of the collector layer 31 opposite to the buffer layer 32. The semiconductor device 10 is manufactured through these steps. Note that Figures 8 to 21 show only a part of the manufacturing process of the semiconductor device 10, and the manufacturing method of the semiconductor device 10 may include steps not shown in Figures 8 to 21.

[0142] (Operation of the first embodiment) The operation of the semiconductor device 10 of this embodiment will now be described. The passivation film 13, which is an organic insulating film such as polyimide, is formed over the entire main surface 10s of the apparatus to protect against external ions. In other words, the passivation film 13 covers the entire outer peripheral region 12. However, because the passivation film 13 has a high diffusion coefficient, there is a risk that external ions may diffuse and pass through the passivation film 13.

[0143] When the intermediate insulating film 39 and insulating films 38,38A, which have a silicon oxide film, are charged by external ions that have passed through the passivation film 13, in particular when the intermediate insulating film 39 and insulating film 38A in the outer peripheral region 12 (for example, the FLR portion 25) are charged by external ions, the spread of the electric field in each guard ring 25a to 25d will differ, which may result in a voltage lower than the preset breakdown voltage.

[0144] Therefore, in order to suppress the charging of the intermediate insulating film 39 and insulating films 38,38A by external ions, it is conceivable to provide a barrier layer having a silicon nitride film with a low diffusion coefficient. In one example, when a barrier layer is provided in the FLR section 25, the barrier layer may be provided, for example, on the surface 39s of the intermediate insulating film 39 and on the surfaces of the field plates 25e to 25h.

[0145] However, because the z-direction positions of the surfaces of the field plates 25e~25h and the surface 39s of the intermediate insulating film 39 are different, the portion of the barrier layer between the surface 39s of the intermediate insulating film 39 and the surfaces of the field plates 25e~25h forms a stepped shape. If the stepped shape of the barrier layer becomes large, there is a risk of cracks occurring. If cracks occur in the barrier layer, external ions may penetrate the intermediate insulating film 39 through the cracks, potentially causing it to become charged.

[0146] On the other hand, in this embodiment, the field plates 25e to 25h are formed such that the thickness T1 of their protruding portions 28a is thinner than the thickness T2 of the electrode body portion 21c of the emitter electrode 21. As a result, the stepped shape of the barrier layer 40 covering the protruding portions 28a is smaller than the stepped shape of the barrier layer 40 covering the electrode body portion 21c of the emitter electrode 21 (not shown in Figure 3). Therefore, the occurrence of cracks in the stepped portion of the barrier layer 40 is suppressed, and thus the charging of the intermediate insulating film 39 by external ions due to cracks can be suppressed.

[0147] (Effects of the first embodiment) The semiconductor device 10 of this embodiment provides the following advantages. (1-1) The cell region 11 of the semiconductor device 10 is equipped with an emitter electrode 21 having an electrode body portion 21c laminated on an intermediate insulating film 39. Each of the field plates 25e to 25h that individually contact the guard rings 25a to 25d has a protrusion 28a laminated on the intermediate insulating film 39. The semiconductor device 10 is equipped with an intermediate insulating film 39, a barrier layer 40 which is a stepped layer formed by covering the field plates 25e to 25h together with the protrusion 28a and has a smaller diffusion coefficient than the intermediate insulating film 39 and the insulating film 38, and a passivation film 13 which is laminated on the barrier layer 40 and has a larger diffusion coefficient than the barrier layer 40. The thickness T1 of the protrusion 28a is thinner than the thickness T2 of the electrode body portion 21c.

[0148] With this configuration, cracks are less likely to occur in the stepped portions of the barrier layer 40 covering the field plates 25e to 25h, thus suppressing the passage of external ions through the barrier layer 40 due to cracks. This suppresses the charging of the intermediate insulating film 39 by external ions, and therefore suppresses the change in potential of the guard rings 25a to 25d due to the charging of the intermediate insulating film 39. Consequently, a decrease in the dielectric breakdown voltage of the semiconductor device 10 can be suppressed. Similarly, cracks are less likely to occur in the stepped portions of the barrier layer 40 of the gate fingers 23A, 23B, emitter routing portion 24, and equipotential ring 26, thus suppressing the passage of external ions through the barrier layer 40 due to cracks.

[0149] (1-2) The thickness T1 of the protruding portion 28a of the field plate 25e~25h is less than the sum of the thickness T6 of the insulating film 38A and the thickness T4 of the intermediate insulating film 39, which is T3. This configuration makes it less likely for cracks to occur in the stepped portions of the barrier layer 40 covering the field plates 25e to 25h, thereby suppressing the passage of external ions through the barrier layer 40 due to cracks.

[0150] (1-3) The field plates 25e to 25h have a configuration in which the protruding portion 28a and the embedded electrode portion 27 are integrated. With this configuration, the number of steps required to manufacture the field plates 25e to 25h can be reduced compared to the case where the protruding portion 28a and the embedded electrode portion 27 of the field plates 25e to 25h are formed individually, thus simplifying the manufacturing process of the field plates 25e to 25h.

[0151] (1-4) The protruding portion 28a of the field plates 25e to 25h covers the outer edge of the guard rings 25a to 25d when viewed from the z direction. With this configuration, the stepped portion of the barrier layer 40 covering the field plates 25e to 25h is positioned further outward than the outer edges of the guard rings 25a to 25d when viewed from the z direction. Therefore, even if cracks occur in the stepped portion of the barrier layer 40, it becomes difficult for external ions to penetrate the guard rings 25a to 25d.

[0152] (1-5) The protruding portion 28a of the field plates 25e to 25h has a portion that extends beyond the outer edge of the guard rings 25a to 25d when viewed from the z direction. With this configuration, the stepped portion of the barrier layer 40 covering the field plates 25e to 25h is positioned further outward and spaced further away from the outer edges of the guard rings 25a to 25d when viewed from the z direction. Therefore, even if cracks occur in the stepped portion of the barrier layer 40, it becomes difficult for external ions to penetrate the guard rings 25a to 25d.

[0153] (1-6) The protruding portion 28a of the field plate 25e to 25h has an inclined surface 28b that slopes toward the intermediate insulating film 39 as it approaches the lateral tip of the protruding portion 28a. With this configuration, the stepped portion of the barrier layer 40 covering the field plates 25e to 25h also becomes inclined along the inclined surface 28b, thus reducing the bending of the barrier layer 40 in the stepped portion. Consequently, cracks are less likely to occur in the stepped portion of the barrier layer 40.

[0154] (1-7) The field plate 25e has a surface 25s that is furthest from the intermediate insulating film 39 and a curved surface 28c that connects the surface 25s and the inclined surface 28b. The field plates 25f to 25h have a similar shape.

[0155] With this configuration, the shape of the barrier layer 40 covering the curved surface 28c of the field plate 25e becomes curved, and the bending of the barrier layer 40 becomes less pronounced. Therefore, cracks are less likely to occur in the stepped portion of the barrier layer 40. Similarly, cracks are less likely to occur in the stepped portion of the barrier layer 40 covering the field plates 25f to 25h.

[0156] (1-8) The inclined surface 28b of the protruding portion 28a of the field plate 25e~25h is curved. With this configuration, the step in the stepped portion of the barrier layer 40 that covers the intermediate insulating film 39 and the inclined surface 28b becomes smaller, making it less likely for cracks to occur.

[0157] (1-9) The thickness T5 of the barrier layer 40 is thinner than the thickness T1 of the protrusions 28a of the field plate 25e~25h. This configuration makes it possible to make the semiconductor device 10 thinner. In addition, even if the barrier layer 40 is formed thinly, the thickness T1 of the protruding portion 28a of the field plate 25e~25h is formed thinner than the thickness T2 of the electrode body portion 21c of the emitter electrode 21, so that cracks do not occur in the stepped portion of the barrier layer 40.

[0158] (1-10) Both the insulating film 38 and the intermediate insulating film 39 are silicon oxide films, the passivation film 13 is an organic insulating film containing polyimide, and the barrier layer 40 is a silicon nitride film.

[0159] With this configuration, the diffusion coefficient of the barrier layer 40 becomes smaller than that of the insulating film 38, the intermediate insulating film 39, and the passivation film 13. Therefore, the same effect as described in (1-1) above can be obtained.

[0160] (1-11) The method for manufacturing the semiconductor device 10 is n -The process includes the steps of: preparing a semiconductor substrate 830 on which a p-type drift layer 33 is formed; partially forming a p-type well region 834 in the drift layer 33; forming an insulating film 838 and an intermediate insulating film 839 on the substrate surface 30s of the semiconductor substrate 30; forming an emitter electrode 21 having an electrode body portion 21c laminated on the intermediate insulating film 39; forming openings in the insulating film 838 and the intermediate insulating film 839 that expose a part of the surface of the well region 834; forming field plates 25e to 25h that protrude laterally from the openings and have protruding portions 28a laminated on the intermediate insulating film 839, and that are in contact with the portion of the well region 834 exposed by the openings; forming a barrier layer 840 having a smaller diffusion coefficient than the insulating film 838 and the intermediate insulating film 839 in a stepped manner so as to cover both the intermediate insulating film 839 and the field plates 25e to 25h; and laminating a passivation film 13 having a larger diffusion coefficient than the barrier layer 40 on the barrier layer 840. In the process of forming the field plates 25e to 25h, the thickness T1 of the protruding portion 28a is formed to be thinner than the thickness T2 of the electrode body portion 21c. With this configuration, the same effect as in (1-1) above can be obtained.

[0161] [Second Embodiment] The semiconductor device 10 of the second embodiment will be described with reference to Figures 22 to 37. The semiconductor device 10 of this embodiment differs from the semiconductor device 10 of the first embodiment in its wiring structure and insulating film structure. In the following description, the differences from the semiconductor device 10 of the first embodiment will be described in detail, and components common to the semiconductor device 10 of the first embodiment will be denoted by the same reference numerals and their descriptions will be omitted.

[0162] (Configuration of a semiconductor device) The configuration of the semiconductor device of this embodiment will be described with reference to Figures 22 and 23. Figure 22 shows a part of the cross-sectional structure of the cell region 11. As shown in Figure 22, the wiring structure of the emitter electrode 21 in the cell region 11 of this embodiment differs from that of the first embodiment. For this reason, the wiring structure of the emitter electrode 21 will be described in detail below, and other parts will be given the same reference numerals as in the first embodiment, and their descriptions will be omitted.

[0163] As shown in Figure 22, the emitter electrode 21 has an individually formed embedded electrode portion 21b and an electrode body portion 21c. In other words, unlike the first embodiment, the emitter electrode 21 has a first electrode layer 21g corresponding to the embedded electrode portion 21b and a second electrode layer 21h corresponding to the electrode body portion 21c.

[0164] The first electrode layer 21g is embedded in a hole surrounded by a barrier metal layer 21e. The first electrode layer 21g is formed of a material containing, for example, tungsten (W). In this embodiment, the upper end surface of the first electrode layer 21g and the upper end surface of the barrier metal layer 21e are flush with each other.

[0165] The electrode body portion 21c is formed on the embedded electrode portion 21b. The electrode body portion 21c can also be said to be laminated on the surface 39s of the intermediate insulating film 39, similar to the first embodiment. The second electrode layer 21h is in contact with both the upper end surface of the first electrode layer 21g and the upper end surface of the barrier metal layer 21e. The thickness T2 of the electrode body portion 21c is the same as the thickness T2 of the first embodiment (see Figure 3). Also, the thickness TA of the emitter electrode 21 is the same as the thickness TA of the first embodiment (see Figure 3).

[0166] Figure 23 shows a part of the cross-sectional structure of the FLR section 25. Note that the wiring structure and insulating film structure of the gate fingers 23A, 23B and the emitter routing section 24 (see Figure 4 for both) are the same as those of the FLR section 25, so their explanation is omitted.

[0167] As shown in Figure 23, a LOCOS oxide film 60 is formed on the substrate surface 30s of the semiconductor substrate 30 in place of the substrate-side insulating film 38B. In other words, in this embodiment, the insulating film 38A consists of a laminated structure of the LOCOS oxide film 60 and the insulating film 38. The LOCOS oxide film 60 has a surface 60s and a back surface 60r that face opposite each other in the z direction. The back surface 60r of the LOCOS oxide film 60 is in contact with the substrate surface 30s of the semiconductor substrate 30.

[0168] The LOCOS oxide film 60 has a thick film portion 61, a thin film portion 62, and a sloped portion 63. The thick film portion 61 is a portion of the LOCOS oxide film 60 that is relatively thick, and is provided, for example, between adjacent outer peripheral openings 52. The thin film portion 62 is a portion of the LOCOS oxide film 60 that is relatively thin, and is provided, for example, in a position that overlaps with the outer peripheral openings 52 when viewed from the z direction. For this reason, it can also be said that the outer peripheral openings 52 are provided in the thin film portion 62 of the LOCOS oxide film 60. The inclined portion 63 is provided between the thick film portion 61 and the thin film portion 62, and is a portion that connects the thick film portion 61 and the thin film portion 62. On both sides of the front surface 60s and the back surface 60r, the inclined portion 63 is inclined such that the thickness of the LOCOS oxide film 60 increases from the thin film portion 62 toward the thick film portion 61.

[0169] The thick film portion 61 is formed to penetrate the substrate surface 30s of the semiconductor substrate 30. As a result, the semiconductor substrate 30 has a recessed portion 30a formed in the substrate surface 30s. The configuration of the LOCOS oxide film 60 can be arbitrarily changed. In one example, the thin film portion 62 may be omitted from the LOCOS oxide film 60. In this case, the LOCOS oxide film 60 will have a configuration in which multiple oxide films consisting of a thick film portion 61 and an inclined portion 63 are provided spaced apart from each other.

[0170] In this embodiment, an insulating film 38 is formed on the surface 60s of the LOCOS oxide film 60. The insulating film 38 is laminated on the LOCOS oxide film 60 according to its shape. That is, the insulating film 38 is inclined along the shape of the inclined portion 63 of the LOCOS oxide film 60. In this embodiment, the insulating film 38 is formed over the entire surface 60s of the LOCOS oxide film 60. An intermediate insulating film 39 is formed on the surface 38s of the insulating film 38. Therefore, the intermediate insulating film 39 is formed to cover all of the thick film portion 61, thin film portion 62, and inclined portion 63 of the LOCOS oxide film 60. In this embodiment, the intermediate insulating film 39 has a two-layer laminated structure.

[0171] In this embodiment, the outer peripheral opening 52 penetrates the intermediate insulating film 39, the insulating film 38, and the LOCOS oxide film 60. As a result, the guard ring 25a is exposed from the intermediate insulating film 39, the insulating film 38, and the LOCOS oxide film 60 through the outer peripheral opening 52. In this embodiment, the outer peripheral opening 52 penetrates the thin film portion 62 of the LOCOS oxide film 60.

[0172] The field plate 25e has an electrode layer 70 formed on the surface 39s of the intermediate insulating film 39, the insulating film 38A constituting the outer peripheral opening 52, and the inner surface 52a of the intermediate insulating film 39, and an embedded electrode portion 71 embedded in the outer peripheral opening 52. In this embodiment, the electrode layer 70 and the embedded electrode portion 71 are formed separately. The electrode layer 70 is formed from a material containing, for example, titanium nitride (TiN), and the embedded electrode portion 71 is formed from a material containing, for example, tungsten (W). The electrode layer 70 can also be said to be a barrier metal layer.

[0173] The electrode layer 70 has an electrode surface 70s and an electrode back surface 70r facing opposite directions. The electrode surface 70s is the surface facing the same side as the surface 39s of the intermediate insulating film 39, and the electrode back surface 70r is the surface facing the intermediate insulating film 39. In this embodiment, the electrode back surface 70r is in contact with the surface 39s of the intermediate insulating film 39.

[0174] The electrode layer 70 has an opening-side electrode layer 73 that contacts the inner surface 52a of the outer peripheral opening 52 and the surface of the guard ring 25a (the substrate surface 30s of the semiconductor substrate 30), and a protruding portion 74 that extends outward from the outer peripheral opening 52. In this embodiment, the opening-side electrode layer 73 and the protruding portion 74 are integrated.

[0175] The protruding portion 74 is the part that covers the intermediate insulating film 39 when viewed from the z direction. When viewed from the z direction, the protruding portion 74 constitutes the part of the field plate 25e that extends outward from the outer peripheral opening 52 in a direction perpendicular to the direction in which the field plate 25e extends, that is, the part that extends outward from the outer peripheral opening 52 in the width direction of the field plate 25e. In this embodiment, when viewed from the z direction, the protruding portion 74 covers the entire guard ring 25a. When viewed from the z direction, the protruding portion 74 has a portion that extends beyond the outer edge of the guard ring 25a. The protruding portion 74 that covers the guard ring 25a and the protruding portion 74 that covers the guard ring 25b are spaced apart from each other.

[0176] The thickness TB of the field plate 25e is thinner than the thickness TA of the emitter electrode 21, as in the first embodiment. In this embodiment, the thickness T10 of the electrode layer 70 is set to be constant. Therefore, it can also be said that the thickness of the protruding portion 74 is set to be constant.

[0177] The thickness T10 of the electrode layer 70 is thinner than the thickness T2 of the electrode body portion 21c of the emitter electrode 21. The thickness T10 of the electrode layer 70 is thinner than the thickness T11 of the embedded electrode portion 71. The thickness T10 of the electrode layer 70 is thinner than the thickness T4 of the intermediate insulating film 39. The thickness T10 of the electrode layer 70 is thinner than the thickness T12 of the thick film portion 61 of the LOCOS oxide film 60. The thickness T10 of the electrode layer 70 is, for example, 2 μm or less, and preferably less than 1 μm. Also, the thickness T10 of the electrode layer 70 is, for example, 50 nm or more. In this embodiment, the thickness T10 of the electrode layer 70 is about 100 nm.

[0178] Here, the thickness T10 of the electrode layer 70 is the thickness of the protrusion 74, which is the portion of the electrode layer 70 formed on the surface 39s of the intermediate insulating film 39. The thickness T10 is the distance in the z direction between the electrode surface 70s and the electrode back surface 70r at the protrusion 74. In this embodiment, the thickness T10 of the electrode layer 70 is the average thickness when the thickness of the protrusion 74 of the electrode layer 70 is measured at multiple locations on the protrusion 74.

[0179] Furthermore, the definition of the electrode layer thickness T10 is not limited to the average thickness described above, but may be changed as follows: The electrode layer thickness T10 may be the maximum thickness when the electrode layer thickness is measured at multiple locations on the electrode layer 70, or it may be the minimum thickness when the electrode layer thickness is measured at multiple locations on the electrode layer 70.

[0180] Furthermore, the thickness T11 of the embedded electrode portion 71 is the distance between the bottom surface 70b formed on the surface of the guard ring 25a (the substrate surface 30s of the semiconductor substrate 30) of the electrode layer 70 and the upper end surface 71a of the embedded electrode portion 71. In this embodiment, the thickness T11 of the embedded electrode portion 71 is the average thickness when the thickness of the embedded electrode portion 71 is measured at multiple locations on the embedded electrode portion 71. In this embodiment, the thickness T11 of the embedded electrode portion 71 is the same as the thickness TB of the field plate 25e.

[0181] Furthermore, the thickness T12 of the thick film portion 61 is the distance between the surface 60s of the thick film portion 61 and the back surface 60r facing the opposite side of the surface 60s. The back surface 60r is in contact with the recess 30a of the semiconductor substrate 30. In other words, the thickness T12 of the thick film portion 61 can also be said to be the distance between the substrate surface 30s and the surface 60s of the thick film portion 61 in the recess 30a of the semiconductor substrate 30. The thickness T12 of the thick film portion 61 is the average thickness when the thickness of the thick film portion 61 is measured at multiple locations.

[0182] Furthermore, the definition of the thickness T11 of the embedded electrode portion 71 is not limited to the average thickness described above, but may be changed as follows: The thickness T11 of the embedded electrode portion 71 may be the maximum thickness when the thickness of the embedded electrode portion 71 is measured at multiple locations on the embedded electrode portion 71, or it may be the minimum thickness when the thickness of the embedded electrode portion 71 is measured at multiple locations on the embedded electrode portion 71.

[0183] Furthermore, even if the thickness T10 of the electrode layer 70 is defined as the maximum thickness when the thickness of the electrode layer 70 is measured at multiple locations on the electrode layer 70, and the thickness T11 of the embedded electrode portion 71 is defined as the minimum thickness when the thickness of the embedded electrode portion 71 is measured at multiple locations, it is preferable that the thickness T10 of the electrode layer 70 is thinner than the thickness T11 of the embedded electrode portion 71.

[0184] Furthermore, the definition of the thickness T12 of the thick film portion 61 is not limited to the average thickness described above, but may be changed as follows: The thickness T12 of the thick film portion 61 may be the maximum thickness when the thickness of the thick film portion 61 is measured at multiple locations on the thick film portion 61, or it may be the minimum thickness when the thickness of the thick film portion 61 is measured at multiple locations on the thick film portion 61.

[0185] The barrier layer 40 is a stepped layer that covers both the intermediate insulating film 39 and the field plate 25e. In other words, the barrier layer 40 has a plate cover portion 41 that covers the field plate 25e. Stepped portions 42 are formed in the plate cover portion 41 that covers both ends of the electrode layer 70 in the width direction. The stepped portions 42 are formed in the barrier layer 40 at the boundary between the tip of the protruding portion 74 of the field plate 25e and the intermediate insulating film 39. Since the protruding portion 74 extends beyond the outer edge of the guard ring 25a when viewed from the z direction, the stepped portions 42 are located outward from the outer edge of the guard ring 25a.

[0186] The plate cover portion 41 of the barrier layer 40 has a shape that conforms to the surface shape of the electrode layer 70 and the upper end surface 71a of the embedded electrode portion 71. The passivation film 13 is laminated on the barrier layer 40.

[0187] In this embodiment, the thickness T5 of the barrier layer 40 is greater than the thickness T10 of the electrode layer 70. Also, the thickness T5 of the barrier layer 40 is greater than or equal to the thickness of the thin film portion 62 of the LOCOS oxide film 60. Furthermore, the thickness T5 of the barrier layer 40 is less than the thickness of the thick film portion 61 of the LOCOS oxide film 60. Note that the thickness T5 of the barrier layer 40 is arbitrary; for example, it may be less than the thickness of the thin film portion 62 of the LOCOS oxide film 60, or less than the thickness T10 of the electrode layer 70.

[0188] (Method of manufacturing semiconductor devices) The manufacturing method of the semiconductor device 10 of this embodiment will be described with reference to Figures 24 to 37. In the manufacturing method of the semiconductor device 10 of this embodiment, the method for forming the insulating film formed on the substrate surface 830s of the semiconductor substrate 830 and the method for forming the electrodes differ from those of the manufacturing method of the semiconductor device 10 of the first embodiment. For this reason, the following description will explain the differences from the first embodiment and omit the description of the manufacturing process common to the first embodiment. Also, for convenience, the manufacturing method of the semiconductor device 10 of this embodiment will mainly describe the manufacturing process of the cell region 11 and the FLR portion 25.

[0189] As shown in Figures 24 to 26, the manufacturing method of the semiconductor device 10 of this embodiment includes a step of forming a LOCOS oxide film 850. As shown in Figure 24, first, a semiconductor substrate 830 formed from a material containing Si is prepared. A drift layer 33 is formed on the semiconductor substrate 830. Next, an oxide film 851 is formed over the entire substrate surface 830s of the semiconductor substrate 830, for example by CVD. The oxide film 851 has, for example, a silicon oxide film (SiO2 film). Next, a mask 852 is formed over the entire surface 851s of the oxide film 851, for example by CVD. The mask 852 has, for example, a silicon nitride film (Si3N4 film).

[0190] Next, as shown in Figure 25, the mask 852 is selectively etched. This partially exposes the oxide film 851 from the mask 852. Thus, it can be said that the mask 852 is formed on a portion of the surface of the drift layer 33. Subsequently, as shown in Figure 26, the oxide film 851 is thermally grown. This increases the thickness of the portion of the oxide film 851 not covered by the mask 852. On the other hand, the thermal growth of the oxide film 851 is suppressed in the portion covered by the mask 852. As a result, the oxide film 851 becomes partially thicker. Through these steps, the LOCOS oxide film 850 is formed. Next, the mask 852 is removed.

[0191] As shown in Figure 27, the manufacturing method of the semiconductor device 10 of this embodiment includes a step of forming a p-type well region 834, which is a second conductivity type semiconductor region. Specifically, p-type impurities are selectively implanted into the substrate surface 830s of the semiconductor substrate 830. Subsequently, the p-type impurities are diffused by heat treatment of the semiconductor substrate 830. This forms the well region 834. Here, the well region 834 includes a well region 34A (see Figure 28) and guard rings 25a to 25d. In Figure 27, guard rings 25a to 25c are shown.

[0192] Although not shown in the figures, the manufacturing method of the semiconductor device 10 in this embodiment includes the same steps as in the first embodiment, of forming a trench 835, an insulating film 838, a gate trench 22A and an emitter trench 21A, a base region 34, an emitter region 36, and a channel stop region 26a in the cell region 11. The insulating film 838 is formed over both the cell region 11 and the outer peripheral region 12. In the outer peripheral region 12, the insulating film 838 is formed on the surface 851s of the oxide film 851 (see Figure 28).

[0193] As shown in Figure 28, the manufacturing method of the semiconductor device 10 of this embodiment includes a step of forming an intermediate insulating film 839. The method of forming the intermediate insulating film 839 is the same as in the first embodiment. The intermediate insulating film 839 is formed on the surface 838s of the insulating film 838. Here, in this embodiment, the steps of forming the insulating film 838 and the intermediate insulating film 839 correspond to the "step of forming an insulating film that covers a plurality of cells in the cell region". The steps of forming the LOCOS oxide film 850, the insulating film 838, and the intermediate insulating film 839 correspond to the "step of forming an outer peripheral insulating film that covers the surface of the first semiconductor layer and the surface of the second semiconductor region".

[0194] As shown in Figure 29, the manufacturing method of the semiconductor device 10 in this embodiment includes the steps of forming openings 861 and 862, and forming the base contact region 37 and contact regions 34B and 25p. The method for forming the openings 861 and 862 is the same as in the first embodiment. This forms the LOCOS oxide film 60, the insulating film 38, and the intermediate insulating film 39. The method for forming the base contact region 37 and contact regions 34B and 25p is also the same as in the first embodiment. Note that Figure 29 shows the base contact region 37 and contact region 25p.

[0195] As shown in Figure 30, the manufacturing method of the semiconductor device 10 of this embodiment includes a step of forming a first electrode layer 870. The first electrode layer 870 is a component corresponding to the electrode layer 70 and the barrier metal layer 21e. The first electrode layer 870 is formed from a material containing, for example, Ti or TiN, and is formed by sputtering on the surface 39s and openings 861, 862 of the intermediate insulating film 39. Therefore, the first electrode layer 870 is formed to be in contact with the base contact region 37 exposed by the opening 861 and the contact region 25p of the guard rings 25a to 25d. Furthermore, the first electrode layer 870 is formed over the entire surface 39s of the intermediate insulating film 39. Thus, in the step of forming the first electrode layer 870, the first electrode layer 870 is formed in both the cell region 11 and the outer peripheral region 12. In other words, the process of forming the first electrode layer 870 in the process of forming the emitter electrode 21 is carried out in the same way as the process of forming the first electrode layer 870 in the process of forming the gate fingers 23A, 23B, emitter routing section 24, field plates 25e to 25h, and equipotential ring 26.

[0196] As shown in Figures 31 and 32, the manufacturing method of the semiconductor device 10 of this embodiment includes a step of forming an embedded electrode portion 871. The embedded electrode portion 871 is a component corresponding to the embedded electrode portions 21b and 71.

[0197] As shown in Figure 31, first, the embedded electrode portion 871 is formed from a material containing, for example, W (tungsten), and is formed on the first electrode layer 870 by CVD. The embedded electrode portion 871 is embedded in the openings 861 and 862 and is formed to extend above the openings 861 and 862.

[0198] Next, as shown in Figure 32, the embedded electrode portion 871 is etched back. This forms the embedded electrode portion 21b in the cell region 11 and the embedded electrode portion 71 corresponding to the guard rings 25a to 25d. Thus, in the process of forming the embedded electrode portion 871, the embedded electrode portion 871 is formed in both the cell region 11 and the outer peripheral region 12. In other words, the process of forming the embedded electrode portion 871 in the process of forming the emitter electrode 21 is carried out in the same process as the process of forming the embedded electrode portion 871 in the process of forming the gate fingers 23A, 23B, the emitter routing portion 24, and the field plates 25e to 25h.

[0199] As shown in Figure 33, the manufacturing method of the semiconductor device 10 in this embodiment includes a step of forming a second electrode layer 872. The second electrode layer 872 is a component corresponding to the electrode body portion 21c. The second electrode layer 872 is formed from a material containing AlCu, for example, and is formed on the first electrode layer 870 and the embedded electrode portion 71 by sputtering. As can be seen from Figure 33, the second electrode layer 872 is formed such that its thickness is greater than the thickness of the first electrode layer 870. In this way, in the step of forming the second electrode layer 872, the second electrode layer 872 is formed in both the cell region 11 and the outer peripheral region 12. In other words, the step of forming the second electrode layer 872 in the step of forming the emitter electrode 21 is carried out in the same step as the step of forming the second electrode layer 872 in the step of forming the gate fingers 23A, 23B, the emitter routing portion 24, the field plates 25e to 25h, and the equipotential ring 26.

[0200] As shown in Figures 34 to 37, the manufacturing method of the semiconductor device 10 in this embodiment includes a step of etching the second electrode layer 872 in the outer peripheral region 12. As shown in Figure 34, a mask 880 is formed on the second electrode layer 872. Multiple openings 881 are formed in the portion of the mask 880 that covers the outer peripheral region 12. The second electrode layer 872 is exposed through the multiple openings 881. In Figure 34, the mask 880 is formed in the portion of the second electrode layer 872 where the field plates 25e to 25g are formed. Although not shown, the mask 880 is also formed in the portion where the field plate 25h is formed.

[0201] Next, as shown in Figure 35, the second electrode layer 872 exposed from each opening 881 is etched. As a result, in the second electrode layer 872 covering the cell region 11, the openings 881 are formed to conform to the outer shape of the emitter electrode 21, and the electrode body portion 21c is formed by etching the second electrode layer 872. This forms the emitter electrode 21. In the second electrode layer 872 covering the outer peripheral region 12, after the second electrode layer 872 is etched through the openings 881, the first electrode layer 870 exposed from each opening 881 is etched. This forms the electrode layer 70. After that, the mask 880 is removed. Figure 35 shows the state after the mask 880 has been removed.

[0202] Next, as shown in Figure 36, a mask 890 is formed on the second electrode layer 872 of the cell region 11. That is, the second electrode layer 872 in the outer peripheral region 12 is exposed from the mask 890. Subsequently, as shown in Figure 37, the second electrode layer 872 in the outer peripheral region 12 is removed by etching.

[0203] Although not shown in the figures, the manufacturing method of the semiconductor device 10 in this embodiment includes a step of forming a barrier layer 840, similar to the first embodiment. The barrier layer 840 is formed to cover the electrode body portion 21c and the electrode layer 70 and the embedded electrode portion 71. The subsequent manufacturing steps are the same as in the first embodiment.

[0204] (Effects of the second embodiment) According to this embodiment, in addition to the effects of the first embodiment, the following effects can be obtained. (2-1) The thickness T10 of the electrode layer 70 is thinner than the thickness T5 of the barrier layer 40.

[0205] With this configuration, the stepped portion 42 of the barrier layer 40 covering the electrode layer 70 of the field plate 25e to 25h becomes smaller, thus further suppressing the occurrence of cracks caused by the stepped portion 42.

[0206] (2-2) The thickness T10 of the electrode layer 70 of the field plates 25e to 25h is less than 1 μm (in this embodiment, the thickness T10 is about 100 nm). This configuration yields the same effect as described in (2-1) above.

[0207] (2-3) The thickness T10 of the electrode layer 70 is thinner than the thickness T4 of the intermediate insulating film 39. With this configuration, cracks are less likely to occur in the stepped portion of the barrier layer 40 covering the field plate 25e~25h, and thus the passage of external ions through the barrier layer 40 due to cracks can be further suppressed.

[0208] (2-4) The thickness T10 of the electrode layer 70 is thinner than the thickness T6 of the insulating film 38A. With this configuration, cracks are less likely to occur in the stepped portions of the barrier layer 40 covering the field plates 25e to 25h, thus further suppressing the passage of external ions through the barrier layer 40 due to cracks.

[0209] (2-5) The thickness T10 of the electrode layer 70 is thinner than the thickness T12 of the thick film portion 61 of the LOCOS oxide film 60. With this configuration, cracks are less likely to occur in the stepped portions of the barrier layer 40 covering the field plates 25e to 25h, thus further suppressing the passage of external ions through the barrier layer 40 due to cracks.

[0210] [Example of changes] The embodiments described above are illustrative of possible forms of the semiconductor device according to this disclosure and are not intended to limit its form. The semiconductor device according to this disclosure may take forms different from those illustrated in the embodiments described above. One example is a form in which some of the configurations of the embodiments described above are replaced, modified, or omitted, or a form in which new configurations are added to the embodiments described above. Furthermore, the following modifications can be combined with each other as long as they do not contradict each other technically. In the following modifications, parts common to the embodiments described above are denoted by the same reference numerals as in the embodiments described above, and their descriptions are omitted.

[0211] In the first embodiment, the shape of the protrusions 28a of the field plates 25e to 25h can be arbitrarily changed. For example, the curved surface 28c may be omitted from the protrusion 28a. Alternatively, the curved surface 28c and the inclined surface 28b may be omitted from the protrusion 28a. In this case, the cross-sectional shape of the plate body portion 28 including the protrusion 28a, when cut by a plane along its width direction and z direction, is rectangular.

[0212] Furthermore, the inclined surface 28b of the protruding portion 28a does not have to be curved. In the cross-sectional shape of the plate body portion 28 cut by a plane along its width direction and z direction, the inclined surface 28b may be straight. In this case, the cross-sectional shape of the plate body portion 28 cut by a plane along its width direction and z direction will be trapezoidal.

[0213] Furthermore, in the first embodiment, the shape of the protrusions 28a of the field plates 25e to 25h was the shape when the field plates 25e to 25h were formed by wet etching, but this is not limited to this. For example, the shape of the protrusions 28a of the field plates 25e to 25h may be the shape when the field plates 25e to 25h were formed by dry etching.

[0214] In the first embodiment, the thickness T1 of the protruding portion 28a of the field plate 25e to 25h may be thinner than the thickness T4 of the intermediate insulating film 39. With this configuration, cracks are less likely to occur in the stepped portion of the barrier layer 40 covering the field plate 25e to 25h, and thus the passage of external ions through the barrier layer 40 due to cracks can be further suppressed.

[0215] In the first embodiment, the thickness T1 of the protruding portion 28a of the field plate 25e to 25h may be thinner than the thickness T6 of the insulating film 38A. With this configuration, cracks are less likely to occur in the stepped portion of the barrier layer 40 covering the field plate 25e to 25h, and thus the passage of external ions through the barrier layer 40 due to cracks can be further suppressed.

[0216] In the first embodiment, the thickness T1 of the protrusions 28a of the field plates 25e to 25h may be equal to the thickness T5 of the barrier layer 40. Alternatively, the thickness T1 of the protrusions 28a may be thinner than the thickness T5 of the barrier layer 40.

[0217] In the second embodiment, the field plates 25e to 25h may have a configuration in which a second electrode layer 872 is formed on the electrode layer 70 and the embedded electrode portion 71. In this case, the second electrode layer 872 is etched such that the thickness T1 of the protruding portion 28a, which is the distance between the surface of the second electrode layer 872 and the surface 39s of the intermediate insulating film 39, is thinner than the thickness T2 of the electrode body portion 21c.

[0218] In the second embodiment, the thickness T10 of the electrode layer 70 may be equal to the thickness T5 of the barrier layer 40. Alternatively, the thickness T10 of the electrode layer 70 may be thicker than the thickness T5 of the barrier layer 40.

[0219] In the second embodiment, the thickness T10 of the electrode layer 70 may be greater than or equal to the thickness T4 of the intermediate insulating film 39. In the second embodiment, the thickness T10 of the electrode layer 70 may be greater than or equal to the thickness T6 of the insulating film 38A.

[0220] In each embodiment, the positional relationship between the protrusions 28a of the field plates 25e to 25h and the outer edges of the guard rings 25a to 25d can be arbitrarily changed. When viewed from the z direction, the tip of the protrusion 28a may be positioned to overlap with the outer edges of the guard rings 25a to 25d, or it may be positioned to be inward from the outer edges of the guard rings 25a to 25d.

[0221] In the first embodiment, the thickness of at least one of the gate fingers 23A, 23B, the emitter routing portion 24, and the equipotential ring 26 may be greater than or equal to the thickness T2 of the electrode body portion 21c of the emitter electrode 21.

[0222] In the second embodiment, at least one of the gate fingers 23A, 23B, the emitter routing portion 24, and the equipotential ring 26 may have a second electrode layer 872. In the first embodiment, the structure of the insulating film 38A may be changed to a laminated structure of LOCOS oxide film 60 and insulating film 38, which is the structure of the insulating film 38A in the second embodiment.

[0223] In the second embodiment, the configuration of the insulating film 38A may be changed to a laminated structure of substrate-side insulating film 38B and insulating film 38, which is the configuration of insulating film 38A in the first embodiment. In each embodiment, both the insulating film 38 and the intermediate insulating film 39 are formed as common insulating films for both the cell region 11 and the outer peripheral region 12, but this is not limited to this. For example, the insulating film 38 and intermediate insulating film 39 covering the cell region 11 and the insulating film 38 and intermediate insulating film 39 covering the outer peripheral region 12 may be formed separately. In this case, the insulating film 38 and intermediate insulating film 39 covering the outer peripheral region 12 correspond to the "outer peripheral insulating film".

[0224] In each embodiment, the semiconductor device 10 may be a planar gate type IGBT instead of a trench gate type IGBT. In each embodiment, the semiconductor device 10 is embodied as an IGBT, but it is not limited to this, and the semiconductor device 10 may be, for example, a SiCMOSFET (metal-oxide-semiconductor field-effect transistor) or a SiMOSFET.

[0225] As used in this disclosure, the term “on / above” includes the meanings of “on / above” and “above / beyond” unless the context clearly indicates otherwise. Therefore, the expression “A is formed on B” is intended to mean that in this embodiment, A may be in contact with B and directly positioned on B, but as a modified example, A may be positioned above B without contacting B. In other words, the term “on / above” does not preclude structures in which other members are formed between A and B.

[0226] The z-direction used in this disclosure does not necessarily have to be vertical, nor does it have to coincide perfectly with the vertical. Therefore, the various structures described herein are not limited to the z-direction "up" and "down" being the same as the z-direction "up" and "down" being the same as the vertical. For example, the x-direction may be vertical, or the y-direction may be vertical.

[0227] In this specification, the phrase "at least one of A and B" should be understood to mean "A alone, or B alone, or both A and B." [Note] The technical concepts that can be understood from each of the above embodiments and their respective modifications are described below. The reference numerals for the components of the embodiments corresponding to the components described in each appendix are shown in parentheses. These reference numerals are provided as examples to aid understanding, and the components described in each appendix should not be limited to those indicated by these reference numerals.

[0228] (Note 1) A cell region (11) in which multiple cells (11A) are formed, The cell region (11) is surrounded by an outer peripheral region (12) located outside the cell region (11), The cell region (11) includes: an insulating film (38, 39) covering the plurality of cells (11A); an electrode portion (21) having a stacked portion (21c) laminated on the insulating film (38, 39). The outer peripheral region (12) includes: a first semiconductor layer (33) of a first conductivity type; second semiconductor regions (25a to 25d) of a second conductivity type partially formed in the first semiconductor layer (33); an outer peripheral insulating film (38A, 39) covering the surface (30s) of the first semiconductor layer (33) and the surface (30s) of the second semiconductor regions (25a to 25d), and having an opening (52) that exposes a part of the surface (30s) of the second semiconductor regions (25a to 25d); an outer peripheral electrode portion (25e to 25h) that protrudes laterally from the opening (52) and is laminated on the outer peripheral insulating film (38A, 39), and that contacts a portion of the surface (30s) of the second semiconductor regions (25a to 25d) exposed by the opening (52); a barrier layer (40) covering both the outer peripheral insulating film (38A, 39) and the outer peripheral electrode portion (25e to 25h) and having a smaller diffusion coefficient than the outer peripheral insulating film (38A, 39); a passivation film (13) laminated on the barrier layer (40) and having a larger diffusion coefficient than the barrier layer (40). The thickness (T2 / T) of the protruding portion (28a / 74) is thinner than the thickness (T1) of the stacked portion (21c). A semiconductor device (10).

[0229] (Appendix 2) The thickness (T2 / T) of the protruding portion (28a / 74) is thinner than the thickness (T3) of the outer peripheral insulating film (38A, 39). The semiconductor device according to Appendix 1.

[0230] (Appendix 3) The outer peripheral electrode portion (25e to 25h) has an embedded electrode portion (27) embedded in the opening (52). The protruding portion (28a) and the embedded electrode portion (27) are integrated. Semiconductor device as described in Appendix 1 or 2.

[0231] (Note 4) The outer peripheral electrode portion (25e~25h) has an electrode layer (70) formed on the surface (39s) of the outer peripheral insulating film (38A, 39) and on the inner surface (52a) of the outer peripheral insulating film (38A, 39) that constitutes the opening (52), and an embedded electrode (71) embedded in the opening (52). The protruding portion (74) is formed by the electrode layer (70). Semiconductor device as described in Appendix 1 or 2.

[0232] (Note 5) The thickness (T2 / T10) of the aforementioned protrusion (28a / 74) is 2 μm or less. A semiconductor device as described in any one of the appendices 1 to 4.

[0233] (Note 6) The aforementioned protrusions (28a / 74) cover the entire second semiconductor region (25a / 25b / 25c / 25d) when viewed from the thickness direction (z direction) of the first semiconductor layer (33). A semiconductor device as described in any one of the appendices 1 to 5.

[0234] (Note 7) The aforementioned protrusions (28a / 74) have portions that extend beyond the outer edge of the second semiconductor region (25a / 25b / 25c / 25d) when viewed from the thickness direction (z direction) of the first semiconductor layer (33). Semiconductor device as described in Appendix 6.

[0235] (Note 8) The protruding portion (28a) has an inclined surface (28b) that slopes toward the outer peripheral insulating film (38A, 39) as it approaches the lateral tip of the protruding portion (28a). Semiconductor device as described in Appendix 3.

[0236] (Note 9) The outer peripheral electrode portions (25e to 25h) are The surface (25s) of the outer peripheral electrode portions (25e to 25h) that is farthest from the outer peripheral insulating films (38A, 39), and the curved surface (25c) that connects the inclined surface (25b) and the surface (25s). The semiconductor device according to appended note 8.

[0237] (Appended note 10) The inclined surface (28b) is curved. The semiconductor device according to appended note 8 or 9.

[0238] (Appended note 11) The thickness (T5) of the barrier layer (40) is thinner than the thickness of the passivation film (13). The semiconductor device according to any one of appended notes 1 to 10.

[0239] (Appended note 12) The thickness (T10) of the protrusion (74) is thinner than the thickness (T5) of the barrier layer (40). The semiconductor device according to any one of appended notes 1 to 11.

[0240] (Appended note 13) The thickness (T5) of the barrier layer (40) is thinner than the thickness (T2) of the protrusion (28a). The semiconductor device according to any one of appended notes 1 to 11.

[0241] (Appended note 14) The outer peripheral insulating films (38A, 39) are silicon oxide films, The passivation film (13) is an organic insulating film, The barrier layer (40) is a silicon nitride film. The semiconductor device according to any one of appended notes 1 to 13.

[0242] (Appended note 15) A cell region (11) in which a plurality of cells (11A) are formed, The cell region (11) is surrounded by an outer peripheral region (12) located outside the cell region (11), The aforementioned cell region (11) is An insulating film (38, 39) covering the plurality of cells (11A), The device comprises an electrode portion (21) having a laminated portion (21c) stacked on the insulating film (38,39), The aforementioned outer peripheral region (12) is A first semiconductor layer (33) of the first conductivity type, A second semiconductor region (25a to 25d) of the second conductivity type partially formed in the first semiconductor layer (33), An outer peripheral insulating film (38A, 39) formed of a silicon oxide film covers the surface (30s) of the first semiconductor layer (33) and the surface (30s) of the second semiconductor region (25a~25d), and has an opening (52) that exposes a part of the surface (30s) of the second semiconductor region (25a~25d), The outer electrode portion (25e~25h) has a protrusion (28a / 74) that protrudes laterally from the opening (52) and is laminated on the outer peripheral insulating film (38A,39), and is in contact with the portion of the surface (30s) of the second semiconductor region (25a~25d) that is exposed by the opening (52), A barrier layer (40) formed of a silicon nitride film covers both the outer peripheral insulating film (38A, 39) and the outer peripheral electrode portion (25e~25h), The barrier layer (40) is laminated with a passivation film (13) formed of an organic insulating film, The thickness (T2 / T10) of the protruding portion (28a / 74) is thinner than the thickness (T1) of the laminated portion (21c). Semiconductor equipment.

[0243] (Note 16) A cell region (11) in which multiple cells (11A) are formed, A method for manufacturing a semiconductor device (10) comprising an outer peripheral region (12) provided outside the cell region (11) so as to surround the cell region (11), A step of forming insulating film (838, 839) covering the plurality of cells (11A) in the cell region (11), A step of forming electrode portions (821, 822) having laminated portions (822) stacked on the insulating film (838, 839), A step of forming a first semiconductor layer (33) of the first conductivity type in the outer peripheral region (12), A step of partially forming a second semiconductor region (25a to 25d) of the second conductivity type in the first semiconductor layer (33), A step of forming an outer peripheral insulating film (38A, 39) that covers the surface (30s) of the first semiconductor layer (33) and the surface (30s) of the second semiconductor region (25a~25d), A step of forming an opening (862) in the outer peripheral insulating film (838B / 850, 838, 839) that exposes a part of the surface (30s) of the second semiconductor region (25a~25d), A step of forming an outer peripheral electrode portion (25e~25h) having a protruding portion (28a / 74) that protrudes laterally from the opening (862) and is laminated on the outer peripheral insulating film (838B, 838, 839), and which is in contact with the portion of the second semiconductor region (834 / 25a~25d) exposed by the opening (862), A step of forming a barrier layer (840) having a smaller diffusion coefficient than the outer peripheral insulating film (838B / 850, 838, 839) so as to cover both the outer peripheral insulating film (838B / 850, 838, 839) and the outer peripheral electrode portion (25a~25h), The process includes laminating a passivation film (13) with a diffusion coefficient greater than that of the barrier layer (840) onto the barrier layer (840), In the process of forming the outer peripheral electrode portion (25a~25h), the thickness (T2 / T10) of the protruding portion (28a / 74) is formed to be thinner than the thickness (T1) of the laminated portion (822 / 21c). A method for manufacturing a semiconductor device.

[0244] (Note 17) The step of forming the electrode portion (21) includes the step of forming electrode layers (821, 822) on both the insulating film (838, 839) and the outer peripheral insulating film (838B / 850, 838, 839), The step of forming the outer peripheral electrode portion (25e~25h) includes a step of making the thickness of the portion of the electrode layer (821,822) formed on the outer peripheral insulating film (838B / 850,838,839) thinner than the thickness of the portion formed on the insulating film (838,839). The method for manufacturing a semiconductor device as described in Appendix 15.

[0245] (Note 18) The process of forming the outer peripheral electrode portion (25e~25h) is as follows: A step of forming a first electrode layer (870) on the surface of the outer peripheral insulating film (838B / 850, 838, 839) and on the inner surface of the outer peripheral insulating film (838B / 850, 838, 839) that constitutes the opening (862), A step of forming an embedded electrode portion (871) which has a thickness greater than the first electrode layer (870) and is embedded in the opening (862), A step of forming a second electrode layer (872) on the insulating film (838, 839), on the outer peripheral insulating film (838B / 850, 838, 839), and on the embedded electrode portion (871), The process includes removing the portion of the second electrode layer (872) that is on the outer peripheral insulating film (838B / 850, 838, 839) and the portion that is on the first electrode layer (871). The method for manufacturing a semiconductor device as described in Appendix 15.

[0246] (Note 19) The step of forming the electrode portion (21) is as follows: The steps include forming the first electrode layer (870) on the inner surface of the cell opening (861) that penetrates the insulating film (838, 839) and on the surface of the insulating film (838, 839), A step of forming an embedded electrode portion (871) which has a thickness greater than the first electrode layer (870) and is embedded in the cell opening (861), The process includes the step of forming the second electrode layer (872) on the embedded electrode portion (871) and on the insulating film (838, 839), The step of forming the first electrode layer (870) in the step of forming the electrode portion (21) is carried out in the same way as the step of forming the first electrode layer (870) in the step of forming the outer peripheral electrode portion (25e~25h). The step of forming the embedded electrode portion (871) in the step of forming the electrode portion (21) is carried out in the same way as the step of forming the embedded electrode portion (871) in the step of forming the outer peripheral electrode portion (25e~25h). The step of forming the second electrode layer (872) in the step of forming the electrode portion (21) is carried out in the same way as the step of forming the second electrode layer (872) in the step of forming the outer peripheral electrode portion (25e~25h). The method for manufacturing a semiconductor device as described in Appendix 18.

[0247] (Note 20) The step of forming the outer peripheral insulating film (838B / 850, 838, 839) is as follows: A step of forming a first insulating film (838B / 850,838) by thermal oxidation of both the surface (830s) of the first semiconductor layer (33) and the surface (830s) of the second semiconductor region (25a~25d), The process includes the step of forming a second insulating film (839) on the surface of the first insulating film (838B, 838) by CVD, In the step of forming the barrier layer (840), the barrier layer (840) is formed on the surface of the second insulating film (839). A method for manufacturing a semiconductor device as described in any one of the appendices 16 to 19.

[0248] (Note 21) The step of forming the first insulating film (850) is as follows: A step of forming a mask (852) on a part of the surface (830s) of the first semiconductor layer (33) and the surface (830s) of the second semiconductor region (25a~25d), The process includes a step of oxidizing the portion of the surface (830s) of the first semiconductor layer (33) and the surface (830s) of the second semiconductor region (25a~25d) that is exposed from the mask (852) to form a thermal oxide film (851). The method for manufacturing a semiconductor device as described in Appendix 20.

[0249] (Note 22) The step of forming the first insulating film (838B) is as follows: A step of forming a first insulating layer (838B) by thermal oxidation of both the surface (830s) of the first semiconductor layer (33) and the surface (830s) of the second semiconductor region (25a~25d), The process includes a step of wet etching the first insulating layer (838B) followed by dry etching. The method for manufacturing a semiconductor device as described in Appendix 20.

[0250] (Note 23) A cell region (11) in which multiple cells (11A) are formed, A method for manufacturing a semiconductor device (10) comprising an outer peripheral region (12) provided outside the cell region (11) so as to surround the cell region (11), A step of forming insulating film (838, 839) covering the plurality of cells (11A) in the cell region (11), A step of forming electrode portions (821, 822) having laminated portions (822) stacked on the insulating film (838, 839), A step of forming a first semiconductor layer (33) of the first conductivity type in the outer peripheral region (12), A step of partially forming a second semiconductor region (25a to 25d) of the second conductivity type in the first semiconductor layer (33), A step of forming an outer peripheral insulating film (838B / 850) formed by a silicon oxide film covering the surface (830s) of the first semiconductor layer (33) and the surface (830s) of the second semiconductor region (25a~25d), A step of forming an opening (862) in the outer peripheral insulating film (838B / 850, 838, 839) that exposes a part of the surface (830s) of the second semiconductor region (25a~25d), A step of forming an outer peripheral electrode portion (25e~25h) which has a protruding portion that protrudes laterally from the opening (862) and is laminated on the outer peripheral insulating film (838B / 850,838,839), and which is in contact with the portion of the second semiconductor region (25a~25d) that is exposed by the opening (862), A step of forming a barrier layer (840) made of a silicon nitride film so as to cover both the outer peripheral insulating film (838B / 850, 838, 839) and the outer peripheral electrode portion (25e~25h), The process includes a step of laminating a passivation film (13) formed of an organic insulating film onto the barrier layer (840), In the process of forming the outer peripheral electrode portion (25e~25h), the thickness (T2 / T10) of the protruding portion (28a / 870) is formed to be thinner than the thickness (T1) of the laminated portion (822 / 21c). A method for manufacturing a semiconductor device. [Explanation of symbols]

[0251] 10… Semiconductor equipment 11…Cell area 11A... Main cell (cell) 12...Outer area 13… Passivation membrane 21…Emitter electrode 21c... Electrode body (laminated section) 22… gate 23... Gate Finger 23ba...Implanted electrode section 23bc…Protrusion 24...Emitter routing section 24a...Embedded electrode section 24c...Protruding part 25...FLR section 25a~25d...Guard ring (second semiconductor region) 25e~25h...Field plate (outer electrode section) 25s…Surface 27…Implanted electrode section 28a...Protruding part 28b…Slanted surface 28c... curved surface 28s…Surface 30… Semiconductor substrates 30s…Substrate surface (surface of the first semiconductor layer, surface of the second semiconductor region) 33…Drift layer (first semiconductor layer) 34A...Base area 35...Trench 36…Emitter region 37…Base contact area 38…Insulating film 38A…Insulating film 39…Interlayer film 40… Barrier layer 41... Stepped section 51... Inner circumferential opening 52, 53, 54... Perimeter openings (openings) 52a...Inner surface 60…LOCOS oxide film 70...electrode layer 71…Implanted electrode section 74...Protruding part T1...Thickness of the protruding part T2...Thickness of the laminated layer T3... The total thickness of insulating film 38A and the intermediate insulating film 39 (thickness of the outer insulating film) T5... Barrier layer thickness T10...Thickness of the electrode layer

Claims

1. A cell region in which multiple cells are formed, An outer peripheral region is provided outside the cell region so as to surround the cell region, Equipped with, The aforementioned cell region is An insulating film covering the plurality of cells, An electrode portion having a laminated portion and an embedded electrode portion stacked on the insulating film, A first semiconductor layer of the first conductivity type, A second semiconductor region of a second conductivity type partially formed in the first semiconductor layer, A plurality of gate structures are arranged spaced apart in a first direction in a plan view, each comprising an electrode material electrically connected to a gate electrode and a gate insulating layer, A barrier layer that covers both the insulating film and the electrode portion and has a smaller diffusion coefficient than the insulating film, A passivation film laminated on the barrier layer and having a diffusion coefficient greater than that of the barrier layer, Equipped with, The insulating film covers the surface of the first semiconductor layer and the electrode material of the plurality of gate structures, and includes a plurality of openings that expose a portion of the surface of the cell region. At least one of the plurality of openings is provided between the plurality of gate structures, The embedded electrode portion is embedded in the opening provided between the plurality of gate structures. The barrier layer, viewed from the thickness direction of the first semiconductor layer, has a portion that is formed in a first direction with respect to the openings provided between the plurality of gate structures. Semiconductor equipment.

2. The barrier layer is in contact with the electrode portion. The semiconductor device according to claim 1.

3. The gate structure is a planar type gate structure. The semiconductor device according to claim 1.

4. The thickness of the barrier layer is thinner than the thickness of the passivation film. The semiconductor device according to claim 1.

5. A cell region in which multiple cells are formed, An outer peripheral region is provided outside the cell region so as to surround the cell region, Equipped with, The aforementioned cell region is An insulating film formed by a silicon oxide film covering the plurality of cells, An electrode portion having a laminated portion and an embedded electrode portion stacked on the insulating film, A first semiconductor layer of the first conductivity type, A second semiconductor region of a second conductivity type partially formed in the first semiconductor layer, A plurality of gate structures are arranged spaced apart in a first direction in a plan view, each comprising an electrode material electrically connected to a gate electrode and a gate insulating layer, A barrier layer formed of a silicon nitride film covers both the insulating film and the electrode portion, A passivation film formed of an organic insulating film is laminated on the barrier layer, Equipped with, The insulating film covers the surface of the first semiconductor layer and the electrode material of the plurality of gate structures, and includes a plurality of openings that expose a portion of the surface of the cell region. At least one of the plurality of openings is provided between the plurality of gate structures, The embedded electrode portion is embedded in the opening provided between the plurality of gate structures. The barrier layer, viewed from the thickness direction of the first semiconductor layer, has a portion that is formed in a first direction with respect to the openings provided between the plurality of gate structures. Semiconductor equipment.

Images