Semiconductor device and method for manufacturing a semiconductor device

Abstract

To provide: a semiconductor device in which voids in a bonding layer can be reduced more than in the past and a substrate and a semiconductor chip are joined by sintering; and a method for manufacturing a semiconductor device in which a solvent in a bonding layer raw material paste can be removed in a shorter time than in the past.SOLUTION: A semiconductor device according to the present invention includes a substrate 113, a semiconductor chip 100, and a bonding layer 110 for bonding the substrate 113 and the semiconductor chip 100. The bonding layer 110 is made of sintered metal and has concave portions 111 constricted toward the center of the bonding layer 110 when the semiconductor device is viewed from above.SELECTED DRAWING: Figure 1B

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

Background Art

[0002] Sintering bonding for joining a substrate and a semiconductor chip constituting a semiconductor device is generally a technique for joining a semiconductor chip to a substrate by a bonding layer obtained by sintering metal particles having a diameter of nanometers to submicrons. The sintering bonding process is approximately as follows. First, as a coating process, a paste serving as a raw material for a bonding layer in which metal particles are dispersed is supplied onto a substrate using a printer or a dispenser. Next, as a preliminary drying process, the solvent contained in the paste is dried by heating or the like. Next, a semiconductor chip is mounted on the dried sintered metal. Finally, as a sintering process (furnace passing process), the metal particles are sintered by applying pressure and heat to join the substrate and the chip via a sintering layer. However, the above process is merely an example, and various forms are conceivable for the sintering bonding process, such as a case where pressure is not required. In the above sintering bonding, if the solvent contained in the paste remains at the time of sintering, voids (cavities) may be formed in the bonding layer, which may cause poor bonding. Therefore, the development of a technique capable of reducing these voids is desired.

[0003] As a conventional technique for sintering a substrate and a semiconductor chip, for example, Patent Document 1 describes a method for manufacturing a structure in which a sintered metal layer 34 is placed on the contact surfaces 16, 56 of a first element (substrate) 10 and a second bonding element (power semiconductor element) 50. The method includes the steps of applying a layer of sintered paste 30, consisting of sintered metal particles and a solvent, to the first contact surface 16; applying heat to the sintered paste 30 to expel the solvent so as to form a sintered layer 32; placing the second bonding element 50; and further applying heat and pressure to convert the sintered layer into a homogeneous sintered metal layer 34. In other words, in the sintering bonding step of the manufacturing method in Patent Document 1, after applying a sintered paste containing sintered metal particles and a solvent, which are the raw materials for the sintered metal layer, to the substrate, the paste is heated to expel the solvent before mounting the semiconductor chip. It is said that a uniform bonding layer with a maximum void diameter of 10 μm can be obtained by such a manufacturing method. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2011-249801 [Overview of the project] [Problems that the invention aims to solve]

[0005] After the semiconductor chip is mounted, the top surface of the paste becomes the contact surface with the semiconductor chip. As a result, the solvent only escapes from the edges of the paste applied to the substrate, and the central part of the paste tends to retain solvent. This tendency is particularly pronounced in large-area bonding layers applied to large-area semiconductor chips mounted on high-heat-resistant power modules used in electric railways, electric vehicles, and industrial applications. Therefore, a technology was needed to remove the solvent that tends to remain, especially in the central part of the paste.

[0006] In the technology described in Patent Document 1, heating is performed before mounting the semiconductor chip to remove the solvent in advance during the pre-drying process, thereby reducing the likelihood of voids forming in the bonding layer and obtaining a uniform bonding layer.

[0007] However, considering production efficiency, it is desirable to effectively remove the solvent by heating during the sintering process after semiconductor chip mounting, as this would shorten the pre-drying process or eliminate the pre-drying process altogether.

[0008] In view of the above objectives, the present invention aims to provide a semiconductor device in which a substrate and a semiconductor chip are joined by sintering bonding, which can reduce voids in the bonding layer compared to conventional methods, and to provide a method for manufacturing a semiconductor device that can remove solvents in the bonding layer raw material paste in a shorter time than conventional methods. [Means for solving the problem]

[0009] To achieve the above objective, one aspect of the present invention provides a semiconductor device having a substrate, a semiconductor chip, and a bonding layer that bonds the substrate and the semiconductor chip, wherein the bonding layer is made of sintered metal and, when the semiconductor device is viewed in plan view, has a constricted recess toward the center of the bonding layer Furthermore, only one recess is provided on each side of the semiconductor chip, and the four corners of the bonding layer and the deep portion of the recess are positioned within the region directly beneath the terminal structure region of the semiconductor chip, and the bonding layer is such that, when the semiconductor device is viewed from above, the ratio a / x of the constriction amount a of the recess to the length x of the bonding layer connecting both ends of the recess is 0.08 or greater. This semiconductor device is characterized by the following features.

[0010] Furthermore, another aspect of the present invention for achieving the above objective is a method for manufacturing a semiconductor device having a substrate, a semiconductor chip, and a bonding layer for bonding the substrate and the semiconductor chip, comprising: a substrate preparation step for preparing the substrate; a bonding layer raw material paste application step for applying a bonding layer raw material paste, which is to be the raw material for the bonding layer, to the substrate; a semiconductor chip installation step for installing the semiconductor chip on the bonding layer raw material paste; and a sintering step for heating and sintering the bonding layer raw material paste, wherein the shape of the bonding layer is the shape of the bonding layer of the semiconductor device of the present invention described above.

[0011] A more specific configuration of the present invention is described in the claims. [Effects of the Invention]

[0012] According to the present invention, a semiconductor device is provided in which a substrate and a semiconductor chip are joined by sintering bonding, and the number of voids in the bonding layer is reduced compared to conventional methods. Furthermore, a method for manufacturing a semiconductor device is provided that allows for the removal of solvents in the bonding layer raw material paste in a shorter time than conventional methods. This makes it possible to obtain a homogeneous bonding layer and a semiconductor device with high bonding strength between the substrate and the semiconductor device. In addition, in the method for manufacturing a semiconductor device, the pre-drying step for removing solvents can be shortened or the step itself can be reduced, thereby improving productivity.

[0013] Other issues, configurations, and effects not mentioned above will be clarified by the following description of the embodiments. [Brief explanation of the drawing]

[0014] [Figure 1A] Cross-sectional view of the semiconductor device of Example 1 [Figure 1B] This is a plan view of the semiconductor device of Example 1. [Figure 2] This table shows the effects of the present invention. [Figure 3A] Plan view showing the first shape (triangular) of the bonding layer of the semiconductor device of the present invention. [Figure 3B] Plan view showing the second shape (parabolic) of the bonding layer of the semiconductor device of the present invention. [Figure 3C] Plan view showing the third shape (trapezoidal) of the bonding layer of the semiconductor device of the present invention. [Figure 4] Plan view showing the first aspect of the bonding layer of Example 2 [Figure 5] Plan view showing a second aspect of the bonding layer of Example 2. [Figure 6] Plan view showing the first aspect of the bonding layer of Example 3 [Figure 7] Plan view showing a second aspect of the bonding layer in Example 3. [Figure 8A] Top view of the semiconductor device of Example 4 [Figure 8B] Plan view of Figure 8A [Figure 9] Flowchart showing an example of a method for manufacturing a semiconductor device of the present invention

Mode for Carrying Out the Invention

[0015] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following embodiments.

[0016] [Semiconductor device] [Example 1] FIG. 1A is a cross-sectional view of the semiconductor device of Example 1, and FIG. 1B is a plan view of the semiconductor device of Example 1. As shown in FIG. 1A, the semiconductor device 200 of the present invention includes a substrate 113, a semiconductor chip 100, and a bonding layer 110 that bonds the substrate 113 and the semiconductor chip 100. Then, as shown in FIG. 1B, the bonding layer 110 has a recess 111 that tapers toward the center C of the bonding layer 110 when the semiconductor device 200 is viewed in plan. The bonding layer 110 in FIG. 1 has a shape in which the four sides of a virtual rectangular bonding layer 112 each have a recess 111. By having such a shape, the bonding area is smaller than that of the rectangular bonding layer 112 by the amount of the recess 111.

[0017] The bonding layer of the present invention is composed of a sintered metal (for example, sintered silver, sintered copper, etc.) and has excellent heat dissipation compared to a solder bonding layer. Therefore, even if the bonding layer 110 is located inside the region directly below the semiconductor chip 100 (not shown) or has a constriction, heat dissipation can be ensured at a practical level even if the bonding area with the semiconductor chip is small. <�

[0018] As shown in Figure 1B, by reducing the bonding area, the amount of paste can be reduced, and the absolute amount of solvent that needs to be dried can be reduced. Also, compared to the case where the bonding layer is a rectangular shape of the same area, the proportion of the side surface area of ​​the bonding layer 110 increases. This increases the escape route for the solvent to be discharged to the outside of the bonding layer by heating during the sintering process, so the solvent can be removed effectively. As mentioned above, the area where the solvent is least likely to escape in the bonding layer 110 is near the center C of the bonding layer 110, but the recess 111 shortens the distance from near the center C of the bonding layer 110 to the side surface of the bonding layer 110, so the solvent near the center C of the bonding layer 110 can be volatilized and removed more effectively than in a rectangular bonding layer 112 without the recess 111.

[0019] In Figure 1B, all four corners of the junction layer are positioned within the area directly beneath the semiconductor chip 100, but the corners of the junction layer may extend outside the area directly beneath the semiconductor chip 100.

[0020] This section describes an experiment demonstrating the effectiveness of this embodiment. In this experiment, a simulated semiconductor device was prepared by printing a paste, which is the raw material for the bonding layer, onto a copper substrate and mounting a glass plate, which represents a semiconductor chip, on top of it. The printed patterns were all the same in terms of the amount of paste applied, but the ratio of the amount of constriction a to the length x of both ends of the recess (the length connecting adjacent corners of the applied layer) was set to be different (a / x). In this experiment, the a / x values ​​after paste application and before pressing the glass plate were set to 0, 0.13, 0.27, and 0.40. The a / x values ​​after the sintering process are also shown in the table in Figure 2.

[0021] For the above samples, we observed and compared the voids that formed in the sintered paste when the heating rate was varied (50°C / min, 80°C / min, 100°C / min) and the temperature was raised from room temperature to approximately 300°C.

[0022] Figure 2 shows two binarized images of the sintered paste's appearance after heating for each condition. The a / x value was calculated by measuring the actual ratio of the sample at eight locations and averaging the results. As shown in Figure 2, no voids were generated in the bonding layer without recesses (a / x=0) at a heating rate of 50°C / min, but large voids were observed at heating rates of 80°C / min and 100°C / min. On the other hand, the bonding layer with recesses (a / x=0.13 or higher after paste application and before semiconductor chip mounting (strictly speaking, in Figure 2 it is a glass plate representing a semiconductor chip, but it is thought to be the same for an actual semiconductor chip, so it will be referred to as a semiconductor chip. The same applies hereafter) and a / x=0.087 or higher after the sintering process) were able to suppress void generation at all heating rates. From this, it can be concluded that the configuration of the present invention is particularly effective when the heating rate is increased, and therefore the drying time of the paste can be reduced.

[0023] Furthermore, it can be seen that, at the same heating rate, a larger constriction in the recess suppresses void formation. Therefore, for the same bonding area, having a recess can achieve void suppression and improved production speed.

[0024] The above results confirmed the effect when a / x = 0.13 or higher after paste application and before semiconductor chip mounting, and when a / x = 0.087 or higher after the sintering process. However, even when the value of a / x is smaller than this, it is considered that a favorable effect can be obtained compared to the case without recesses (a / x = greater than 0). Therefore, it is desirable that a / x = 0.08 or higher after the sintering process. Furthermore, it is even more desirable that a / x = 0.20 or higher after the sintering process. In addition, although recesses 111 are provided on all four sides of a hypothetical rectangular bonding layer, it is considered that the effect of the present invention can be obtained if at least one side of the hypothetical rectangular shape has a recess. In other words, the bonding layer 110 only needs to have a configuration in which at least one side has a recess.

[0025] Figures 3A to 3C show examples of the shape of the bonding layer of the semiconductor device of the present invention. The shape of the recess 111 of the bonding layer 110 is not limited to the triangular shape shown in Figures 1B and 3A, but may also be a parabolic shape as shown in Figure 3B, or a trapezoidal shape as shown in Figure 3C.

[0026] [Example 2] Figure 4 is a plan view showing a first embodiment of the bonding layer in Example 2. In Figure 4, the substrate and semiconductor chip shown in Figure 1B are omitted. In this embodiment, the entire outer periphery of the bonding layer 110 is located within the area directly below the termination structure region 101 of the semiconductor chip.

[0027] The semiconductor chip used in power modules has a region (effective region 102) that generates heat when current flows through it. On the other hand, a termination structure region 101 such as an FLR (Field Limiting Ring) may be provided on the outer periphery to ensure voltage resistance, and this termination structure region 101 does not generate as much heat as the effective region 102. Therefore, in a configuration where the effect of the recess 111 can be expected, and where the junction area, which serves as a heat dissipation path, is to be secured as much as possible, a configuration can be found as shown in Figure 4, in which the deepest part of the recess 111 is outside the region directly below the effective region 102, and the entire outer periphery of the junction layer 110, including the recess 111, is contained within the region directly below the termination structure region 101. In Figure 4, the four corners of the junction layer 110 and the deepest part of the recess 111 are arranged so that they are contained within the region directly below the termination structure region 110 of the semiconductor chip.

[0028] Figure 5 is a plan view showing a second aspect of the bonding layer in Example 2. Since sintering bonding generally has superior heat dissipation compared to soldering, even if a part of the recess 111 is located within the area directly below the effective area 102 as shown in Figure 5, sufficient heat dissipation can be ensured.

[0029] [Example 3] Figure 6 is a plan view showing a first embodiment of the semiconductor device of Example 3. In this embodiment, the bonding layer 110 has a shape in which only the long side of a hypothetical rectangle has a recess 111. Semiconductor chips include not only square chips but also rectangular chips. In this case, the ratio of the length x connecting each adjacent corner of the bonding layer 110 to the amount of constriction a is not constant and can be changed as appropriate. For example, as mentioned above, in order to volatilize the solvent, it is effective to make the distance from the center of the bonding layer to the side surface as short as possible. In the case of a rectangular shape, sufficient effect can be obtained even if only the long side of the bonding layer 110 is constricted, as shown in Figure 6.

[0030] Furthermore, if a constriction is also provided on the short side of the bonding layer 110, the effect of volatilizing the solvent can be further enhanced. Figure 7 is a plan view showing a second embodiment of the semiconductor device of Example 3. As shown in Figure 7, by allowing the solvent volatilization effect to be exerted in the constriction on the long side of the bonding layer 110, and by making the penetration area (A3+A4) into the area directly below the effective area 102 of the constriction on the short side smaller than the penetration area on the long side (A1+A2), the effect of providing the recess 111 can be enhanced without unnecessarily reducing heat dissipation.

[0031] [Example 4] Figure 8A is a top view of the semiconductor device of Embodiment 4, and Figure 8B is a plan view of Figure 8A. As shown in Figure 8A, the top surface of the semiconductor chip 100 used in the power module may have wires 120 bonded to the wire mounting portion 103. This wire bonding is performed by ultrasonic bonding, but if there is no bonding layer 110 directly beneath the contact surface where the wires 120 are driven, there is a risk that the semiconductor chip 100 will crack due to the load during ultrasonic bonding. Therefore, in this embodiment, as shown in Figure 8B, even if the bonding layer 110 has a recess 111, the recess 111 of the bonding layer 110 does not extend into the area directly beneath the wire mounting portion 103, and the bonding layer 110 is configured to be positioned in the area directly beneath the wire mounting portion 103.

[0032] [Manufacturing method for semiconductor devices] Figure 9 is a flowchart showing an example of a semiconductor device manufacturing method according to the present invention. As shown in Figure 9, the semiconductor device manufacturing method according to the present invention comprises a substrate preparation step (S1), a bonding layer material paste application step (S2) in which bonding layer material paste is applied to the substrate, a semiconductor chip installation step (S3) in which a semiconductor chip is placed on the bonding layer material paste, and a sintering step (S4) in which the bonding layer material paste is heated and sintered.

[0033] The bonding layer raw material paste application step (S2) can be formed, for example, by printing the bonding layer raw material paste onto the substrate 113 using a printing mask having openings similar in shape to the bonding layer 110 shown in Figure 1B. Alternatively, it can be formed by dispensing the paste in the shape of the bonding layer 110 shown in Figure 1B using a dispenser.

[0034] According to the semiconductor device of the present invention, since the bonding layer 110 has recesses 111, the solvent in the bonding layer raw material paste evaporates more easily, thus shortening or eliminating the time required for the pre-drying step to dry the bonding layer raw material paste. As a result, the manufacturability of the semiconductor device can be improved.

[0035] As described above, the present invention provides a semiconductor device in which a substrate and a semiconductor chip are joined by sintering bonding, which can reduce the number of voids in the bonding layer compared to conventional methods, and also provides a method for manufacturing a semiconductor device that can remove the solvent in the bonding layer raw material paste in a shorter time than conventional methods.

[0036] It should be noted that the present invention is not limited to the embodiments described above, and various modifications are included. For example, the embodiments described above are described in detail for the purpose of explaining the present invention in an easy-to-understand manner, and are not necessarily limited to those having all the configurations described. Furthermore, it is possible to replace parts of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add configurations from other embodiments to the configuration of one embodiment. In addition, it is possible to add, delete, or replace parts of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0037] A1, A2, A3, A4... Part of the effective area without a bonding layer directly beneath it, 100... Semiconductor chip, 101... Termination structure area, 102... Effective area, 103... Wire installation area, 110... Bonding layer, 111... Recess, 112... Imaginary rectangular bonding layer without a recess, 113... Substrate, 115... Void, 120... Wire, 200... Semiconductor device.

Claims

1. A semiconductor device having a substrate, a semiconductor chip, and a bonding layer that joins the substrate and the semiconductor chip, The bonding layer is made of sintered metal, and when the semiconductor device is viewed in plan view, it has a constricted recess toward the center of the bonding layer. Only one recess is provided on each side of the semiconductor chip. The four corners of the bonding layer and the deep portion of the recess are positioned to fit within the region directly beneath the termination structure region of the semiconductor chip. The bonding layer is characterized in that, when the semiconductor device is viewed in plan, the ratio a / x of the amount of constriction a of the recess to the length x of the bonding layer connecting both ends of the recess is 0.08 or more.

2. A semiconductor device according to claim 1, characterized in that the recess has a triangular shape, a parabolic shape, or a trapezoidal shape when the semiconductor device is viewed from above.

3. A semiconductor device according to claim 1, wherein the bonding layer is characterized in that, when the semiconductor device is viewed in plan, the ratio a / x of the amount of constriction a of the recess to the length x of the bonding layer connecting both ends of the recess is 0.20 or more.

4. A semiconductor device according to claim 1, wherein the upper surface of the semiconductor chip has a wire mounting portion on which wire bonding is performed, A semiconductor device characterized in that it is arranged such that the recess of the bonding layer does not overlap the area directly below the wire installation portion.

5. A method for manufacturing a semiconductor device having a substrate, a semiconductor chip, and a bonding layer that joins the substrate and the semiconductor chip, The process includes: a substrate preparation step for preparing the substrate; a bonding layer material paste application step for applying a bonding layer material paste, which is the raw material for the bonding layer, to the substrate; a semiconductor chip installation step for installing the semiconductor chip on the bonding layer material paste; and a sintering step for heating and sintering the bonding layer material paste. A method for manufacturing a semiconductor device, characterized in that the shape of the bonding layer has the shape of the bonding layer of a semiconductor device described in any one of claims 1 to 4.

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