Silicon carbide semiconductor equipment

Abstract

A silicon carbide semiconductor device comprising a silicon carbide substrate that has a first main surface and a second main surface that is on the opposite side to the first main surface. The silicon carbide substrate has: a first conductivity-type drift region; a body region that is provided upon the drift region and has a second conductivity type that is different to the first conductivity type; and a first conductivity-type source region that is provided upon the body region so as to be distanced from the drift region. The first main surface has a gate trench that is defined by: side surfaces that penetrate the source region and the body region and reach the drift region; and a base surface that connects to the side surfaces. The silicon carbide substrate also has a first electric field attenuation region that is provided between the base surface and the second main surface and has a second conductivity-type. The first electric field attenuation region has, in a direction perpendicular to the first main surface: a first surface having the maximum concentration of second conductivity-type impurities; and a second surface that is further on the second main surface side than the first surface and has a concentration of second conductivity-type impurities that is 1 / 10 of the maximum concentration. The distance between the first surface and the second surface is at least 1.0 μm and the distance, from the first main surface, of the interface between the first electric field attenuation region and the drift region on the second main surface side is at least 2.0 μm.

Description

[Technical Field]

[0001] This disclosure relates to silicon carbide semiconductor devices.

[0002] This application claims priority under Japanese application No. 2021-104166 filed on June 23, 2021, and incorporates all the provisions contained in the said Japanese application. [Background technology]

[0003] One example of a silicon carbide semiconductor device is a MOS-type field-effect transistor (MOSFET) equipped with a gate trench that penetrates the source region and the body region (for example, Patent Document 1). [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2014-41990 [Overview of the project]

[0005] The silicon carbide semiconductor device of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate includes a drift region having a first conductivity type, a body region provided on the drift region and having a second conductivity type different from the first conductivity type, and a source region provided on the body region so as to be separated from the drift region and having the first conductivity type. On the first main surface, a gate trench defined by a side surface that penetrates the source region and the body region and reaches the drift region, and a bottom surface continuous with the side surface is provided. The silicon carbide substrate further includes a first electric field relaxation region provided between the bottom surface and the second main surface and having the second conductivity type. The first electric field relaxation region has a first surface where the concentration of impurities of the second conductivity type is the maximum value, and a second surface where the concentration of impurities of the second conductivity type is 1 / 10 of the maximum value and is on the second main surface side of the first surface in a direction perpendicular to the first main surface. The distance between the first surface and the second surface is 1.0 μm or more, and the distance from the first main surface to the interface between the drift region on the second main surface side of the first electric field relaxation region is 2.0 μm or more.

Brief Description of the Drawings

[0006] [Figure 1] FIG. 1 is a diagram showing the layout of a silicon carbide semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to an embodiment. [Figure 3] FIG. 3 is a diagram showing an example of the concentration profile of p-type impurities in the electric field relaxation region in an embodiment. [Figure 4] FIG. 4 is a cross-sectional view (Part 1) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 5] FIG. 5 is a cross-sectional view (Part 2) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 6] FIG. 6 is a cross-sectional view (Part 3) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 7]Figure 7 is a cross-sectional view (part 4) showing a method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 8] Figure 8 is a cross-sectional view (part 5) showing a method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 9] Figure 9 is a cross-sectional view (part 6) showing a method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 10] Figure 10 is a cross-sectional view (part 7) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 11] Figure 11 is a cross-sectional view (part 8) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 12] Figure 12 is a cross-sectional view (part 9) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 13] Figure 13 shows an example of the concentration profile of p-type impurities in the electric field relaxation region in the reference example and embodiment. [Figure 14] Figure 14 shows the relationship between drain voltage and drain current in the embodiments and reference examples. [Figure 15] Figure 15 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to a modified embodiment. [Modes for carrying out the invention]

[0007] [Issues this disclosure aims to address] Conventional silicon carbide semiconductor devices require multiple epitaxial layer formations on a silicon carbide single crystal substrate. To reduce costs, it is desirable to reduce the number of epitaxial layer formations.

[0008] This disclosure aims to provide a silicon carbide semiconductor device that can reduce the number of times an epitaxial layer is formed.

[0009] [Effects of this disclosure] According to this disclosure, the number of times the epitaxial layer is formed can be reduced.

[0010] The implementation methods are described below.

[0011] [Description of Embodiments in this Disclosure] The embodiments of this disclosure are listed and described below. In the following description, the same or corresponding elements are denoted by the same reference numeral, and the same description is not repeated. In the crystallographic descriptions herein, individual orientations are indicated by [], collective orientations by <>, individual planes by () and collective planes by {}. Also, while negative crystallographic exponents are usually indicated by placing a "-" (bar) above the number, in this specification a negative sign is placed before the number.

[0012] [1] A silicon carbide semiconductor device according to one aspect of the present disclosure comprises a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, wherein the silicon carbide substrate has a drift region having a first conductivity type, a body region provided on the drift region and having a second conductivity type different from the first conductivity type, and a source region provided on the body region so as to be separated from the drift region and having the first conductivity type, and the first main surface is provided with a gate trench defined by a side surface that penetrates the source region and the body region and reaches the drift region, and a bottom surface connected to the side surface. The silicon carbide substrate is provided between the bottom surface and the second main surface and further has a first field relaxation region having the second conductivity type, the first field relaxation region having a first surface in a direction perpendicular to the first main surface where the concentration of impurities of the second conductivity type is at its maximum value, and a second surface where the concentration of impurities of the second conductivity type is 1 / 10 of the maximum value and is closer to the second main surface than the first surface, the distance between the first surface and the second surface is 1.0 μm or more, and the distance from the first main surface to the interface of the first field relaxation region with the drift region on the second main surface side is 2.0 μm or more.

[0013] In the first field relaxation region, the distance between the first surface, where the concentration of the second conductivity type impurity is at its maximum, and the second surface, where the concentration of the second conductivity type impurity is 1 / 10 of the maximum, is 1.0 μm or more. Furthermore, the distance from the first main surface to the interface between the first field relaxation region and the drift region on the second main surface side is 2.0 μm or more. Therefore, the source region, body region, drift region, and first field relaxation region can be appropriately formed without forming multiple epitaxial layers. In addition, since the concentration of the second conductivity type impurity changes gradually within the first field relaxation region, the breakdown voltage can be improved and short-circuit current can be suppressed while suppressing on-resistance.

[0014] [2] In [1], the first field relaxation region further contains impurities of the first conductivity type, and the total amount of impurities of the second conductivity type contained in the first field relaxation region may be greater than the total amount of impurities of the first conductivity type contained in the first field relaxation region. In this case, the first field relaxation region can be formed by ion implantation of impurities of the second conductivity type into the region containing impurities of the first conductivity type. Then, by adjusting the concentrations of impurities of the first conductivity type and the second conductivity type, desired on-resistance, breakdown voltage, and short-circuit withstand voltage can be obtained.

[0015] [3] In [1] or [2], the distance between the first main surface and the bottom surface may be less than 0.8 μm, and the distance between the first main surface and the first surface may be 0.8 μm or more. In this case, the on-resistance in the region between the body region and the first electric field relaxation region is easily reduced.

[0016] [4] In [1] to [3], the maximum effective concentration of the second conductive type impurity in the body region is 1.0 × 10 18 cm -3 The above 5.0 × 10 18 cm -3 The following is also acceptable. In this case, the threshold voltage can be increased, making it easier to improve short-circuit withstand capability.

[0017] [5] In [1] to [4], the distance between the first main surface and the first surface may be 3.0 μm or less. In this case, the first electric field relaxation region is easily formed by ion implantation through the first main surface.

[0018] [6] In [1] to [5], the device has an active region including the body region, the source region, and the first field relaxation region, and a termination region provided around the active region and including a second field relaxation region having the second conductivity type, wherein the second field relaxation region has a third surface in a direction perpendicular to the first main surface where the concentration of impurities of the second conductivity type is at its maximum value, and a fourth surface where the concentration of impurities of the second conductivity type is 1 / 10 of the maximum value and is closer to the second main surface than the third surface, and the distance between the third surface and the fourth surface may be 1.0 μm or more. In this case, the breakdown voltage of the termination region can be made higher than the breakdown voltage of the active region to improve the avalanche withstand capability.

[0019] [7] In [6], the second electric field relaxation region may be electrically connected to the first electric field relaxation region. In this case, it is easier to control the first electric field relaxation region and the second electric field relaxation region to the same potential.

[0020] [8] In [1] to [7], the side surface of the gate trench may include a {0-33-8} plane. Including a {0-33-8} plane on the side surface allows for good mobility on the side surface of the gate trench and reduces channel resistance.

[0021] [Embodiments of this Disclosure] Embodiments of this disclosure relate to a so-called vertical MOSFET (silicon carbide semiconductor device). Figure 1 is a diagram showing the layout of a silicon carbide semiconductor device according to an embodiment. Figure 2 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to an embodiment. Figure 2 corresponds to a cross-sectional view along the line II-II in Figure 1.

[0022] As shown in Figures 1 and 2, the MOSFET 100 according to this embodiment mainly comprises a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, a drain electrode 70, a barrier metal film 84, and a passivation film 85. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, polytype 4H hexagonal silicon carbide. The silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has an n-type conductivity (first conductivity type).

[0023] The first main surface 1 is the {0001} surface or a surface inclined by an off-angle of 8° or less in the off-direction. Preferably, the first main surface 1 is the (000-1) surface or a surface inclined by an off-angle of 8° or less in the off-direction. The off-direction may be, for example, the <11-20> direction or the <1-100> direction. The off-angle may be, for example, 1° or more or 2° or more. The off-angle may be 6° or less or 4° or less.

[0024] When viewed from above from a direction perpendicular to the first main surface 1, the MOSFET 100 has an active region 6 and a termination region 7 provided around the active region 6.

[0025] The silicon carbide epitaxial layer 40 mainly comprises a drift region 11, a body region 12, a source region 13, a current diffusion region 14, an electric field relaxation region 15, a connection region 19, a contact region 16, an embedded junction termination extension (JTE) region 17, and a surface JTE region 18. The body region 12, source region 13, current diffusion region 14, electric field relaxation region 15, contact region 16, and connection region 19 are located within the active region 6. The embedded JTE region 17 and surface JTE region 18 are located within the termination region 7. The drift region 11 extends across the active region 6 and the termination region 7.

[0026] The drift region 11 contains n-type impurities such as nitrogen or phosphorus (P), and has an n-type conductivity. The drift region 11 mainly consists of, for example, a first region 11A, a second region 11B, and a third region 11C.

[0027] The current diffusion region 14 is located on the drift region 11. The current diffusion region 14 contains n-type impurities such as phosphorus and has an n-type conductivity. The current diffusion region 14 is located between the body region 12 and the first region 11A in a direction perpendicular to the second main surface 2. The current diffusion region 14 is in contact with the body region 12 and the first region 11A. The current diffusion region 14 is located closer to the second main surface 2 than the body region 12. The current diffusion region 14 is located closer to the first main surface 1 than the first region 11A. The current diffusion region 14 is also in contact with the side surface 3. The peak effective concentration of the n-type impurities in the current diffusion region 14 is preferably 5 × 10⁻¹⁰ to suppress short-circuit current. 17 cm -3 The following applies: The peak effective concentration of n-type impurities in the current diffusion region 14 is preferably 2 × 10⁻⁶ to suppress on-resistance. 17 cm -3 That concludes the explanation. The current diffusion region 14 constitutes part of the drift region.

[0028] The body region 12 is provided on the current diffusion region 14. The body region 12 contains a p-type impurity such as aluminum (Al) or the like and has a p-type conductivity type (second conductivity type). The body region 12 is between the source region 13 and the current diffusion region 14 in a direction perpendicular to the second main surface 2. The body region 12 is in contact with the source region 13 and the current diffusion region 14. The body region 12 is on the side of the second main surface 2 rather than the source region 13. The body region 12 is on the side of the first main surface 1 rather than the current diffusion region 14. The body region 12 is also in contact with the side surface 3. The effective concentration of the p-type impurity in the body region 12 is, for example, 5×10 17 cm -3 or more and 5×10 18 cm -3 or less. The maximum value of the effective concentration of the p-type impurity in the body region 12 is preferably 1.0×10 18 cm -3 or more and 5.0×10 18 cm -3 or less. The short-channel effect (punch-through) can occur when the depletion layer spreads from the pn junction region into the channel region and the entire channel region becomes a depletion layer. By increasing the effective concentration of the p-type impurity in the body region 12, the spread of the depletion layer formed in the channel region can be reduced. Thereby, it is easy to increase the threshold voltage and improve the short-circuit withstand capacity.

[0029] The source region 13 is on the body region 12 in a direction perpendicular to the second main surface 2. The source region 13 is in contact with the body region 12. The source region 13 is provided on the body region 12 so as to be separated from the current diffusion region 14 by the body region 12. The source region 13 is on the side of the first main surface 1 rather than the body region 12. The source region 13 is also in contact with the side surface 3. The source region 13 is covered with the gate insulating film 81. The source region 13 is in direct contact with the gate insulating film 81. The source region 13 contains an n-type impurity such as nitrogen or phosphorus or the like and has an n-type conductivity type. The source region 13 constitutes the first main surface 1. The effective concentration of the n-type impurity in the source region 13 is, for example, 5×10 18 cm -3 or more and 5×10 19 cm -3The following applies: The effective concentration of n-type impurities on the first main surface 1 of the source region 13 is preferably 1 × 10⁻⁶ to reduce sheet resistance. 19 cm -3 That's all.

[0030] The contact region 16 contains p-type impurities, such as aluminum, and has a p-type conductivity. The effective concentration of p-type impurities in the contact region 16 is higher than, for example, the effective concentration of p-type impurities in the body region 12. The contact region 16 penetrates the source region 13 and is in contact with the body region 12. The contact region 16 constitutes the first main surface 1. The effective concentration of p-type impurities in the contact region 16 is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 20 cm -3 The following applies:

[0031] The first principal surface 1 is provided with a gate trench 5 defined by a side surface 3 and a bottom surface 4. The side surface 3 penetrates the source region 13, the body region 12, the current diffusion region 14, and the drift region 11 to reach the electric field relaxation region 15. The bottom surface 4 is continuous with the side surface 3. The bottom surface 4 is located in the electric field relaxation region 15. The bottom surface 4 is, for example, a plane parallel to the second principal surface 2. The angle θ1 of the side surface 3 with respect to the plane containing the bottom surface 4 is, for example, 45° or more and 65° or less. The angle θ1 may be, for example, 50° or more. The angle θ1 may be, for example, 60° or less. The side surface 3 preferably has a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility. The gate trench 5 extends in a stripe shape along a first direction parallel to the first principal surface 1, for example. When viewed from above from a direction perpendicular to the first main surface 1, a plurality of gate trenches 5 are provided at regular intervals in a second direction perpendicular to the first direction. The plurality of gate trenches 5 may be provided, for example, in an array.

[0032] The electric field relaxation region 15 contains p-type impurities such as aluminum and has a p-type conductivity. The electric field relaxation region 15 may further contain n-type impurities such as nitrogen or phosphorus. The total amount of p-type impurities contained in the electric field relaxation region 15 is greater than the total amount of n-type impurities contained in the electric field relaxation region 15. The electric field relaxation region 15 is located between the current diffusion region 14 and the second main surface 2. When viewed from a plane perpendicular to the first main surface 1, the electric field relaxation region 15 includes a portion that overlaps with the gate trench 5. For example, the electric field relaxation region 15 is located between the bottom surface 4 of the gate trench 5 and the second main surface 2, and the upper end surface of the electric field relaxation region 15 includes, for example, the bottom surface 4 of the gate trench 5. A portion of the upper end surface of the electric field relaxation region 15 faces a portion of the lower end surface of the current diffusion region 14. The electric field relaxation region 15 has a side end face 92 that is further away from the gate trench 5 than the first position 91 where the current diffusion region 14, the body region 12, and the side surface 3 are in contact with each other, when viewed from a plane perpendicular to the first main surface 1. The electric field relaxation region 15 may be electrically connected to the source electrode 60. The effective concentration of p-type impurities in the electric field relaxation region 15 is, for example, 5 × 10⁻⁶. 17 cm -3 The above 5 x 10 18 cm -3 The following applies:

[0033] Figure 3 shows an example of the concentration profile of p-type impurities in the field relaxation region 15. In Figure 3, the horizontal axis represents the distance from the first main surface 1, and the vertical axis represents the concentration of p-type impurities. The field relaxation region 15 has a first surface 15A where the concentration of p-type impurities is at its maximum in the direction perpendicular to the first main surface 1, and a second surface 15B where the concentration of p-type impurities is 1 / 10 of the maximum and is located on the second main surface 2 side of the first surface 15A. For example, the concentration of p-type impurities on the first surface 15A is 3.4 × 10⁻⁶. 17 cm -3 Therefore, the concentration of p-type impurities on the second surface 15B is 3.4 × 10⁻⁶. 16 cm -3Furthermore, the distance D1 between the first surface 15A and the second surface 15B is 1.0 μm or greater. For example, the distance D2 between the first main surface 1 and the first surface 15A is about 1.0 μm, the distance D3 between the first main surface 1 and the second surface 15B is about 3.2 μm, and the distance D1 between the first surface 15A and the second surface 15B is about 2.2 μm. The electric field relaxation region 15 is an example of the first electric field relaxation region.

[0034] The connection region 19 contains p-type impurities such as aluminum and has a p-type conductivity. When viewed from a plane perpendicular to the first main surface 1, the connection region 19 is located near the boundary between the active region 6 and the terminal region 7 and has an annular planar shape. The connection region 19 is located on the first main surface 1 side of the electric field relaxation region 15. The lower end surface of the connection region 19 is in contact with the upper end surface of the electric field relaxation region 15. The contact region 16 is also formed on top of the connection region 19. The upper end surface of the connection region 19 is in contact with the lower end surface of the contact region 16.

[0035] The first region 11A of the drift region 11 lies between the current diffusion region 14 and the field relaxation region 15. The first region 11A is in contact with the current diffusion region 14 and the field relaxation region 15. The first region 11A is located on the second main surface 2 side of the current diffusion region 14. The first region 11A is located on the first main surface 1 side of the field relaxation region 15. The effective concentration of n-type impurities in the first region 11A is, for example, 5 × 10⁻⁶. 15 cm -3 The above 5 x 10 16 cm -3 The following applies:

[0036] The second region 11B is located closer to the second principal surface 2 than the first region 11A. The second region 11B is continuous with the first region 11A. The second region 11B is in contact with the field relaxation region 15 in a direction parallel to the second principal surface 2. The second region 11B and the field relaxation region 15 may be located on the same plane parallel to the second principal surface 2. The effective concentration of n-type impurities in the second region 11B may be higher than the effective concentration of n-type impurities in the first region 11A. The effective concentration of n-type impurities in the second region 11B is, for example, 5 × 10⁻⁶. 15 cm -3 The above 5 x 10 16 cm-3 The following applies:

[0037] The third region 11C is located on the second main surface 2 side of the second region 11B. The third region 11C is continuous with the second region 11B. The third region 11C is in contact with the field relaxation region 15. The third region 11C is located on the second main surface 2 side of the field relaxation region 15. The third region 11C may be located between the second region 11B and the silicon carbide single crystal substrate 50. The third region 11C may be continuous with the silicon carbide single crystal substrate 50. The effective concentration of n-type impurities in the third region 11C is, for example, 5 × 10⁻⁶. 15 cm -3 The above 5 x 10 16 cm -3 The following applies:

[0038] The lower end surface of the electric field relaxation region 15 is in contact with the upper end surface of the third region 11C of the drift region 11. The distance D4 from the first main surface 1 to the interface 93 between the electric field relaxation region 15 and the drift region 11 on the second main surface 2 side is 2.0 μm or more (see Figure 3). At interface 93, the concentrations of p-type impurities and n-type impurities are equal, with the concentration of p-type impurities being higher than that of n-type impurities within the electric field relaxation region 15, and the concentration of p-type impurities being lower than that of n-type impurities within the third region 11C. For example, the concentration of n-type impurities in the electric field relaxation region 15 and the drift region 11 is 1.00 × 10⁻⁶. 16 cm -3 Therefore, the concentration of p-type impurities in the electric field relaxation region 15 is 1.00 × 10⁻⁶. 16 cm -3 The concentration of p-type impurities in the drift region 11 is 1.00 × 10⁻⁶. 16 cm -3 It is less than.

[0039] The embedded JTE region 17 contains p-type impurities such as aluminum and has a p-type conductivity. The concentration of p-type impurities in the embedded JTE region 17 may be lower than the concentration of p-type impurities in the field relaxation region 15. The embedded JTE region 17 may further contain n-type impurities such as nitrogen or phosphorus. The total amount of p-type impurities contained in the embedded JTE region 17 is greater than the total amount of n-type impurities contained in the embedded JTE region 17. The embedded JTE region 17 is provided on top of the drift region 11. The embedded JTE region 17 is in contact with the field relaxation region 15 in a direction parallel to the first main surface 1. The embedded JTE region 17 is an example of a second field relaxation region.

[0040] The embedded JTE region 17 has a third surface 17A where the concentration of p-type impurities is at its maximum in a direction perpendicular to the first main surface 1, and a fourth surface 17B where the concentration of p-type impurities is 1 / 10 of the maximum and is located on the second main surface 2 side of the third surface 17A. Furthermore, the distance D5 between the third surface 17A and the fourth surface 17B is 1.0 μm or more.

[0041] The surface JTE region 18 contains p-type impurities, such as aluminum, and has a p-type conductivity. The surface JTE region 18 is located on top of the embedded JTE region 17. The end of the surface JTE region 18 opposite to the active region 6 is further from the active region 6 than the end of the embedded JTE region 17 opposite to the active region 6. The effective concentration of p-type impurities in the surface JTE region 18 may be approximately the same as the effective concentration of p-type impurities in the embedded JTE region 17. The surface JTE region 18 is in contact with the contact region 16 and the connection region 19 in a direction parallel to the first main surface 1. The surface JTE region 18 constitutes the first main surface 1.

[0042] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is composed of a material containing, for example, silicon dioxide. The gate insulating film 81 is in contact with the side surface 3 and the bottom surface 4. The gate insulating film 81 is in contact with the electric field relaxation region 15 at the bottom surface 4. The gate insulating film 81 is in contact with the source region 13, the body region 12, the current diffusion region 14, and the first region 11A at the side surface 3. The gate insulating film 81 may also be in contact with the source region 13 at the first main surface 1.

[0043] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon (polySi) containing conductive impurities. The gate electrode 82 is located inside the gate trench 5. A portion of the gate electrode 82 may be located on the first main surface 1.

[0044] The interlayer insulating film 83 is provided in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is made of a material containing, for example, silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 from the source electrode 60. A portion of the interlayer insulating film 83 may be provided inside the gate trench 5.

[0045] Contact holes 86 are formed at regular intervals in the second direction in the interlayer insulating film 83 and the gate insulating film 81. The contact holes 86 are arranged such that, when viewed from a plane perpendicular to the first main surface 1, the gate trench 5 is positioned between adjacent contact holes 86 in the second direction. The contact holes 86 extend in the first direction. The source region 13 and the contact region 16 are exposed from the interlayer insulating film 83 and the gate insulating film 81 through the contact holes 86. The contact region 16 does not need to be arranged throughout the entire first direction (the longitudinal direction of the gate trench 5), but may be arranged periodically.

[0046] The barrier metal film 84 covers the upper and side surfaces of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81. The barrier metal film 84 is in contact with both the interlayer insulating film 83 and the gate insulating film 81. The barrier metal film 84 is made of a material containing, for example, titanium nitride (TiN).

[0047] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 has a contact electrode 61 and a source wiring 62. The contact electrode 61 may be in contact with the source region 13 and the contact region 16 on the first main surface 1. The contact electrode 61 is made of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be made of a material containing titanium, aluminum, and silicon. The contact electrode 61 is ohmic-bonded to the contact region 16. The source wiring 62 covers the upper and side surfaces of the barrier metal film 84 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with the barrier metal film 84 and the contact electrode 61, respectively. The source wiring 62 is made of a material containing, for example, aluminum.

[0048] The passivation film 85 covers the upper surface of the source wiring 62. The passivation film 85 is in contact with the source wiring 62. The passivation film 85 is made of a material including, for example, polyimide. The passivation film 85 has an opening 87 that exposes a portion of the upper surface of the source wiring 62.

[0049] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 on the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing, for example, nickel silicide. The drain electrode 70 may be made of a material containing titanium, aluminum, and silicon. The drain electrode 70 is ohmic bonded to the silicon carbide single crystal substrate 50.

[0050] In a direction perpendicular to the second main surface 2, the upper end surface of the electric field relaxation region 15 may be spaced apart from the bottom surface 4. In this case, for example, the bottom surface 4 may be located in the drift region 11, and the side surface 3 may penetrate the source region 13, the body region 12, and the current diffusion region 14 to reach the drift region 11. For example, there may be a first region 11A between the upper end surface of the electric field relaxation region 15 and the bottom surface 4.

[0051] A buffer layer containing n-type impurities, such as nitrogen, and having an n-type conductivity may be provided between the silicon carbide single crystal substrate 50 and the third region 11C. The effective concentration of n-type impurities in the buffer layer may be higher than the effective concentration of n-type impurities in the third region 11C.

[0052] In this disclosure, the effective concentration of p-type impurities is the difference between the concentration of p-type impurities and the concentration of n-type impurities, and the effective concentration of n-type impurities is the difference between the concentration of n-type impurities and the concentration of p-type impurities. The effective concentration can be measured, for example, by the following procedure 1 to 4.

[0053] (Step 1) Identify the element region by observing the surface of the semiconductor device.

[0054] (Step 2) Process the semiconductor device so that the cross-section of the semiconductor region shown in Figure 2 is revealed. For example, the cross-section of the semiconductor device can be processed using a focused ion beam (FIB) device.

[0055] (Step 3) Using a scanning electron microscope (SEM), determine whether the conductivity type of the impurity-injected region is p-type or n-type. For example, when SEM observation is performed under conditions of an acceleration voltage of 3kV and a magnification of 10,000x, the bright region is the p-type region, and the dark region is the n-type region.

[0056] (Procedure 4) The impurity concentrations in the p-type and n-type regions of the above cross-section are measured using a scanning spreading resistance microscope (SSRM). The concentration in the p-type region is the effective concentration of p-type impurities, and the concentration in the n-type region is the effective concentration of n-type impurities.

[0057] Next, a method for manufacturing the MOSFET 100 according to the embodiment will be described. Figures 4 to 12 are cross-sectional views showing the method for manufacturing the MOSFET 100 according to the embodiment. Figures 4 to 12, like Figure 2, correspond to cross-sectional views along the line II-II in Figure 1.

[0058] First, as shown in Figure 4, a silicon carbide single crystal substrate 50 is prepared. For example, a silicon carbide ingot (not shown) manufactured by sublimation is sliced ​​to prepare the silicon carbide single crystal substrate 50. A buffer layer (not shown) may be formed on the silicon carbide single crystal substrate 50. The buffer layer can be formed, for example, by chemical vapor deposition (CVD) using a mixed gas of silane (SiH4) and propane (C3H8) as the raw material gas and hydrogen (H2) as the carrier gas. During the epitaxial growth of the buffer layer, n-type impurities such as nitrogen may be introduced into the buffer layer.

[0059] Next, as also shown in Figure 4, an epitaxial layer 21 is formed. For example, the epitaxial layer 21 is formed on the silicon carbide single crystal substrate 50 by a CVD method using a mixed gas of silane and propane as the raw material gas and hydrogen as the carrier gas. During epitaxial growth, n-type impurities such as nitrogen are introduced into the epitaxial layer 21. The epitaxial layer 21 has an n-type conductivity. The effective concentration of n-type impurities in the epitaxial layer 21 may be lower than the effective concentration of n-type impurities in the buffer layer.

[0060] Next, as shown in Figure 5, an electric field relaxation region 15 is formed. For example, a mask layer (not shown) having an opening is formed on the region where the electric field relaxation region 15 is formed. Next, p-type impurity ions capable of imparting p-type properties, such as aluminum ions, are implanted into the epitaxial layer 21. This implantation of p-type impurity ions is carried out under conditions that cause channeling. This forms an electric field relaxation region 15 having a first surface 15A and a second surface 15B. For example, the implantation energy of the p-type impurity ions during the formation of the electric field relaxation region 15 may be 900 keV or more and 1000 keV or less, and the dose is 3.5 × 10⁻⁶. 13 cm -2 The above 4.5 × 10 13 cm -2The following may also be performed: The mask layer is removed after the formation of the electric field relaxation region 15.

[0061] Next, as also shown in Figure 5, an embedded JTE region 17 is formed. For example, a mask layer (not shown) having an opening is formed on the region where the embedded JTE region 17 is formed. Next, p-type impurity ions capable of imparting p-type properties, such as aluminum ions, are implanted into the epitaxial layer 21. This implantation of p-type impurity ions is carried out under conditions that cause channeling. This forms an embedded JTE region 17 having a third surface 17A and a fourth surface 17B. For example, the implantation energy of the p-type impurity ions during the formation of the embedded JTE region 17 may be 900 keV to 1000 keV, and the dose is 0.5 × 10⁻⁶. 13 cm -2 The above 1.5 × 10 13 cm -2 The following may also be performed: The mask layer is removed after the formation of the embedded JTE region 17.

[0062] Next, a connection region 19 is formed, as shown in Figure 6. For example, a mask layer (not shown) having an opening is formed on the region where the connection region 19 is formed. Next, p-type impurity ions capable of imparting p-type properties, such as aluminum ions, are implanted into the epitaxial layer 21. This forms the connection region 19. After the formation of the connection region 19, the mask layer is removed.

[0063] Next, as also shown in Figure 6, a body region 12 is formed. For example, a mask layer (not shown) having an opening is formed on the region where the body region 12 is formed. Next, p-type impurity ions capable of imparting p-type properties, such as aluminum ions, are implanted into the epitaxial layer 21. This forms the body region 12.

[0064] Next, as also shown in Figure 6, a current diffusion region 14 is formed. For example, n-type impurity ions that can impart n-type properties, such as phosphorus ions, are implanted into the epitaxial layer 21. This forms the current diffusion region 14.

[0065] Next, as also shown in Figure 6, a source region 13 is formed. For example, n-type impurity ions that can impart n-type properties, such as phosphate ions, are implanted into the epitaxial layer 21. This forms the source region 13. After the formation of the source region 13, the mask layer is removed.

[0066] Next, as also shown in Figure 6, a contact region 16 is formed. For example, a mask layer (not shown) having an opening is formed on the region where the contact region 16 is formed. Next, a p-type impurity capable of imparting p-type properties, such as aluminum ions, is injected into the epitaxial layer 21. This forms the contact region 16.

[0067] Next, as also shown in Figure 6, a surface JTE region 18 is formed. For example, a mask layer (not shown) having an opening is formed on the region where the surface JTE region 18 is formed. Next, a p-type impurity capable of imparting p-type properties, such as aluminum ions, is implanted into the epitaxial layer 21. This forms the surface JTE region 18.

[0068] Next, activation annealing is performed to activate the impurity ions implanted in the silicon carbide substrate 10. The activation annealing temperature is preferably between 1500°C and 1900°C, for example, around 1700°C. The activation annealing time is, for example, around 30 minutes. The activation annealing atmosphere is preferably an inert gas atmosphere, for example, an argon (Ar) atmosphere.

[0069] Next, as shown in Figure 7, a gate trench 5 is formed. For example, a mask layer (not shown) having an opening at the location where the gate trench 5 is formed is formed on the first main surface 1. Using the mask layer, a portion of the source region 13, a portion of the body region 12, a portion of the current diffusion region 14, and a portion of the drift region 11 are removed by etching. As an etching method, for example, reactive ion etching, in particular inductively coupled plasma reactive ion etching can be used. Specifically, for example, inductively coupled plasma reactive ion etching using sulfur hexafluoride (SF6) or a mixed gas of SF6 and oxygen (O2) as the reaction gas can be used. By etching, a recess (not shown) is formed in the region where the gate trench 5 is to be formed, having a side portion that is substantially perpendicular to the first main surface 1 and a bottom portion that is continuously provided with the side portion and substantially parallel to the first main surface 1.

[0070] Next, thermal etching is performed in the recesses. Thermal etching can be performed by heating in an atmosphere containing a reactive gas having at least one type of halogen atom, with a mask layer formed on the first main surface 1. The at least one type of halogen atom includes at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere contains, for example, chlorine (Cl2), boron trichloride (BCl3), SF6, or carbon tetrafluoride (CF4). For example, a mixed gas of chlorine gas and oxygen gas is used as the reaction gas, and thermal etching is performed at a heat treatment temperature of, for example, 800°C to 900°C. The reaction gas may also contain a carrier gas in addition to the chlorine gas and oxygen gas mentioned above. As the carrier gas, for example, nitrogen gas, argon gas, or helium gas can be used.

[0071] The above thermal etching process forms a gate trench 5 on the first main surface 1 of the silicon carbide substrate 10. The gate trench 5 is defined by a side surface 3 and a bottom surface 4. The side surface 3 consists of a source region 13, a body region 12, a current diffusion region 14, and a drift region 11. The bottom surface 4 consists of an electric field relaxation region 15. The angle θ1 between the side surface 3 and the plane containing the bottom surface 4 is, for example, between 45° and 65°. Next, the mask layer is removed from the first main surface 1.

[0072] Next, as shown in Figure 8, a gate insulating film 81 is formed. For example, by thermal oxidation of the silicon carbide substrate 10, a gate insulating film 81 is formed that is in contact with the source region 13, the body region 12, the current diffusion region 14, the drift region 11, the electric field relaxation region 15, and the contact region 16. Specifically, the silicon carbide substrate 10 is heated in an oxygen-containing atmosphere at a temperature of, for example, 1300°C to 1400°C. This forms a gate insulating film 81 that is in contact with the first main surface 1, the side surface 3, and the bottom surface 4. When the gate insulating film 81 is formed by thermal oxidation, strictly speaking, a part of the silicon carbide substrate 10 is incorporated into the gate insulating film 81. Therefore, in the subsequent processing, it is assumed that the first main surface 1, the side surface 3, and the bottom surface 4 have moved slightly to the interface between the thermally oxidized gate insulating film 81 and the silicon carbide substrate 10.

[0073] Next, the silicon carbide substrate 10 may be subjected to heat treatment (NO annealing) in a nitric oxide (NO) gas atmosphere. In NO annealing, the silicon carbide substrate 10 is held for about 1 hour under conditions of, for example, 1100°C to 1400°C. This introduces nitrogen atoms into the interface region between the gate insulating film 81 and the body region 12. As a result, the formation of interface states in the interface region is suppressed, thereby improving channel mobility.

[0074] After NO annealing, Ar annealing may be performed using argon (Ar) as the ambient gas. The heating temperature for Ar annealing is, for example, higher than the heating temperature for NO annealing. The Ar annealing time is, for example, about 1 hour. This further suppresses the formation of interface states in the interface region between the gate insulating film 81 and the body region 12. Note that other inert gases such as nitrogen gas may be used as the ambient gas instead of Ar gas.

[0075] Next, as shown in Figure 9, the gate electrode 82 is formed. The gate electrode 82 is formed on the gate insulating film 81. The gate electrode 82 is formed, for example, by the Low Pressure Chemical Vapor Deposition (LP-CVD) method. The gate electrode 82 is formed so as to face the source region 13, the body region 12, the current diffusion region 14, and the drift region 11, respectively.

[0076] Next, as shown in Figure 10, an interlayer insulating film 83 is formed. Specifically, the interlayer insulating film 83 is formed to cover the gate electrode 82 and to be in contact with the gate insulating film 81. The interlayer insulating film 83 is formed, for example, by the CVD method. The interlayer insulating film 83 is composed of a material containing, for example, silicon dioxide. A portion of the interlayer insulating film 83 may be formed inside the gate trench 5.

[0077] Next, as shown in Figure 11, contact holes 86 are formed in the interlayer insulating film 83 and the gate insulating film 81. The contact region 16 is exposed through the contact holes 86 from the interlayer insulating film 83 and the gate insulating film 81.

[0078] Next, as shown in Figure 12, a barrier metal film 84, a contact electrode 61, and a drain electrode 70 are formed. For example, a barrier metal film 84 is formed that covers the upper and side surfaces of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81. The barrier metal film 84 is made of a material containing, for example, titanium nitride. The barrier metal film 84 is formed, for example, by sputtering and reactive ion etching (RIE). Next, a metal film (not shown) for the contact electrode 61 that contacts the contact region 16 is formed on the first main surface 1. The metal film for the contact electrode 61 is formed, for example, by sputtering. The metal film for the contact electrode 61 is made of a material containing, for example, nickel. Next, a metal film (not shown) for the drain electrode 70 that contacts the silicon carbide single crystal substrate 50 is formed on the second main surface 2. The metal film for the drain electrode 70 is formed, for example, by sputtering. The metal film for the drain electrode 70 is made of a material containing, for example, nickel.

[0079] Next, alloying annealing is performed. The metal film for the contact electrode 61 and the metal film for the drain electrode 70 are held at a temperature of, for example, 900°C to 1100°C for about 5 minutes. As a result, at least a portion of the metal film for the contact electrode 61 and at least a portion of the metal film for the drain electrode 70 react with the silicon contained in the silicon carbide substrate 10 and silicide is formed. This forms the contact electrode 61 which is ohmic bonded to the contact region 16 and the drain electrode 70 which is ohmic bonded to the silicon carbide single crystal substrate 50. The contact electrode 61 may be made of a material containing titanium, aluminum, and silicon. The drain electrode 70 may be made of a material containing titanium, aluminum, and silicon.

[0080] Next, the source wiring 62 is formed. Specifically, the source wiring 62 is formed to cover the contact electrode 61 and the barrier metal film 84. The source wiring 62 is formed, for example, by film deposition using a sputtering method and RIE. The source wiring 62 is made of a material containing, for example, aluminum. In this way, a source electrode 60 having the contact electrode 61 and the source wiring 62 is formed.

[0081] Next, a passivation film 85 is formed. Specifically, a passivation film 85 is formed to cover the source wiring 62. The passivation film 85 is made of a material including, for example, polyimide. The passivation film 85 is formed, for example, by a coating method. Next, an opening 87 is formed in the passivation film 85.

[0082] In this way, the MOSFET 100 according to the embodiment is completed.

[0083] Next, the effects and benefits of the MOSFET according to this embodiment will be described.

[0084] In the MOSFET 100 according to this embodiment, in the electric field relaxation region 15, the distance between the first surface 15A, where the concentration of p-type impurities is at its maximum, and the second surface 15B, where the concentration of p-type impurities is 1 / 10 of the maximum, is 1.0 μm or more. Also, the distance D4 from the first main surface 1 to the interface 93 between the electric field relaxation region 15 and the drift region 11 on the second main surface 2 side is 2.0 μm or more. Therefore, the source region 13, body region 12, drift region 11, and electric field relaxation region 15 can be appropriately formed without forming multiple epitaxial layers. Furthermore, since the concentration of p-type impurities changes gradually within the electric field relaxation region 15, the breakdown voltage can be improved while suppressing on-resistance and obtaining a high breakdown voltage, and the short-circuit current can be suppressed. By suppressing the short-circuit current, the short-circuit withstand capability is improved. In addition, even if heat is generated during a short circuit, the heat is generated at a location away from the first main surface 1, so the effect of heat on the source electrode 60 can be mitigated, and the short-circuit withstand capability can be improved.

[0085] Here, we will explain the effect of reducing the short-circuit current compared to a reference example in which the concentration profile of p-type impurities in the electric field relaxation region 15 differs. Figure 13 shows an example of the concentration profile of p-type impurities in the electric field relaxation region 15 in the reference example. In Figure 13, the horizontal axis represents the distance from the first main surface 1, and the vertical axis represents the concentration of p-type impurities. Figure 13 also shows an example of the concentration profile in the embodiment.

[0086] As shown in Figure 13, in the reference example, the change in the concentration of p-type impurities is steep, and the distance between the first surface 15A and the second surface 15B is less than 1.0 μm. Also, in the reference example, the distance D4 from the first main surface 1 to the interface 93 between the electric field relaxation region 15 and the drift region 11 on the second main surface 2 side is less than 2.0 μm.

[0087] Figure 14 shows the relationship between drain voltage and drain current in the embodiment and reference example. In Figure 14, the horizontal axis represents the drain voltage (source-drain voltage), and the vertical axis represents the drain current. As shown in Figure 14, according to the embodiment, compared to the reference example, the ratio of the change in drain current to the change in drain voltage when the drain voltage is 20V or higher is suppressed. This indicates that the short-circuit current is suppressed by the embodiment.

[0088] Furthermore, in this embodiment, the total amount of p-type impurities contained in the electric field relaxation region 15 is greater than the total amount of n-type impurities contained in the electric field relaxation region 15. As described above, the electric field relaxation region 15 can be formed by ion implantation of p-type impurities into the epitaxial layer 21 having n-type impurities. By adjusting the concentrations of n-type and p-type impurities in the electric field relaxation region 15, desired on-resistance, breakdown voltage, and short-circuit withstand voltage can be obtained.

[0089] In this embodiment, in the embedded JTE region 17 of the terminal region 7, the distance between the third surface 17A, where the concentration of p-type impurities is at its maximum, and the fourth surface 17B, where the concentration of p-type impurities is 1 / 10 of the maximum, is 1.0 μm or more. Therefore, the withstand voltage of the terminal region 7 can be made higher than that of the active region 6, thereby improving the avalanche resistance.

[0090] The embedded JTE region 17 is electrically connected to the electric field relaxation region 15. Therefore, it is easy to control the electric field relaxation region 15 and the embedded JTE region 17 to the same potential.

[0091] Preferably, the distance between the first main surface 1 and the bottom surface 4 is less than 0.8 μm, and the distance D2 between the first main surface 1 and the first surface 15A is 0.8 μm or more. In this case, it is easier to reduce the on-resistance in the region between the body region 12 and the electric field relaxation region 15, i.e., the current diffusion region 14 and the first region 11A.

[0092] The distance D2 between the first main surface 1 and the first surface 15A is, for example, 3.0 μm or less, preferably 2.0 μm or less, and more preferably 1.5 μm or less. The smaller the distance D2, the easier it is to form the electric field relaxation region 15 by ion implantation through the first main surface 1.

[0093] [Differentiation] Next, a modified example of the embodiment will be described. The modified example differs from the embodiment mainly in the shape of the gate trench. Figure 15 is a cross-sectional view showing the configuration of a MOSFET (silicon carbide semiconductor device) according to a modified example of the embodiment. Figure 15 shows a cross-section similar to the cross-section along line II-II in Figure 1.

[0094] As shown in Figure 15, in the modified MOSFET 200, the gate trench 5 is a vertical trench. That is, the angle θ1 of the side surface 3 with respect to the plane including the bottom surface 4 may be 90°. The other configurations are the same as in the embodiment.

[0095] Similar effects to those of the embodiment can be obtained through such modifications.

[0096] In the above embodiments and reference examples, n-type was described as the first conductivity type and p-type as the second conductivity type, but p-type may be described as the first conductivity type and n-type as the second conductivity type. In the above embodiments and reference examples, a MOSFET was given as an example of a silicon carbide semiconductor device, but the silicon carbide semiconductor device may be, for example, an insulated gate bipolar transistor (IGBT). The effective concentration of p-type impurities and the effective concentration of n-type impurities in each of the above impurity regions can be measured, for example, by scanning capacitance microscopy (SCM) or secondary ion mass spectrometry (SIMS). The position of the interface between the p-type region and the n-type region (i.e., the pn junction interface) can be determined, for example, by SCM or SIMS. The distribution of the effective concentration of majority carriers in the current diffusion region can be determined without measuring the effective concentration, for example, based on the distribution of the depletion layer thickness generated by the pn junction between the current diffusion region and the body region. The thickness of the depletion layer can be determined, for example, by the SCM method or SIMS method.

[0097] The gate trenches may extend in a honeycomb pattern or be scattered in an island-like manner.

[0098] Although embodiments have been described in detail above, the invention is not limited to any particular embodiment, and various modifications and changes are possible within the scope described in the claims. [Explanation of symbols]

[0099] 1. First main surface 2. Second main surface 3 Sides 4. Bottom 5 Gate Trench 6 Active area 7 Termination area 10 Silicon carbide substrate 11. Drift Region 11A 1st area 11B 2nd area 11C Third area 12 Body Region 13 Source Area 14 Current Diffusion Region 15. Electric field relaxation region (first electric field relaxation region) 15A 1st page 15B 2nd side 16 Contact Area 17. Embedded JTE region (second electric field relaxation region) 17A 3rd page 17B Side 4 18 Surface JTE area 19 Connection Area 21 Epitaxial layer 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 source electrodes 61 Contact electrodes 62 Source Wiring 70 Drain electrode 81 Gate Insulator 82 Grid gate 83 Interlayer insulating film 84 Barrier metal film 85 Passivation membrane 86 Contact Holes 87 Opening 91 1st position 92 Side end face 93 Interface 100, 200 MOSFETs

Claims

1. A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, The silicon carbide substrate is A drift region having a first conductivity type, A body region provided on the drift region and having a second conductivity type different from the first conductivity type, A source region having the first conductivity type is provided on the body region so as to be separated from the drift region, It has, The first main surface is provided with a gate trench defined by a side surface that penetrates the source region and the body region and reaches the drift region, and a bottom surface connected to the side surface. The silicon carbide substrate further has a first field relaxation region provided between the bottom surface and the second main surface, and having the second conductivity type. The first electric field relaxation region is in a direction perpendicular to the first principal surface, The first surface where the concentration of the second type of impurity is at its maximum, The concentration of the second conductive type impurity is 1 / 10 of the maximum value, and the second surface is on the second main surface side of the first surface, It has, The distance between the first surface and the second surface is 1.0 μm or more. A silicon carbide semiconductor device wherein the distance from the first main surface to the interface between the first electric field relaxation region and the drift region on the second main surface side is 2.0 μm or more.

2. The first electric field relaxation region further contains impurities of the first conductivity type, The silicon carbide semiconductor device according to claim 1, wherein the total amount of impurities of the second conductivity type contained in the first field relaxation region is greater than the total amount of impurities of the first conductivity type contained in the first field relaxation region.

3. The distance between the first main surface and the bottom surface is less than 0.8 μm. The silicon carbide semiconductor device according to claim 1 or claim 2, wherein the distance between the first main surface and the first surface is 0.8 μm or more.

4. The maximum effective concentration of the second conductivity type impurity in the body region is 1.0 × 10⁻⁶ １８ cm －３ The above 5.0 x 10 １８ cm －３ The silicon carbide semiconductor device according to claim 1 or claim 2, wherein the following applies:

5. The silicon carbide semiconductor device according to claim 1 or claim 2, wherein the distance between the first main surface and the first surface is 3.0 μm or less.

6. The active region includes the body region, the source region, and the first electric field relaxation region, A termination region provided around the active region and including a second field relaxation region having the second conductivity type, It has, The second electric field relaxation region is in a direction perpendicular to the first main surface, The third surface where the concentration of the second conductivity type impurity is at its maximum value, The concentration of the second conductive type impurity is 1 / 10 of the maximum value, and the fourth surface is on the second main surface side of the third surface, It has, The silicon carbide semiconductor device according to claim 1 or claim 2, wherein the distance between the third surface and the fourth surface is 1.0 μm or more.

7. The silicon carbide semiconductor device according to claim 6, wherein the second field relaxation region is electrically connected to the first field relaxation region.

8. The silicon carbide semiconductor device according to claim 1 or claim 2, wherein the side surface of the gate trench includes a {0-33-8} plane.

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