Pseudo-vertical flip-chip light-emitting diode structure and method for manufacturing the same

Abstract

This invention provides a pseudo-vertical flip-chip light-emitting diode structure and a method for manufacturing the same. [Solution] The pseudo-vertical flip-chip light-emitting diode structure comprises a first semiconductor layer 10, a multiple quantum well layer 11, a second semiconductor layer 12, an insulating block 13, a conductive structure 14, an insulating ring 15, a current diffusion layer 16, a conductive block 17, and an insulating layer 18. The first semiconductor layer 10 and the multiple quantum well layer 11 are provided with grooves G, and the second semiconductor layer 12 has vias V that communicate with the grooves G. The conductive structure 14 is installed in the grooves G and vias V by the insulating block 13 and is exposed from within the vias V. The insulating ring 15 is installed in the second semiconductor layer 12 and covers the side wall of the conductive structure 14. The current diffusion layer 16 and the conductive block 17 are installed in the remaining area of ​​the second semiconductor layer 12, and the current diffusion layer 16 is located between the conductive block 17 and the conductive structure 14. The insulating layer 18 is installed in the current diffusion layer 16.

Description

Technical Field

[0001] The present invention relates to the field of diode manufacturing technology, and more particularly, to a pseudo vertical flip chip light emitting diode structure and a manufacturing method thereof.

Background Art

[0002] Conventional vertical light emitting diode structures include a lower electrode and an upper electrode. However, the upper electrode may partially block the light emitted by the active layer, which may affect the light emission efficiency. To solve this problem, the industry has been developing flip-chip LED structures. By moving the two electrodes to the same side, the light emitting surface is bonded to the substrate so that it faces downward, which not only prevents the problem of metal blocking light, but also can improve the package density and heat dissipation performance. Such a structure does not require wire bonding, simplifies the process, and has potential for high-power applications.

Summary of the Invention

Problems to be Solved by the Invention

[0003] However, although conventional flip-chip LEDs have the advantages of preventing light shielding and simplifying the package, they have faced difficulties in terms of current diffusion and thermal management. Since all the electrodes are installed on the same side, it is necessary to conduct the current horizontally across the entire active surface, resulting in non-uniform current distribution, non-uniform brightness, heat concentration on a single surface, and reduced long-term stability and effectiveness of the device. There is a hope that this problem can be improved by the arrangement of the backside electrode. However, when realizing the above structure according to the prior art, various complicated processes are required, resulting in an increase in manufacturing cost and problems in reliability.

[0004] As a result of diligent research, the inventors discovered that the above objective can be achieved by employing a pseudo-vertical flip-chip light-emitting diode structure and a method for manufacturing the same, and thus completed the present invention.

[0005] This invention has been made in view of the above circumstances, and one of its objectives is to solve the problems described above. Specifically, the present invention aims to provide a pseudo-vertical flip-chip light-emitting diode structure and a method for manufacturing the same that can simplify the process and improve the uniformity of the current distribution and the heat dissipation effect. [Means for solving the problem]

[0006] To achieve the above objective, a pseudo-vertical flip-chip light-emitting diode structure according to one aspect of the present invention comprises a first semiconductor layer, a multiple quantum well layer, a second semiconductor layer, an insulating block, a conductive structure, an insulating ring, a current diffusion layer, a conductive block, and an insulating layer. The multiple quantum well layer is installed on the first semiconductor layer, and grooves are provided in both the first semiconductor layer and the multiple quantum well layer. The second semiconductor layer is installed on the multiple quantum well layer, and the conductivity types of the first and second semiconductor layers are opposite. The second semiconductor layer has vias penetrating it, the vias are in communication with the grooves, and the cross-sectional area of ​​the vias is larger than the cross-sectional area of ​​the grooves. The insulating block is installed in the grooves and vias, covering the inner walls of the grooves and vias and the bottoms of the vias, while exposing the bottoms of the grooves. The conductive structure is installed in the grooves and vias, covering the insulating block and the first semiconductor layer, and the upper surface of the conductive structure is higher than the upper surface of the second semiconductor layer. The insulating ring is installed in the second semiconductor layer and covers the sidewall of the conductive structure, exposing the remaining area of ​​the second semiconductor layer. The current diffusion layer and conductive block are installed in the remaining area of ​​the second semiconductor layer, with the current diffusion layer located between the conductive block and the conductive structure. The insulating layer is installed in the current diffusion layer.

[0007] In a preferred example of the present invention, when a voltage is applied to the conductive block and the conductive structure, the current path is connected to the conductive block and the conductive structure and is distributed radially.

[0008] In a preferred example of the present invention, the first semiconductor layer and the second semiconductor layer are a P-type semiconductor layer and an N-type semiconductor layer, respectively.

[0009] In a preferred example of the present invention, the first semiconductor layer and the second semiconductor layer are an N-type semiconductor layer and a P-type semiconductor layer, respectively.

[0010] In a preferred example of the present invention, the insulating block, insulating ring, and insulating layer are made of the same material.

[0011] In a preferred example of the present invention, the current diffusion layer comprises a transparent metal oxide or indium tin oxide.

[0012] In preferred examples of the present invention, the conductive structure and the conductive block contain copper or nickel.

[0013] Furthermore, in order to solve the above-mentioned problems and achieve the objective, another aspect of the present invention, a method for manufacturing a pseudo-vertical flip-chip light-emitting diode structure, comprises the steps of sequentially forming a first semiconductor layer, a multiple quantum well layer, and a second semiconductor layer on an epitaxy substrate, wherein the conductivity types of the first and second semiconductor layers are opposite; forming multiple vias by penetrating the multiple quantum well layer and removing a portion of the first semiconductor layer, thereby forming multiple grooves, and penetrating the second semiconductor layer, wherein the vias are in communication with the grooves, and the cross-sectional area of ​​each via is made wider than the cross-sectional area of ​​each groove; forming multiple insulating blocks in the grooves and vias, respectively, covering the inner walls of the grooves and vias and the bottoms of the vias, while exposing the bottoms of the grooves; forming multiple conductive structures in the grooves and vias, respectively, covering the insulating blocks and the first semiconductor layer, and making the upper surface of the conductive structures higher than the upper surface of the second semiconductor layer; and forming multiple insulating blocks on the second semiconductor layer. The process includes the steps of: forming rings to cover the sidewalls of the conductive structure and expose the remaining region of the second semiconductor layer; sequentially forming a current diffusion layer and an insulating layer on the remaining region of the second semiconductor layer; removing multiple regions of the insulating layer and the current diffusion layer below them to expose multiple regions of the second semiconductor layer; forming multiple conductive blocks in the region of the second semiconductor layer; forming a temporary substrate on the conductive structure, conductive blocks, and insulating layer with a removable double-sided tape layer; removing the epitaxy substrate from the first semiconductor layer; cutting the conductive blocks and the second semiconductor layer, multiple quantum well layer, and first semiconductor layer below them to form multiple pseudo-vertical flip-chip light-emitting diode structures on the temporary substrate; and removing the removable double-sided tape layer and temporary substrate from the pseudo-vertical flip-chip light-emitting diode structures.

[0014] In a preferred example of the present invention, the epitaxy substrate is removed from the first semiconductor layer by a laser peeling process.

[0015] In a preferred example of the present invention, the conductive block and the second semiconductor layer, multiple quantum well layer, and first semiconductor layer located below it are cut by inductively coupled plasma etching (ICP).

[0016] In a preferred example of the present invention, the first semiconductor layer and the second semiconductor layer are a P-type semiconductor layer and an N-type semiconductor layer, respectively.

[0017] In a preferred example of the present invention, the first semiconductor layer and the second semiconductor layer are an N-type semiconductor layer and a P-type semiconductor layer, respectively.

[0018] In a preferred example of the present invention, the removable double-sided tape layer is a UV-release tape layer or a heat-release tape layer.

[0019] In a preferred example of the present invention, the insulating block, insulating ring, and insulating layer are made of the same material.

[0020] In a preferred example of the present invention, the current diffusion layer comprises a transparent metal oxide or indium tin oxide.

[0021] In a preferred example of the present invention, the temporary substrate is a silicon substrate or a ceramic substrate.

[0022] In preferred examples of the present invention, the epitaxy substrate is a semiconductor substrate, a silicon substrate, a silicon carbide substrate, a sapphire substrate, a gallium arsenide substrate, or a gallium nitride substrate.

[0023] In a preferred example of the present invention, the conductive structure and the conductive block include copper or nickel. [Effects of the Invention]

[0024] As the present invention is configured as described above, it produces the following effects. As described above, the pseudo-vertical flip-chip light-emitting diode structure and its manufacturing method simplify the process by forming a conductive block that encloses the conductive structure and by isolating the conductive block from the conductive structure with an insulating material, thereby distributing the current path radially and improving the uniformity of the current distribution and the heat dissipation effect.

[0025] Other features of the present invention will be clarified by the description in this specification and the accompanying drawings.

Brief Description of the Drawings

[0026] [Figure 1] It is a cross-sectional view showing a pseudo-vertical flip-chip light-emitting diode structure according to an embodiment of the present invention. [Figure 2a] It is a cross-sectional view showing the structure of each step of a pseudo-vertical flip-chip light-emitting diode structure according to an embodiment of the present invention. [Figure 2b] It is a cross-sectional view showing the structure of each step of a pseudo-vertical flip-chip light-emitting diode structure according to an embodiment of the present invention. [Figure 2c] It is a cross-sectional view showing the structure of each step of a pseudo-vertical flip-chip light-emitting diode structure according to an embodiment of the present invention. [Figure 2d] It is a cross-sectional view showing the structure of each step of a pseudo-vertical flip-chip light-emitting diode structure according to an embodiment of the present invention. [Figure 2e] It is a cross-sectional view showing the structure of each step of a pseudo-vertical flip-chip light-emitting diode structure according to an embodiment of the present invention. [Figure 2f] It is a cross-sectional view showing the structure of each step of a pseudo-vertical flip-chip light-emitting diode structure according to an embodiment of the present invention. [Figure 2g] It is a cross-sectional view showing the structure of each step of a pseudo-vertical flip-chip light-emitting diode structure according to an embodiment of the present invention. [Figure 2h] It is a cross-sectional view showing the structure of each step of a pseudo-vertical flip-chip light-emitting diode structure according to an embodiment of the present invention. [Figure 2i] It is a cross-sectional view showing the structure of each step of a pseudo-vertical flip-chip light-emitting diode structure according to an embodiment of the present invention. [Figure 2j] It is a cross-sectional view showing the structure of each step of a pseudo-vertical flip-chip light-emitting diode structure according to an embodiment of the present invention. [Figure 2k]This is a cross-sectional view showing the structure of each step in a pseudo-vertical flip-chip light-emitting diode structure according to one embodiment of the present invention. [Figure 2l] This is a cross-sectional view showing the structure of each step in a pseudo-vertical flip-chip light-emitting diode structure according to one embodiment of the present invention. [Figure 3] Figure 2l is a top view showing a pseudo-vertical flip-chip light-emitting diode structure. [Modes for carrying out the invention]

[0027] Embodiments of the present invention will be described below with reference to the drawings. In the drawings and specification, the same reference numerals indicate the same or similar components. In the drawings, the shape and thickness may be enlarged for simplification or ease of representation. It should be noted that components not disclosed in the drawings or described in the specification are obvious to those skilled in the art. Those skilled in the art can make various changes and improvements based on the content of the present invention. When an element is described as being "on...", it generally means that the element is directly on another element, although the other element may be located between them. Conversely, when an element is described as being "directly" on another element, the other element cannot be located between them. The "and / or" used in this text includes any combination of one or more of the related items listed. In this specification, the phrase "one embodiment" or "example" refers to a specific element, structure, or feature relating to at least one embodiment. Therefore, the phrase "one embodiment" or "example" in this specification does not necessarily refer to the same embodiment. Furthermore, specific components, structures, and features described in multiple embodiments can be appropriately combined. The following is merely illustrative, and it will be understood by those skilled in the art that various modifications are possible, and that such modifications also fall within the scope of the present invention. The scope of the present invention is defined by the appended claims. In the specification and claims, "one" and "the foregoing" refer to "one or at least one" element or component unless otherwise specified. Also, singular articles include the meaning of multiple elements or components unless it is clearly indicated as plural from the surrounding sentences. In addition, "inside" includes the meaning of "inside" and "on top" unless otherwise specified. Unless otherwise specified, the terms used in the specification and claims have the same meaning as understood by those skilled in the art. In addition, some specific terms will be clearly defined and explained below. The terms used in the specification are merely illustrative and do not limit the scope of the present invention. Furthermore, the present invention is not limited to the following embodiments. The terms "comprising, including, involving," "having," and "containing" used herein are in open-ended form, meaning they are not limited to those listed. Furthermore, no embodiment or claim of the present invention is required to achieve all of the purposes, advantages, or features disclosed herein. In addition, the abstract and title of the invention are for use in searching patent documents and do not limit the scope of the claims of the present invention. Furthermore, "(electrical) connection" refers to direct and indirect means of (electrical) connection. For example, when a first device is said to be connected to a second device, it means that the first device is directly connected to the second device, or that it is indirectly connected to the second device via another device or other means of connection. Also, while electrical signals may undergo attenuation or other changes during their transmission, unless otherwise specified, the signal at the source or provider and the signal at the receiver should be considered to be the same signal. For example, when an electrical signal S is transmitted from terminal A of an electronic circuit to terminal B of an electronic circuit, a voltage drop occurs as it passes through the source and drain electrodes and / or parasitic capacitance of a transistor switch. However, unless the attenuation or other changes that occur during transmission are intentionally used to achieve a specific technical effect, the electrical signal S at terminal A of the electronic circuit and the electrical signal S at terminal B should be considered to be the same signal. Unless otherwise specified, conditional statements or words such as "can" or "might" are often intended to express features, components, or steps that are present in this embodiment but may also be interpreted as unnecessary. In other embodiments, these features, components, or steps may not be necessary.

[0028] The pseudo-vertical flip-chip light-emitting diode structure and its manufacturing method according to the present invention simplify the process by forming a conductive block that encloses the conductive structure and by isolating the conductive block and the conductive structure with an insulating material, thereby distributing the current path radially and improving the uniformity of the current distribution and the heat dissipation effect.

[0029] Figure 1 is a cross-sectional view showing a pseudo-vertical flip-chip light-emitting diode structure according to one embodiment of the present invention. Next, an embodiment of the pseudo-vertical flip-chip light-emitting diode structure according to the present invention will be described with reference to Figure 1.

[0030] The pseudo-vertical flip-chip light-emitting diode structure 1 comprises a first semiconductor layer 10, a multiple quantum well layer 11, a second semiconductor layer 12, an insulating block 13, a conductive structure 14, an insulating ring 15, a current diffusion layer 16, a conductive block 17, and an insulating layer 18. In this embodiment, the first semiconductor layer 10 and the second semiconductor layer 12 are a P-type semiconductor layer and an N-type semiconductor layer, respectively. In other embodiments, the first semiconductor layer 10 and the second semiconductor layer 12 are an N-type semiconductor layer and a P-type semiconductor layer, respectively. The insulating block 13, the insulating ring 15, and the insulating layer 18 may be made of the same material. The conductive structure 14 and the conductive block 17 may contain copper or nickel, however, the present invention is not limited to these. The multiple quantum well layer 11 is installed on the first semiconductor layer 10, and grooves G are provided in the first semiconductor layer 10 and the multiple quantum well layer 11. The second semiconductor layer 12 is installed in the multiple quantum well layer 11, and the conductivity types of the first semiconductor layer 10 and the second semiconductor layer 12 are opposite. The second semiconductor layer 12 has vias V that penetrate it, and the vias V are in communication with the groove G, and the cross-sectional area of ​​the vias V is larger than the cross-sectional area of ​​the groove G. The insulating block 13 is installed in the groove G and vias V, covering the inner walls of the groove G and vias V and the bottom of the vias V, while exposing the bottom of the groove G. The conductive structure 14 is installed in the groove G and vias V, covering the insulating block 13 and the first semiconductor layer 10, and the upper surface of the conductive structure 14 is higher than the upper surface of the second semiconductor layer 12. The insulating ring 15 is installed in the second semiconductor layer 12, covering the side walls of the conductive structure 14, while exposing the remaining area of ​​the second semiconductor layer 12. The current diffusion layer 16 and the conductive block 17 are installed in the remaining area of ​​the second semiconductor layer 12, with the current diffusion layer 16 located between the conductive block 17 and the conductive structure 14. The insulating layer 18 is installed in the current diffusion layer 16. The current diffusion layer 16 can be used for conductivity and may also contain a transparent metal oxide or indium tin oxide. When a voltage is applied to the conductive block 17 and the conductive structure 14, the current path is connected to the conductive block 17 and the conductive structure 14 and is distributed radially (shown by dashed lines in the figure). At this time, light rays are emitted downward from the multiple quantum well layer 11. Because the cross-sectional area of ​​via V is wider than the cross-sectional area of ​​groove G, the contact area of ​​the conductive structure 14 is increased, and the light emission area is also increased.As described above, the conductive block 17 encloses the conductive structure 14, and the conductive block 17 and the conductive structure 14 are isolated by an insulating material, thereby simplifying the process, distributing the current path radially, and improving the uniformity of the high current distribution, heat dissipation effect, and light emission effect with the multiple quantum well layer 11.

[0031] Figures 2a to 2l are cross-sectional views showing the structure of each step in a pseudo-vertical flip-chip light-emitting diode structure according to one embodiment of the present invention. Figure 3 is a top view showing the pseudo-vertical flip-chip light-emitting diode structure shown in Figure 2l.

[0032] First, as shown in Figure 2a, a first semiconductor layer 10, a multiple quantum well layer 11, and a second semiconductor layer 12 are sequentially formed on an epitaxy substrate 2, with the conductivity types of the first semiconductor layer 10 and the second semiconductor layer 12 being opposite. The epitaxy substrate 2 may be a semiconductor substrate, a silicon substrate, a silicon carbide substrate, a sapphire substrate, a gallium arsenide substrate, or a gallium nitride substrate, but the present invention is not limited to these. Next, as shown in Figure 2b, a plurality of grooves G are formed by penetrating the multiple quantum well layer 11 and removing a portion of the first semiconductor layer 10, and a plurality of vias V are formed by penetrating the second semiconductor layer 12. Each via V is in communication with a groove G, and the cross-sectional area of ​​each via V is larger than the cross-sectional area of ​​each groove G. As shown in Figure 2c, a plurality of insulating blocks 13 are formed in the grooves G and vias V, respectively, covering the inner walls of the grooves G and vias V and the bottoms of the vias V, while exposing the bottoms of the grooves G. As shown in Figure 2d, the insulating block 13 and the first semiconductor layer 10 are covered by forming multiple conductive structures 14 in the grooves G and vias V, respectively, and the upper surface of the conductive structures 14 is higher than the upper surface of the second semiconductor layer 12. As shown in Figure 2e, the side walls of the conductive structures 14 are covered by forming multiple insulating rings 15 on the second semiconductor layer 12, respectively, while exposing the remaining area of ​​the second semiconductor layer 12. As shown in Figure 2f, a current diffusion layer 16 and an insulating layer 18 are sequentially formed on the remaining area of ​​the second semiconductor layer 12. As shown in Figure 2g, multiple areas of the second semiconductor layer 12 are exposed by removing multiple areas of the insulating layer 18 and the current diffusion layer 16 below it. As shown in Figure 2h, multiple conductive blocks 17 are formed on the aforementioned areas of the second semiconductor layer 12. As shown in Figure 2i, a temporary substrate 4 is formed on the conductive structures 14, conductive blocks 17, and insulating layer 18 using a removable double-sided tape layer 3. For example, the removable double-sided tape layer 3 is a UV-release tape layer or a heat-release tape layer. The temporary substrate 4 may be a silicon substrate or a ceramic substrate, but the present invention is not limited to these. As shown in Figure 2j, the epitaxy substrate 2 is removed from the first semiconductor layer 10. For example, the epitaxy substrate 2 is removed from the first semiconductor layer 10 by a laser peeling process.As shown in Figure 2k, multiple pseudo-vertical flip-chip light-emitting diode structures 1 are formed on a temporary substrate 4 by cutting the conductive block 17 and the second semiconductor layer 12, multiple quantum well layer 11, and first semiconductor layer 10 located beneath it. For example, the conductive block 17 and the second semiconductor layer 12, multiple quantum well layer 11, and first semiconductor layer 10 located beneath it are cut by inductively coupled plasma etching (ICP). As shown in Figure 2l, the double-sided tape layer 3 and temporary substrate 4 that can be removed from the pseudo-vertical flip-chip light-emitting diode structure 1 are removed, for example, by light irradiation or heating. Figure 3 is a bottom view showing all the matrix-arranged pseudo-vertical flip-chip light-emitting diode structures 1. If substantially the same results can be obtained, these steps do not necessarily have to be performed in the execution order shown in Figures 2a to 2l.

[0033] According to the above-described embodiment, the pseudo-vertical flip-chip light-emitting diode structure and its manufacturing method simplify the process by forming a conductive block that encloses the conductive structure and by isolating the conductive block and the conductive structure with an insulating material, thereby distributing the current path radially and improving the uniformity of the current distribution and the heat dissipation effect.

[0034] Although embodiments of the present invention have been described in detail above with reference to the drawings, the specific configuration is not limited to these embodiments, and design modifications and the like are also included within the scope of the gist of the present invention. [Explanation of Symbols]

[0035] 1. Pseudo-vertical flip-chip light-emitting diode structure 10 First Semiconductor Layer 11 Multiple quantum well layers 12 Second Semiconductor Layer 13 Insulating Block 14 Conductive structure 15 Insulating ring 16 Current Diffusion Layer 17 Conductive Block 18 Insulating layer V Via G groove

Claims

1. The first semiconductor layer, A multiple quantum well layer installed on the first semiconductor layer, wherein grooves are provided in the first semiconductor layer and the multiple quantum well layer, A second semiconductor layer installed in the multiple quantum well layer, wherein the conductivity types of the first and second semiconductor layers are opposite, the second semiconductor layer has vias penetrating it, the vias are in communication with the groove, and the cross-sectional area of ​​the vias is wider than the cross-sectional area of ​​the groove. An insulating block is installed in the groove and the via, covering the inner walls of the groove and the via and the bottom of the via, while exposing the bottom of the groove. A conductive structure installed in the groove and the via, covering the insulating block and the first semiconductor layer, wherein the upper surface of the conductive structure is higher than the upper surface of the second semiconductor layer, An insulating ring is installed on the second semiconductor layer, covering the side wall of the conductive structure and exposing the remaining area of ​​the second semiconductor layer, A current diffusion layer and a conductive block are installed in the remaining region of the second semiconductor layer, wherein the current diffusion layer is located between the conductive block and the conductive structure, A pseudo-vertical flip-chip light-emitting diode structure characterized by comprising an insulating layer installed in the current diffusion layer.

2. The pseudo-vertical flip-chip light-emitting diode structure according to claim 1, characterized in that when a voltage is applied to the conductive block and the conductive structure, the current path is connected to the conductive block and the conductive structure and is distributed radially.

3. The pseudo-vertical flip-chip light-emitting diode structure according to claim 1, characterized in that the first semiconductor layer and the second semiconductor layer are a P-type semiconductor layer and an N-type semiconductor layer, respectively.

4. The pseudo-vertical flip-chip light-emitting diode structure according to claim 1, characterized in that the first semiconductor layer and the second semiconductor layer are an N-type semiconductor layer and a P-type semiconductor layer, respectively.

5. A first semiconductor layer, a multiple quantum well layer, and a second semiconductor layer are sequentially formed on an epitaxy substrate, wherein the conductivity types of the first and second semiconductor layers are opposite. The steps include: penetrating the multiple quantum well layer and removing a portion of the first semiconductor layer to form a plurality of grooves, penetrating the second semiconductor layer and forming a plurality of vias, each of which vias is in communication with each of the grooves, and the cross-sectional area of ​​each via is made wider than the cross-sectional area of ​​each groove; The steps include forming a plurality of insulating blocks in these grooves and these vias, covering the inner walls of these grooves and these vias and the bottoms of these vias, while exposing the bottoms of the grooves, The steps include forming a plurality of conductive structures in these grooves and these vias, covering the insulating block and the first semiconductor layer, and making the upper surface of these conductive structures higher than the upper surface of the second semiconductor layer, The steps include forming a plurality of insulating rings on the second semiconductor layer such that they cover the side walls of the conductive structures and expose the remaining area of ​​the second semiconductor layer, The steps include sequentially forming a current diffusion layer and an insulating layer on the remaining region of the second semiconductor layer, The steps include removing multiple regions of the insulating layer and the current diffusion layer located below them, thereby exposing multiple regions of the second semiconductor layer, The steps include forming a plurality of conductive blocks on these regions of the second semiconductor layer, The steps include forming a temporary substrate on these conductive structures, these conductive blocks, and the insulating layer using a removable double-sided tape layer, The steps include removing the epitaxy substrate from the first semiconductor layer, The steps include cutting these conductive blocks and the second semiconductor layer, the multiple quantum well layer, and the first semiconductor layer located below them, and forming a plurality of pseudo-vertical flip-chip light-emitting diode structures on the temporary substrate, A method for manufacturing a pseudo-vertical flip-chip light-emitting diode structure, characterized by comprising the step of removing the removable double-sided tape layer and the temporary substrate from the pseudo-vertical flip-chip light-emitting diode structure.

6. A method for manufacturing a pseudo-vertical flip-chip light-emitting diode structure according to claim 5, characterized in that the epitaxy substrate is removed from the first semiconductor layer by a laser peeling process.

7. The method for manufacturing a pseudo-vertical flip-chip light-emitting diode structure according to claim 5, characterized in that the conductive block and the second semiconductor layer, the multiple quantum well layer, and the first semiconductor layer located below it are cut by inductively coupled plasma etching (ICP).

8. The method for manufacturing a pseudo-vertical flip-chip light-emitting diode structure according to claim 5, characterized in that the first semiconductor layer and the second semiconductor layer are a P-type semiconductor layer and an N-type semiconductor layer, respectively.

9. The method for manufacturing a pseudo-vertical flip-chip light-emitting diode structure according to claim 5, characterized in that the first semiconductor layer and the second semiconductor layer are an N-type semiconductor layer and a P-type semiconductor layer, respectively.

10. The method for manufacturing a pseudo-vertical flip-chip light-emitting diode structure according to claim 5, characterized in that the removable double-sided tape layer is a UV release tape layer or a heat release tape layer.

Images