Semiconductor equipment

Abstract

To provide a semiconductor device that uses an oxide semiconductor and is highly reliable.SOLUTION: A semiconductor device includes a laminated structure including an oxide semiconductor layer and an insulation layer in contact with the oxide semiconductor layer. The oxide semiconductor layer includes a first layer where a channel is formed, and a second layer that is provided between the first layer and the insulation layer and has energy at a bottom end of a conduction band closer to a vacuum level than that at a bottom end of the conduction band of the first layer. In the above, the second layer functions as an insulation layer in contact with the oxide semiconductor layer, and a barrier layer that suppresses formation of defect level between the second layer and the channel. Further, the first layer and the second layer each include an ultra-fine crystal portion to such an extent that an atomic arrangement has no periodicity macroscopically or to such an extent that the atomic arrangement has no long-range order macroscopically. The first layer and the second layer include the crystal portion that the atomic arrangement is confirmed to have periodicity in a range of 1 nm or more and 10 nm or less, for example.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The inventions disclosed herein relate to semiconductor devices and methods for manufacturing semiconductor devices.

[0002] In this specification, a semiconductor device refers to a device that can function by utilizing semiconductor properties. This refers to all types of devices, including electro-optical devices, semiconductor circuits, display devices, light-emitting devices, and electronic equipment, all of which are semiconductors. It is a body device. [Background technology]

[0003] A technology that constructs transistors using semiconductor films formed on substrates with insulating surfaces is attracting attention. It is being considered. The transistor is used in integrated circuits (ICs) and image display devices (also simply as a display device). It is widely applied to electronic devices such as (denoted as follows). Semiconductors applicable to transistors Silicon-based semiconductor materials are widely known as conductive films, but other materials also have semiconductor properties Metal oxides (oxide semiconductors) exhibiting properties are attracting attention.

[0004] For example, using amorphous oxides containing In, Zn, Ga, Sn, etc. as oxide semiconductors A technique for fabricating transistors is disclosed in Patent Document 1. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2006-165529 [Overview of the project] [Problems that the invention aims to solve]

[0006] Although transistors using oxide semiconductors can obtain transistor characteristics relatively easily, The physical properties are liable to become unstable, and it is difficult to ensure reliability.

[0007] Therefore, one aspect of the present invention is to provide a highly reliable semiconductor device including an oxide semiconductor, and this is taken as one of the problems. is taken as one of the problems.

[0008] Note that the description of the above problems does not prevent the existence of other problems. Other problems than the above will be apparent from the description in the specification and the like, and it is possible to extract other problems than the above from the description in the specification and the like. will be apparent from the description in the specification and the like, and it is possible to extract other problems than the above from the description in the specification and the like. from the description in the specification and the like.

Means for Solving the Problems

[0009] One aspect of the disclosed invention includes a stacked structure including an oxide semiconductor layer and an insulating layer in contact with the oxide semiconductor layer. The oxide semiconductor layer includes a first layer in which a channel is formed, and a second layer provided between the first layer and the insulating layer and having a conduction band lower end energy closer to the vacuum level than the conduction band lower end energy of the first layer. Herein, the second layer functions as a barrier layer that suppresses the formation of defect levels between the insulating layer in contact with the oxide semiconductor layer and the channel. Further, the first layer and the second layer each include extremely fine crystal portions that macroscopically have no periodicity in the atomic arrangement. For example, they include crystal portions in which periodicity in the atomic arrangement is confirmed in the range of 1 nm or more and 10 nm or less. The first layer and the second layer including the crystal portions are oxide semiconductor layers in which the defect level density is reduced as compared with an amorphous oxide semiconductor layer, and by applying such an oxide semiconductor layer, it is possible to suppress fluctuations in the electrical characteristics of the transistor due to the defect level density. The oxide semiconductor layer includes a first layer in which a channel is formed, and a second layer provided between the first layer and the insulating layer and having a conduction band lower end energy closer to the vacuum level than the conduction band lower end energy of the first layer. The oxide semiconductor layer includes a first layer in which a channel is formed, and a second layer provided between the first layer and the insulating layer and having a conduction band lower end energy closer to the vacuum level than the conduction band lower end energy of the first layer. Herein, the second layer functions as a barrier layer that suppresses the formation of defect levels between the insulating layer in contact with the oxide semiconductor layer and the channel. Herein, the second layer functions as a barrier layer that suppresses the formation of defect levels between the insulating layer in contact with the oxide semiconductor layer and the channel. Herein, the second layer functions as a barrier layer that suppresses the formation of defect levels between the insulating layer in contact with the oxide semiconductor layer and the channel. Further, the first layer and the second layer each include extremely fine crystal portions that macroscopically have no periodicity in the atomic arrangement. For example, they include crystal portions in which periodicity in the atomic arrangement is confirmed in the range of 1 nm or more and 10 nm or less. The first layer and the second layer including the crystal portions are oxide semiconductor layers in which the defect level density is reduced as compared with an amorphous oxide semiconductor layer, and by applying such an oxide semiconductor layer, it is possible to suppress fluctuations in the electrical characteristics of the transistor due to the defect level density. The first layer and the second layer including the crystal portions are oxide semiconductor layers in which the defect level density is reduced as compared with an amorphous oxide semiconductor layer, and by applying such an oxide semiconductor layer, it is possible to suppress fluctuations in the electrical characteristics of the transistor due to the defect level density. and it is possible to suppress fluctuations in the electrical characteristics of the transistor due to the defect level density.

[0010] More specifically, for example, the following configuration can be adopted.

[0011] One aspect of the present invention comprises an oxide semiconductor layer and a gate electrode layer overlapping the oxide semiconductor layer, A gate insulating layer between the oxide semiconductor layer and the gate electrode layer, and an electrically connected oxide semiconductor layer. The source electrode layer and drain electrode layer overlap each other via an oxide semiconductor layer with the gate insulating layer. The oxide semiconductor layer has an insulating layer and a first layer in which a channel is formed and a first layer The structure includes a laminated structure of a first layer and a second layer between the first and second layers, each of which is 10 It contains crystals with a size of less than nm, and the first and second layers are each In-M-Zn oxide Oxidation expressed as a substance (where M is Al, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf) It is a semiconductor layer, and the atomic ratio of M to indium in the second layer is the same as that of the indium in the first layer. This semiconductor device is characterized by having a higher atomic ratio of M to zinc.

[0012] Furthermore, one aspect of the present invention includes an oxide semiconductor layer and a gate electrode that overlaps with the oxide semiconductor layer. The layer, the gate insulating layer between the oxide semiconductor layer and the gate electrode layer, and the oxide semiconductor layer and electrically The source electrode layer and drain electrode layer are connected to the gate insulating layer via an oxide semiconductor layer. The oxide semiconductor layer has an insulating layer that overlaps it, and the first layer in which a channel is formed, and the second It includes a second layer between the first layer and the insulating layer, and a third layer between the first layer and the gate insulating layer. The first to third layers each contain crystals with a size of 10 nm or less, and the first layer, The second and third layers are In-M-Zn oxide (where M is Al, Ga, Ge, Y), respectively. An oxide semiconductor layer represented by (Zr, Sn, La, Ce or Hf), and a second The atomic ratio of M to indium in the third layer and the atomic ratio of M to indium in the third layer are Each semiconductor is characterized by having a higher atomic ratio of M to indium in the first layer. It is a body device.

[0013] In the semiconductor device described above, the third layer has an electron beam probe diameter of 1 nm to 10 nm. In the diffraction pattern of nanobeam electron diffraction focused to a specific direction, the circumferentially arranged Multiple spots are observed.

[0014] Furthermore, in the semiconductor device described above, the first layer and the second layer have an electron beam probe diameter of 1n In the diffraction pattern of nanobeam electron diffraction focused to m or less than 10 nm, Multiple spots arranged in a circular pattern are observed.

[0015] Furthermore, in the semiconductor device described above, the energy at the lower end of the conduction band of the second layer is the same as the energy at the lower end of the conduction band of the first layer. The energy level is closer to the vacuum level in the range of 0.05 eV to 2 eV below the energy at the bottom of the guide band. preferable.

[0016] Furthermore, in the above semiconductor device, the insulating layer is provided in contact with the oxide semiconductor layer, and insulating In a contact hole (also called an opening) provided in the layer, the oxide semiconductor layer and the saw The source electrode layer and the drain electrode layer may be electrically connected. In this case, the source electrode layer and The drain electrode layer is provided in the insulating layer and in the contact holes provided in the second layer, It is preferable to electrically connect to the layer.

[0017] Furthermore, in the semiconductor device described above, the source electrode layer and the drain electrode layer are located on the side of the first layer. and provided so as to be in contact with a part of the upper surface, the third layer is the source electrode layer and the drain electrode layer It is provided on the source electrode layer and the drain electrode layer so as to be in contact with a portion of the first layer that is exposed from there. It's okay if it's done that way. [Effects of the Invention]

[0018] According to one aspect of the present invention, a highly reliable semiconductor device can be provided. [Brief explanation of the drawing]

[0019] [Figure 1] A schematic diagram showing an example of a laminated structure included in a semiconductor device according to one embodiment of the present invention and its band diagram. [Figure 2] A schematic diagram showing an example of a laminated structure included in a semiconductor device according to one embodiment of the present invention and its band diagram. [Figure 3] A schematic diagram showing an example of a laminated structure included in a semiconductor device according to one embodiment of the present invention and its band diagram. [Figure 4] Figure showing a cross-sectional TEM image and nanobeam electron diffraction pattern of a nanocrystalline oxide semiconductor layer. [Figure 5] A schematic diagram showing the method for preparing the sample used as a reference example. [Figure 6] A diagram showing the nanobeam electron diffraction pattern of a nanocrystalline oxide semiconductor layer. [Figure 7] A diagram showing a cross-sectional TEM image of a nanocrystalline oxide semiconductor layer. [Figure 8] A diagram showing the nanobeam electron diffraction pattern of a nanocrystalline oxide semiconductor layer. [Figure 9] A diagram showing the nanobeam electron diffraction pattern of a quartz glass substrate. [Figure 10] A diagram showing the nanobeam electron diffraction pattern of a nanocrystalline oxide semiconductor layer. [Figure 11] This figure shows the measurement results of the XRD spectrum of a nanocrystalline oxide semiconductor layer. [Figure 12] A plan view and a cross-sectional view showing one embodiment of a semiconductor device. [Figure 13] A plan view and a cross-sectional view showing one embodiment of a semiconductor device. [Figure 14] A diagram showing an example of a method for manufacturing a semiconductor device. [Figure 15]A plan view and a cross-sectional view showing one embodiment of a semiconductor device. [Figure 16] A plan view and a cross-sectional view showing one embodiment of a semiconductor device. [Figure 17] A diagram showing an example of a method for manufacturing a semiconductor device. [Figure 18] Circuit diagram of a semiconductor device according to one aspect of the present invention. [Figure 19] Circuit diagram and conceptual diagram of a semiconductor device according to one aspect of the present invention. [Figure 20] A diagram illustrating the configuration of a display panel according to an embodiment. [Figure 21] A diagram illustrating a block diagram of an electronic device according to an embodiment. [Figure 22] A diagram illustrating the external view of an electronic device according to an embodiment. [Modes for carrying out the invention]

[0020] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is... It is easy for anyone skilled in the art to see that the form and details can be modified in various ways, without being limited to the description below. This is understood to mean that the present invention is construed to be limited to the embodiments described below. It's not that.

[0021] In the configuration of the present invention described below, the same part or a part having a similar function is The same reference numerals are used consistently across different drawings, and explanations of their repetition are omitted. When referring to a part that has the function of the same, the hatch pattern is the same, and in cases where no special designation is given, There is a match.

[0022] In each figure described herein, the size of each component, the thickness of the film, or the area is clearly indicated. It may be exaggerated for illustrative purposes. Therefore, it is not necessarily limited to that scale.

[0023] In this specification, the ordinal numbers used as "1st," "2nd," etc., are for convenience only. It does not indicate the order of processes or stacking order. Therefore, for example, "the first" is not "the second." This can be appropriately replaced with "" or "the third," etc., in the explanation. The ordinal numbers used and the ordinal numbers used to specify one aspect of the present invention do not coincide. There is a match.

[0024] (Embodiment 1) In this embodiment, the oxide semiconductor layer included in a semiconductor device according to one aspect of the present invention is shown in Figure This will be explained with reference to Figures 1 through 11.

[0025] Figure 1(A) is a schematic diagram showing an example of a laminated structure included in a semiconductor device according to one embodiment of the present invention. A semiconductor device according to one aspect of the present invention comprises a gate electrode layer 102 and a gate electrode layer 102. A gate insulating layer 104, an oxide semiconductor layer 106 on the gate insulating layer 104, and an oxide semiconductor layer The laminated structure includes an insulating layer 108 on 106.

[0026] The oxide semiconductor layer 106 is located between the first layer 106a and the insulating layer 108. It has a laminated structure with a second layer 106b.

[0027] The first layer 106a and the second layer 106b show no periodicity in their atomic arrangement macroscopically. It is an oxide semiconductor layer containing extremely fine crystalline parts. Specifically, the first layer 106a and Layer 106b of 2 is 1 nm to 10 nm or 1 nm to 3 nm in size. The crystalline portion of the material (hereinafter referred to as nanocrystal (nc) in this specification, etc.) It also includes the notation.

[0028] The crystalline portions contained in the first layer 106a and the second layer 106b are close in size to the size of the crystalline portions. or an electric probe with a probe diameter smaller than the size of the crystal (for example, 1 nm to 30 nm) In the electron diffraction pattern obtained by irradiating with a sub-beam, the light shines in a circular (ring-like) pattern. It has a high-intensity region, and multiple spots (bright points) are observed within the high-luminosity region. The arrangement of several spots in a circular pattern forms a ring-shaped area of ​​high brightness. This can also be rephrased as follows.

[0029] Furthermore, the measurement range by electron diffraction is defined in both the planar and depth directions, including the crystalline portion. By reducing the size to a range close to or smaller than the size of the crystal part, In the sub-ray diffraction pattern, if spots exhibiting regularity in a crystalline state are observed, Yes. To reduce the measurement range in the planar direction, the electron beam probe diameter can be reduced (for example, 1 nm). The measurement should be less than 30 nm. Furthermore, to reduce the measurement range in the depth direction, for example, The region should be thinned to 10 nm or less by ion milling or similar processing before measurement.

[0030] Furthermore, both the first layer 106a and the second layer 106b have electrical currents in both the cross-sectional and planar directions. In the sub-ray diffraction pattern, multiple spoilage particles are arranged within the aforementioned ring-shaped high-luminosity region. It is possible to confirm the crystalline portion. The crystalline portion does not have directionality in the cross-sectional or planar direction. By being randomly included in the film, spots can be identified by electron diffraction patterns in the cross-sectional direction. The spots observed in the electron diffraction pattern in the planar direction show a similar trend.

[0031] Furthermore, the crystalline portion contained in the oxide semiconductor layer is 10 nm or less, and the probe diameter used is If the crystalline portion is larger, the electron diffraction patterns in the cross-sectional direction and the planar direction will be different. In some cases, this tendency may be observed. For example, the periphery of an atomic arrangement that is larger than the probe diameter in the cross-sectional direction. It has periodicity, and the atomic arrangement has a periodicity in the plane that is equal to or smaller than the probe diameter. When measuring the crystalline portion having this, the spots confirmed by the electron diffraction pattern in the cross-sectional direction are The spots can be broader than those observed in the electron diffraction pattern in the plane. Furthermore, the first layer 106a and the second layer 106b are electrically charged in the cross-sectional and planar directions, respectively. A field having regions where the trends of the sub-ray diffraction patterns are similar and regions where different trends are observed. There is a match. For example, in the first layer 106a, near the interface with the second layer 106b The electron diffraction patterns in the cross-sectional and planar directions show different trends, and the gate insulating layer 1 Near the interface with 04, the electron diffraction patterns in the cross-sectional and planar directions show similar trends. This may indicate that.

[0032] As mentioned above, the atomic arrangement in the first layer 106a and the second layer 106b has a periodicity. The region exhibiting this property is, for example, a very small range of 1 nm to 10 nm, and also different connections. No order is observed in the crystal orientation between the crystal regions. Therefore, the first layer 106a and the second layer No orientation is observed in the entire film of 106b. Therefore, the oxide semiconductor layer 106 Depending on the analysis method, the crystalline portions contained in the first layer 106a and the second layer 106b can be analyzed. In some cases, this is not possible, making it indistinguishable from an amorphous oxide semiconductor layer.

[0033] For example, the first layer 106a or the second layer 106b containing the crystalline portion are respectively viewed in the cross-sectional direction and Transmission electron microscope (TEM) from a planar direction Even when observed with a microscope, it is difficult to clearly confirm the crystal structure. That is the case.

[0034] Furthermore, the oxide semiconductor layer 106 is contained in the first layer 106a and the second layer 106b X-ray diffraction (XRD) is a method that uses X-rays with a diameter larger than that of the crystal region. When structural analysis is performed using a (tion) device, analysis using the out-of-plane method is No peaks indicating crystal planes were detected.

[0035] Furthermore, a probe larger than the crystalline portion is used with respect to the first layer 106a or the second layer 106b. Electron diffraction (also called limited-field electron diffraction) uses an electron beam with a diameter (for example, 100 nm or more). In some cases, a diffraction pattern resembling a halo pattern may be observed.

[0036] Furthermore, as the probe diameter of the electron beam increases, the aforementioned ring-shaped region of high brightness appears It is confirmed that the ring becomes broader and wider. Also, the probe diameter can be changed, for example, If the wavelength is 50 nm or higher, it becomes difficult to observe a spot within a ring-shaped area of ​​high brightness. Yes.

[0037] The oxide semiconductor layer containing nanocrystals shown in this embodiment (hereinafter also referred to as the nanocrystalline oxide semiconductor layer) It is a dense film with a higher film density compared to an amorphous oxide semiconductor layer. The fewer defects there are in a semiconductor layer, or the lower the concentration of impurities such as hydrogen, the higher the film density. For oxide semiconductor layers, oxygen vacancies and / or impurities such as hydrogen are factors that generate defect levels. Therefore, the first layer 106a and the second layer 106b, which contain nanocrystals, are amorphous oxide semiconductors. This region can be described as having a reduced defect level density compared to the conductive layer. An amorphous oxide semiconductor layer, for example, has a disordered atomic arrangement and does not contain crystalline components. This refers to an oxide semiconductor layer.

[0038] Furthermore, the first layer 106a and the second layer 106b contain at least indium and zinc. It is preferable to use a metal oxide containing the constituent element. Also, the first layer 106a and the second The constituent elements of layer 106b may be the same, but the compositions of the two layers may be different.

[0039] In this embodiment, both the first layer 106a and the second layer 106b are at least It is also a nanocrystalline oxide semiconductor layer containing indium and zinc, and depending on the material and deposition conditions In some cases, the interfaces between each region may become unclear. Therefore, in Figure 1, the first layer 10 The interface between 6a and the second layer 106b is schematically shown with a dotted line. This will be shown in subsequent drawings. The same applies even if they are present.

[0040] The first layer 106a is In-M-Zn oxide (where M is Al, Ga, Ge, Y, Zr, Sn, If it is an oxide semiconductor layer denoted as La, Ce, or Hf, then the second layer 106b is This is similar to the first layer 106a, which is an In-M-Zn oxide (where M is Al, Ga, Ge, Y, Z). It is denoted as r, Sn, La, Ce, or Hf, and is more indium than the first layer 106a. It is preferable to use an oxide semiconductor layer with a high atomic ratio of M.

[0041] More specifically, as the second layer 106b, the aforementioned elements are present in a quantity of 1.5 times greater than that of the first layer 106a. Oxide semiconductors containing more than twice, preferably more than twice, and more preferably more than three times higher in atomic ratio. Apply the body layer. As mentioned above, element M bonds more strongly with oxygen than indium, therefore indium Oxide semiconductors with a high atomic ratio of M to M are less prone to oxygen vacancies in the film. The second layer 106b is an oxide semiconductor layer that is less prone to oxygen vacancies than the first layer 106a. Furthermore, the higher the atomic ratio of M to indium, the more energy the oxide semiconductor layer has. Because the gap (band gap) becomes larger, the atomic ratio of M to indium is higher. Therefore, the second layer 106b functions as an insulating layer. Thus, the second layer 106b is a semiconductor. It is preferable to adjust the atomic ratio of M to indium to such an extent that it can function as a layer.

[0042] The first layer 106a and the second layer 106b each contain at least indium, zinc, and Contains M (metals such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf). When it is an In-M-Zn oxide, the first layer 106a is In:M:Zn=x1:y1:z 1 [atomic ratio], the second layer 106b is In:M:Zn=x2:y2:z2 [atomic ratio] Therefore, it is preferable to make y2 / x2 larger than y1 / x1. y2 / x2 is y1 / This should be 1.5 times or more than x1, preferably 2 times or more, and more preferably 3 times or more. In this case, if y1 is greater than or equal to x1 in the first layer 106a, the electrical characteristics of the transistor are stable. It can be fixed. However, when y1 becomes 3 times or more x1, the field effect of the transistor Because fruit mobility decreases, it is preferable that y1 be less than three times x1.

[0043] Furthermore, when the first layer 106a is an In-M-Zn oxide, I excluding Zn and O The atomic ratio of n to M is preferably 25 atomic% or more for In and 75 atomic% for M. Less than %, more preferably In is 34 atomic% or more and M is less than 66 atomic%. Let's assume that when the second layer 106b is In-M-Zn oxide, remove Zn and O. The atomic ratio of In to M is preferably less than 50 atomic% for In and 50 atomic% for M. 0% or more, more preferably In is less than 25 atomic% and M is 75 atomic The percentage must be c% or higher.

[0044] Furthermore, the energy at the lower end of the conduction band of the second layer 106b is 0.0 5eV, 0.07eV, 0.1eV, 0.15eV or more, and 2eV, 1 Oxide semiconductors close to the vacuum level in the range of eV, 0.5eV, or 0.4eV or less It is preferable to do so.

[0045] In such a structure, when an electric field is applied to the gate electrode layer 102, the oxide semiconductor layer 10 Of the 6, the first layer 106a, which has the lowest energy at the lower end of the conduction band, is the carrier This becomes the main migration path (channel). Here, the channel formation region (first layer 106a) and the boundary By including a second layer 106b between the edge layer 108 and the insulating layer, the oxide semiconductor layer 106 and the insulating layer Trap levels that may be formed by impurities and defects at the interface with 108, and channel type There is a gap between the forming region and the surrounding area. As a result, electrons flowing through the first layer 106a are trapped. It is less likely to be trapped in the position, and it is possible to increase the on-current of the transistor, and The field effect mobility can be increased. Also, when an electron is trapped in a trap level, the electron This becomes a negative fixed charge, which becomes a factor in the fluctuation of the transistor's threshold voltage. However, However, because there is a gap between the first layer 106a and the trap level, at the trap level This makes it possible to reduce electron trapping and thus reduce fluctuations in the threshold voltage. .

[0046] Furthermore, the first layer 106a and the second layer 106b are not simply stacked but are connected in a continuous manner. A combination (in this case, a structure in which the energy at the lower end of the conduction band changes continuously between each layer) is formed. It is manufactured in such a way that defects such as trap centers and recombination centers are present at the interface of each layer. The layered structure is designed so that no impurities that would form energy levels are present. If impurities are present between layer 106a and the second layer 106b, the energy band Continuity is lost, carriers get trapped or recombine at the interface, and disappear. .

[0047] To form continuous bonds, a multi-chamber deposition apparatus equipped with a load-lock chamber is required. (Using a sputtering device) to continuously stack each film without exposing it to the atmosphere. This is necessary. Each chamber in the sputtering apparatus is inefficient for the oxide semiconductor layer. To remove as much pure water as possible, an adsorption-type vacuum pump such as a cryopump is used. Using high vacuum evacuation (5 × 10 -7 Pa~1×10 -4 It is preferable to do so (up to about Pa). Alternatively, a turbomolecular pump and a cold trap can be combined to run from the exhaust system to the chamber. It is preferable to prevent gases, particularly those containing carbon or hydrogen, from flowing back into the container.

[0048] Figure 1(B) schematically shows a portion of the band structure in D1-D2 of the laminated structure in Figure 1(A). This shows the gate insulating layer 104, which is an insulating layer in contact with the oxide semiconductor layer 106. The case in which a silicon oxide layer is provided as the insulating layer 108 will be explained. Note that Figure 1(B In this case, Evac represents the energy of the vacuum level, and Ec represents the energy of the lower end of the conduction band. show.

[0049] As shown in Figure 1(B), in the first layer 106a and the second layer 106b, the lower end of the conduction band The energy changes smoothly without any barriers. In other words, it changes continuously. This is possible because the first layer 106a and the second layer 106b contain common elements, and both This is because a mixed layer is formed due to the mutual movement of oxygen between these regions. Cut.

[0050] From Figure 1(B), in the oxide semiconductor layer 106, the first layer 106a becomes a well. It can be seen that the channel region is formed in the first layer 106a. Note that the oxide semiconductor layer Because the energy at the lower end of the conduction band changes continuously, the first layer 106a and the second It could also be said that layer 106b of layer 2 is continuously joined to this layer.

[0051] Near the interface between the second layer 106b and the insulating layer 108, the constituent elements of the insulating layer 108 (for example, s) Although trap levels may be formed due to impurities such as carbon or defects, By providing a second layer 106b between the first layer 106a in which the channel is formed, This allows the first layer 106a and the trap level to be kept apart. However, the first layer 10 When the energy difference between 6a and the second layer 106b is small, electrons in the first layer 106a The energy difference can exceed the trap level, causing electrons to be trapped. As a result, a negative fixed charge is generated at the insulating film interface, and the transistor's threshold voltage becomes positive. It shifts in that direction. Therefore, below the conduction band between the first layer 106a and the second layer 106b. If the energy difference at the end is 0.05 eV or more, preferably 0.15 eV or more, then the transistor This is preferable because it reduces fluctuations in the threshold voltage of the zista, resulting in stable electrical characteristics.

[0052] In semiconductor devices using oxide semiconductor layers, to improve reliability, a channel is used. It is necessary to reduce the defect level density of the oxide semiconductor layer and its interface. In particular, oxide Negative fluctuations in the threshold voltage of a transistor using a solid semiconductor layer are due to the channel and The cause is a defect level resulting from oxygen vacancies in the oxide semiconductor layer and its interface. It's possible.

[0053] Therefore, as shown in this embodiment, compared to an amorphous oxide semiconductor layer, the defect level density is low. An oxide semiconductor layer including the reduced first layer 106a and second layer 106b is used in a transistor. By using this method, the fluctuations in the electrical characteristics of the transistor caused by irradiation with visible light and ultraviolet light are reduced. This is possible. Therefore, the reliability of the transistor can be improved.

[0054] Figure 2(A) is a schematic diagram showing another example of a laminated structure included in a semiconductor device according to one embodiment of the present invention. The stacked structure shown in Figure 2(A) is similar to the stacked structure in Figure 1(A), with gate electrode layer 1 02, the gate insulating layer 104 on the gate electrode layer 102, and the oxide on the gate insulating layer 104. The oxide semiconductor layer includes a semiconductor layer 116 and an insulating layer 108 on the oxide semiconductor layer 116. 116 is a first layer 116a in which a channel is formed, and the first layer 116a and the insulating layer 108 The second layer 116b between the first layer 116a and the gate insulating layer 104, and the third layer between the first layer 116a and the gate insulating layer 104 Includes 116c.

[0055] The oxide semiconductor layer 116 shown in Figure 2(A) is the first layer 116 which functions as a channel. The acid shown in Figure 1(A) includes a third layer 116c between a and the gate insulating layer 104. Unlike the ion semiconductor layer 106, the other configurations can be the same as those in Figure 1(A). For example, the first layer 116a of the oxide semiconductor layer 116 is the oxide semiconductor layer 106 shown earlier. You can refer to the explanation of the first layer 106a, and the second oxide semiconductor layer 116 Layer 116b is described in relation to the second layer 106b of the oxide semiconductor layer 106 shown earlier. It can be taken into consideration.

[0056] The first layer 116a, the second layer 116b, and the third layer 11 included in the oxide semiconductor layer 116. 6c is an oxide semiconductor layer containing nanocrystals. The third layer 116c is Similar to layer 116a and layer 216b, at least indium and zinc are constituent elements. It is preferable to use a metal oxide that has as an element. Also, the first layer 116a to the third layer The constituent elements of layer 116c may be the same, but their respective compositions may differ.

[0057] The first layer 116a is In-M-Zn oxide (where M is Al, Ga, Ge, Y, Zr, Sn, If it is an oxide semiconductor layer denoted as La, Ce, or Hf, then the third layer 116c is This is similar to the first layer 116a, and is an In-M-Zn oxide (where M is Al, Ga, Ge, Y, Z). It is expressed as r, Sn, La, Ce, or Hf, and is more indium than the first layer 116a. It is preferable to use an oxide semiconductor layer with a high atomic ratio of M. That is, the third layer 116 c is an oxide semiconductor layer that is less prone to oxygen vacancies than the first layer 116a. In this layer, the third layer 116c contains at least 1.5 times more of the aforementioned elements than the first layer 116a. Apply an oxide semiconductor layer containing atoms at a ratio that is at least twice, and more preferably at least three times, higher in terms of the number of atoms. do.

[0058] Furthermore, the third layer 116c, the first layer 116a, and the second layer 116b are at least in Dium, zinc, and M(Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce or H) When the third layer 116c is an In-M-Zn oxide containing metals such as f, n=x3:y3:z3[atomic ratio], first layer 116a In:M:Zn=x1:y1: z1 [atomic ratio], second layer 116b In:M:Zn=x2:y2:z2 [atomic ratio] Therefore, it is preferable that y3 / x3 and y2 / x2 are greater than y1 / x1. y3 / x3 and y2 / x2 are 1.5 times or more, preferably 2 times or more, than y1 / x1. Preferably, the ratio is 3 times or more. In this case, in the first layer 116a, y1 is x1 or greater. This allows the electrical characteristics of the transistor to be stabilized. However, y1 is 3 times x1. At this point, the field-effect mobility of the transistor decreases, so y1 is three times x1. It is preferable that it be less than [a certain value].

[0059] Furthermore, when the third layer 116c is an In-M-Zn oxide, I excluding Zn and O The atomic ratio of n to M is preferably less than 50 atomics for In and 50 atomics for M. % or more, more preferably In is less than 25 atomic%, and M is 75 atomic% or more. Let's assume that when the first layer 116a is an In-M-Zn oxide, remove Zn and O. The atomic ratio of In to M is preferably 25 atomic% or more for In and 75 atomic% for M. Less than 0 omic%, more preferably In is 34 atomic% or more, and M is 66 atomic%. The amount of Zn is less than c%. Also, when the second layer 116b is In-M-Zn oxide, the amount of Zn is less than c%. Excluding O, the atomic ratio of In to M is preferably less than 50 atomic%, and M is 50% or more, more preferably In is less than 25% and M is 75a The tomic percentage must be greater than or equal to %.

[0060] Furthermore, the third layer 116c and the second layer 116b may be layers containing different constituent elements. Alternatively, the layers may contain the same constituent elements in the same atomic ratio or in different atomic ratios.

[0061] Furthermore, the energy at the lower end of the conduction band of the third layer 116c and the second layer 116b is the same as that of the first layer 1 A value greater than 16a is 0.05eV, 0.07eV, 0.1eV, or 0.15eV. and the vacuum level is within the range of 2eV, 1eV, 0.5eV, or 0.4eV. It is preferable to form it with a similar oxide semiconductor.

[0062] A schematic diagram of the band structure at D3-D4 in the laminated structure of Figure 2(A) is shown in Figure 2(B).

[0063] As shown in Figure 2(B), in the oxide semiconductor layer 116, the first layer 116a is a well The door is formed, and the channel region is formed in the first layer 116a. Note that the oxide semiconductor layer 11 6 is because the energy at the lower end of the conduction band is continuously changing, so the third layer 116c and the first It can also be said that layer 116a and the second layer 116b are continuously joined together.

[0064] A third layer 116c is provided above or below the first layer 116a, which functions as a channel. Alternatively, the second layer 116b functions as a barrier layer and is in contact with the oxide semiconductor layer 116 as an insulating layer. Formed at the interface between the gate insulating layer 104 and the insulating layer 108) and the oxide semiconductor layer 116 The influence of trap levels is the first major carrier path for transistors. This can prevent the substance from extending to layer 106a.

[0065] For example, oxygen vacancies contained in an oxide semiconductor layer are within the energy gap of the oxide semiconductor. It manifests as a localized energy level located at a deep energy level. Carriers Because the trapping of A reduces the reliability of the transistor, the oxide semiconductor layer contains It is necessary to reduce the oxygen deficiency that occurs. In the layered structure shown in Figure 2, the first layer The third layer 116c is an oxide semiconductor layer that is less prone to oxygen vacancies compared to 116a, and By providing the second layer 116b in contact with the top and bottom of the first layer 116a, it functions as a channel. This makes it possible to reduce oxygen deficiency in the first layer 116a.

[0066] Furthermore, the oxide semiconductor layer 116 contains an insulating layer with different constituent elements (for example, a silicon oxide film). When in contact with an underlying insulating layer, an interface state is formed at the interface between the two layers, and this interface state is channel This can form a second transistor with a different threshold voltage. As a result, the apparent threshold voltage of the transistor may fluctuate. However, Figure In a transistor including the stacked structure shown in 2, the first layer 116a to the third layer 116c Each of them is composed of at least indium and zinc, and therefore functions as a channel. It becomes difficult to form interface states at the interface of the first layer 116a. Therefore, the transistor This can reduce variations in electrical characteristics such as threshold voltage.

[0067] Furthermore, when a channel is formed at the interface between the gate insulating layer 104 and the oxide semiconductor layer 116 Interfacial scattering occurs at the interface, and the field-effect mobility of the transistor decreases. However, In the transistor including the stacked structure of this embodiment, the first channel is formed A third layer 116c, which contains an oxide semiconductor, is placed between layer 116a and the gate insulating layer 104. A structure is provided, and at the interface between the third layer 116c and the first layer 116a, carrier scattering occurs. This is unlikely to occur. Therefore, the field-effect mobility of the transistor can be increased.

[0068] Furthermore, the third layer 116c and the second layer 116b are gate insulating layer 104 and insulating layer, respectively. The constituent elements of layer 108 are mixed into the first layer 116a where the channel is formed, and impurities It also functions as a barrier layer to suppress the formation of certain energy levels.

[0069] In Figure 2(B), the energy at the lower end of the conduction band of the third layer 116c is the same as that of the second layer 116c. Although an example was given where the energy of the lower end of the conduction band of b is closer to the vacuum level, this is one aspect of the present invention. This is not limited to the above. The third layer 116c and the second layer 116b are, The energy below the conduction band is closer to the vacuum level than the energy at the lower end of the conduction band of at least the first layer 116a. It is sufficient that it has edge energy, and the third layer 116c is the lower end of the conduction band of the second layer 116b. The energy of the lower end of the conduction band may be further from the vacuum level than the energy of the lower end of the conduction band. It is also acceptable for both to have the same energy.

[0070] Furthermore, in the above explanation, the oxide semiconductor layer including at least the first layer and the second layer is We have described a bottom gate structure provided on the gate electrode layer via a gate insulating layer, The present invention is not limited to this aspect.

[0071] Figure 3(A) is a schematic diagram showing another example of a laminated structure included in a semiconductor device according to one embodiment of the present invention. This is shown. The layered structure shown in Figure 3(A) consists of an insulating layer 108 and an oxide semiconductor on the insulating layer 108. Layer 116, gate insulating layer 104 on oxide semiconductor layer 116, and on gate insulating layer 104 The gate electrode layer 102 and the oxide semiconductor layer 116 include a first channel in which a channel is formed. Layer 116a, a second layer 116b between the first layer 116a and the insulating layer 108, and the first layer It includes a third layer 116c between 116a and the gate insulating layer 104.

[0072] Furthermore, a portion of the band structure at D5-D6 in the laminated structure of Figure 3(A) is schematically shown in Figure 3(B). To illustrate this point.

[0073] The stacked structure shown in Figure 3 is a top-gate structure created by reversing the stacking order of the stacked structure shown in Figure 2. This is shown as an example. The configuration of each layer can be the same as described above. (See Figure 3) Details of the top gate structure can be found in the explanation in Figure 2, and similar effects can be achieved. It is possible to play it.

[0074] In Figure 3, the second layer 116b and the third layer overlap the first layer 116a above and below it. Although a top-gate type structure with 116c provided is shown, one aspect of the present invention is this It is not limited to this. For example, by providing an oxide semiconductor layer on top of the first layer 116a to form a two-layer structure, This is applied to a top-gate type structure having a gate electrode layer above the two oxide semiconductor layers. That's good too.

[0075] As described above, the transistor including the stacked structure of this embodiment has an oxide semiconductor layer By having a second layer between the first layer in which a channel is formed and the insulating layer, Because the interface of the semiconductor layer and the channel can be separated, the influence of interface states on the channel is reduced. It becomes possible to suppress it.

[0076] Furthermore, the first layer 116a to the third layer 116c have fewer defects compared to amorphous oxide semiconductors. It is composed of nanocrystalline oxide semiconductors with reduced defect level density. By using an oxide semiconductor layer including the first to third layer in a transistor, the transistor This can reduce fluctuations in electrical characteristics and improve reliability.

[0077] (Reference example) In this reference example, the nanocrystals contained in the oxide semiconductor layer of this embodiment are treated with a nanobeam. This will be explained using electron diffraction patterns.

[0078] ≪Nanobeam electron diffraction pattern in the cross-sectional direction of an oxide semiconductor layer≫ Sample 1 used in this reference example The method for fabricating it is shown below. Sample 1 is an example of an oxide semiconductor layer corresponding to the first layer. An In-Ga-Zn oxide film was deposited on a quartz glass substrate to a thickness of 50 nm. The conditions are as follows: Using an oxide target with In:Ga:Zn = 1:1:1 (atomic ratio), Under an oxygen atmosphere (flow rate 45 sccm), pressure 0.4 Pa, DC power supply 0.5 kW, base The plate temperature was set to room temperature. After depositing the oxide semiconductor layer, it was subjected to 1 hour of deposition at 450°C under a nitrogen atmosphere. A first heat treatment in between, and a second heat treatment at 450°C in a nitrogen and oxygen atmosphere for 1 hour. He carried out the rationale.

[0079] The oxide semiconductor layer after the second heat treatment was subjected to ion milling using Ar ions. The material was thinned to approximately 0 nm (40 nm ± 10 nm). First, oxidation was performed to reinforce the thinning process. After bonding a quartz glass substrate with a semiconductor layer to a dummy substrate, it is cut and polished. Therefore, the material was thinned to a thickness of approximately 50 μm. Subsequently, as shown in Figure 5, the oxide semiconductor layer 2 With respect to the quartz glass substrate 200 and dummy substrate 202 on which 04 is provided, at a low angle (approximately Ion milling is performed by irradiating with argon ions from 3°, to about 50nm (40nm). A thin section of region 210a (±10 nm) was formed, and its cross-section was observed.

[0080] The oxide semiconductor layers after the first and second heat treatments are made to a thickness of approximately 50 nm (40 nm ± 10 nm). Figure 4(A) shows a cross-sectional TEM image of the thinned sample 1. Furthermore, the cross-section shown in Figure 4(A) is... The electron diffraction patterns measured by nanobeam electron diffraction are shown in Figures 4(B) to 4(E). Figure 4(B) shows the electron diffraction pattern obtained by irradiating with an electron beam focused to a probe diameter of 1 nm. This is the electron beam. Figure 4(C) shows the electron beam irradiated with an electron beam focused to a probe diameter of 10 nm. This is the diffraction pattern. Figure 4(D) shows the result of irradiating with an electron beam focused to a probe diameter of 20 nm. This is the electron diffraction pattern. Figure 4(E) shows the result when the probe diameter is focused to 30 nm. This is an electron diffraction pattern obtained by irradiating with an electron beam.

[0081] As shown in Figure 4(B), in the electron diffraction pattern in the cross-sectional direction of sample 1, a ring shape is observed. It has a region of high brightness, and multiple spots (bright points) are observed within that region. Furthermore, as shown in Figures 4(C) to 4(E), the measurement range can be widened by increasing the probe diameter of the electron beam. As a result, the multiple spots gradually broaden, and the width of the ring-shaped area of ​​high brightness also increases. It is confirmed that this is happening.

[0082] If the size of the crystalline portion contained in Sample 1 of this reference example is 10 nm or less, or 5 nm or less: In sample 1, in which the oxide semiconductor layer was thinned to about 50 nm, the measurement range in the depth direction was Because the measurement range is larger than the size of the crystal portion, multiple crystal portions may be included within the measurement range. Therefore, an oxide semiconductor layer fabricated using the same method as sample 1 was made to a size of 10 nm or less, preferably 5 nm. A region thinned to less than 3 nm, more preferably less than 3 nm, is designated as sample 2, and its cross-section is nanob Observed by electron diffraction.

[0083] Ion milling was performed using Ar ions, and as shown in Figure 5, the size was reduced to 10 nm or less, for example, 5 nm. A thin section of region 210b, approximately 10 nm thick, was formed, and its cross-section was observed.

[0084] Figures 6(A) to 6(D) show four arbitrary points on sample 2, which has been thinned to less than 10 nm, using probes. This shows the nanobeam electron diffraction pattern measured using an electron beam focused to a diameter of 1 nm.

[0085] Figures 6(A) and 6(B) show a regularity in the crystalline state that is oriented on a specific plane. A crystalline portion is observed. From this, it can be concluded that the oxide semiconductor layer according to this embodiment certainly has a crystalline portion. It can be seen that this is happening. On the other hand, in Figures 6(C) and 6(D), a ring-shaped area with high brightness is visible. Multiple spots are observed within the area.

[0086] As mentioned above, the size of the crystalline portion contained in the nanocrystalline oxide semiconductor layer is, for example, 10n The particles are extremely fine, less than m or less than 5 nm. Therefore, for example, if the sample is thinned to less than 10 nm... By transforming the electron beam and focusing it to 1 nm, the measurement range is reduced in both the planar and depth directions. For example, if the region is reduced to a size smaller than that of a single crystal, the measurement area will vary depending on the region being measured. In this case, it is possible to observe spots that exhibit a regularity in the crystalline state oriented toward a specific plane. It is possible. Also, if the measurement area contains multiple crystalline parts, the electron beam that has passed through the crystalline parts will be able to reach the crystal. By spreading out beyond its size, crystal spots in the depth direction can be observed. In this case, it is assumed that multiple spots will be observed in the nanobeam electron diffraction pattern. It is possible.

[0087] Next, an oxide semiconductor layer with a different composition from sample 1 and sample 2 was fabricated as sample 3, and nano The electron diffraction pattern was confirmed by irradiating it with a beam electron beam. Sample 3 is the oxidation of this embodiment. This is an example of an oxide semiconductor layer corresponding to the second or third layer in a material semiconductor layer.

[0088] The method for preparing sample 3 is shown below. In sample 3, an In-Ga-Zn oxide film was laid on quartz glass. A film was deposited on the substrate with a thickness of 100 nm. The deposition conditions were In:Ga:Zn=1:3:2( Using an oxide target with an atomic ratio, under an oxygen and argon atmosphere (Ar flow rate 30 sccm, oxygen flow rate 15 sccm), pressure 0.4 Pa, direct current (DC) power supply 0.5 kW, base The plate temperature was set to room temperature.

[0089] Sample 3, in which the deposited oxide semiconductor layer was thinned to approximately 50 nm (40 nm ± 10 nm), A cross-sectional TEM image is shown in Figure 7. Furthermore, the cross-section shown in Figure 7 was measured by nanobeam electron diffraction. The defined electron diffraction patterns are shown in Figures 8(A), 8(B), 8(C), 8(D), and 8( This is shown in E) and Figure 8(F). Figure 8(A) shows an electron beam focused to a probe diameter of 1 nm. This is the electron diffraction pattern of the emitted electron beam. Figure 8(B) shows the electron diffraction pattern when the probe diameter is focused to 10 nm. This is the electron diffraction pattern after irradiation with a sub-beam. Figure 8(C) shows the probe diameter focused to 20 nm. This is the electron diffraction pattern obtained by irradiating with an electron beam. Figure 8(D) shows the probe diameter set to 30n This is the electron diffraction pattern obtained by irradiating with an electron beam focused to m. Figure 8(E) shows the probe diameter. This is an electron diffraction pattern obtained by irradiating with an electron beam focused to 50 nm. And, Figure 8(F This is an electron diffraction pattern obtained by irradiating with an electron beam focused to a probe diameter of 100 nm. .

[0090] As shown in Figure 8, even in sample 3, which has a different composition from sample 1, the electron diffraction pattern in the cross-sectional direction was In the field, there is a ring-shaped area of ​​high brightness, and within the area of ​​high brightness there are multiple spots Bright spots are observed. Also, see Figures 8(A), 8(B), 8(C), 8(D), and Figure From 8(E) and Figure 8(F), increasing the probe diameter of the electron beam expands the measurement range. These multiple spots gradually broaden, and the width of the ring-shaped, high-luminosity area also increases. It is confirmed that this is the case.

[0091] ≪Nanobeam electron diffraction pattern on a quartz glass substrate≫ Figure 9 shows the nanobeam electron diffraction pattern on a quartz glass substrate. The nanobeam electron diffraction pattern is shown. The measurement conditions in Figure 9 are the same as those in Figures 4(B) and 8(A). The same procedure was followed, but the electron beam probe diameter was focused to 1 nm.

[0092] As shown in Figure 9, in a quartz glass substrate with an amorphous structure, diffraction does not occur at specific spots, and the main A halo pattern with continuously changing brightness is observed from the spot. Thus, amorphous In films with a structure, even if electron diffraction is performed on an extremely small area, this embodiment Multiple circumferentially arranged spots, as observed in oxide semiconductor layers, are not observed. Therefore, the multiple spots arranged in a circular pattern observed in Samples 1 to 3 of this reference example This is confirmed to be unique to the oxide semiconductor layer in this reference example.

[0093] <<Nanobeam electron diffraction patterns in the cross-sectional and planar directions of oxide semiconductor layers>> Next, For the filmed oxide semiconductor layer, electron beams were irradiated from the cross-sectional direction and the planar direction, respectively. The sub-ray diffraction patterns were compared. The preparation method for sample 4 used for comparison is shown below.

[0094] In sample 4, an In-Ga-Zn oxide film was deposited on a quartz glass substrate to a thickness of 50 nm. The film deposition conditions are for an oxide target with an In:Ga:Zn ratio of 1:1:1 (atomic ratio). Using this, under an oxygen atmosphere (flow rate 45 sccm), pressure 0.4 Pa, and DC power supply 0. The power consumption was set to 5kW and the substrate temperature was set to room temperature.

[0095] Nanobeam electron diffraction pattern obtained by irradiating a deposited oxide semiconductor layer with an electron beam from a planar direction. The turn is shown in Figure 10(A). After thinning the oxide semiconductor layer to about 50 nm, cut Figure 10(B) shows the electron diffraction pattern of a nanobeam irradiated with an electron beam in the planar direction. Figure 10 (A) and Figure 10(B) both show electron beams irradiated with a probe diameter focused to 1 nm. This is a sub-ray diffraction pattern.

[0096] As shown in Figures 10(A) and 10(B), even in the electron diffraction pattern in the planar direction, , it has a ring-shaped region of high brightness similar to the electron diffraction pattern in the cross-sectional direction, and the brightness Multiple spots (bright spots) were observed within the high-concentration area. Therefore, in sample 4 of this reference example, It was confirmed that the crystalline portion was contained substantially uniformly without bias in the cross-sectional or planar direction within the film. Ta.

[0097] <<Analysis by X-ray diffraction> Next, sample 5, which has an oxide semiconductor layer provided on a quartz glass substrate, was examined. The results were analyzed using X-ray diffraction (XRD). Figure 11 The results of measuring the XRD spectrum using the out-of-plane method are shown below. The preparation method for sample 5 was the same as that for sample 4 described above.

[0098] In Figure 11, the vertical axis represents X-ray diffraction intensity (in arbitrary units), and the horizontal axis represents the diffraction angle 2θ (deg. ) The XRD spectrum was measured using a Bruker AXS X-ray diffractometer D -8 ADVANCE was used.

[0099] As shown in Figure 11, a peak at around 2θ = 20~23° is observed, which is attributed to quartz. No peaks originating from the crystalline portion contained in the oxide semiconductor layer can be observed. Therefore, Figure From the results in 11, it can be seen that the crystalline parts contained in the oxide semiconductor layer of this reference example are extremely fine crystalline parts. This suggests that...

[0100] As shown above, the size of the crystalline portion included in the oxide semiconductor layer according to this embodiment is, for example, For example, it is presumed to be 10 nm or less, or 5 nm or less. Acid according to this embodiment The crystalline semiconductor layer is, for example, a crystalline portion of 1 nm to 10 nm (nanocrystal (nc: nano This is an oxide semiconductor layer containing crystal.

[0101] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0102] (Embodiment 2) In this embodiment, regarding the semiconductor device having the stacked structure shown in Embodiment 1, Figure 12 Further explanation will be provided with reference to Figure 17.

[0103] <Transistor Configuration Example 1> Figure 12 shows an example of a semiconductor device configuration. In Figure 12, as an example of a semiconductor device, a bottom gate is shown. A transistor with a 3D structure is illustrated. Figure 12(A) is a plan view of transistor 450. Yes, Figure 12(B) is a cross-sectional view of V1-W1 in Figure 12(A), and Figure 12(C) This is a cross-sectional view taken along X1-Y1 in Figure 12(A). Note that Figure 12(A) is complex. To avoid this, some of the components (for example, the insulating layer 408) are omitted from the illustration. This also applies to subsequent floor plans.

[0104] The transistor 450 shown in Figure 12 has a gate electrode layer 402 provided on the substrate 400, A gate insulating layer 404 on the gate electrode layer 402, and a gate insulating layer 404 provided on the gate insulating layer 404, The electrode layer 402 and the oxide semiconductor layer 406 overlapping each other, and the oxide semiconductor layer 406 and electrical A source electrode layer 410a and a drain electrode layer 410b connected to it, and an oxide semiconductor layer 406 It includes a gate insulating layer 404 and an insulating layer 408 that overlap each other via a gate insulating layer 404.

[0105] The oxide semiconductor layer 406 contained in transistor 450 is the first layer in which the channel is formed. The laminated structure of 406a and the second layer 406b between the first layer 406a and the insulating layer 408 Includes. The first layer 406a and the second layer 406b are oxide semiconductor layers containing nanocrystals, respectively. These correspond to the first layer 106a and the second layer 106b shown in Figure 1, respectively.

[0106] As described above, the first layer 406a and the second layer 406b are made of indium and sub-dioxide, respectively. The material contains lead as a constituent element, and the energy at the lower end of the conduction band of the second layer 406b is the same as the first layer Vacuum level in the range of 0.05 eV to 2 eV above the energy of the lower end of the conduction band of layer 406a It's close to the rank.

[0107] The first layer 406a and the second layer 406b contain nanocrystals, thus the oxide semiconductor layer 406 This results in an oxide semiconductor layer with a reduced defect level density compared to amorphous oxide semiconductors. It is possible. Also, the first layer 406a in which a channel is formed in the oxide semiconductor layer 406 and By including a second layer 406b between the insulating layer 408 and the oxide semiconductor layer 406 and the insulating layer 4 The trap level that may form between 08 and the channel reduces or suppresses its impact. This makes it possible to stabilize the electrical characteristics of transistor 450.

[0108] Furthermore, the first layer 406a in which a channel is formed in the oxide semiconductor layer 406 is hydrogen It is preferable that it be reduced as much as possible. Specifically, in the first layer 406a, two Secondary Ion Mass Spectroscopy (SIMS) The hydrogen concentration obtained by (ometry) is 2 × 10 20 atoms / cm 3 The following are preferred Or 5 x 10 19 atoms / cm3 Hereinafter, 1×10 19 atoms / cm 3 Hereinafter, 5 ×10 18 atoms / cm 3 Hereinafter, 1×10 18 atoms / cm 3 Hereinafter, 5×10 1 7 atoms / cm 3 Hereinafter, more preferably 1×10 16 atoms / cm 3 Hereinafter, it is set to .

[0109] In the transistor 450, the gate insulating layer 404 has a stacked structure of an insulating layer 404a and an insulating layer 404b . The insulating layer 404a and the insulating layer 404b can each be made of silicon oxynitride , silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride , aluminum nitride oxide, hafnium oxide, gallium oxide, or a Ga-Zn-based metal oxide, etc. In this embodiment, the case where the gate insulating layer 404 having a stacked structure of the insulating layer 404a and the insulating layer 404b is provided is shown as an example, but it is not limited to this. It may be a single-layer gate insulating layer or a gate insulating layer including a stacked structure of three or more layers .

[0110] In the gate insulating layer 404, as the insulating layer 404a in contact with the gate electrode layer 402, by forming a nitride insulating film such as silicon nitride, silicon oxynitride, aluminum nitride, or aluminum oxynitride, diffusion of the metal elements constituting the gate electrode layer 402 can be prevented , which is preferable .

[0111] Also, as the insulating layer 404a, it is preferable to use a silicon nitride film or a silicon oxynitride film ​is preferable. Since the silicon nitride film or silicon oxynitride film has a higher relative dielectric constant than the silicon oxide film and a larger film thickness required to obtain the same capacitance, the gate insulating layer can be physically thickened. For example, the film thickness of the insulating layer 404a can be set to 300 nm or more and 400 nm or less. Therefore, it is possible to suppress a decrease in the breakdown voltage of the transistor 450 or improve the breakdown voltage, and it is possible to suppress electrostatic breakdown of the semiconductor device. The relative dielectric constant is high, and since the film thickness required to obtain the same capacitance is large, the gate insulating layer can be physically thickened. For example, the film thickness of the insulating layer 404a can be set to 300 nm or more and 400 nm or less. Therefore, it is possible to suppress a decrease in the breakdown voltage of the transistor 450 or improve the breakdown voltage, and it is possible to suppress electrostatic breakdown of the semiconductor device. 耐圧を向上させることができ、半導体装置の静電破壊を抑制することができる。

[0112] In addition, the nitride insulating film that can be suitably used as the insulating layer 404a can form a dense film and prevent the diffusion of the metal element of the gate electrode layer 402. On the other hand, since the density of defect levels and the internal stress are large, there is a risk of causing fluctuations in the threshold voltage when forming the interface with the oxide semiconductor layer 406. Therefore, when forming a nitride insulating film as the insulating layer 404a, it is preferable to provide an oxide insulating film such as silicon oxide, silicon oxynitride, aluminum oxide, or aluminum oxynitride as the insulating layer 404b between the oxide semiconductor layer 406 and the nitride insulating film. By forming the insulating layer 404b made of an oxide insulating film between the oxide semiconductor layer 406 and the insulating layer 404a made of a nitride insulating film, it is possible to stabilize the interface between the gate insulating layer 404 and the oxide semiconductor layer 406. 可能でゲート電極層402の金属元素の拡散を防ぐことができる一方で、欠陥準位密度や内部応力が大きいので、酸化物半導体層406との界面を形成するとしきい値電圧の変動を引き起こす恐れがある。 内部応力が大きいので、酸化物半導体層406との界面を形成するとしきい値電圧の変動を引き起こす恐れがある。 よって、絶縁層404aとして窒化物絶縁膜を形成する場合には、酸化物半導体層406との間に絶縁層404bとして酸化シリコン、酸化窒化シリコン、酸化アルミニウム、酸化窒化アルミニウム等の酸化物絶縁膜を設けることが好ましい。 は、酸化物半導体層406との間に絶縁層404bとして酸化シリコン、酸化窒化シリコン、酸化アルミニウム、酸化窒化アルミニウム等の酸化物絶縁膜を設けることが好ましい。 ン、酸化アルミニウム、酸化窒化アルミニウム等の酸化物絶縁膜を設けることが好ましい。 。酸化物半導体層406と窒化物絶縁膜でなる絶縁層404aとの間に酸化物絶縁膜でなる絶縁層404bを形成することで、ゲート絶縁層404と酸化物半導体層406の界面を安定化することが可能となる。 る絶縁層404bを形成することで、ゲート絶縁層404と酸化物半導体層406の界面を安定化することが可能となる。 を安定化することが可能となる。

[0113] The film thickness of the insulating layer 404b can be, for example, 25 nm or more and 150 nm or less. Note that by using an oxide insulating film for the insulating layer 404b in contact with the oxide semiconductor layer 406, it is also possible to supply oxygen to the oxide semiconductor layer 406. Oxygen vacancies contained in the oxide semiconductor n-type the oxide semiconductor and cause fluctuations in electrical characteristics. Therefore, oxygen is supplied from the insulating layer 404b. 、酸化物半導体層406と接する絶縁層404bに酸化物絶縁膜を用いることで、酸化物半導体層406に酸素を供給することも可能である。 半導体層406に酸素を供給することも可能である。酸化物半導体中に含まれる酸素欠損は、酸化物半導体をn型化し、電気特性の変動を引き起こすため、絶縁層404bから酸素を供給することができる。 は、酸化物半導体をn型化し、電気特性の変動を引き起こすため、絶縁層404bから酸素を供給することができる。 Supplying the element and compensating for the oxygen deficiency are effective in improving reliability.

[0114] Alternatively, as the gate insulating layer 404, hafnium silicate (HfSiO x ), hafnium silicate (HfSi with nitrogen added (HfSi x O y N z ), hafnium aluminate (HfAl ) with nitrogen added (HfAl x O y N z ), high -k materials such as hafnium oxide and yttrium oxide can be used to reduce the gate leakage of the transistor.

[0115] <00009�Also, in the transistor 450, as the insulating layer 408 provided in contact with the upper layer of the oxide semiconductor layer 406, an insulating layer containing oxygen (oxide insulating layer), in other words, an insulating layer capable of releasing oxygen is preferably included. By releasing oxygen from the insulating layer 408, oxygen can be supplied to the oxide semiconductor layer 406 (more specifically, the first layer 406a where the channel is formed), and the oxygen deficiency in the film or at the interface of the oxide semiconductor layer 406 can be compensated. As the insulating layer capable of releasing oxygen, a silicon oxide layer, a silicon oxynitride layer, or an aluminum oxide layer can be applied.

[0116] In this embodiment, the insulating layer 408 has a stacked structure of an insulating layer 408a and an insulating layer 408b. As the insulating layer 408a, an oxide insulating film capable of reducing the oxygen deficiency of the oxide semiconductor is used, and as the insulating layer 408b, a nitride insulating film capable of preventing impurities from the outside from moving to the oxide semiconductor layer 406 is used. Hereinafter, it is preferably used as the insulating layer 408a. 、絶縁層408aとして、酸化物半導体の酸素欠損を低減することが可能な酸化物絶縁膜 を用い、絶縁層408bとして外部からの不純物が酸化物半導体層406に移動するのを 防ぐことが可能な窒化物絶縁膜を用いている。以下に、絶縁層408aとして好適に用い ​​​​​​​​​​​​An oxide insulating film that can be subjected to this process, and a nitride that can be suitably used as an insulating layer 408b. This section will explain the details of the material insulating film.

[0117] The oxide insulating film uses an oxide insulating film that contains more oxygen than satisfactorily satisfactorily satisfactorily. It is formed by adding more oxygen than satisfactorily satisfying the stoichiometric composition. Heat causes some of the oxygen to be removed. Acids contain more oxygen than the oxygen required to satisfy the stoichiometric composition. In the ionized insulating film, TDS analysis showed that the amount of oxygen desorption, converted to oxygen atoms, was 1.0 × 10⁻¹⁶. 18 atoms / cm 3 Preferably 3.0 × 10 20 atoms / cm 3 The above is the acid It is a monoxide insulating film. Note that the substrate temperature during the above TDS analysis was 100°C or higher. A temperature of 0°C or lower, or a range of 100°C to 500°C, is preferred.

[0118] As an oxide insulating film that can be used as the insulating layer 408a, a thickness of 30 nm or more is required. silicon oxide, silicon oxidnitride, silicon 0.00 nm or less, preferably 50 nm to 400 nm Cones and the like can be used.

[0119] Nitride insulating films that can be used as insulating layer 408b include oxygen, hydrogen, water, alkali gold It has a blocking effect on alkaline earth metals, etc. The insulating film 124 is a nitride insulating film. By providing this, oxygen diffuses from the semiconductor layer 110 to the outside and from the outside into the semiconductor layer 110. It can prevent the intrusion of hydrogen, water, etc. into the film. Examples of nitride insulating films include silicon nitride and nitride Examples include silicon oxide, aluminum nitride, and aluminum oxide nitride. Furthermore, oxygen, hydrogen, Instead of the nitride insulating film having a blocking effect such as water, an alkali metal, or an alkaline earth metal, an oxide insulating film having a blocking effect such as oxygen, hydrogen, or water may be provided. As the oxide insulating film having a blocking effect such as oxygen, hydrogen, or water, there are aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc. Instead, an oxide insulating film having a blocking effect such as oxygen, hydrogen, or water may be provided. Examples of the oxide insulating film having a blocking effect such as oxygen, hydrogen, or water include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, and the like.

[0120] <Configuration Example 2 of Transistor> In FIG. 13, a transistor 460 is illustrated as a modified example of the transistor 450. FIG. 13(A) is a plan view of the transistor 460, FIG. 13(B) is a cross-sectional view taken along V2-W2 of FIG. 13(A), and FIG. 13(C) is a cross-sectional view taken along X2-Y2 of FIG. 13(A). <00​​​​​​​​​​​​​​​​​​​​​​​​​​​​Furthermore, the stacking order with the insulating layer 408 differs from that of transistor 450 shown in Figure 12. In transistor 450, the source electrode layer 41 covers the island-shaped oxide semiconductor layer 406. After forming conductive films that will become 0a and the drain electrode layer 410b, the conductive films are processed to form the source electrode. Layer 410a and drain electrode layer 410b are formed, source electrode layer 410a and drain electrode The source electrode layer 410 covers a portion of the oxide semiconductor layer 406 exposed from the polar layer 410b. an insulating layer 408 is formed on the drain electrode layer 410b. Therefore, transistor 45 At 0, the source electrode layer is in contact with the side and part of the top surface of the island-shaped oxide semiconductor layer 406. Layers 410a and 410b of the drain electrode are formed.

[0123] On the other hand, in transistor 460, an insulating layer 408 covers the island-shaped oxide semiconductor layer 406. After forming and creating contact holes in the insulating layer 408, in the contact holes The source electrode layer 410a and drain electrode layer 410b are connected to the oxide semiconductor layer 406. Therefore, in transistor 460, a portion of the upper surface of the oxide semiconductor layer 406 is in contact. The source electrode layer 410a and the drain electrode layer 410b are formed in this manner. However, the insulating layer 4 Depending on the conditions for forming the contact hole to 08, a portion of the oxide semiconductor layer 406 may simultaneously Etching may occur. For example, contact holes may form between the second layer 406b and the insulating layer 408. A layer is formed, with a source electrode layer 410a, a drain electrode layer 410b, and a first layer 406a There are cases where they come into contact.

[0124] The other components included in transistor 460 shall be the same as those of transistor 450. It is possible.

[0125] <Transistor Fabrication Method 1> Below, an example of how to fabricate transistor 460 will be explained with reference to Figure 14.

[0126] First, a gate electrode layer 402 (including wiring formed in the same layer) is placed on the substrate 400. A gate insulating layer 404 is formed on the gate electrode layer 402 (see Figure 14(A)).

[0127] There are no major restrictions on the material of the substrate 400, but it should at least be able to withstand subsequent heat treatment. It must have heat resistance. For example, glass substrate, ceramic substrate, quartz substrate, saffron A wire substrate or the like may be used as the substrate 400. Alternatively, silicon or silicon carbide may be used. Single-crystal semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, S It is also possible to apply OI substrates, etc., and semiconductor elements are provided on these substrates. The above may be used as the substrate 400. 6th generation (1500mm x 1850mm), 7th generation (1870mm x 2200mm) 8th generation (2200mm x 2400mm), 9th generation (2400mm x 2800mm) By using large-area substrates such as the 10th generation (2950mm x 3400mm), large-scale displays can be created. A display device can be manufactured.

[0128] Furthermore, a flexible substrate is used as the substrate 400, and the transistor 460 is directly mounted on the flexible substrate. A semiconductor device in one aspect of the present invention may form an oxide semiconductor layer at room temperature. Because it is possible to form a film, even flexible substrates with low heat resistance can be suitably used. This is possible. Alternatively, a release layer may be provided between the substrate 400 and the transistor 460. The abscission layer is separated from the substrate 400 after the semiconductor device is partially or completely completed on it. It can be used to transfer to other substrates. In that case, transistor 460 has inferior heat resistance. It can also be mounted on flexible substrates.

[0129] The material of the gate electrode layer 402 is molybdenum, titanium, tantalum, tungsten, aluminum Metal materials such as um, copper, chromium, neodymium, scandium, or alloys with these as the main components. It can be formed using materials. In addition, impurity sources such as phosphorus can be used as the gate electrode layer 402. Semiconductor films such as polycrystalline silicon films doped with a specific element, and nickel silicides. A reside film may be used. The gate electrode layer 402 may have a single layer structure or a multilayer structure. The gate electrode layer 402 may also be tapered, for example, with a taper angle of 15° or less. The angle should be 70° or less. Here, the taper angle is the angle between the side surface of the layer having a tapered shape and the opposite side. This refers to the angle between the bottom surface of the layer and the surrounding area.

[0130] Furthermore, the material of the gate electrode layer 402 includes indium tin oxide and tungsten oxide. Indium oxide, indium zinc oxide containing tungsten oxide, and titanium oxide containing Indium oxide, indium tin oxide containing titanium oxide, indium oxide zinc oxide, acid Conductive materials such as indium tin oxide with added silicon dioxide can also be used.

[0131] Alternatively, as the material for the gate electrode layer 402, an In-Ga-Zn oxide containing nitrogen, nitrogen In-Sn oxides containing nitrogen, In-Ga oxides containing nitrogen, In-Zn oxides containing nitrogen Indioxides, nitrogen-containing Sn-based oxides, nitrogen-containing In-based oxides, metal nitride films (indioxides) You may also use a film such as a tungsten nitride film, zinc nitride film, tantalum nitride film, or tungsten nitride film. Since these materials have a work function of 5 electron volts or more, these materials can be used to form gate electrodes. By forming layer 402, the threshold voltage of the transistor can be made positive, This makes it possible to implement Mario's switching transistor.

[0132] The gate insulating layer 404 is formed by plasma CVD, sputtering, etc. Cone layer, silicon oxide nitride layer, silicon nitride oxide layer, silicon nitride layer, aluminum oxide Layer, hafnium oxide layer, yttrium oxide layer, zirconium oxide layer, gallium oxide layer, acid Tantalum oxide layer, magnesium oxide layer, lanthanum oxide layer, cerium oxide layer, and neodymium oxide layer An insulating layer containing one or more types of um layers can be used. The gate insulating layer 404 is as described above. A laminated structure using insulating layer material may also be used.

[0133] Furthermore, the insulating layer 404b that comes into contact with the oxide semiconductor layer 406, which is formed later, is made of oxide insulating layer A region that is preferable and contains an excess of oxygen compared to the stoichiometric composition (oxygen-rich region). It is more preferable to have. To form an oxygen-rich region in the insulating layer 404b, for example, acid The insulating layer 404b can be formed in an oxygen-free atmosphere. Alternatively, oxygen can be added to the insulating layer 404b after film formation. A region with excess oxygen may be formed by introducing oxygen. Methods for introducing oxygen include ion implantation and On-doping, plasma immersion ion implantation, plasma treatment, etc. can be used. can.

[0134] In this embodiment, a silicon nitride film is formed as the insulating layer 404a, and the insulating layer 404b and This forms a silicon oxide nitride film.

[0135] Next, a first oxide semiconductor film 407a, which will become the first layer 406a, is placed on the gate insulating layer 404. Then, a second oxide semiconductor film 407b, which becomes the second layer 406b, is stacked on top of it.

[0136] In this embodiment, the first oxide semiconductor film 407a is made of In-M-Zn oxide (M is Oxide semiconductors (represented by Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf) The body is used. Furthermore, the atomic ratio of In to M is preferably such that In is 50 atomically less than M is 50 atomic% or more, and more preferably In is less than 25 atomic%, M is defined as 75% or higher atomically.

[0137] Furthermore, in this embodiment, the second oxide semiconductor film 407b is made of In-M-Zn oxide (M represents a metal such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf) It is noted that the acid has a higher atomic ratio of M to indium than the first oxide semiconductor film 407a. An oxide semiconductor is applied. Specifically, the element M is 1 / 1 of the first oxide semiconductor film 407a. The oxide containing an atomic ratio that is 5 times or more, preferably 2 times or more, and more preferably 3 times or more higher. It is preferable to use a conductor. Since element M bonds more strongly with oxygen than indium, oxygen It has the function of suppressing the occurrence of defects. Therefore, the second oxide semiconductor film 407b is This allows for the creation of an oxide semiconductor film that is less prone to oxygen vacancies than oxide semiconductor film 407a. Cut.

[0138] Furthermore, as the second oxide semiconductor film 407b, the energy at the lower end of the conduction band is the same as that of the first oxide semiconductor film. An oxide semiconductor with a vacuum level closer than that of the conductive film 407a is applied. For example, a second oxide semiconductor The energy at the lower end of the conduction band of the conductive film 407b and the energy at the lower end of the conduction band of the first oxide semiconductor film 407a The difference from the end energy is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, The voltage is 0.15 eV or higher, and 2 eV or lower, 1 eV or lower, 0.5 eV or lower, or 0.4 eV. The following is preferable.

[0139] For example, in the second oxide semiconductor film 407b, the atomic ratio of In to M is preferably In is 25 atomic% or more, M is less than 75 atomic%, and more preferably I n is defined as 34 atomic% or greater, and M is defined as less than 66 atomic%.

[0140] Also, for example, the first oxide semiconductor film 407a may have an In:Ga:Zn ratio of 1:1:1. In-Ga-Zn oxide with an atomic ratio of 3:1:2 can be used. Also, the second For oxide semiconductor film 407b, In:Ga:Zn = 1:3:2, 1:3:4, 1:3:6 In-Ga-Zn oxides with atomic ratios of 1:6:4 or 1:9:6 can be used. The atoms of the first oxide semiconductor film 407a and the second oxide semiconductor film 407b Each numerical ratio includes a variation of plus or minus 20% from the atomic ratios mentioned above.

[0141] Furthermore, this is not limited to the semiconductor characteristics and electrical characteristics (field effect) of the transistor as needed. A suitable composition should be used depending on the mobility, threshold voltage, etc. To obtain the semiconductor characteristics of the transistor, a first oxide semiconductor film 407a and a second oxide The carrier density, impurity concentration, defect density, and atomic ratio of metal elements to oxygen of the semiconductor film 407b. It is preferable to set appropriate interatomic distances, densities, etc.

[0142] The method for depositing the first oxide semiconductor film 407a and the second oxide semiconductor film 407b is a spa Taring method, MBE (Molecular Beam Epitaxy) method, CVD method, Pulsed laser deposition, ALD (Atomic Layer Deposition), etc. It can be used as appropriate.

[0143] Furthermore, in order to reduce oxygen vacancies in the oxide semiconductor film after deposition, under an oxygen-containing atmosphere It is preferable to form the first oxide semiconductor film 407a and the second oxide semiconductor film 407b. Furthermore, the interface between the first oxide semiconductor film 407a and the second oxide semiconductor film 407b. To prevent impurities from being introduced, the first oxide semiconductor film 407a is deposited and then exposed to the atmosphere. It is preferable to continuously deposit the second oxide semiconductor film 407b without interruption.

[0144] For example, by using a sputtering target containing polycrystalline material, By forming the first oxide semiconductor film 407a and the second oxide semiconductor film 407b, A first oxide semiconductor film 407a and a second oxide semiconductor film 407b containing nanocrystals are formed. It is possible.

[0145] Furthermore, when forming the first oxide semiconductor film 407a and the second oxide semiconductor film 407b, It is preferable to reduce the hydrogen concentration contained in the membrane as much as possible. For example, when performing film deposition using the sputtering method, the deposition chamber is evacuated to a high vacuum. Furthermore, it is also necessary to increase the purity of the sputtering gas. The oxygen gas used as the sputtering gas... The argon gas has a dew point of -40°C or lower, preferably -80°C or lower, more preferably -1 By using a gas purified to below 0°C, more preferably below -120°C, oxidation can be eliminated. This makes it possible to prevent moisture and other substances from being incorporated into the semiconductor film 208 as much as possible.

[0146] Furthermore, in order to remove residual moisture in the deposition chamber, an adsorption-type vacuum pump, such as a cryo- It is preferable to use a pump, an ion pump, or a titanium sublimation pump. A turbomolecular pump may also be provided with a cold trap. A cryopump is, For example, hydrogen molecules, compounds containing hydrogen atoms such as water (H2O), compounds containing carbon atoms, etc. Because of its high exhaust capacity, it is contained in films deposited in a deposition chamber evacuated using a cryopump. The concentration of impurities can be reduced.

[0147] Furthermore, the first oxide semiconductor film 407a and the second oxide semiconductor film 407b are sputtered. When depositing a film using the 3D method, the relative density (filling density) of the metal oxide target used for film deposition is 90%. The relative density should be 100% or less, preferably 95% to 99.9%. By using a chromium target, the resulting film can be made dense.

[0148] The first oxide semiconductor film 407a and the second oxide semiconductor film 407b were prepared at room temperature. It is preferable to form a film. First oxide semiconductor film 407a and second oxide semiconductor film 40 By depositing 7b at room temperature, an oxide semiconductor film containing nanocrystals can be formed with high productivity. It becomes possible to do so.

[0149] Next, the first oxide semiconductor film 407a and the second oxide semiconductor film 407b are placed in the desired region. By processing, an island-shaped oxide semiconductor layer including the first layer 406a and the second layer 406b is formed. Form 406. Note that when processing the oxide semiconductor layer 406, the gate insulating layer 404 A portion (the area exposed from the first layer 406a and the second layer 406b) is etched and the film thickness is reduced. It may decrease.

[0150] It is preferable to perform heat treatment after forming island-shaped oxide semiconductor layers 406. The heat treatment is performed at 250°C. °C to 650°C, preferably 300°C to 400°C, more preferably 320°C or below At temperatures below 370°C, in an inert gas atmosphere, or an atmosphere containing 10 ppm or more of an oxidizing gas, Alternatively, the process can be carried out under reduced pressure. Furthermore, the heat treatment should be performed under an inert gas atmosphere. Even if you perform the procedure in an atmosphere containing 10 ppm or more of oxidizing gas to replenish the removed oxygen, Good. The heat treatment here reduces the amount of the gate insulating layer 404 and the oxide semiconductor layer 406. Furthermore, impurities such as hydrogen and water can be removed from scratch. Before processing the first oxide semiconductor film 407a and the second oxide semiconductor film 407b into island shapes, That's fine.

[0151] Next, an insulating layer 408 is formed on the oxide semiconductor layer 406 (see Figure 14(C)).

[0152] For the insulating layer 408, the same material as the gate insulating layer 404 is used, either as a single layer or in a multilayer configuration. It is possible.

[0153] In this embodiment, the insulating layer 408 consists of an insulating layer 408a made of an oxide insulating layer and a nitride insulating layer The insulating layer 408a is a silicon oxidizide film, and the insulating layer 408a is an insulating layer 408b. A silicon nitride film is formed as layer 408b. The insulating layer 408a has a stoichiometric composition. It is more preferable to have a region containing an excess of oxygen (oxygen-rich region).

[0154] It is preferable to perform heat treatment after forming the insulating layer 408a. A portion of the oxygen contained in a is moved to the oxide semiconductor layer 406, and in the oxide semiconductor layer 406 It is possible to compensate for oxygen deficiencies. The heat treatment conditions are as follows: after forming the oxide semiconductor layer 406 The heat treatment can be the same as that used for the previous method.

[0155] Next, by processing the insulating layer 408 into the desired region, the oxide semiconductor layer 406 is formed. This forms a tact hole 409 (see Figure 14(D)).

[0156] Furthermore, the contact hole 409 is formed such that a portion of the oxide semiconductor layer 406 is exposed. When forming the contact hole 409, the second layer 406b of the oxide semiconductor layer 406 is reduced. At the very least, remove a portion of it to reduce the thickness of the second layer 406b that overlaps with the contact hole 409. It is preferable to reduce it. Alternatively, when forming the contact hole 409, the first layer 406a It is preferable to form a contact hole in the second layer 406b so that a portion of it is exposed. .

[0157] Removing a portion of the second layer 406b, or forming a contact hole in the second layer 406b Therefore, in the oxide semiconductor layer 406, the source electrode layer 410a and the drain electrode layer that are formed later are The film thickness at the location in contact with the electrode layer 410b can be reduced compared to the other film thicknesses. As a result, the oxide semiconductor layer 406, the source electrode layer 410a, and the drain electrode layer 410b This is preferable because it can reduce the contact resistance. As described above, the second layer 40 6b, compared to the first layer 406a, has element M (where M is Al, Ga) relative to indium. This is a region with a high atomic ratio of Ge, Y, Zr, Sn, La, Ce, or Hf. The higher the atomic ratio of element M, the greater the energy gap (band gap) of the oxide semiconductor layer. Because the gap becomes larger, the second layer 406b has a higher insulating acid than the first layer 406a. It is a phosphate film. Therefore, the source electrode layer 410a and drain electrode layer 410 that are formed later In order to reduce the contact resistance between b and the oxide semiconductor layer 406, the second layer 406b Reducing the film thickness or partially removing the second layer 406b is effective.

[0158] For example, a dry etching method can be used to form the contact hole 409. This is possible. However, the method for forming the contact hole 409 is not limited to this, Wet etching method, or a combination of dry etching and wet etching methods. It can also be used as a formation method.

[0159] Next, a conductive film is formed on the contact hole 409 and the insulating layer 408, and then processed. This forms the source electrode layer 410a and the drain electrode layer 410b (see Figure 14(E)). (see).

[0160] The material for the conductive film that forms the source electrode layer 410a and the drain electrode layer 410b is aluminum. nium, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver A single metal consisting of tantalum or tungsten, or an alloy having these as its main component. It can be used as a layered or laminated structure. For example, a titanium film on an aluminum film. A two-layer structure in which layers are stacked, a two-layer structure in which a titanium film is stacked on a tungsten film, copper-magnesium A two-layer structure consisting of a copper film laminated on an aluminum alloy film, a titanium film or a titanium nitride film, An aluminum film or copper film is laminated on top of the titanium film or titanium nitride film, and further A three-layer structure formed by forming a titanium film or titanium nitride film on top of that, or a molybdenum film or molybdenum nitride film. A molybdenum film, and an aluminum film or a molybdenum nitride film layered on top of the molybdenum film or molybdenum nitride film. A three-layer structure in which copper films are stacked, and then a molybdenum film or molybdenum nitride film is formed on top of them. These include the following. Furthermore, transparent conductive materials containing indium oxide, tin oxide, or zinc oxide can also be used. That's good. Furthermore, the conductive film can be formed, for example, using a sputtering method.

[0161] Through the above process, a channel-protected transistor 460 can be formed.

[0162] <Example 3 of semiconductor device configuration> Figure 15 shows an example configuration of transistor 350. Transistor 350 is shown in Figure 1. This is a top-gate transistor having a stacked structure as described using 3. Figure 15( A) is a plan view of transistor 350, and Figure 15(B) is V3-W3 of Figure 15(A). This is a cross-sectional view, and Figure 15(C) is a cross-sectional view of Figure 15(A) along the line X3-Y3. .

[0163] Note that the components of transistor 350 are largely the same as those previously described, except for a different stacking order. It shares the same structure as top-gate transistors. Therefore, for detailed configuration, see the previous section. Since explanations can be consulted, details may be omitted.

[0164] The transistor 350 shown in Figure 15 is located on an insulating layer 308 provided on a substrate 300, forming an island shape. The oxide semiconductor layer 316 and the source electrode layer 31 which is electrically connected to the oxide semiconductor layer 316 0a and drain electrode layer 310b, source electrode layer 310a and drain electrode layer 310b A gate insulating layer 304 that is in contact with a portion of the oxide semiconductor layer 316 that has been exposed from the gate insulating layer It includes an oxide semiconductor layer 316 and a gate electrode layer 302 that overlap each other via 304.

[0165] The oxide semiconductor layer 316 contained in transistor 350 is the first layer in which the channel is formed. 316a, the second layer 316b between the first layer 316a and the insulating layer 308, and the first layer 3 The laminated structure includes a third layer 316c between 16a and the gate insulating layer 304, and the first layer 316a, the second layer 316b, and the third layer 316c are oxide semiconductors containing nanocrystals, respectively. These are body layers, and are the first layer 106a, the second layer 106b, and the third layer 1 shown in Embodiment 1. These correspond to 06c respectively.

[0166] Furthermore, the first layer 316a, the second layer 316b, and the third layer 316c are each made of indiu It contains aluminum and zinc as constituent elements, and the conduction of the second layer 316b and the third layer 316c The energy at the bottom edge of the band is 0.0 compared to the energy at the bottom edge of the conduction band of the first layer 316a. It is close to the vacuum level in the range of 0.5eV to 2eV.

[0167] In transistor 350, the insulating layer 308, which functions as an underlying insulating layer, is on substrate 300 or In addition to preventing the diffusion of impurities, the second layer 316b and / or the first layer 31 It is responsible for supplying oxygen to 6a. Therefore, an insulating layer containing oxygen is used for the insulating layer 308. The details can be the same as the insulating layer 408a. By supplying oxygen, it is possible to reduce oxygen vacancies in the oxide semiconductor layer 316. This is possible. Furthermore, if other semiconductor elements are formed on the substrate 300, the insulating layer 308 is... It also functions as an interlayer insulating film. In that case, CMP (Che) is used to make the surface flat. Perform a planar treatment using methods such as mechanical polishing. It is preferable.

[0168] <Example of semiconductor device configuration 4> Figure 16 shows an example configuration of transistor 360. Transistor 360 is connected to transistor 35 This is a top-gate transistor with a configuration that differs in some aspects from that of transistor 0. Figure 16(A) This is a plan view of transistor 360, and Figure 16(B) is the same as V4-W4 in Figure 16(A). This is a cross-sectional view, and Figure 16(C) is a cross-sectional view of Figure 16(A) along the line X4-Y4.

[0169] The transistor 360 shown in Figure 16 is located on an insulating layer 308 provided on a substrate 300, forming an island shape. The oxide semiconductor layer 316 and the source electrode layer 31 which is electrically connected to the oxide semiconductor layer 316 0a and drain electrode layer 310b and gate insulating layer 304 in contact with oxide semiconductor layer 316 The gate electrode layer 30 overlaps with the oxide semiconductor layer 316 via the gate insulating layer 304. Includes 2 and .

[0170] The oxide semiconductor layer 316 consists of a first layer 316a, a second layer 316b, and a third layer 316c. Including the second layer 316b which is provided in contact with the insulating layer 308, and the first layer 316a which is the second It is provided in contact with layer 316b. The source electrode layer 310a and the drain electrode layer 310b are , one side of the island-shaped second layer 316b and the first layer 316a and the upper surface of the first layer 316a It is provided so as to cover a part of it. Also, the third layer 316c is the source electrode layer 310a and Located on the rain electrode layer 310b, and the source electrode layer 310a and drain electrode layer 310b It is in contact with a portion of the first layer 316a that has been exposed.

[0171] As shown in Figure 16(B), transistor 360 has island-shaped second segments in a cross-section along the length of W. The third layer 316c covers the sides of layer 316b and the first layer 316a, and further the third layer 3 The side surface of 16c is covered by a gate insulating layer 304. With this configuration, To reduce the influence of parasitic channels that may occur at the W-length edge of the oxide semiconductor layer 316. It is possible.

[0172] Furthermore, as shown in Figures 16(A) and 16(C), the third layer 316c and the gate insulating layer 304 has the same planar shape as the gate electrode layer 302, in other words, in the cross-sectional view The upper end of the third layer 316c coincides with the lower end of the gate insulating layer 304, and the gate insulating layer The upper end of 304 coincides with the lower end of the gate electrode layer 302. This shape is a gate Using the electrode layer 302 as a mask (or the same mask on which the gate electrode layer 302 is formed) By processing the third layer 316c and the gate insulating layer 304 (using a special tool), the following is formed. This is possible. Furthermore, in this specification, the expressions "identical" or "same" mean strictly identical, or This term is used to indicate that exact agreement is not required, and includes the category of "approximately identical" or "approximately the same." For example, the degree of agreement in shapes obtained by etching using the same mask. Includes.

[0173] <Method for fabricating semiconductor devices, part 2> An example of a method for fabricating the transistor 360 shown in Figure 16 will be explained using Figure 17.

[0174] First, an insulating layer 308 and a second oxide semiconductor film which will become the second layer 316b are placed on the substrate 300. Form 317b and the first oxide semiconductor film 317a which will become the first layer 316a (Figure 17). (See (A)).

[0175] The insulating layer 308 may be a single layer or a multilayer. However, at least the oxidation that is formed later The region in contact with the semiconductor layer 316 is formed of an oxygen-containing material. It is preferable to form it as a layer.

[0176] Furthermore, it is preferable that the hydrogen concentration in the insulating layer 308 is reduced. After forming layer 308, a heat treatment (dehydration treatment or dehydrogenation treatment) is performed to remove hydrogen. It is preferable to do so. Note that oxygen may be removed from the insulating layer 308 due to heat treatment. Therefore, a process is performed to introduce oxygen into the insulating layer 308 that has undergone dehydration or dehydrogenation treatment. It is preferable to do so.

[0177] The second oxide semiconductor film 317b is made of the same materials and methods as the second oxide semiconductor film 407b. It can be formed by the first oxide semiconductor film 317a. It can be formed using the same materials and methods as film 407a.

[0178] After forming the second oxide semiconductor film 317b and the first oxide semiconductor film 317a, heat treatment is performed. It is preferable that the heat treatment be performed at 250°C to 650°C, preferably 300°C to 50°C. At temperatures below 0°C, in an inert gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or reduced temperature It should be done in a compressed atmosphere. Also, the heat treatment atmosphere should be after the heat treatment has been performed in an inert gas atmosphere. Alternatively, the process may be carried out in an atmosphere containing 10 ppm or more of an oxidizing gas to replenish the desorbed oxygen.

[0179] Next, the second oxide semiconductor film 317b and the first oxide semiconductor film 317a are processed to form an island A second layer 316b and a first layer 316a are formed in this manner. Here, the second layer 316b and The first layer 316a can be processed by etching using the same mask. Therefore, the planar shapes of the second layer 316b and the first layer 316a are identical, and the second layer 316 The upper end of b and the lower end of the first layer 316a coincide.

[0180] Furthermore, when processing the second layer 316b and the first layer 316a, the second oxide semiconductor film 3 Due to over-etching of 17b, a portion of the insulating layer 308 (from the island-like second layer 316b) is removed. The exposed area may be etched, which can reduce the film thickness.

[0181] Next, a conductive film is formed on the first layer 316a, and the conductive film is processed to create the source electrode layer 310a. And a drain electrode layer 310b is formed (see Figure 17(B)).

[0182] In this embodiment, the edges of the source electrode layer 310a and the drain electrode layer 310b The shape will have multiple steps arranged in a staircase-like manner. The end portion will be processed by ashing to create a resistant finish. The process of retracting the mask and etching is performed alternately multiple times to form the mask. can.

[0183] In this embodiment, the edges of the source electrode layer 310a and the drain electrode layer 310b The example shows a shape with two steps in the section, but the number of steps may be three or more, and the processing method The number of layers may be reduced to one without performing resist ashing inside. Source electrode layer 310a and Furthermore, the thicker the film thickness of the drain electrode layer 310b, the more preferable it is to increase the number of such layers. The edges of the source electrode layer 310a and the drain electrode layer 310b do not need to be symmetrical. A curved surface with an arbitrary radius of curvature may be formed between the top surface and the cross-section of each step shape. .

[0184] The source electrode layer 310a and the drain electrode layer 310b are provided with multiple steps as described above. By doing so, the film formed above them, specifically the third layer 316c, gate insulation The coating properties of the margin layer 304 and other components are improved, thereby enhancing the electrical characteristics and long-term reliability of the transistor. It is possible.

[0185] Furthermore, when processing the source electrode layer 310a and the drain electrode layer 310b, the conductive film may be over-processed. - By etching, a portion of the insulating layer 308 and a portion of the first layer 316a (source electrode layer) are removed. The areas exposed from 310a and the drain electrode layer 310b are etched and the film thickness decreases. It can happen.

[0186] Furthermore, the conductive films that form the source electrode layer 310a and the drain electrode layer 310b are considered as residue. If the residue remains on layer 316a, it will be an impurity in the first layer 316a or at the interface. A state may be formed. Alternatively, oxygen may be drawn from the first layer 316a by the residue. This can lead to oxygen depletion.

[0187] Therefore, after forming the source electrode layer 310a and the drain electrode layer 310b, the first layer 316a The surface may be subjected to a residue removal treatment. The residue removal treatment may involve etching (for example, welding Treatment by (etching) or plasma treatment using oxygen or nitrous oxide. This can be done by removing the residue from the source electrode layer 310a and the drain. The thickness of a portion of the first layer 316a exposed between the in electrode layers 310b is between 1 nm and 3 nm. It may decrease to some extent.

[0188] Next, a third layer 316c is added on top of the source electrode layer 310a and the drain electrode layer 310b. A third oxide semiconductor film 317c and a gate insulating film 303 which will become a gate insulating layer 304 are laminated. This is how it is formed (see Figure 17(C)).

[0189] Furthermore, the third oxide semiconductor film 317c and the gate insulating film 303 are not exposed to the atmosphere and are continuous. When formed, impurities such as hydrogen and moisture are adsorbed onto the surface of the third oxide semiconductor film 317c. This is preferable because it can prevent this from happening.

[0190] The third oxide semiconductor film 317c is made of the same materials and uses the same methods as the second oxide semiconductor film 317b. It can be formed using [this method].

[0191] The gate insulating film 303 is formed using the same materials and methods as the gate insulating layer 404. It is possible.

[0192] Next, a gate electrode layer 302 is formed on the gate insulating film 403. After that, the gate electrode Using layer 302 as a mask, the third oxide semiconductor film 317c and the gate insulating film 303 are processed. Then, the third layer 316c and the gate insulating layer 304 are formed (see Figure 17(D)). Using the electrode layer 302 as a mask, the third layer 316c and the gate insulating layer 304 are added in a self-aligned manner. This method is preferable because it does not increase the number of masks required.

[0193] The gate electrode layer 302 is formed using the same materials and methods as the gate electrode layer 402. It is possible.

[0194] By processing the third oxide semiconductor film 317c into the third layer 316c, the third layer 316 The outward diffusion of indium contained in c can be suppressed. This can cause fluctuations in the electrical characteristics of transistors and contribute to contamination in the deposition chamber during the process. Therefore, processing the third layer 316c using the gate electrode layer 302 as a mask is effective.

[0195] Based on the above, transistor 360 can be fabricated.

[0196] The transistor shown in this embodiment includes the stacked structure of Embodiment 1, and the oxide semiconductor layer In this configuration, a third layer is provided between the first layer in which the channel is formed and the insulating layer, thus preventing oxidation. Because the interface of the semiconductor layer and the channel can be separated, the influence of the interface state on the channel is reduced. This makes it possible to suppress [the following]. In addition, the first to third layers are compared with amorphous oxide semiconductors. It is composed of nanocrystalline oxide semiconductors with a reduced defect level density. By using an oxide semiconductor layer containing the reduced first to third layers in a transistor, This reduces fluctuations in the electrical characteristics of the transistor and improves its reliability.

[0197] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0198] (Embodiment 3) As an example of a semiconductor device according to one aspect of the present invention, the circuit diagram of a NOR type circuit which is a logic circuit is An example is shown in Figure 18(A). Figure 18(B) is a circuit diagram of a NAND gate.

[0199] In the NOR type circuit shown in Figure 18(A), the p-channel transistor is Ta 801 and 802 are semiconductor materials other than oxide semiconductors (for example, silica) in the channel formation region. A transistor using a capacitor (such as a capacitor) is used, and the transistor is an n-channel transistor, transistor 8 03 and 804 contain an oxide semiconductor and have a structure similar to the transistor shown in Embodiment 2. A transistor is used.

[0200] Transistors using semiconductor materials such as silicon are easy to operate at high speeds. On the other hand, oxides Transistors, which use semiconductors, can retain charge for extended periods due to their properties.

[0201] To miniaturize logic circuits, n-channel transistors such as transistors 803 and 8 04 is stacked on top of transistors 801 and 802, which are p-channel type transistors. It is preferable. For example, transistors 801 and 802 are formed using a single-crystal silicon substrate. This forms transistors 803 and 804 on top of transistors 801 and 802 via an insulating layer. It is possible to achieve this.

[0202] Furthermore, in the NAND type circuit shown in Figure 18(B), the p-channel transistor is called a transistor. ZISTAS 811 and 814 use semiconductor materials other than oxide semiconductors in the channel formation region (for example, A transistor made of silicon, etc., and an n-channel type transistor 812 and 813 include an oxide semiconductor layer and are the same as the transistor shown in Embodiment 2 above. A transistor with a similar structure is used.

[0203] Also, similar to the NOR circuit shown in Figure 18(A), to miniaturize the logic circuit, n channels Transistors 812 and 813, which are of type p, are p-channel type transistors. It is preferable that they are stacked on transistors 811 and 814.

[0204] In the semiconductor device shown in this embodiment, an oxide semiconductor is used in the channel formation region for off-current By using extremely small transistors, power consumption can be significantly reduced. .

[0205] Furthermore, miniaturization and high integration can be achieved by stacking semiconductor elements made of different semiconductor materials. A semiconductor device that achieves and provides stable and high electrical characteristics, and the fabrication of the semiconductor device. We can provide a method.

[0206] Furthermore, by applying the configuration of a transistor including an oxide semiconductor layer according to one aspect of the present invention This allows us to provide NOR-type and NAND-type circuits that exhibit high reliability and stable characteristics. Cut.

[0207] In this embodiment, a NOR type circuit using the transistor shown in Embodiment 2 and N An example of an AND type circuit is shown, but it is not particularly limited, and the transistors shown in Embodiment 2 can be used. It is also possible to form AND gates, OR gates, and other types of circuits.

[0208] Alternatively, the transistor described in this embodiment or another embodiment may be combined with a display element. It is possible to configure a display device by combining a display element and a device having a display element. Display devices, light-emitting elements, and light-emitting devices having light-emitting elements can take various forms It can use or have various elements. Display element, display device, light-emitting element or One example of a light-emitting device is an EL (electroluminescent) element (organic and inorganic materials) EL elements (including organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs) Color LEDs, blue LEDs, etc.), transistors (transistors that emit light according to the current), electric Micro-emission elements, liquid crystal elements, electronic inks, electrophoretic elements, grating light bulbs (GL V) Plasma display panels (PDPs), digital micromirror devices (DM) D) Piezoelectric ceramic displays, carbon nanotubes, etc., due to electromagnetic effects Some display media have properties such as contrast, brightness, reflectance, and transmittance that change over time. An example of a display device using EL elements is an EL display. An example of a display device using this is a field emission display (FED) or SED flat-panel display (SED: Surface-conduction electroluminescent) Examples include LCD-emitter displays. One example of placement is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display). (Reflective liquid crystal displays, direct-view liquid crystal displays, projection liquid crystal displays) Examples include electronic paper. These are some examples.

[0209] The configurations and methods described in this embodiment are suitable for use with configurations and methods described in other embodiments. They can be used in any combination.

[0210] (Embodiment 4) In this embodiment, the transistor shown in Embodiment 2 is used, in a situation where no power is supplied. However, a semiconductor device (memory device) that can retain its contents and has no limit on the number of write cycles is required. An example of this will be explained using a diagram.

[0211] Figure 19(A) is a circuit diagram showing the semiconductor device of this embodiment.

[0212] The transistor 260 shown in Figure 19(A) is made of semiconductor material other than oxide semiconductors (for example, s Transistors using (such as recon) can be applied, making high-speed operation easy. The transistor 262 includes an oxide semiconductor layer according to one aspect of the present invention, as shown in Embodiment 2. A transistor with a structure similar to a transistor can be applied, and its characteristics make it long This enables the retention of electrical charge over time.

[0213] The above explanation assumes that all transistors are n-channel transistors. However, the transistor used in the semiconductor device shown in this embodiment is a p-channel type transistor. You can also use a generator.

[0214] In Figure 19(A), the first line and the source of transistor 260. The electrode layer is electrically connected to the second line and transistor 260. It is electrically connected to the drain electrode layer. Also, the third wiring (3rd Line) ) and either the source electrode layer or the drain electrode layer of transistor 262 are electrically connected. The fourth wire (4th Line) and the gate electrode layer of transistor 262 are electrically connected. They are precisely connected. And the gate electrode layer of transistor 260 and transistor 26 The other of the source electrode layer or drain electrode layer of 2 is electrically connected to one of the electrodes of the capacitive element 264. The fifth line and the other electrode of the capacitive element 264 are electrically connected. It is connected.

[0215] In the semiconductor device shown in Figure 19(A), the potential of the gate electrode layer of transistor 260 can be maintained. By utilizing its unique characteristics, it is possible to write, store, and read information in the following ways: ru.

[0216] This section will explain how to write and retain information. First, the potential of the fourth wire is set to the transistor. The potential is set so that transistor 262 is ON, thereby turning on transistor 262. The potential of the third wiring is supplied to the gate electrode layer of transistor 260 and the capacitive element 264. It is obtained. That is, a predetermined charge is given to the gate electrode layer of transistor 260. (Writing). Here, a charge that gives two different potential levels (hereinafter referred to as Low-level charge) Let either of the following be given: (referred to as a high-level charge). Then, the fourth wiring The potential is set to the potential at which transistor 262 is in the off state, thereby turning off transistor 262. By setting it to this state, the charge applied to the gate electrode layer of transistor 260 is retained. (to hold).

[0217] Because the off-current of transistor 262 is extremely small, the gate electrode layer of transistor 260 The charge is retained for a long time.

[0218] Next, we will explain how to read the information. The first wiring is under the condition that a predetermined potential (constant potential) is applied. Then, when the appropriate potential (readout potential) is applied to the fifth wire, the gate of transistor 260 Depending on the amount of charge held in the electrode layer, the second wiring takes on a different potential. Generally, If transistor 260 is an n-channel type, then the gate electrode layer of transistor 260 will have a high level Apparent threshold V when a charge is given th_H This is the gate of transistor 260. Apparent threshold V when a low level charge is applied to the electrode layer th_L twist This is because it becomes lower. Here, the apparent threshold voltage is the voltage at which transistor 260 is turned "on". This refers to the potential of the fifth wiring necessary to achieve the "state". Therefore, the fifth wiring The potential of V th_H and V th_L By setting the potential V0 between these points, transistor 260 The charge applied to the gate electrode layer can be determined. For example, in writing, High-Re If a Bell charge is given, the potential of the fifth wire is V0 (>V th_H ) Transistor 260 turns "on" when a low-level charge is applied. The potential of the fifth wire is V0( <V th_L Even if this happens, transistor 260 will be "off" The state remains the same. Therefore, by looking at the potential of the second wire, the information that is being held can be determined. It can be read.

[0219] When memory cells are arranged in an array, only the information of the desired memory cell is read. It becomes necessary to be able to output the information. If the information is not read in this way, the state of the gate electrode layer. Regardless, the potential at which transistor 260 is in the "off state" is V th_H A smaller potential should be applied to the fifth wiring. Alternatively, regardless of the state of the gate electrode layer... The potential at which the transistor 260 is in the "on state," that is, V th_L Larger potential This should be applied to the fifth wire.

[0220] Figure 19(B) shows an example of one form of a different memory device structure. Figure 19(B) is a semiconductor device. Figure 19(C) is a conceptual diagram showing an example of a circuit configuration, and first, We will explain the semiconductor device shown in Figure 19(B), and then proceed to explain the semiconductor device shown in Figure 19(C). The following is an explanation regarding placement.

[0221] In the semiconductor device shown in Figure 19(B), the bit line BL and the source power of transistor 262 The pole or drain electrode is electrically connected to the word line WL and the gate of transistor 262. The electrode layer is electrically connected to the source electrode or drain electrode of transistor 262. It is electrically connected to the first terminal of the capacitive element 254.

[0222] The oxide semiconductor transistor 262 has the characteristic of having an extremely low off-current. Therefore, by turning off transistor 262, the first capacitive element 254 The potential of the terminal (or the charge accumulated in the capacitive element 254) over an extremely long period of time It is possible to hold it.

[0223] Next, information is written to and stored in the semiconductor device (memory cell 250) shown in Figure 19(B). This explains how to perform this action.

[0224] First, the potential of the word line WL is set to the potential at which transistor 262 turns ON. The zistor 262 is turned ON. This causes the potential of the bit line BL to be the same as that of the capacitive element 254. The first terminal is supplied (written). Then, the potential of the word line WL is set to transistor 2. By setting transistor 262 to the OFF state, which is the potential at which 62 is OFF, The potential of the first terminal of the quantitative element 254 is maintained (held).

[0225] Because the off-current of transistor 262 is extremely small, the potential of the first terminal of capacitive element 254 It can retain (or the charge stored in a capacitive element) for a long period of time.

[0226] Next, we will explain how to read the information. When transistor 262 is turned on, floating In this state, the bit line BL and the capacitive element 254 are conductive, and the bit line BL and the capacitive element 254 Charge is redistributed between them. As a result, the potential of bit line BL changes. The change in position is the potential of the first terminal of the capacitive element 254 (or the potential stored in the capacitive element 254). It takes on different values ​​depending on the charge.

[0227] For example, let V be the potential of the first terminal of the capacitive element 254, C be the capacitance of the capacitive element 254, and let C be the bit line The capacitance component of BL (hereinafter also called bit line capacitance) is called CB, and the capacitance before charge redistribution. If the potential of bit line BL is VB0, then the potential of bit line BL after charge redistribution is: The formula becomes (CB × VB0 + C × V) / (CB + C). Therefore, the memory cell state is 250. And, assuming that the potential of the first terminal of the capacitive element 254 takes two states, V1 and V0 (V1 > V0) Then, the potential of the bit line BL when the potential V1 is maintained is (=(CB × VB0 + C × V1 ) / (CB+C)) is the potential of the bit line BL when the potential V0 is maintained (=(CB× It can be seen that this is higher than (VB0 + C × V0) / (CB + C)).

[0228] Then, by comparing the potential of the bit line BL with a predetermined potential, information can be read out. ru.

[0229] Thus, in the semiconductor device shown in Figure 19(B), the off-current of transistor 262 is extremely low. Due to its small size, the charge stored in the capacitive element 254 can be retained for a long time. This means that refresh operations become unnecessary, or the frequency of refresh operations decreases. Because the temperature can be reduced to an extremely low level, power consumption can be significantly reduced. Furthermore, it is possible to retain the stored data for a long period of time even without a power supply. be.

[0230] Next, we will explain the semiconductor device shown in Figure 19(C).

[0231] The semiconductor device shown in Figure 19(C) has a memory circuit at the top, as shown in Figure 19(B). The memory cell array 251a and memory cell array 251b each have multiple units 250. At the bottom, memory cell array 251 (memory cell array 251a and memory cell array 25 It has peripheral circuits 253 necessary to operate 1b). Note that peripheral circuits 253 are It is electrically connected to the Morisel array 251.

[0232] By using the configuration shown in Figure 19(C), the peripheral circuit 253 is connected to the memory cell array 251. It can be installed directly below (memory cell array 251a and memory cell array 251b). Therefore, it is possible to miniaturize semiconductor devices.

[0233] The transistors provided in the peripheral circuit 253 are made of a different semiconductor material than transistor 262. It is preferable to use silicon, germanium, silicon germanium, Silicon carbide or gallium arsenide can be used, and single-crystal semiconductors can be used. Preferred. Alternatively, organic semiconductor materials may be used. The transistor is capable of high-speed operation. Therefore, the transistor enables high It is possible to suitably realize various circuits (logic circuits, drive circuits, etc.) that require high-speed operation. be.

[0234] In the semiconductor device shown in Figure 19(C), there are two memory cell arrays 251 (memory cells Although a configuration in which a memory cell array 251a and a memory cell array 251b are stacked was illustrated, The number of memory cell arrays is not limited to this. Three or more memory cell arrays can be stacked. This configuration is also acceptable.

[0235] As transistor 262, an oxide semiconductor layer according to one aspect of the present invention is used in the channel formation region. By applying transistors, it is possible to retain memory contents over a long period of time. Yes, that is. In other words, it does not require a refresh operation, or the frequency of refresh operations is extremely low. This makes it possible to use fewer semiconductor memory devices, thereby significantly reducing power consumption. It is possible.

[0236] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0237] (Embodiment 5) In this embodiment, the configuration of a display panel according to one aspect of the present invention will be described with reference to Figure 20. explain.

[0238] Figure 20(A) is a top view of a display panel according to one embodiment of the present invention, and Figure 20(B) is an embodiment of the present invention. A pixel circuit that can be used when applying liquid crystal elements to the pixels of a display panel in one embodiment of the present invention. This is a circuit diagram for illustrative purposes. Figure 20(C) is a diagram of a display panel according to one embodiment of the present invention. A circuit diagram illustrating a pixel circuit that can be used when applying organic EL elements as a base. That is the case.

[0239] The transistors placed in the pixel area can be formed according to Embodiment 2. Since the transistor can easily be made into an n-channel type, the drive circuit consists of n channels. A portion of the drive circuit, which can be constructed using type transistors, is the same type as the transistors in the pixel section. It is formed on a plate. Thus, the transistors shown in Embodiment 3 are used for the pixel section and the driving circuit. This allows us to provide a highly reliable display device.

[0240] An example of a block diagram of an active-matrix display device is shown in Figure 20(A). On the substrate 500 are a pixel section 501, a first scan line driving circuit 502, and a second scan line driving circuit. 503 has a signal line driving circuit 504. Multiple signal lines are driven by the signal line driving circuit in the pixel section 501. Extending from circuit 504, multiple scan lines are arranged to the first scan line drive circuit 502, and It is arranged as an extension from the scan line drive circuit 503. Note that the intersection area of ​​the scan line and signal line Each region has pixels, each containing a display element, arranged in a matrix. The circuit board 500 is for connecting FPC (Flexible Printed Circuit), etc. It is connected to the timing control circuit (also called a controller or control IC) via a component. .

[0241] Figure 20(A) shows the first scan line drive circuit 502, the second scan line drive circuit 503, and the signal line The drive circuit 504 is formed on the same substrate 500 as the pixel unit 501. Therefore, it is not externally installed. Since the number of components such as drive circuits is reduced, costs can be reduced. Also, the circuit board 5 00If an external drive circuit is installed, it becomes necessary to extend the wiring, and the number of connections between wires increases. When a drive circuit is provided on the same circuit board 500, the number of connections between the wires can be reduced. This can lead to improved reliability or increased yield.

[0242] <LCD panel> Furthermore, an example of the pixel circuit configuration is shown in Figure 20(B). Here, a VA-type liquid crystal display panel This shows a pixel circuit that can be applied to a pixel.

[0243] This pixel circuit can be applied to configurations in which a single pixel has multiple pixel electrode layers. The pixel electrode layer is connected to different transistors, and each transistor is driven by a different gate signal. It is configured to allow this to happen. This allows for the individual pixels of a multi-domain designed pixel to be... The signals applied to the electrode layer can be controlled independently.

[0244] The gate wiring 512 of transistor 516 and the gate wiring 513 of transistor 517 are They are separated so that different gate signals can be applied. On the other hand, as data lines The functioning source electrode layer or drain electrode layer 514 is connected to transistor 516 and transistor It is commonly used in 517. Transistors 516 and 517 are in the embodiment. The transistors described in section 2 can be used as appropriate. This allows for a highly reliable liquid crystal display. A display panel can be provided.

[0245] A first pixel electrode layer electrically connected to transistor 516, and an electrical connection between transistor 517 and transistor 517. The shape of the second pixel electrode layer that connects to the first pixel electrode layer will be described. The shape of the electrode layers is separated by slits. The first pixel electrode layer spreads out in a V-shape. The second pixel electrode layer has a shape, and is formed to surround the outside of the first pixel electrode layer.

[0246] The gate electrode layer of transistor 516 is connected to gate wiring 512, and transistor 517 The gate electrode layer is connected to gate wiring 513. Gate wiring 512 and gate wiring 5 By applying different gate signals to 13, the operating timing of transistors 516 and 517 is determined. By varying the setting, the alignment of the liquid crystals can be controlled.

[0247] Furthermore, the capacitive wiring 510, the gate insulating layer which functions as a dielectric, and the first pixel electrode layer A retention capacitance may be formed by a capacitive electrode electrically connected to a second pixel electrode layer.

[0248] The multi-domain structure includes a first liquid crystal element 518 and a second liquid crystal element 519 in each pixel. The first liquid crystal element 518 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer between them. The second liquid crystal element 519 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer between them. ru.

[0249] Note that the pixel circuit shown in Figure 20(B) is not limited to this. For example, as shown in Figure 20(B) A new switch, resistor, capacitive element, transistor, sensor, or logic circuit may be added to the pixel. You can add any of these.

[0250] <OLED panel> Another example of a pixel circuit configuration is shown in Figure 20(C). Here, an organic EL element is used. This shows the pixel structure of the display panel.

[0251] Organic EL elements emit electrons from one of a pair of electrodes when a voltage is applied to the light-emitting element. On the other hand, holes are injected into layers containing luminescent organic compounds, and an electric current flows. Through the recombination of electrons and holes, the luminescent organic compound forms an excited state, It emits light when the excited state returns to the ground state. This mechanism explains why such light emission occurs. The device is called a current-excited light-emitting element.

[0252] Figure 20(C) shows an example of an applicable pixel circuit. Here, an n-channel type An example is shown in which two lampistors are used in one pixel. Note that the oxide semiconductor layer according to one aspect of the present invention This can be used in the channel formation region of an n-channel transistor. The pixel circuit can be fitted with digital time-based grayscale driving.

[0253] Regarding the applicable pixel circuit configuration and the operation of pixels when digital time-gradation driving is applied. I will explain.

[0254] Pixel 520 includes a switching transistor 521, a driving transistor 522, and a light-emitting element. It has a sub-element 524 and a capacitive element 523. The switching transistor 521 is a gateway The electrode layer is connected to scan line 526, and the first electrode (one of the source electrode layer and drain electrode layer) is connected to the first electrode (one of the source electrode layer and drain electrode layer). ) is connected to signal line 525, and the second electrode (the other of the source electrode layer and drain electrode layer) is driven It is connected to the gate electrode layer of the drive transistor 522. The drive transistor 522 is The gate electrode layer is connected to the power line 527 via the capacitive element 523, and the first electrode is connected to the power line 5 It is connected to 27, and the second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 524. The second electrode of the light-emitting element 524 corresponds to the common electrode 528. The common electrode 528 is on the same substrate. It is electrically connected to a common potential line formed therein.

[0255] The switching transistor 521 and the driving transistor 522 are described in Embodiment 3. Transistors can be used as appropriate. This enables highly reliable organic EL displays. We can provide the panels.

[0256] The potential of the second electrode (common electrode 528) of the light-emitting element 524 is set to the low power supply potential. The power supply potential is a potential lower than the high power supply potential set on power line 527, for example, GND. The forward threshold of the light-emitting element 524 The high and low power supply potentials are set so that they are equal to or greater than the specified voltage, and the potential difference between them is used by the light-emitting element 524 By applying a current to the light-emitting element 524, an electric current is passed through it, causing it to emit light. The forward voltage in 4 refers to the voltage required to achieve the desired brightness, and at least the forward voltage is... Includes high-value voltage.

[0257] Furthermore, the capacitive element 523 is replaced by the gate capacitance of the drive transistor 522, thus saving space. It can be abbreviated. Regarding the gate capacitance of the drive transistor 522, the channel formation region and the gate A capacitance may be formed between the electrode layer and the electrode layer.

[0258] Next, we will explain the signal input to the drive transistor 522. Voltage input Voltage drive method In this case, the driving transistor 522 is either fully on or completely off. A video signal like this is input to the drive transistor 522. To operate the 522 in the linear region, a voltage higher than the voltage of the power line 527 is used for the drive. It is applied to the gate electrode layer of the transistor 522. In addition, the signal line 525 is driven by the power line voltage. Apply a voltage greater than or equal to the threshold voltage Vth of transistor 522.

[0259] When performing analog grayscale driving, the gate electrode layer of the driving transistor 522 has an luminescent element 52 A voltage greater than or equal to the sum of the forward voltage of 4 and the threshold voltage Vth of the drive transistor 522 is required. The video signal is input so that the drive transistor 522 operates in the saturation region. Then, current is passed to the light-emitting element 524. Also, the drive transistor 522 is operated in the saturation region. To achieve this, the potential of the power line 527 is set higher than the gate potential of the drive transistor 522. By converting the video signal to analog, a current corresponding to the video signal is supplied to the light-emitting element 524. It can perform analog grayscale driving.

[0260] Note that the pixel circuit configuration is not limited to the pixel configuration shown in Figure 20(C). For example, Figure 20 (C) The pixel circuit shown contains switches, resistors, capacitives, sensors, transistors or logic You may add circuits or other components.

[0261] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0262] (Embodiment 6) In this embodiment, a semiconductor device and electronic device using an oxide semiconductor layer according to one aspect of the present invention. The configuration will be explained with reference to Figures 21 and 22.

[0263] Figure 21 shows a block of electronic equipment including a semiconductor device to which an oxide semiconductor layer according to one embodiment of the present invention is applied. This is a diagram.

[0264] Figure 22 shows the appearance of an electronic device including a semiconductor device to which an oxide semiconductor layer according to one embodiment of the present invention is applied. This is a diagram.

[0265] The electronic equipment shown in Figure 21 consists of an RF circuit 901, an analog baseband circuit 902, and a digital baseband circuit. -band circuit 903, battery 904, power supply circuit 905, application processor SA 906, flash memory 910, display controller 911, memory circuit 91 2. Display 913, touch sensor 919, audio circuit 917, keyboard 918, etc. It is composed of the following.

[0266] Application processor 906 is CPU907, DSP908, interface ( It has an IF)909. Furthermore, the memory circuit 912 is composed of SRAM or DRAM. It is possible.

[0267] By applying the transistor described in Embodiment 2 to the memory circuit 912, information This allows us to provide a highly reliable electronic device capable of writing to and reading data.

[0268] Furthermore, the transistor described in Embodiment 2 is included in the CPU 907 or DSP 908. By applying this to registers, etc., reliable information can be written to and read. We can provide high-quality electronic equipment.

[0269] Furthermore, if the off-leak current of the transistor described in Embodiment 2 is extremely small, We can provide a memory circuit 912 that is capable of retaining data for a specified period and has sufficiently reduced power consumption. Also, during the power-gated period, the state before power-gated is restored. A CPU 907 or DSP 908 that can store data in a device such as a tablet can be provided.

[0270] Furthermore, the display 913 includes a display unit 914, a source driver 915, and a gate driver 91 It is composed of 6.

[0271] The display unit 914 has multiple pixels arranged in a matrix. Each pixel is equipped with a pixel circuit. The pixel circuit is electrically connected to the gate driver 916.

[0272] The transistor described in Embodiment 2 may be used as appropriate in the pixel circuit or gate driver 916. This allows for the provision of a highly reliable display.

[0273] Examples of electronic devices include television equipment (also known as televisions or television receivers). (e.g., computer monitors, digital cameras, digital video cameras, etc.) Digital photo frame, mobile phone (also called mobile phone or mobile phone device), portable Examples include game consoles, personal digital assistants, audio playback devices, and large game machines such as pachinko machines. ru.

[0274] Figure 22(A) shows a portable information terminal, consisting of a main unit 1101, a housing 1102, and a display unit 110 It consists of 3a, 1103b, etc. The display unit 1103b is a touch panel. The screen can be operated by touching the keyboard buttons 1104 displayed on the display unit 1103b. It can be used for creating and inputting text. Of course, the display unit 1103a is configured as a touch panel. The transistor shown in Embodiment 3 can be used as a switching element in a liquid crystal panel or By fabricating an organic light-emitting panel and applying it to the display units 1103a and 1103b, reliability It can be used as a highly portable information terminal.

[0275] The portable information terminal shown in Figure 22(A) can display various types of information (still images, videos, text images, etc.). Functions to display ), calendar, date or time, etc. on the display unit, The function of manipulating or editing the displayed information, and processing it using various software (programs). It can have control functions, etc. Also, external connection terminals can be located on the back or sides of the enclosure. The configuration may also include features such as an earphone jack, a USB port, and a recording medium insertion slot.

[0276] Furthermore, the portable information terminal shown in Figure 22(A) can also be configured to send and receive information wirelessly. Good. Wirelessly, you can purchase and download desired book data from an e-book server. It is also possible to configure it in this way.

[0277] Figure 22(B) shows a portable music player, the main unit 1021 having a display unit 1023 and earpieces. Mounting part 1022, speaker, operation button 1024, external memory slot The transistor shown in Embodiment 3 is used as a switching element. By manufacturing liquid crystal panels or organic light-emitting panels and applying them to the display unit 1023, It can be made into a highly reliable portable music player.

[0278] Furthermore, the portable music player shown in Figure 22(B) has an antenna, microphone function, and wireless function. Furthermore, by linking it with a mobile phone, you can wirelessly use hands-free while driving a car or other vehicle. Conversation is also possible via [platform name].

[0279] Figure 22(C) shows a mobile phone, which consists of two housings, housing 1030 and housing 1031. The enclosure 1031 contains a display panel 1032, a speaker 1033, and a microphone. 1034, pointing device 1036, camera lens 1037, external connection terminal It is equipped with 1038, etc. Also, the housing 1030 has a solar cell for charging mobile phones. It is equipped with a 1040, an external memory slot 1041, etc. The antenna is located on the housing 10 31 It is built inside. The transistor described in Embodiment 3 is displayed on the display panel 1032 By applying this, a highly reliable mobile phone can be created.

[0280] Furthermore, the display panel 1032 is equipped with a touch panel, and an image is displayed in Figure 22(C). Multiple operation keys 1035 are shown with dotted lines. Note that the output of the solar cell 1040 A boost circuit is also implemented to increase the voltage to the voltage required for each circuit.

[0281] For example, power transistors used in power supply circuits such as boost converters are also described in Embodiment 3. The oxide semiconductor layer of the transistor is formed by making the film thickness between 2 μm and 50 μm. It is possible.

[0282] The display panel 1032 changes its display orientation as appropriate depending on the usage mode. Since the camera lens 1037 is located on the same plane as 1032, video calls are possible. Speaker 1033 and microphone 1034 are not limited to voice calls, but also video calls. Recording and playback are possible. Furthermore, housings 1030 and 1031 slide apart, as shown in the figure. As shown in 22(C), it can be changed from an unfolded state to an overlapping state, making it suitable for carrying around. Further miniaturization is possible.

[0283] External connection terminal 1038 can be connected to various cables such as AC adapters and USB cables. It is capable of charging and data communication with personal computers, etc. By inserting a recording medium into memory slot 1041, it becomes possible to store and move larger amounts of data. ru.

[0284] Furthermore, even if it has infrared communication capabilities, television reception capabilities, etc. in addition to the above functions good.

[0285] Figure 22(D) shows an example of a television system. The television system 1050 is The display unit 1053 is incorporated into the housing 1051. The display unit 1053 displays video. It is possible to do so. Also, the CPU is built into the stand 1055 that supports the chassis 1051. The transistors described in Embodiment 3 are applied to the display unit 1053 and the CPU. This makes it possible to create a highly reliable television device 1050.

[0286] The television device 1050 is operated using the control switches on the housing 1051 and a separate remote control. This can be done using the control unit. Furthermore, the remote control unit can be accessed from the said remote control unit. The configuration may also include a display unit that shows the information to be output.

[0287] The television equipment 1050 will be configured to include a receiver, modem, etc. It can receive more general television broadcasts, and furthermore, it can connect via a modem, either wired or wirelessly. By connecting to the communication network, one-way (sender to receiver) or two-way communication is possible. It is also possible to communicate information (between a sender and a receiver, or between receivers, etc.).

[0288] Furthermore, the television device 1050 has an external connection terminal 1054 and a storage medium playback and recording unit 10 52. It has an external memory slot. External connection terminal 1054 is for USB cables, etc. It can be connected to various cables and enables data communication with personal computers, etc. Yes. The storage medium playback and recording unit 1052 inserts a disc-shaped recording medium and records on the recording medium. It is possible to read stored data and write it to the recording medium. Also, external memory Images, videos, and other data stored in the external memory 1056 inserted into the slot are displayed. It is also possible to display it on the display unit 1053.

[0289] Furthermore, if the off-leak current of the transistor described in Embodiment 2 is extremely small, By applying this transistor to the external memory 1056 and the CPU, the power consumption is sufficiently This allows for a television system 1050 with reduced reliability.

[0290] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination. [Explanation of symbols]

[0291] 102 Grid cell layer 104 Gate Insulation Layer 106 Oxide semiconductor layer 106a layer 106b layer 106c layer 108 Insulating layer 110 Semiconductor layer 116 Oxide semiconductor layer 116a layer 116b layer 116c layer 124 Insulating film 200 quartz glass substrate 202 Dummy circuit board 204 oxide semiconductor layer 208 Oxide Semiconductor Film 208a Oxide Semiconductor Layer 208b oxide semiconductor layer 210a area 210b area 250 memory cells 251 memory cell array 251a Memory Cell Array 251b Memory Cell Array 253 Peripheral Circuits 254 Capacitive elements 260 transistors 262 transistors 264 Capacitive elements 300 circuit boards 302 Grid cell layer 303 Gate insulating film 304 Gate Insulation Layer 308 Insulating layer 310a Source electrode layer 310b Drain electrode layer 314a Oxide semiconductor layer 314b oxide semiconductor layer 316 oxide semiconductor layer 316a layer 316b layer 316c layer 317a Oxide semiconductor film 317b oxide semiconductor film 317c oxide semiconductor film 350 transistors 360 transistors 400 circuit boards 402 Guard Layer 403 Gate Insulator 404 Gate Insulation Layer 404a insulating layer 404b insulating layer 406 oxide semiconductor layer 406a layer 406b layer 407a Oxide semiconductor film 407b oxide semiconductor film 408 Insulating layer 408a Insulating layer 408b Insulating layer 409 Contact Hole 410a Source electrode layer 410b Drain electrode layer 450 transistors 460 transistors 500 circuit boards 501 pixel section 502 Scan Line Drive Circuit 503 Scan line drive circuit 504 Signal Line Drive Circuit 510 Capacitance wiring 512 Gate Wiring 513 Gate wiring 514 Drain electrode layer 516 transistors 517 Transistors 518 liquid crystal elements 519 Liquid crystal elements 520 pixels 521 Switching Transistors 522 Driver transistors 523 Capacitive element 524 Light-emitting element 525 Signal Line 526 scan lines 527 Power line 528 Common electrode 801 Transistor 802 Transistors 803 Transistor 804 Transistor 811 Transistors 812 transistors 813 Transistors 814 Transistors 901 RF circuit 902 Analog Baseband Circuit 903 Digital Baseband Circuit 904 Battery 905 Power supply circuit 906 Application Processor 907 CPU 908 DSP 910 Flash Memory 911 Display Controller 912 memory circuit 913 Display 914 Display section 915 Source Driver 916 Gate Driver 917 Audio Circuit 918 Keyboard 919 Touch Sensor 1021 Main Unit 1022 Fixed part 1023 Display section 1024 Operation Buttons 1025 External memory slots 1030 cabinet 1031 Casing 1032 Display Panel 1033 Speakers 1034 Microphone 1035 Operation Keys 1036 Pointing device 1037 Camera Lenses 1038 External connection terminal 1040 solar cells 1041 External memory slots 1050 Television equipment 1051 enclosure 1052 Storage medium playback and recording unit 1053 Display section 1054 External connection terminal 1055 Stand 1056 External memory 1101 Main Unit 1102 enclosure 1103a Display section 1103b Display section 1104 Keyboard Buttons

Claims

[Claim 1] A first conductive layer that functions as the gate electrode of a transistor, A first insulating layer having a region positioned above the first conductive layer, An oxide semiconductor layer having a region positioned in contact with the upper part of the first insulating layer and having a channel formation region for the transistor, A second insulating layer having a region positioned in contact with the above oxide semiconductor layer, A second conductive layer having a region positioned above the second insulating layer and functioning as the source electrode or drain electrode of the transistor, The oxide semiconductor layer comprises a first oxide semiconductor layer and a second oxide semiconductor layer. The second oxide semiconductor layer has a region positioned in contact with the upper part of the first oxide semiconductor layer. The first oxide semiconductor layer and the second oxide semiconductor layer have In-M-Zn oxide (where M is Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf), The atomic ratio of M to In in the second oxide semiconductor layer is higher than the atomic ratio of M to In in the first oxide semiconductor layer. The second insulating layer has a first contact hole, The second oxide semiconductor layer has a second contact hole, The second contact hole overlaps with the first contact hole. The upper surface of the first oxide semiconductor layer has a region that is in contact with the second conductive layer in the region that overlaps with the second contact hole. A semiconductor device wherein the second conductive layer does not have a region in contact with the first insulating layer in a region that overlaps with the second contact hole.

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