Repeated plasma treatment

Abstract

A method for processing a substrate includes performing a repetitive plasma process including a plurality of cycles, each cycle of the plurality of cycles including purging a plasma processing chamber including the substrate with a first deposition gas including carbon. The substrate includes a first layer including silicon and a second layer including a metal oxide. The method further includes exposing the substrate to a first plasma generated from the first deposition gas to selectively deposit a first polymer film on the first layer relative to the second layer, purging the plasma processing chamber with an etching gas including fluorine, and exposing the substrate to a second plasma generated from the etching gas to etch the second layer.

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims the benefit of U.S. Non - Provisional Patent Application No. 17 / 339,495, filed Jun. 4, 2021, which is hereby incorporated by reference in its entirety.

[0002] The present invention generally relates to systems and methods for processing semiconductor devices, and in particular embodiments, to systems and methods for repetitive plasma processing.

Background Art

[0003] Generally, semiconductor devices such as integrated circuits (ICs) are manufactured by sequentially depositing and patterning layers of dielectric, conductive, and semiconductor materials on a substrate to form a network of electronic components and interconnecting elements (e.g., transistors, resistors, capacitors, metal lines, contacts, and vias) integrated in a monolithic structure. The processing flow used to form the constituent structures of a semiconductor device includes depositing and removing various materials. For these purposes, various plasma processes are often used in semiconductor device manufacturing.

[0004] Plasma etching, a type of plasma process, is a common technique for etching a material by exposing it to a plasma of a gas containing charged species, neutral species, or a combination thereof. In plasma etching, the selectivity and directionality (anisotropic or isotropic) of etching are important key characteristics that determine process performance. As new materials and device architectures continue to be introduced through innovation in the semiconductor industry, further development in plasma etching processes is desired, particularly to improve selectivity and directionality to meet the increasing requirements in semiconductor device manufacturing.

Summary of the Invention

Means for Solving the Problems

[0005] A preferred embodiment of the present invention provides a method for processing a substrate, comprising performing a repeating plasma process comprising a plurality of cycles, each cycle comprising: purging a plasma processing chamber containing a substrate with a first deposition gas containing carbon, wherein the substrate comprises a first layer containing silicon and a second layer containing a metal oxide; exposing the substrate to a first plasma generated from the first deposition gas to selectively deposit a first polymer film on the first layer compared to the second layer; purging the plasma processing chamber with an etching gas containing fluorine; and etching the second layer by exposing the substrate to a second plasma generated from the etching gas.

[0006] A preferred embodiment of the present invention provides a method for processing a substrate, comprising performing a repeating plasma process comprising a plurality of cycles, one of which cycles comprises: during a first time interval, applying a first source power to a source electrode of a plasma processing chamber, applying a first bias power to a bias electrode of a plasma processing chamber, and flowing a carbon-containing deposition gas through the plasma processing chamber to selectively deposit a polymer film on a silicon-containing layer compared to a metal oxide layer; during a second time interval, purging the plasma processing chamber with a fluorine-containing etching gas; and during a third time interval, applying a second source power to a source electrode, applying a second bias power to a bias electrode, and flowing an etching gas through the plasma processing chamber to etch the metal oxide layer, wherein the first layer is covered under the polymer film during the third interval.

[0007] A preferred embodiment of the present invention provides a method for processing a substrate, comprising: performing a repeating plasma process comprising a plurality of cycles, each cycle of which involves purging a plasma processing chamber containing a substrate with a deposition gas containing carbon, wherein the substrate comprises a patterned interlayer dielectric (ILD) layer and a hard mask on a metal oxide etch-stop layer (ESL) covering metal wires, the hard mask, the ILD layer and the metal oxide ESL including an outer exposed surface; performing an area-selective plasma deposition process by exposing the substrate to a first plasma generated from the deposition gas to preferentially deposit a polymer film on the hard mask and ILD layer compared to the metal oxide ESL; purging the plasma processing chamber with an etching gas containing fluorine; and performing an etching process by exposing the substrate to a second plasma generated from the etching gas to preferentially etch the metal oxide ESL compared to the hard mask and ILD layer.

[0008] For a more complete understanding of the present invention and its advantages, the following description is to be referenced herein together with the accompanying drawings. [Brief explanation of the drawing]

[0009] [Figure 1A-1M] The figures show cross-sectional views of the substrate at various intermediate stages of manufacturing in a dual damascene wiring (BEOL) process flow undergoing repeated plasma processes (Figures 1G-1I) according to various embodiments. Figure 1A shows the incoming substrate. Figure 1B shows the substrate after trench etching. Figure 1C shows the substrate after trench refilling. Figure 1D shows the substrate after photoresist pattern application. Figure 1E shows the substrate after via etching. Figure 1F shows the substrate after removal of the top barrier layer. Figure 1G shows the substrate after area-selective plasma deposition process. Figure 1H shows the substrate after etching of the etch stop layer (ESL). Figure 1I shows the substrate after completion of repeated plasma processes. Figure 1J shows the substrate after removal of the bottom barrier layer. Figure 1K shows the substrate after diffusion barrier layer deposition. Figure 1L shows the substrate after metal coating. Figure 1M shows the substrate after planarization. [Figure 2A-2E]The images show cross-sectional views of the substrate at various intermediate stages of manufacturing in a dual damascene BEOL processing flow undergoing repeated plasma processes according to an alternative embodiment. Figure 2A shows the incoming substrate. Figure 2B shows the substrate after via etching. Figure 2C shows the substrate after via refilling. Figure 2D shows the substrate after photoresist pattern application. Figure 2E shows the substrate after trench etching. [Figure 3A-3C] Cross-sectional views of substrates undergoing repeated plasma processes according to different embodiments are shown. Figure 3A shows the substrate after a first area-selective plasma deposition process. Figure 3B shows the substrate after a second area-selective plasma deposition process. Figure 3C shows the substrate after etching the etch stop layer (ESL). [Figure 4A] Flowcharts of repeated plasma processes according to various embodiments are shown. Figure 4A shows a repeated plasma process according to the embodiments described in Figures 1G to 1I. [Figure 4B] Figure 4B shows a dual damascene BEOL process including a repeating plasma process (trench-first) according to the exemplary embodiments described in Figures 1A to 1M. [Figure 4C] Figure 4C shows another dual damascene BEOL process, including a repeating plasma process (via-first), according to the alternative embodiments described in Figures 2A-2E and 1F-1M. [Figure 4D] Figure 4D shows a repeatable plasma process according to other alternative embodiments described in Figures 3A to 3C. [Figure 5A] This document describes an embodiment of a repeating plasma process in a plasma processing tool. Figure 5A shows the timing diagram for one cycle of a time-multiplexed embodiment of the repeating plasma process. [Figure 5B] Figure 5B shows a flow diagram of a repeating plasma process according to the embodiment shown in Figure 5A. [Figure 6] Figures 4A-4D and 5A-5B show cross-sectional views of a plasma system for implementing a time-multiplexed embodiment of the repeated plasma etching process shown in the flowcharts. [Figure 7A] Figures 4A-4D and 5A-5B show plasma systems for implementing spatially isolated embodiments of the repeating plasma process shown in the flowcharts. Figure 7A shows a top view. [Figure 7B] Figures 4A-4D and 5A-5B show plasma systems for implementing spatially isolated embodiments of the repeating plasma process shown in the flowcharts. Figure 7B shows a cross-sectional view. [Modes for carrying out the invention]

[0010] This disclosure describes embodiments of a repeating plasma process method for selectively removing metal oxide materials compared to silicon-containing materials or other materials using a fluorine-containing etching gas without causing metal corrosion as seen with corrosive etching gases. As further described below, the repeating plasma process may be used to selectively remove an etch stop layer (ESL) containing a metal oxide, such as aluminum oxide, as part of a damascene wiring (BEOL) process in semiconductor device manufacturing. The embodiments described herein offer the advantage of efficiently removing metal oxide materials while reducing the loss of other materials, such as silicon-containing hard mask materials and interlayer dielectric (ILD) materials, and avoiding metal corrosion. This innovative method achieves this advantage by combining area-selective plasma deposition, which forms a protective layer on silicon-containing materials, with subsequent etching using a fluorine-containing non-corrosive gas to selectively remove a target metal oxide material that has little to no protective layer, as will be described in more detail below. Although this disclosure describes the process in the context of a copper dual damascene process, this repeating plasma process may be applied to other process flows in other structures, as known to those skilled in the art.

[0011] Generally, the dual damascene BEOL process is a crucial step in integrated circuit manufacturing for forming copper (Cu) interconnects. In the dual damascene BEOL process, a first recess, such as a via or trench, is formed and filled with a temporary filler material. Next, a second recess is formed, and then these formed recesses are filled with copper metal, followed by planarization. The process of forming vias and trenches may include the removal of an etch stop layer (ESL). The ESL may be placed between two barrier layers to separate different metal layers. While a stack of these multiple layers is sometimes collectively called an etch stop layer, in this disclosure, these layers are individually referred to as the top barrier layer, the etch stop layer (ESL), and the bottom barrier layer. Conventional ESL materials have been silicon carbide and silicon nitride, but aluminum oxide (Al2O3) may also be preferred for ESLs because of its low dielectric constant (k value of about 4-6 as a thin film) and high density. However, the removal of aluminum oxide ESL is a challenge, and conventional methods for etching aluminum oxide ESL are unsatisfactory. For example, wet etching processes tend to be isotropic, which increases the lower limit dimension and consequently increases the risk of short circuits between vias or between vias and trenches. Dry plasma etching using chlorine-(Cl) or bromine-(Br) containing gases, such as BCl3, HBr, and Cl2, can cause corrosion of metal wires. On the other hand, non-corrosive gases such as carbon fluoride are sometimes used in plasma etching processes, but this can result in low selectivity for ESL etching for hard mask (HM) and interlayer dielectric (ILD) materials. In various embodiments of this disclosure, the method is based on a repeating plasma process comprising an area-selective plasma deposition process and a plasma etching process using one or more fluorine-containing etching gases, which can also advantageously provide better etching selectivity for ESL materials. Such advantages can lead to improved precise control of the limit dimensions of semiconductor devices during manufacturing.

[0012] In various embodiments, a repeated plasma process for selectively removing a metal oxide layer is carried out as part of a dual damascene wiring (BEOL) process in semiconductor manufacturing. While the repeated plasma process of this disclosure may be described as a step in a dual damascene BEOL process, the repeated plasma process may be applied to a single damascene BEOL process or other manufacturing processes.

[0013] First, Figures 1A to 1M show dual damascene BEOL process flows (trench-first) undergoing repeated plasma processes for ESL removal according to various embodiments. Figures 2A to 2E show dual damascene BEOL process flows (via-first) according to alternative embodiments. Furthermore, Figures 3A to 3C show repeated plasma processes having two area-selective plasma deposition process steps according to other alternative embodiments. With respect to different embodiments, several process flows of repeated plasma processes are further described with reference to Figures 4A to 4D. The steps of the repeated plasma process may be separated in time or space. To illustrate temporal / spatial separation, Figure 5A shows a timing diagram of one cycle of an embodiment of time-multiplexing of the repeated plasma process, and Figure 5B shows the corresponding process flowchart. Figure 6 shows an exemplary plasma processing system. Figures 7A and 7B show alternative plasma processing systems and corresponding spatial separation methods.

[0014] Figure 1A shows a cross-sectional view of the incoming substrate 90. In various embodiments, the substrate 90 may be part of a semiconductor device and may have undergone several processing steps following a conventional process, for example. Thus, the substrate 90 may contain semiconductor layers useful in various miniature electronic technologies. For example, the semiconductor structure may include the substrate 90 on which various device regions are formed.

[0015] In one or more embodiments, the substrate 90 may be a silicon wafer or a silicon-on-insulator (SOI) wafer. In certain embodiments, the substrate 90 may include a silicon germanium wafer, a silicon carbide wafer, a gallium arsenide wafer, a gallium nitride wafer, or other compound semiconductors. In other embodiments, the substrate 90 may include hetero layers such as silicon germanium on silicon, gallium nitride on silicon, silicon carbon on silicon, similar to a silicon-on-silicon layer or an SOI substrate. In various embodiments, the substrate 90 is patterned or embedded in other components of the semiconductor device.

[0016] As shown in FIG. 1A, the substrate 90 may further include a metal layer 100 on the substrate. Depending on the embodiment, one or more layers such as a dielectric layer may exist between the substrate 90 and the metal layer 100. In various embodiments, the metal layer 100 may be formed as part of a patterned metal interconnect on the substrate 90. In various embodiments, the metal layer 100 may include copper (Cu), aluminum (Al), doped polycrystalline silicon, tungsten, titanium nitride, tantalum nitride, ruthenium, and other metals. The metal layer 100 may be formed, for example, by deposition using physical vapor deposition (PVD).

[0017] The dielectric layer may be deposited as a bottom barrier layer 115 on the metal layer 100. In certain embodiments, the bottom barrier layer 115 may include a silicon-based dielectric material such as silicon nitride and silicon carbonitride (SiCN). The bottom barrier layer 115 may be deposited using deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), as well as other plasma processes such as plasma CVD (PECVD), sputtering, and other processes.

[0018] As an etch stop layer (ESL) 120 on the bottom cutoff layer 115, another dielectric layer may be further deposited. In various embodiments, the ESL 120 may include aluminum oxide, aluminum nitride, or zirconium oxide. The ESL 120 may be deposited using deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), as well as other plasma processes such as plasma CVD (PECVD), sputtering, and other processes. In certain embodiments, the thickness of the ESL 120 may be between 2 nm and 5 nm.

[0019] Still referring to FIG. 1A, the top cutoff layer 125 may be formed on the ESL 120. In certain embodiments, the top cutoff layer 125 may include a silicon-based dielectric material such as silicon nitride and silicon carbonitride (SiCN). The top cutoff layer 125 may typically be the same material as the bottom cutoff layer 115. The top cutoff layer 125 may be deposited using deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), as well as other plasma processes such as plasma CVD (PECVD), sputtering, and other processes.

[0020] Another dielectric layer may be formed as an interlayer dielectric (ILD) layer 130 on the top cutoff layer 125. The ILD layer 130 may include a silicon-based dielectric material having a low dielectric constant (i.e., a low k value), such as organosilicate glass (SiCOH), high-density SiCOH, porous SiCOH, and other porous dielectric materials. The ILD layer 130 may be deposited using deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), as well as other plasma processes such as plasma CVD (PECVD), sputtering, and other processes.

[0021] As further shown in Figure 1A, the first hard mask 140 may be formed on the interlayer dielectric (ILD) layer 130. In certain embodiments, the first hard mask 140 may contain silicon nitride. In alternative embodiments, the first hard mask 140 may contain silicon dioxide (SiO2) or titanium nitride. Furthermore, the first hard mask 140 may be a laminated hard mask comprising, for example, two or more layers using two different materials. The first layer of the first hard mask 140 may include a metal-based layer such as titanium nitride, titanium, tantalum nitride, tantalum, tungsten-based compounds, ruthenium-based compounds, or aluminum-based compounds, and the second layer of the first hard mask 140 may include a dielectric layer such as silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, amorphous silicon, or polycrystalline silicon. The first hard mask 140 may be deposited using deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), as well as other plasma processes such as plasma CVD (PECVD), sputtering, and other processes.

[0022] The first photoresist 150 may be deposited on the first hard mask 140, for example, using a coating process or a spin-on process. In various embodiments, the first photoresist 150 may contain a photosensitive organic material, which may be applied onto the first hard mask 140 from a solution, for example, by conventional spin-coating techniques. As shown in Figure 1A, the first photoresist 150 may be patterned in a certain pattern using conventional photolithography techniques. In various embodiments, the pattern of the first photoresist 150 may be used for forming a first recess. In a particular embodiment, as shown in Figure 1B, the first pattern may be used for trench formation.

[0023] Figure 1B shows the substrate 90 after trench etching for forming trench features. The first photoresist 150 in Figure 1A acts as a mask layer, and the pattern of the first photoresist 150 is transferred onto it. Trench etching anisotropically removes portions of the first hard mask 140 and interlayer dielectric (ILD) layer 130 that were not masked by the first photoresist 150. As shown in Figure 1B, trench etching may be stopped before the top barrier layer 125 is exposed, leaving space for via formation in a later step. Trench etching may be stopped using an etch stop layer, or in some embodiments, timed etching may be used. In certain embodiments, trench etching includes one or more wet etching processes, plasma etching processes, reactive ion etching (RIE) processes, or a combination of these or other etching processes. The first photoresist 150 remaining after trench etching may be removed from the substrate 90, for example, by conventional plasma ashing techniques.

[0024] Figure 1C shows the substrate 90 after trench refilling and deposition of the second hard mask 142 and the second photoresist 152. In trench refilling, after removing the remaining first hard mask 140, a filler material 160, called a gap filler material or organic bottom anti-reflective coating (BARC), fills the trench features formed in the previous step. The filler material 160 may be spin-coated from a solution of organic solvent. In some embodiments, the filler material 160 may be deposited using other deposition techniques, including vapor deposition. A planarization process, such as a chemical mechanical planarization process, may be used to ensure that the surface of the filler material 160 is coplanar with the main surface of the ILD layer 130.

[0025] Furthermore, still referring to Figure 1C, a second hard mask 142 and a second photoresist 152 are applied for the next step in patterning. The second hard mask 142 may be similar to the first hard mask 140 described previously, but may have a different composition depending on the embodiment. The second hard mask 142 may be deposited using deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), as well as other plasma processes such as plasma CVD (PECVD), sputtering, and other processes. The second photoresist 152 may be similar to the first photoresist 150 described previously, but may have a different composition depending on the embodiment. The second photoresist 152 is applied onto the second hard mask 142 from a solution, for example, by a conventional spin coating technique.

[0026] Figure 1D shows the substrate 90 after the pattern of the second photoresist 152 has been defined by one or more lithography processes. In various embodiments, the pattern of the second photoresist 152 may be used for the formation of a second recess. In certain embodiments, as shown in Figure 1E, the pattern of the second photoresist 152 may be used for via formation.

[0027] Figure 1E shows the substrate 90 after the filler material 160 has been removed following via etching. The second photoresist 152 in Figure 1D acts as a mask layer, and the pattern of the second photoresist 152 is transferred to it. Via etching anisotropically removes portions of the second hard mask 142, filler material 160, and interlayer dielectric (ILD) layer 130 that were not masked by the second photoresist 152. The remaining second photoresist 152 and filler material 160 may be removed, for example, by conventional plasma ashing techniques. This removal step may also remove portions of the second hard mask 142 isolated on the filler material 160. In certain embodiments, the via etching process includes one or more wet etching processes, plasma etching processes, reactive ion etching (RIE) processes, or a combination of these or other etching processes.

[0028] Figure 1F shows the substrate 90 after the removal of the top barrier layer 125 at the bottom of the formed vias. In various embodiments, the removal of the top barrier layer may be performed by an etching process prior to subsequent repeated plasma processes (e.g., Figures 1G to 1I), exposing a portion of the etch stop layer (ESL) 120. In certain embodiments, etching of the top barrier layer 125 includes one or more wet etching processes, plasma etching processes, reactive ion etching (RIE) processes, or a combination of these or other etching processes. In certain embodiments, via etching and etching of the top barrier layer 125 may be performed as a single etching step. In certain embodiments, the repeated plasma processes described below may be performed in such a manner that at least a portion of the objectives of via etching or etching of the top barrier layer 125 are achieved.

[0029] In certain embodiments, before performing repeated plasma processes, an optional pretreatment may be carried out to chemically or physically modify the composition of the surface-terminating groups of layers on the substrate 90 (e.g., the second hard mask 142 and the interlayer dielectric (ILD) layer 130 in Figure 1F) in order to improve the selectivity of subsequent repeated plasma processes. For example, the optional pretreatment may be a plasma treatment using a hydrogen-containing reducing agent. In one embodiment, a plasma treatment using molecular hydrogen (H2) may be carried out.

[0030] Figure 1G shows the substrate 90 after an area-selective plasma deposition process for forming a polymer film 165. Formation of the polymer film 165 is the first plasma step of a repeating plasma process in various embodiments. In various embodiments, the polymer film 165 may be selectively formed on the second hard mask 142 and the interlayer dielectric (ILD) layer 130 compared to the ESL 120 by exposing the substrate 90 to a plasma of deposition gas. In various embodiments, the deposition rate on the second hard mask 142 or the interlayer dielectric (ILD) layer 130 compared to the ESL 120 may be 5:1 to 1000:1, and as a result, little or no polymer film may be formed on the ESL 120. Thus, the polymer film 165 is much thicker on the second hard mask 142 or the interlayer dielectric (ILD) layer 130 than on the ESL 120.

[0031] In various embodiments, the deposition gas comprises a mixture of a polymer film precursor containing carbon and a diluent. For example, in various embodiments, the polymer film precursor is an alkane. In certain embodiments, the deposition gas is a mixture of methane (CH4) and argon (Ar) in any ratio. In some embodiments, the deposition gas may further contain hydrogen (H2) or nitrogen (N2). In some embodiments, the deposition gas may further contain ethane, ethylene, and other hydrocarbons.

[0032] In one embodiment, the area-selective plasma deposition process may be carried out using a mixed gas of CH4 and Ar at a process temperature between 20°C and 120°C, and the polymer film 165 is preferentially formed on an interlayer dielectric (ILD) layer 130 and a second hard mask 142 containing silicon-containing materials such as silicon nitride, silicon oxide, and organosilicate glass (SiCOH), compared with an etch-stop layer (ESL) 120 containing aluminum oxide. The silicon oxide may be prepared, for example, by plasma CVD or fluid CVD using tetraethyl orthosilicate (TEOS) as a precursor. In a different embodiment, the polymer film 165 may be preferentially formed on a second hard mask 142 containing titanium nitride, compared with an ESL 120 containing aluminum oxide.

[0033] Figure 1H shows the substrate 90 after etching of the ESL120 using a fluorine-containing gas in the second plasma step of a repeating plasma process. While the exposed portions of the ESL120 are anisotropically etched, the polymer film 165 formed by the first plasma step (area-selective plasma deposition process) in the steps prior to Figure 1G above acts as a protective layer for the second hard mask 142 and the ILD layer 130. A thicker polymer film 165 formed on the second hard mask 142 or the interlayer dielectric (ILD) layer 130 protects the underlying material from etching and allows the use of non-selective or less selective etching solutions. If a polymer film 165 is present on the ESL120, this polymer film 165 is thinner and will be etched first, followed by the etched exposed ESL120.

[0034] In various embodiments, the fluorine-containing etching gas may include a gas that is not corrosive to metals, including copper. In various embodiments, the fluorine-containing gas may not contain chlorine or bromine and may not cause metal corrosion of metal wires over long periods. This is different from chlorine or bromine-containing gases, which can cause copper corrosion and lead to product failure during the product's lifespan.

[0035] In various embodiments, the fluorine-containing etching gas includes tetrafluoromethane (CF4), nitrogen trifluoride (NF3), fluoroform (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), and combinations thereof. The fluorine-containing etching gas may be selected to be free from sulfur, which can cause metal corrosion of metal wires, as well as chlorine or bromine as described above. In certain embodiments, the etching gas further contains oxygen (O2) in any proportion. In one or more embodiments, the etching gas further contains 0.1% to 10% by volume of oxygen. The etching gas may further contain diluents such as argon (Ar) and nitrogen (N2) in any proportion. In various embodiments, area-selective plasma deposition (first plasma step) and subsequent etching plasma processes (second plasma step) are repeated to achieve selective ESL removal of a target amount. Various embodiments of the repeated plasma processes are further described with reference to Figures 4A to 4D.

[0036] In certain embodiments, an etching plasma process (second plasma step) preferentially removes the aluminum oxide-containing ESL 120 over the second hard mask 142 protected by a polymer film and the interlayer dielectric (ILD) layer 130 containing silicon-containing materials such as silicon nitride, silicon oxide, and organosilicate glass (SiCOH), using a tetrafluoromethane (CF4) plasma at a process temperature between 60°C and 120°C. In different embodiments, the aluminum oxide-containing ESL 120 may be preferentially etched over the second hard mask 142 protected by a polymer film containing titanium nitride.

[0037] Figure 1I shows the substrate 90 after the completion of the repeated plasma process. According to various embodiments, the portion of the ESL 120 corresponding to the pattern of the second photoresist 152 as defined in Figure 1D is removed, and vias are extended to the bottom barrier layer 115. In the embodiment shown in Figure 1I, the process parameters of the repeated plasma process may be optimized to completely remove not only the ESL 120 but also the polymer film 165 from the second hard mask 142 and the ILD layer 130.

[0038] In various embodiments, after repeated plasma processes, further steps of a dual damascene wiring (BEOL) process may be performed to form metal interconnects. Figure 1J shows the substrate 90 after etching to remove a portion of the bottom barrier layer 115, exposing a portion of the metal layer 100 according to the pattern of formed vias. In certain embodiments, etching of the bottom barrier layer 115 includes one or more wet etching processes, plasma etching processes, reactive ion etching (RIE) processes, or a combination of these or other etching processes. In certain embodiments, at least a portion of the etching of the bottom barrier layer 115, or any other subsequent steps of the dual damascene BEOL process, may be integrated as part of the repeated plasma processes described above.

[0039] Figure 1K shows the substrate 90 after the deposition of the diffusion barrier layer 170. In certain embodiments, the diffusion barrier layer 170 may contain tantalum, tantalum nitride, titanium, or titanium nitride. The diffusion barrier layer is intended to prevent the metal in the metal layer 100 from diffusing to other components during manufacturing. The diffusion barrier layer 170 may be deposited using deposition techniques such as sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), as well as other plasma processes such as plasma CVD (PECVD) and other processes.

[0040] Figure 1L shows the substrate 90 after metal deposition. Metal deposition may be carried out by electroplating following the deposition of a seed layer of metal (e.g., copper) using sputtering or physical vapor deposition (PVD) techniques. In this step of metal deposition, vias and trenches are filled with metal. As shown in Figure 1L, in various embodiments, the same metal as the metal layer 100 may typically be used for metal deposition.

[0041] Finally, Figure 1M shows the substrate 90 after planarization, where excess metal has been removed, for example, by chemical mechanical planarization (CMP).

[0042] In the exemplary embodiments shown in Figures 1A to 1M, trench etching (Figure 1B) is performed before via etching (Figure 1E). This sequence is called trench-first. However, in other embodiments, via etching may be performed before trench etching (via-first), as shown below in Figures 2A to 2E.

[0043] In Figure 2A, the incoming substrate 90 has a structure similar to the previous (trench-first) embodiment described above, and comprises a laminate including a metal layer 100, a bottom barrier layer 115, an etch-stop layer (ESL) 120, a top barrier layer 125, and an interlayer dielectric (ILD) layer 130. A first hard mask 240 is formed on the ILD layer 130. A first photoresist 250 may be formed on the first hard mask 240 with a via etching pattern similar to the pattern in Figure 1D. The first hard mask 240 and the first photoresist 250 may be similar to the first hard mask 140 and the first photoresist 150 in Figure 1A, respectively, but depending on the embodiment, they may have different compositions.

[0044] Figure 2B shows the substrate 90 after via etching. The first photoresist 250 in Figure 2A functions as a mask layer, and the pattern of the first photoresist 250 is transferred onto it. As previously described with previous embodiments, via etching can be performed using a suitable etching process to anisotropically remove portions of the first hard mask 240 and interlayer dielectric (ILD) layer 130 that were not masked by the first photoresist 250, exposing the top barrier layer 125 at the bottom of the formed vias.

[0045] Figure 2C shows the substrate 90 after via refilling and deposition of the second hard mask 242 and the second photoresist 252. In via refilling, after removing the remaining first hard mask 240, the filler material 260 fills the via features formed in the previous step. The filler material 260 may be similar to the filler material 160, but may have a different composition depending on the embodiment. The filler material 260 may be spin-coated from a solution of an organic solvent. Depending on the embodiment, the filler material 260 may be deposited using other deposition techniques, including vapor deposition. A planarization process, such as a chemical mechanical planarization process, may be used to ensure that the surface of the filler material 260 is coplanar with the main surface of the ILD layer 130.

[0046] Furthermore, in Figure 2C, similar to Figure 1C, a second hard mask 242 and a second photoresist 252 are formed on the ILD layer 130 and the filler material 260. The second hard mask 242 and the second photoresist 252 may be similar to the first hard mask 240 and the first photoresist 250, respectively, but they may have different compositions. The second hard mask 242 may be deposited using a suitable deposition technique, similar to the second hard mask 142 in Figure 1C. The second photoresist 252 may be coated onto the second hard mask 242 from a solution, for example, by a conventional spin coating technique.

[0047] Figure 2D shows the substrate 90 after the pattern of the second photoresist 252 has been defined by one or more lithography processes. The pattern of the second photoresist 252 may be used for trench formation.

[0048] Figure 2E shows the substrate 90 after trench etching. The patterned second photoresist 252 in Figure 2D acts as a mask layer, and the pattern of the second photoresist 252 is transferred to it. As previously described with previous embodiments, trench etching may be performed using a suitable etching process to anisotropically remove portions of the second hard mask 242, filler material 260, and interlayer dielectric (ILD) layer 130 that were not masked by the second photoresist 252. As shown in Figure 2E, trench etching may be performed to completely remove the filler material 260 and expose the top barrier layer at the bottom of the via, but may be stopped before the portions of the ILD layer 130 that were not masked by the second photoresist 252 are completely removed. Trench etching may be stopped using an etch stop layer, but depending on the embodiment, timed etching may be used. The remaining second photoresist 252 may be removed, for example, by conventional plasma ashing techniques. At this stage, the substrate 90 has a structure with trenches and via features similar to the structure shown in Figure 1E formed by the trench-first embodiment.

[0049] Subsequently, the removal of the top barrier layer 125, repeated plasma processes, and subsequent processes may be carried out in the same manner as in the previous embodiments (for example, in the same manner as in Figures 1F, 1G to 1I, and 1J to 1M, respectively).

[0050] While previous embodiments have been described as part of a dual damascene wiring (BEOL) process, the iterative plasma process of this disclosure is not limited to a dual damascene BEOL process and may be applied to other manufacturing processes to selectively remove a particular material (e.g., aluminum oxide) by using one or more protective layers selectively formed on another material (e.g., silicon-containing material). In one embodiment, the iterative plasma process may be applied to a single damascene BEOL process. In one cycle of a single damascene BEOL process, only one recess, such as a trench or via, may be formed instead of the two recesses in a dual damascene BEOL process. For example, iterative plasma etching may be performed after via formation (e.g., Figure 2B).

[0051] In various embodiments, the repeated plasma process may include two separate area-selective plasma deposition process steps. In this embodiment, selective etching of the target material from a surface containing more than two materials may be improved. The formation of trenches and vias prior to the repeated plasma process may be carried out by a trench-first method (e.g., Figures 1A-1E) or a via-first method (e.g., Figures 2A-2E), yielding the same structure as shown in Figure 1F. The subsequent repeated plasma process steps according to these embodiments are shown in Figures 3A-3C.

[0052] Figure 3A shows the substrate 90 after a first area-selective plasma deposition process (first plasma step) using a first deposition gas. The first deposition gas may be the same as the deposition gas previously described with reference to Figure 1G. As shown, the first polymer film 360 may be preferentially formed on the second hard mask 142 compared to the interlayer dielectric (ILD) layer 130 and the etch stop layer (ESL) 120. The first polymer film 360 may have a similar composition to the polymer film 165 described above and may be formed in a similar manner. At this stage, for example, the composition of the first deposition gas and other process parameters may be selected to achieve a high deposition rate and / or selectivity with respect to the second hard mask 142.

[0053] Next, Figure 3B shows the substrate 90 after a second area-selective plasma deposition process (second plasma step) using a second deposition gas. A second polymer film 362, having a different composition from the first polymer film 360, may be preferentially formed on the ILD layer 130 compared to the second hard mask 142 and ESL 120. The first polymer film 360, the second polymer film 362, or both, may have a composition similar to the polymer film 165. In one embodiment, the first and second polymer films 360 and 362 may have the same composition but may be formed at different rates by selecting different process parameters for the first and second plasma steps. The second deposition gas may be similar to the deposition gas previously described with reference to Figure 1G. For example, the second deposition gas includes a mixture of a second polymer film precursor containing carbon and a diluent. In certain embodiments, the second polymer film precursor is an alkane. In certain embodiments, the deposition gas is a mixture of methane (CH4) and argon (Ar) in any ratio. In some embodiments, the deposition gas may further contain hydrogen (H2) or nitrogen (N2). The second deposition gas may be the same as or different from the first deposition gas of the first area-selective plasma deposition process. The composition of the second deposition gas and other process parameters may be selected to achieve a high deposition rate and / or selectivity with respect to the interlayer dielectric (ILD) layer 130.

[0054] In one embodiment, the process parameters of the first plasma step may be optimized for the formation of a first polymer film 360 on a hard mask containing silicon, while the process parameters of the second plasma step may be optimized for the formation of a second polymer film 362 on an ILD layer 130 containing a low-k dielectric such as SiCOH, and both states are still more selective than an etch stop layer (ESL) 120 containing aluminum oxide.

[0055] Figure 3C shows the substrate 90 after etching of ESL120 using a fluorine-containing gas in the third plasma step of the repeated plasma process. As previously described in Figure 1H, the exposed portions of ESL120 are etched anisotropically. The first and second polymer films 360 and 362 formed by the first and second area-selective plasma deposition process steps (first and second plasma steps) described above function as protective layers to protect the second hard mask 142 and the ILD layer 130, respectively.

[0056] The embodiments described above (for example, Figures 3A to 3C) include two area-selective plasma deposition process steps, but in alternative embodiments, the repeated plasma process may include any number of area-selective plasma deposition process steps and one or more etching processes.

[0057] In the following, Figures 4A to 4D show process flowcharts of the repeating plasma process corresponding to the embodiments described above, with Figure 4A corresponding to Figures 1G to 1I, Figure 4B corresponding to Figures 1A to 1M, Figure 4C corresponding to Figures 2A to 2E and Figures 1F to 1M, and Figure 4D corresponding to Figures 3A to 3C.

[0058] In various embodiments, for example, all steps of the repeating plasma process, corresponding to Figures 1G to 1I, may be carried out inside the plasma processing tool.

[0059] Figure 4A shows process flows of a repeating plasma process according to various embodiments. The repeating plasma process (block 450A) includes the following four main steps: purging the plasma processing chamber of the plasma processing tool with a carbon-containing deposition gas (block 451); exposing the substrate to plasma generated from the deposition gas (block 452) (e.g., Figure 1G); purging the plasma processing chamber with a fluorine-containing etching gas (block 455); and exposing the substrate to plasma of the etching gas (block 456) (e.g., Figure 1H). Each step of the repeating plasma process may be temporally or spatially separated. In certain embodiments, the repeating plasma process may be carried out within a single compartment of the plasma processing chamber by a time-multiplexing process as detailed in Figures 5 and 6. In other embodiments, as shown with reference to Figures 7A and 7B, the repeating plasma process may be carried out within multiple separate compartments of the plasma processing chamber, and the substrate may be transported from one compartment to another to proceed to the next step.

[0060] In block 451, as the first step of a repeating plasma process, the plasma processing chamber is purged with a carbon-containing deposition gas such as methane (CH4), and the substrate temperature may be brought to equilibrium at a certain process temperature. In various embodiments, the substrate temperature may be raised, for example, by a heater and cooled by water cooling or liquid helium cooling, which are controlled by a temperature controller.

[0061] Secondly, in block 452, the first plasma step of a repeating plasma process (area-selective plasma deposition) is carried out by a plasma deposition tool such as a plasma chemical vapor deposition (PECVD) tool (e.g., Figure 1G). By supplying plasma source energy from one or more plasma power sources, a plasma of deposition gas is generated in the plasma processing chamber, and the substrate is exposed to this plasma of deposition gas. Precursor species of the polymer film 165 can be energized by the plasma to form radicals. These radicals may be adsorbed on the surface and react randomly with each other in the plasma polymerization process to form the polymer film 165 (e.g., Figure 1G). Differences in the amount of adsorption between different materials result in different plasma polymerization rates, which can lead to different film growth rates. Therefore, area-selective formation of the polymer film can be achieved by optimizing process parameters such as source power, bias power, gas flow rate, process pressure, process temperature, process time, and gas composition.

[0062] Next, in block 235, after terminating the first plasma step by turning off the plasma source power, the plasma processing chamber is purged with an etching gas containing fluorine. In various embodiments, the substrate temperature may be maintained at the same temperature as in the first plasma step, or it may be at an equilibrium temperature at a different process temperature. In various embodiments, the substrate temperature may be raised, for example, by a heater and cooled by water cooling or liquid helium cooling, which are controlled by a temperature controller.

[0063] In block 456, a second plasma step is performed to etch the metal oxide (e.g., ESL120 in Figure 1H). As shown in Figure 1H, the polymer film 165 may also be partially or completely removed during this step. Plasma of etching gas is generated in the plasma processing chamber, and the substrate is exposed to this plasma of etching gas. In certain embodiments, the polymer film 165 and ESL120, which includes aluminum oxide, are etched anisotropically, while other materials (e.g., the second hard mask 142 and interlayer dielectric (ILD) layer 130 in Figure 1H) are protected.

[0064] In some conventional methods, plasma etching using non-corrosive gases tends to lead to non-selective etching. A common condition for removing metal oxide materials such as aluminum oxide is that other materials, such as silicon-containing materials which may be used as hard masks and interlayer dielectric (ILD) layers, are often damaged. However, in the methods of embodiments of the present disclosure, such damage may be advantageously minimized or completely eliminated thanks to the presence of a polymer film formed on such materials during area-selective deposition in the first plasma step. Process parameters such as source power, bias power, gas flow rate, process pressure, process temperature, process time, and gas composition can be optimized to effectively etch the target metal oxide material while simultaneously achieving removal of the polymer film.

[0065] In certain embodiments, the plasma treatment chamber may be evacuated to a vacuum before either of the purging steps (e.g., blocks 451 and 455). Furthermore, depending on the embodiment, one or more additional treatment steps may be inserted between the steps. The additional treatment may be a thermal treatment under vacuum, a wet process, a plasma treatment similar to the pretreatment (block 445), or another process.

[0066] In various embodiments, this cycle of four steps (blocks 451, 452, 455, and 456) may be repeated to achieve the desired process performance. The cycle may begin at any of these four steps.

[0067] In Figure 4B, according to a particular embodiment, a repeating plasma process may be used to selectively remove the etch stop layer (ESL) from the substrate as part of a dual damascene wiring process (BEOL) using a trench-first method (e.g., Figures 1A-1M).

[0068] The substrate may have undergone various manufacturing steps and may have a layered structure including a first hard mask 140 and a first photoresist 150 (block 400) (e.g., Figure 1A). First, trench etching (block 410) (e.g., Figure 1B) is performed to form trench features as described above. Next, trench refilling, deposition of a second hard mask 142 and a second photoresist 152, and patterning of the second photoresist 152 are performed (block 420) (e.g., Figures 1C and 1D). Subsequently, via etching is performed (block 430) (e.g., Figure 1E). Next, the top barrier layer 125 may be optionally removed (block 440) (e.g., Figure 1F). In some embodiments, this step of removing the top barrier layer 125 may be integrated into a subsequent repeated plasma process (block 450B) (e.g., Figures 1G to 1I). Furthermore, to enhance the selectivity of subsequent repeated plasma processes, an optional pretreatment (block 445) may be performed to chemically or physically modify the composition of the surface-terminating groups of the layers present on the substrate 90 (e.g., the second hard mask 142 and the interlayer dielectric (ILD) layer 130 in Figure 1F). Next, repeated plasma processes (block 450B) (e.g., Figures 1G to 1I) may be performed as described above with reference to block 450A in Figure 4A.

[0069] Still referring to Figure 4B, after the completion of the repeated plasma process (block 450B), the bottom barrier layer 115 may be optionally removed (block 460) (e.g., Figure 1J). Depending on the embodiment, this step of removing the bottom barrier layer 115 may be integrated into the previous repeated plasma process (block 450B) (e.g., Figures 1G to 1I). Subsequently, the diffusion barrier layer 170 is deposited, metal deposition and planarization are carried out to complete the metal interconnect formation cycle (block 470) (e.g., Figures 1K to 1M).

[0070] Figure 4C shows an exemplary process flowchart of a dual damascene routing (BEOL) process using a via-first method according to an alternative embodiment (e.g., Figures 2A-2E and 1F-1M).

[0071] Similar to previous embodiments using the trench-first method, the substrate may have undergone various manufacturing steps and may have a layered structure including a first hard mask 240 and a first photoresist 250 (block 402) (e.g., Figure 2A). First, via etching (block 402) (e.g., Figure 2B) is performed to form via features as described above. Next, via refilling, deposition of a second hard mask 242 and a second photoresist 252, and patterning of the second photoresist 252 are performed (block 422) (e.g., Figures 2C and 2D). Then, trench etching is performed (block 432) (e.g., Figure 2E). The subsequent process may be similar to the process flow of the previously described trench-first embodiments (e.g., Figures 1F-1M and 4B). The top barrier layer 125 may be optionally removed (block 442) (e.g., Figure 1F), but in some embodiments, this step of removing the top barrier layer 125 may be integrated into a subsequent iterative plasma process (block 450B) (e.g., Figures 1G to 1I). Furthermore, to increase the selectivity of subsequent iterative plasma processes, an optional pretreatment (block 447) may be performed to chemically or physically modify the composition of the surface-terminating groups of layers present on the substrate 90 (e.g., the second hard mask 142 and the interlayer dielectric (ILD) layer 130 in Figure 1F). The iterative plasma process (block 450C) and subsequent processes may be similar to those in the earlier embodiments described above (e.g., blocks 450B, 460, and 470 in Figure 4B). After the completion of the repeated plasma process (block 450C), the bottom barrier layer 115 may be optionally removed (block 462) (e.g., Figure 1J), but in some embodiments, this step of removing the bottom barrier layer 115 may be integrated into the previous repeated plasma process (block 450C) (e.g., Figures 1G to 1I). Finally, deposition of the diffusion barrier layer 170, metal deposition, and planarization are carried out (block 472) (e.g., Figures 1K to 1M).

[0072] Figure 4D shows an exemplary process flowchart of a repeating plasma process including two area-selective plasma deposition process steps and one etching process, according to different embodiments (e.g., Figures 3A-3C). As mentioned above, in certain embodiments, a repeating plasma process including two area-selective plasma deposition process steps may be used to enable two optimized states for plasma deposition of two polymer films on two different materials compared to the target etching material.

[0073] In these embodiments, the iterative plasma process may include six steps. In addition to the four steps previously described (for example, blocks 451, 452, 455, and 456 in Figures 4A to 4C), a purging step using a second deposition gas (block 453) and an area-selective plasma deposition process using a second deposition gas (block 454) are inserted after the first area-selective plasma deposition step (block 452).

[0074] In this disclosure, details of repeatable plasma processes and alternative embodiments will focus on four main steps, namely two purging steps and area-selective plasma deposition and etching (e.g., block 450A in Figure 4A). However, it is assumed that such details may be applicable to repeatable plasma processes including any number of plasma deposition and etching steps (e.g., block 450D as an example having two deposition process steps and one etching process).

[0075] Figure 5A shows a timing diagram of four steps in one cycle of a time-multiplexed embodiment of a repeating plasma process, such as the flow chart in Figure 4A. The six horizontal axes in Figure 5A represent the progression of time. The four time intervals T1, T2, T3, and T4 for the four steps in one cycle of the repeating plasma etching process 230 are schematically shown by four double arrows adjacent to a single time axis. Referring to Figure 4A, T1, T2, T3, and T4 correspond to purging with deposition gas (block 451), area-selective plasma deposition process (block 452), purging with etching gas (block 455), and plasma etching (block 456), respectively. Four vertical dotted lines intersecting the time axis define the boundaries of the non-overlapping time intervals T1, T2, T3, and T4. In certain embodiments, T1 may be approximately 5 to 60 seconds, T2 approximately 1 to 5 seconds, T3 approximately 5 to 60 seconds, and T4 approximately 1 to 5 seconds. The durations of the time intervals T1, T2, T3, and T4 do not have to be equal, according to the respective process recipe. The six time axes are used to schematically plot the relationship between six process parameters and time for one cycle of multiple cycles of an exemplary repeating plasma etching process 450A, as shown in Figure 4A. The six process parameters plotted in Figure 5A are source power, bias power, process pressure, deposition gas flow rate, etching gas flow rate, and dilution gas flow rate.

[0076] Although not specifically shown in Figure 5A, other arbitrary process parameters, such as temperature, may be controlled independently at each step of the repeating plasma process, according to each process recipe. In certain embodiments, the time intervals T1 and T3 may be adjusted to stabilize the process temperature between T2 and T4, respectively.

[0077] In various embodiments, the substrate is maintained at a temperature between 5°C and 120°C. In some embodiments, the temperature may change in each step of the repeated plasma process, and a purge step is used to stabilize the system before generating the plasma. In alternative embodiments, the temperature may be programmed to rise or cool during the plasma steps, i.e., time intervals T2 and T4.

[0078] During the time interval T1 shown in Figure 5A, while the source power and bias power are off, the deposition gas is introduced to purge the plasma processing chamber. In certain embodiments, a diluent gas is also optionally used. In various embodiments, the total gas flow rate may be between 20 and 1000 sccm. The process pressure may be between 5 and 100 mTorr. In some embodiments, the CH4 / Ar gas flow rate is 30 / 150 sccm and the process pressure is 10 mTorr.

[0079] Switching from time interval T1 to the next time interval T2 for area-selective plasma deposition is performed by turning on source power and bias power. In this step, a radical-rich environment is desirable for polymer film formation. A sufficiently high source power may be applied to achieve a radical-rich environment. In various embodiments, the source power may be between 50W and 1000W, and the bias power may be between 0W and 200W. The total gas flow rate may be between 20 and 1000 sccm. The process pressure may be between 5 and 100 mTorr. In one embodiment, the source power is 500W and the bias power is 100W. The CH4 / Ar gas flow rate is 30 / 150 sccm. The process pressure is 10 mTorr. In certain embodiments, the gas flow rate of the diluent gas may vary between T1 and T2.

[0080] Next, time interval T3 is initiated by turning off the source power and bias power. Simultaneously, the gas flow is also switched from the deposition gas to the etching gas to purge the plasma processing chamber. The gas flow rate is selected independently of the states at T1 and T2. In various embodiments, the total gas flow rate may be between 20 and 1000 sccm. The process pressure may be between 5 and 100 mTorr. In some embodiments, the CF4 / CHF3 / Ar gas flow rates are 60 / 60 / 520 sccm and the process pressure is 10 mTorr.

[0081] After the plasma processing chamber has been purged using etching gas, a time interval T4 is initiated by turning on the source power and bias power, releasing the etching gas and generating plasma. In this etching step, it is important to achieve conditions for anisotropic etching, such that the material at the bottom of the via is sufficiently etched while causing little to no damage to the sidewalls. For anisotropic etching conditions, a relatively higher bias power is desirable compared to the deposition step. In various embodiments, the source power may be between 10 and 1000 W, and the bias power may be between 50 and 500 W. The total gas flow rate may be between 20 and 1000 sccm. The process pressure may be between 5 and 100 mTorr. In one embodiment, the source power is 50 W and the bias power is 600 W. The CF4 / CHF3 / Ar gas flow rate is 60 / 60 / 520 sccm, and the process pressure is 10 mTorr.

[0082] After time interval T4, the next cycle of four time intervals may be performed. This cycle may be repeated any number of times to achieve the desired process performance. Figure 5A shows a single set of states for one cycle of a repeating plasma process, but in various embodiments, each cycle may have different process parameter states than the first cycle, and the process parameters may include any of the time intervals (T1, T2, T3, and T4), gas flow rate, gas composition, process pressure, process temperature, source power, and bias power.

[0083] Furthermore, it should be noted that the plots in Figure 5A are for illustrative purposes only. For example, these plots show how process parameters change as a step function, but it should be understood that instantaneous changes in process parameters are not feasible, and that a finite response time until the physical parameters stabilize should be taken into account. Moreover, as mentioned above, one or more additional treatment steps, such as vacuum evacuation, thermal treatment under vacuum, wet processing, plasma treatment, etc., may be inserted after any of the time intervals (T1, T2, T3, and T4).

[0084] Figure 5B shows a flow diagram of a repeating plasma process according to the embodiment of Figure 5A. In the first time interval (T1) (block 510), the source power and bias power are turned off if they are on, and a deposition gas containing carbon and diluent gas is introduced into the plasma processing chamber containing the substrate at a first gas flow rate, and the plasma processing chamber is purged. In the second time interval (T2) (block 520), source power is applied at a first level to form a plasma of deposition gas, and the substrate is exposed to this plasma of deposition gas. In the third time interval (T3) (block 530), the source power, the first bias power, and the deposition gas are turned off, and an etching gas containing tetrafluoromethane (CF4), nitrogen trifluoride (NF3), fluoroform (CHF3), difluoromethane (CH2F2), or fluoromethane (CH3F), and diluent gas is introduced into the plasma chamber at a second gas flow rate, and the plasma processing chamber is purged. Finally, in the fourth time interval (T4) (block 540), source power is applied at a second level to form an etching gas plasma, and the substrate is exposed to this etching gas plasma.

[0085] Figure 6 shows a plasma system 600 for implementing a time-multiplexed embodiment of a repeating plasma etching process, for example, as shown in the flow diagrams of Figures 4A to 4C. The plasma system 600 has a plasma processing chamber 650 configured to maintain plasma directly above a substrate 602 loaded on a substrate holder 610. Process gas may be introduced into the plasma processing chamber 650 through a gas inlet 622 and pumped out of the plasma processing chamber 650 through a gas outlet 624. The gas inlet 622 and gas outlet 624 may each include a set of multiple gas inlets and gas outlets. Gas flow rate and chamber pressure may be controlled by a gas flow control system 620 coupled to the gas inlet 622 and gas outlet 624. The gas flow control system 620 may include various components such as a high-pressure gas canister, valves (e.g., throttle valves), pressure sensors, gas flow sensors, a vacuum pump, pipes, and an electronically programmable controller. RF bias power supplies 634 and RF source power supplies 630 may be coupled to the respective electrodes of the plasma processing chamber 650. The substrate holder 610 may also be an electrode coupled to the RF bias power supply 634. The RF source power supply 630 is shown coupled to a helical electrode 632 wound around the dielectric sidewall 616. In Figure 6, the gas inlet 622 is an opening in the upper plate 612, and the gas outlet 624 is an opening in the bottom plate 614. The upper plate 612 and the bottom plate 614 may be conductive and may be electrically connected to the system ground (reference potential).

[0086] Plasma system 600 is merely an example. In various alternative embodiments, plasma system 600 may be configured to maintain inductively coupled plasma (ICP) using RF source power coupled to a planar coil on an upper dielectric cover, or capacitively coupled plasma (CCP) maintained using a disc-shaped upper electrode within a plasma processing chamber 650. Gas inlets and outlets may be coupled to the side walls of the plasma processing chamber, and in some embodiments, pulsed RF power supplies and pulsed DC power supplies may also be used.

[0087] Figures 7A and 7B show a plasma system 700 for carrying out a spatially isolated embodiment of a repeating plasma process, with Figure 7A being a top view and Figure 7B being a cross-sectional view. In the plasma system 700, the four components of each cycle may be carried out within four spatially isolated compartments of a spatial plasma processing chamber 740. For example, the four components of each cycle of a repeating plasma etching process may be carried out by moving a substrate through the four spatially isolated compartments of the spatial plasma processing chamber 740 using a rotatable stage 710.

[0088] In the top view shown in Figure 7A, the rotatable stage 710 is separated into four sections: a first purge section 745, a first plasma section 750, a second purge section 755, and a second plasma section 760. These four sections may be separated, for example, by an inert gas curtain 730. Each section may have one or more gas inlets and gas outlets. In Figure 7A, the first plasma section 750 has a gas inlet 752 and a gas outlet 724, the second plasma section 760 has a gas inlet 723 and a gas outlet 725, and the two purge sections 745 and 755 have a gas inlet 720 and a gas outlet 726. Purge using a deposition gas (block 451 in Figures 4A to 4D) may be performed in the first purging section 745, area-selective plasma deposition (block 452 in Figures 4A to 4D) may be performed in the first plasma section 750, purging using an etching gas (block 455 in Figures 4A to 4D) may be performed in the second purging section 755, and plasma etching (block 456 in Figures 4A to 4D) may be performed in the second plasma section 760.

[0089] For example, as shown in Figure 7A, multiple substrates may be loaded onto the rotatable stage 710. A first substrate 702, shown loaded onto the rotatable stage 710 within a first plasma compartment 750, may undergo one deposition step of one cycle of a repeating plasma etching process, and then be moved to a second purge compartment 755, followed by the next plasma etching step. Simultaneously, another substrate 704, after its plasma etching step, returns to the first purge compartment 745, followed by the next plasma deposition step of the cycle. Thus, multiple substrates may simultaneously undergo different steps of the repeating plasma process. One rotation of the rotatable stage 710 is equivalent to performing one cycle of the repeating plasma etching process.

[0090] In the cross-sectional view shown in Figure 7B, plasma compartments 750 and 760 are visible. In the exemplary spatial plasma processing chamber 740, plasma compartments 750 and 760 are configured to maintain a capacitively coupled plasma (CCP) using an upper electrode 712 coupled to an RF power supply 714. In the exemplary embodiment shown in Figure 7B, a rotatable stage 710 is electrically coupled to ground. The grounded rotatable stage 710 may also function as a bottom electrode. Gas outlets 724, 725, and 726 are connected to a vacuum pump of the gas flow system and may be controlled to maintain a desired pressure and gas flow rate in the corresponding compartments. One of the inert gas curtains 730 is schematically shown by a dashed line. The inert curtain 730 may be a flow of an inert gas (e.g., argon or helium) introduced through one of the gas inlets 720.

[0091] Herein, exemplary embodiments of the present invention are summarized. Other embodiments will also be understood from the entirety of this specification and the claims filed herein. [Examples]

[0092] Example 1. A method for processing a substrate, comprising performing a repeating plasma process comprising a plurality of cycles, each cycle comprising purging a plasma processing chamber containing a substrate with a first deposition gas containing carbon, wherein the substrate comprises a first layer containing silicon and a second layer containing a metal oxide, exposing the substrate to a first plasma generated from the first deposition gas to selectively deposit a first polymer film on the first layer compared to the second layer, purging the plasma processing chamber with an etching gas containing fluorine, and etching the second layer by exposing the substrate to a second plasma generated from the etching gas.

[0093] Example 2. The method according to Example 1, wherein the substrate includes a third layer containing silicon and oxygen, the third layer being made of a different material from the first layer, and the first polymer film is selectively deposited on the third layer compared to the second layer while the substrate is exposed to a first plasma.

[0094] Example 3. The method according to either Example 1 or 2, further comprising exposing a substrate to a third plasma generated from a second depositing gas containing carbon to selectively deposit a second polymer film on the third layer compared to the second layer.

[0095] Example 4. The method according to any one of Examples 1 to 3, further comprising performing a pretreatment step before the repeated plasma process to change the composition of the surface-terminating groups of the first or second layer.

[0096] Example 5. The method according to any one of Examples 1 to 4, wherein the exposure of the substrate to the deposition gas plasma and the exposure of the substrate to the etching gas plasma are temporally separated by time-multiplexed processing within a fixed zone of the plasma processing chamber.

[0097] Example 6. The method according to any one of Examples 1 to 5, wherein the substrate is exposed to a deposition gas plasma and the substrate is exposed to an etching gas plasma, which are spatially separated within multiple separate compartments of a plasma processing chamber.

[0098] Example 7. The method according to any one of Examples 1 to 6, wherein the first layer comprises silicon nitride or silicon dioxide and the second layer comprises aluminum oxide.

[0099] Example 8. The method according to any one of Examples 1 to 7, further comprising: maintaining the substrate at a first temperature while it is exposed to a first plasma; and maintaining the substrate at a second temperature while it is exposed to a second plasma, wherein the second temperature is different from the first temperature.

[0100] Example 9. The method according to any one of Examples 1 to 8, wherein the first deposition gas contains methane (CH4) and the etching gas contains tetrafluoromethane (CF4), nitrogen trifluoride (NF3), fluoroform (CHF3), difluoromethane (CH2F2), or fluoromethane (CH3F).

[0101] Example 10. The method according to any one of Examples 1 to 9, wherein the first deposit gas further comprises a mixture containing hydrogen (H2), argon (Ar), or nitrogen (N2).

[0102] Example 11. A method for processing a substrate, comprising performing a repeating plasma process comprising a plurality of cycles, one of which cycles comprises: applying a first source power to the source electrode of a plasma processing chamber, applying a first bias power to the bias electrode of a plasma processing chamber, and flowing a carbon-containing deposition gas into the plasma processing chamber to selectively deposit a polymer film on a silicon-containing layer compared to a metal oxide layer during a first time interval; purging the plasma processing chamber with a fluorine-containing etching gas during a second time interval; and etching the metal oxide layer during a third time interval by applying a second source power to the source electrode, applying a second bias power to the bias electrode, and flowing an etching gas into the plasma processing chamber, wherein the first layer is covered under the polymer film during the third interval.

[0103] Example 12. The method according to Example 11, wherein one of the cycles further includes purging the plasma processing chamber with a deposit gas during a fourth time interval.

[0104] Example 13. The method according to either Example 11 or 12, wherein the first source power is higher than the second source power, and the second bias power is higher than the first bias power.

[0105] Example 14. The method according to any one of Examples 11 to 13, wherein one of the multiple cycles further comprises flowing a diluent gas through a plasma processing chamber over first, second, and third time intervals, the flow rate of the diluent gas being higher during the second interval than during the first interval.

[0106] Example 15. The method according to any one of Examples 11 to 14, wherein the depositing gas contains hydrocarbons, the diluent gas contains argon, and the etching gas contains tetrafluoromethane (CF4), nitrogen trifluoride (NF3), fluoroform (CHF3), difluoromethane (CH2F2), or fluoromethane (CH3F).

[0107] Example 16. The method according to any one of Examples 11 to 15, wherein the metal oxide layer contains aluminum oxide.

[0108] Example 17. The method according to any one of Examples 11-16, wherein the third time interval is selected to completely remove the polymer film.

[0109] Example 18. A method for processing a substrate, comprising: performing a repeating plasma process comprising a plurality of cycles, each cycle comprising purging a plasma processing chamber containing a substrate with a carbon-containing deposition gas, wherein the substrate comprises a patterned interlayer dielectric (ILD) layer and a hard mask on a metal oxide etch-stop layer (ESL) covering metal wires, the hard mask, the ILD layer and the metal oxide ESL including an outer exposed surface; performing an area-selective plasma deposition process by exposing the substrate to a first plasma generated from the deposition gas to preferentially deposit a polymer film on the hard mask and ILD layer compared to the metal oxide ESL; purging the plasma processing chamber with a fluorine-containing etching gas; and performing an etching process by exposing the substrate to a second plasma generated from the etching gas to preferentially etch the metal oxide ESL compared to the hard mask and ILD layer.

[0110] Example 19. The method according to Example 18, wherein the metal oxide ESL contains aluminum oxide, the deposit gas contains methane, and the etching gas contains tetrafluoromethane (CF4), nitrogen trifluoride (NF3), fluoroform (CHF3), difluoromethane (CH2F2), or fluoromethane (CH3F).

[0111] Example 20. The method according to either Example 18 or 19, wherein the repeated plasma process is part of a dual damascene process.

[0112] While the present invention has been described with reference to exemplary embodiments, this specification is not intended to be constrained. Those skilled in the art will see by reference to this specification various modifications and combinations of those exemplary embodiments, as well as other embodiments of the present invention. Accordingly, the appended claims are intended to encompass all such modifications or embodiments.

Claims

1. A method for processing a substrate, The method includes the step of performing a repetitive plasma process that includes multiple cycles, Each of the aforementioned plurality of cycles is: A step of purging a plasma processing chamber containing the substrate with a first deposition gas containing methane, ethane, or ethylene, wherein the substrate comprises a silicon-containing hard mask layer and a metal oxide layer, the silicon-containing hard mask layer having a first outer surface, and the metal oxide layer having a second outer surface, The steps include: exposing the first and second outer surfaces to a first plasma generated from the first deposition gas, and selectively depositing a first polymer film on the silicon-containing hard mask layer relative to the metal oxide layer; The step of stopping the first plasma exposure step and purging the plasma processing chamber with an etching gas containing fluorine, A step of exposing the substrate to a second plasma generated from the etching gas and etching the metal oxide layer, wherein the first polymer film prevents the silicon-containing hard mask layer from being etched by the second plasma, A method having

2. The substrate has a third layer containing silicon and oxygen, the third layer has a third outer surface exposed to the first plasma, and the third layer is made of a different material from the silicon-containing hard mask layer. The method according to claim 1, wherein the first polymer film is selectively deposited on the third layer relative to the metal oxide layer during the step of exposing the substrate to the first plasma.

3. The method according to claim 2, further comprising the step of exposing the substrate to a third plasma generated from a second deposition gas containing carbon, and selectively depositing a second polymer film on the third layer relative to the metal oxide layer.

4. The method according to claim 1, further comprising a pretreatment step of performing a pretreatment step before the repeated plasma process to modify the composition of the surface termination groups of the silicon-containing hard mask layer or the metal oxide layer.

5. The method according to claim 1, wherein the steps of exposing the substrate to the first plasma of the first deposition gas and exposing the substrate to the second plasma of the etching gas are performed in a fixed zone of the plasma processing chamber and are separated in time.

6. The method according to claim 1, wherein the steps of exposing the substrate to the first plasma of the first deposition gas and exposing the substrate to the second plasma of the etching gas are spatially separated in an isolated compartment of the plasma processing chamber.

7. The method according to claim 1, wherein the silicon-containing hard mask layer comprises silicon nitride or silicon dioxide, and the metal oxide layer comprises aluminum oxide.

8. moreover, During the step of exposing the substrate to the first plasma, the step of maintaining the substrate at a first temperature, The step of exposing the substrate to the second plasma, and the step of maintaining the substrate at a second temperature, wherein the second temperature is different from the first temperature, The method according to claim 1, comprising:

9. The first deposit gas contains methane (CH4), The method according to claim 1, wherein the etching gas comprises tetrafluoromethane (CF4), nitrogen trifluoride (NF3), fluoroform (CHF3), difluoromethane (CH2F2), or fluoromethane (CH3F).

10. The method according to claim 1, wherein the first deposit gas further comprises a mixture containing hydrogen (H2), argon (Ar), or nitrogen (N2).

11. A method for processing a substrate, The method comprises the step of performing a repetitive plasma process to selectively etch the metal oxide layer of the substrate, wherein the substrate has a silicon-containing layer, and the repetitive plasma process comprises a plurality of cycles. One of the aforementioned multiple cycles is The steps include applying a first source power to the source electrode of the plasma processing chamber, applying a first bias power to the bias electrode of the plasma processing chamber, and flowing a deposition gas containing methane, ethane, or ethylene through the plasma processing chamber to selectively deposit a polymer film on the silicon-containing layer onto the metal oxide layer, during a first time interval. During the second time interval, the steps of flowing the deposit gas and applying the first source power and the first bias power are stopped, and the plasma processing chamber is purged using an etching gas containing fluorine. The steps include applying a second source power to the source electrode and a second bias power to the bias electrode during a third time interval, flowing the etching gas through the plasma processing chamber, and etching the metal oxide layer, wherein the silicon-containing layer is covered on the underside of the polymer film during the third time interval. A method having

12. The method according to claim 11, wherein the first source power is higher than the second source power, and the second bias power is higher than the first bias power.

13. Each of the plurality of cycles further comprises the step of flowing a diluent gas through the plasma processing chamber over the first, second, and third time intervals, The method according to claim 11, wherein the flow rate of the dilution gas is higher during the second time interval than during the first time interval.

14. The method according to claim 11, wherein the deposition gas comprises argon, and the etching gas comprises tetrafluoromethane (CF4), nitrogen trifluoride (NF3), fluoroform (CHF3), difluoromethane (CH2F2), or fluoromethane (CH3F).

15. The method according to claim 11, wherein the metal oxide layer comprises aluminum oxide.

16. The method according to claim 11, wherein the third time interval is selected to completely remove the polymer film.

17. A method for processing a substrate, The method includes the step of performing a repetitive plasma process that includes multiple cycles, Each of the aforementioned plurality of cycles is: A step of purging a plasma processing chamber containing the substrate with a deposition gas containing fluorine-free hydrocarbons, wherein the substrate has a hard mask and an interlayer dielectric (ILD) layer, the ILD layer is patterned on top of a metal oxide etch stop layer (ESL) covering a metal wire, and the hard mask, the ILD layer, and the metal oxide ESL include an outer exposed surface, The steps include: exposing the substrate to a first plasma generated from the deposition gas, and performing an area-selective plasma deposition process by preferentially depositing a polymer film on the metal oxide ESL on the hard mask and the ILD layer; After the step of carrying out the area-selective plasma deposition process, the plasma processing chamber is purged using an etching gas containing fluorine. The step of purging the plasma processing chamber, followed by the step of exposing the substrate to a second plasma generated from the etching gas, and performing an etching process by preferentially etching the metal oxide ESL against the hard mask and the ILD layer, A method having

18. The method according to claim 17, wherein the metal oxide ESL comprises aluminum oxide, the deposit gas comprises methane, and the etching gas comprises tetrafluoromethane (CF4), nitrogen trifluoride (NF3), fluoroform (CHF3), difluoromethane (CH2F2), or fluoromethane (CH3F).

19. The method according to claim 1, wherein the first and second outer surfaces are parallel to each other.

20. The cycle of the plurality of cycles further, The method according to claim 11, further comprising the step of purging the plasma processing chamber with the deposit gas during a fourth time interval.

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