Indication device

Abstract

To improve luminance of a display device.SOLUTION: A display device comprises: a first nitride insulating film provided on a first substrate; a gate electrode provided on the first nitride insulating film; a second nitride insulating film provided on the gate electrode; a first oxide insulating film provided on the second nitride insulating film; and an oxide semiconductor layer provided on the first oxide insulating film. The gate electrode is formed by successively laminating a first titanium layer, an aluminum layer and a second titanium layer in this order from a first nitride insulating film side, and the thickness of the second titanium layer is larger than thickness of the first titanium layer.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, progress has been made in the development of transparent displays that allow the background of one side to be seen from the other side (see Patent Document 1). With a transparent display, images can be viewed from both the front and back sides, so images or text can be seen from two opposing directions with the transparent display in between.

[0003] In display devices such as transparent displays, it is preferable to use low-resistance wiring materials to reduce the wiring resistance of gate wiring and source wiring. By using low-resistance wiring materials such as aluminum and copper, signal delay can be reduced. On the other hand, aluminum has low heat resistance, and it is known that migration can cause irregularities on the wiring surface. Therefore, aluminum migration is suppressed by laminating a metal material with a higher melting point than aluminum, such as titanium, molybdenum, or tungsten, on top of the aluminum. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-160254 [Patent Document 2] International Publication No. 2018 / 130920 [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] When using a wiring material with low heat resistance, such as aluminum, to form a laminated wiring structure, etching residue may occur on the sides of the wiring. If such etching residue occurs on the sides of the wiring, it may obstruct light guidance in a display device, potentially reducing brightness.

[0006] One embodiment of the present invention aims to improve the brightness of a display device. [Means for solving the problem]

[0007] A display device according to one embodiment of the present invention includes a first nitride insulating film provided on a first substrate, a gate electrode provided on the first nitride insulating film, a second nitride insulating film provided on the gate electrode, a first oxide insulating film provided on the second nitride insulating film, and an oxide semiconductor layer provided on the first oxide insulating film, wherein the gate electrode is constructed by stacking a first titanium layer, an aluminum layer, and a second titanium layer in order from the first nitride insulating film side, and the thickness of the second titanium layer is greater than the thickness of the first titanium layer. [Brief explanation of the drawing]

[0008] [Figure 1] This is a perspective view illustrating the overview of a display device according to one embodiment of the present invention. [Figure 2] This is a schematic cross-sectional view showing the structure corresponding to the area between A1 and A2 of the display device shown in Figure 1. [Figure 3] This is a plan view illustrating the configuration of a display device according to one embodiment of the present invention. [Figure 4] This is a cross-sectional view of a pixel in a display device according to one embodiment of the present invention. [Figure 5] This is a block diagram representing pixels in a display device according to one embodiment of the present invention. [Figure 6] This is a timing chart of pixels in a display device according to one embodiment of the present invention. [Figure 7] This is a planar layout of pixels in a display device according to one embodiment of the present invention. [Figure 8] It is the planar layout of pixels in a display device according to an embodiment of the present invention. [Figure 9] It is the planar layout of pixels in a display device according to an embodiment of the present invention. [Figure 10] It is the planar layout of pixels in a display device according to an embodiment of the present invention. [Figure 11] It is the planar layout of pixels in a display device according to an embodiment of the present invention. [Figure 12] SEM photographs of the surface unevenness and the shape of the ends of the gate electrodes were observed for each of Samples A to I. [Figure 13] SEM photographs of the surface unevenness and the shape of the ends of the gate electrodes were observed for each of Samples J to M. [Figure 14] It is a model diagram of the optical simulation in this example. [Figure 15] It is an xy chromaticity diagram obtained by the optical simulation in this example. [Figure 16] It is an xy chromaticity diagram obtained by the optical simulation in this example. [Figure 17] It is an xy chromaticity diagram obtained by the optical simulation in this example. [Figure 18] It is an xy chromaticity diagram obtained by the optical simulation in this example. [Figure 19] It is an xy chromaticity diagram obtained by the optical simulation in this example. [Figure 20] It is an xy chromaticity diagram obtained by the optical simulation in this example. [Figure 21] It is an xy chromaticity diagram obtained by the optical simulation in this example. [Figure 22] It is an xy chromaticity diagram obtained by the optical simulation in this example. [Figure 23] It is an xy chromaticity diagram obtained by the optical simulation in this example. [Figure 24]This is the xy chromaticity diagram obtained by the optical simulation in this embodiment. [Figure 25] This is the xy chromaticity diagram obtained by the optical simulation in this embodiment. [Modes for carrying out the invention]

[0009] The embodiments of the present invention will be described below with reference to the drawings, etc. However, the present invention can be implemented in various forms without departing from its gist, and is not to be interpreted as being limited to the embodiments described below. Furthermore, in order to clarify the explanation with respect to the drawings, the width, thickness, shape, etc. of each part may be schematically represented compared to the actual embodiment, but these schematic figures are just examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, the same or similar reference numerals are used for elements that have been described with respect to previously shown figures, and redundant explanations may be omitted. In this specification, etc., ordinal numbers are assigned for convenience to distinguish parts, parts, etc., and do not indicate priority or order.

[0010] In this invention, when multiple films are formed by processing a single film, these multiple films may have different functions and roles. However, these multiple films originate from a film formed as the same layer in the same process, and have the same layer structure and the same material. Therefore, these multiple films are defined as existing in the same layer. Furthermore, when multiple films are formed by processing a single film, they may be described separately as -1, -2, etc. in this specification.

[0011] In this specification, expressions such as "above" and "below" describe the relative positional relationship between the structure of interest and other structures. In this specification, in a side view, the direction from the first substrate (described later) toward the pixel electrode is defined as "above," and the opposite direction is defined as "below." In this specification and the claims, when describing a manner in which one structure is placed on top of another structure, unless otherwise specified, the expression "above" includes both cases: when one structure is placed directly above another structure so as to be in contact with it, and when another structure is placed above another structure via yet another structure.

[0012] Furthermore, in this specification, bottom gate drive refers to a system where the on / off state is controlled by a gate electrode located below the semiconductor layer. Furthermore, in this specification, top gate drive refers to a system where the on / off state is controlled by a gate electrode located above the semiconductor layer. Furthermore, in this specification, dual gate drive refers to a system where the on / off state is controlled by inputting the same control signal to gate electrodes located above and below the semiconductor layer.

[0013] (First Embodiment) A display device 10 according to one embodiment of the present invention will be described with reference to Figures 1 to 11.

[0014] <Overview of the display device> Figure 1 shows a perspective view of a display device 10 according to one embodiment of the present invention. The display device 10 includes a display panel 102 which includes an array substrate 150, a counter substrate 152, a liquid crystal layer (not shown) between the array substrate 150 and the counter substrate 152, a gate drive circuit 28, a source drive circuit 38, a light source 104, and a first transparent substrate 151A and a second transparent substrate 151B which sandwich the display panel 102. In the following description with reference to Figure 1, one direction of the plane in the display panel 102 is referred to as the D1 direction, the direction perpendicular to the D1 direction is referred to as the D2 direction, and the direction perpendicular to the D1-D2 plane is referred to as the D3 direction.

[0015] The array substrate 150 and the opposing substrate 152 are light-transmitting. Preferably, the array substrate 150 and the opposing substrate 152 are transparent to visible light. The opposing substrate 152 is positioned in the D3 direction so as to face the array substrate 150. The array substrate 150 and the opposing substrate 152 are bonded together by a sealing material 154 while facing each other with a gap between them. A liquid crystal layer (not shown) is provided in the gap between the array substrate 150 and the opposing substrate 152.

[0016] The display panel 102 has a display area 12 and a peripheral area 14 outside the display area 12. Multiple pixels PIX are arranged in the row direction and column direction in the display area 12. Here, the row direction refers to the direction parallel to the D1 direction, and the column direction refers to the direction parallel to the D2 direction. In the display area 12, m pixels are arranged in the row direction and n pixels are arranged in the column direction. The values ​​of m and n are set appropriately according to the vertical display resolution and the horizontal display resolution. Gate wiring (also called scan signal lines) is arranged in the D1 direction in the display area 12, and source wiring (also called data signal lines) is arranged in the D2 direction.

[0017] A gate drive circuit 28 and a source drive circuit 38 are provided in the peripheral region 14 of the array substrate 150. Figure 1 shows an embodiment in which the gate drive circuit 28 and the source drive circuit 38 are provided as integrated circuits (ICs) and mounted on the array substrate 150 using the COG (Chip on Glass) method. The gate drive circuit 28 and the source drive circuit 38 are not limited to the embodiment shown, and may be mounted using the COF (Chip on Film) method, or may be formed by thin-film transistors (TFTs) on the array substrate 150.

[0018] The peripheral region 14 includes a gate wiring region 32, a common wiring region 22, and a source wiring region 42. The gate wiring region 32 is a region where a pattern is formed by wiring connecting the gate drive circuit 28 and the gate wiring GL arranged in the display region 12. The common wiring region 22 is a region where a pattern is formed by common wiring. Circuit-wise, the common wiring region 22 is used as wiring to apply a common voltage to the common electrode 218 (see Figure 4) provided on the opposing substrate 152. The source wiring region 42 is a region where a pattern is formed by wiring connecting the source drive circuit 38 and the data signal line 109 arranged in the display region 12.

[0019] The light source 104 has a structure aligned along the D1 direction. The light source 104 is composed of, for example, light-emitting diodes (LEDs) arranged along the D1 direction. The detailed structure of the light source 104 is not limited, and in addition to light-emitting diodes arranged along the D1 direction, optical components such as reflectors, diffusers, and lenses may be included. The light source 104 and the light emission control circuit 110 that controls the light source 104 may be provided as separate components independent of the display panel 102. Furthermore, the timing of light emission of the light source 104 may be controlled by the light emission control circuit 110 which is synchronized with the gate drive circuit 28 and the source drive circuit 38. The light emission control circuit 110 that controls the light source 104 may be provided as a separate component, like the light source 104, separate from the display panel 102, or it may be mounted on the array substrate 150 as an individual component, or it may be incorporated into the gate drive circuit 28 or the source drive circuit 38.

[0020] The first transparent substrate 151A and the second transparent substrate 151B are provided so as to sandwich the display area 12 and the peripheral area 14. The first transparent substrate 151A and the second transparent substrate 151B function as protective members for the display panel 102. Furthermore, as will be explained with reference to Figure 2, the first transparent substrate 151A and the second transparent substrate 151B also function as light guide plates that introduce light emitted from the light source 104 into the display panel 102.

[0021] Figure 2 shows the cross-sectional structure of the display device 10 corresponding to the area between A1 and A2 shown in Figure 1. As shown in Figure 2, a first transparent substrate 151A is provided on the array substrate 150 side of the display panel 102, and a second transparent substrate 151B is provided on the opposing substrate 152 side. The first transparent substrate 151A and the second transparent substrate 151B are made of glass or plastic. Preferably, the first transparent substrate 151A and the second transparent substrate 151B have the same refractive index as the array substrate 150 and the opposing substrate 152. The array substrate 150 and the first transparent substrate 151A, and the opposing substrate 152 and the second transparent substrate 151B are bonded together with a transparent adhesive (not shown).

[0022] The display panel 102 is arranged with an array substrate 150 and a counter substrate 152 facing each other, with a liquid crystal layer 210 provided between them. The array substrate 150 is larger than the counter substrate 152, and is sized such that a portion of the peripheral region 14 is exposed from the counter substrate 152. A drive circuit (source drive circuit 38 in Figure 2) is mounted on the array substrate 150. A flexible wiring board 124 is attached to the periphery of the array substrate 150.

[0023] The light source 104 is positioned adjacent to one side of either the first transparent substrate 151A or the second transparent substrate 151B. Figure 2 shows a configuration in which the light source 104 is positioned along one side of the second transparent substrate 151B. Figure 2 also shows a configuration in which the light source 104 is mounted on the array substrate 150, but there are no limitations on the configuration in which the light source 104 is positioned, and there are no limitations on the mounting structure as long as the mounting position can be fixed. The light source 104 may be supported, for example, by a housing surrounding the display panel 102.

[0024] As shown in Figure 2, the light source 104 is positioned along the first side surface 15C of the second transparent substrate 151B. As shown in Figure 2, the light source 104 irradiates light L onto the first side surface 15C of the second transparent substrate 151B. The light source 104 is sometimes called a side light source because it emits light L toward the first side surface 15C. The first side surface 15C of the second transparent substrate 151B facing the light source 104 becomes the light incident surface.

[0025] As schematically shown in Figure 2, light L incident on the first side surface 15C of the second transparent substrate 151B propagates in the direction away from the first side surface 15C (direction D2) while being reflected by the second plane 15B of the opposing substrate 152 and the first plane 15A of the first transparent substrate 151A. When light L moves outward from the first plane 15A of the first transparent substrate 151A and the second plane 15B of the second transparent substrate 151B, it moves from a medium with a high refractive index to a medium with a low refractive index. At this time, if the angle of incidence of light L incident on the first plane 15A and the second plane 15B is greater than the critical angle, total internal reflection occurs, and the light is guided in the direction D2 while being reflected by the first plane 15A and the second plane 15B.

[0026] The liquid crystal layer 210 is formed of polymer-dispersed liquid crystal. The liquid crystal layer 210, formed of polymer-dispersed liquid crystal, is controlled to have a scattering state and a non-scattering state for each pixel PIX (see Figure 1). As shown in Figure 2, when light L propagates while reflecting off the first plane 15A and the second plane 15B, if there is a pixel in the liquid crystal layer 210 that is in a scattering state, at least a portion of the light is scattered, and the incident angle of the scattered light becomes smaller than the critical angle, causing the scattered light LA ​​and LB to be emitted to the outside from the first plane 15A and the second plane 15B, respectively, and the emitted scattered light LA ​​and LB are observed by the observer. In the display panel 102, the areas other than those from which the scattered light LA ​​and LB are emitted are substantially transparent because the array substrate 150 and the opposing substrate 152, as well as the first transparent substrate 151A and the second transparent substrate 151B, are light-transmitting (transparent to visible light), and the liquid crystal layer 210 is in a non-scattering state, allowing the observer to see the back side through the display panel 102.

[0027] Figure 3 is a plan view illustrating the configuration of the array substrate 150 of a display device 10 according to one embodiment of the present invention. As shown in Figure 3, the array substrate 150 includes a display area 12 and a peripheral area 14.

[0028] The display area 12 has multiple pixels PIX arranged in a matrix. Each of the multiple pixels PIX has multiple transistors and liquid crystal elements.

[0029] The peripheral region 14 is provided so as to surround the display region 12. The peripheral region 14 refers to the area on the array substrate 150 from the display region 12 to the edge of the array substrate 150. In other words, the peripheral region 14 refers to the area on the array substrate 150 other than the area on which the display region 12 is provided (i.e., the area outside the display region 12).

[0030] In addition to the gate drive circuit 28 and source drive circuit 38, the peripheral region 14 is provided with a gate wiring region 32, a source wiring region 42, common wiring 16, 18, common wiring region 22, terminal sections 26, 36, flexible printed circuits 24, 34, and various test circuits. The terminal sections 26, 36 are arranged along one side of the array substrate 150.

[0031] A flexible printed circuit board 24 is connected to the terminal section 26. The flexible printed circuit board 24 supplies various signals to the gate drive circuit 28, common wiring 16, 18, ESD protection circuit 59, and QD pad 56. The gate drive circuit 28 is connected to multiple gate wiring GLs, and each of the multiple gate wiring GLs is electrically connected to each of the multiple pixels PIX in the display area 12. In Figure 3, the area where multiple gate wiring GLs are provided is represented as the gate wiring area 32, and the detailed arrangement of the multiple gate wiring GLs is not shown. The number of gate wiring GLs connected to the two gate drive circuits 28 corresponds to the number of rows of pixels PIX in the display area 12. In Figure 3, the gate wiring area 32 is shown to be spaced apart from the display area 12, but in reality, the gate wiring GLs and pixels PIX are electrically connected.

[0032] A flexible printed circuit 34 is connected to the terminal section 36. The flexible printed circuit 34 supplies a video signal to the source drive circuit 38. The source drive circuit 38 is connected to a plurality of source wirings SL, and each of the plurality of source wirings SL is electrically connected to each of the plurality of pixels PIX in the display area 12. In Figure 3, the area where the plurality of source wirings SL are provided is represented as the source wiring area 42, and the detailed arrangement of the plurality of source wirings SL is not shown. The number of source wirings SL connected to the eight source drive circuits 38 corresponds to at least three times the number of rows of pixels PIX in the display area 12. In this embodiment, the case where the number of source wirings SL is four times the number of rows of pixels PIX in the display area 12 will be described. Note that in Figure 3, the source wiring area 42 is shown to be provided separately from the display area 12, but in reality, the source wirings SL and pixels PIX are electrically connected.

[0033] Between the gate wiring area 32 and the display area 12, a common wiring 18, an ESD protection circuit 46, a gate inspection circuit 48, and an inspection line 54 are provided. Between the source wiring area 42 and the display area 12, a common wiring 18, an ESD protection circuit 46, a source inspection circuit 52, and an inspection line 54 are provided. The inspection line 54 is connected to the ESD protection circuit 58 and the QD pad 56. The common wiring 18 is also connected to the ESD protection circuit 59.

[0034] The common wiring 16 is provided so as to surround the peripheral region 14 on the array substrate 150, and signals are supplied from the two flexible printed circuits 24. The common wiring 16 is also electrically connected to the mesh-like common wiring region 22.

[0035] <Cross-sectional structure of pixels> Referring to Figure 4, the configuration of the display device 10 according to one embodiment of the present invention will be described. Figure 4 is a cross-sectional view of a pixel PIX in the display device 10 according to one embodiment of the present invention.

[0036] As shown in Figure 4, a transistor Tr is provided on the array substrate 150. The transistor Tr has a conductive layer 202-1 provided on the array substrate 150, an oxide semiconductor layer 204-1 provided opposite to the conductive layer 202-1, a gate insulating film 203 provided between the conductive layer 202-1 and the oxide semiconductor layer 204-1, and conductive layers 206-3 and 206-4 provided on the oxide semiconductor layer 204-1. Here, the conductive layer 202-1 functions as a gate trace GL (gate electrode), and the conductive layer 206-4 functions as a source trace SL (source electrode). In this embodiment, an example in which a bottom-gate type transistor is used as the transistor Tr will be described.

[0037] When the display device 10 is applied to a large or high-resolution panel, it is preferable to use wiring materials with low resistance in order to reduce the wiring resistance of gate wiring GL and source wiring SL. By using materials such as aluminum or copper as low-resistance wiring materials, signal delay can be reduced. On the other hand, aluminum has low heat resistance and is known to cause unevenness on the wiring surface due to migration. Therefore, aluminum migration is suppressed by laminating a metal material with a higher melting point than aluminum, such as titanium, molybdenum, or tungsten, on top of the aluminum.

[0038] For example, when depositing a thick layer of titanium onto aluminum, the titanium grows in a columnar shape during the deposition process. If a resist mask is formed on this titanium and etching is performed, the titanium will be etched in a columnar shape along the edges of the resist mask. Furthermore, this columnar etched titanium acts as a mask, causing the aluminum to be etched in a columnar shape as well. As a result, etching residue is generated on the sides of the wiring.

[0039] As explained in Figure 2, in a transparent display, light emitted from the light source 104 is incident on the first side surface 15C of the second transparent substrate 151B, and guided in the direction D2 through repeated total internal reflection. Therefore, if there are irregularities on the surface of the gate wiring GL and source wiring SL, or if etching residue is present on the side surface, it will hinder light guidance and may reduce brightness.

[0040] Furthermore, a translucent oxide semiconductor is used as the semiconductor layer for the transistor Tr that constitutes the transparent display. Oxide semiconductors have the property of easily generating oxygen vacancies during the film formation process. By bringing the oxide semiconductor layer and the oxide insulating film into contact, oxygen is released from the silicon oxide film during the heat treatment in the manufacturing process of the display panel 102, and the oxygen vacancies can be repaired by the oxygen. It is preferable to use, for example, a silicon oxide film as the oxide insulating film that is in contact with the oxide semiconductor layer.

[0041] In bottom-gate transistors, when a silicon oxide film is used as the gate insulating film, the silicon oxide film may come into contact with the array substrate. However, there is a risk that impurity elements contained in the array substrate may reach the oxide semiconductor layer through the silicon oxide film. When a silicon nitride film and a silicon oxide film are stacked from the gate electrode side as the gate insulating film, the contact between the silicon nitride film and the array substrate can block the impurity elements contained in the array substrate.

[0042] Thus, when a silicon nitride film and a silicon oxide film are stacked as a gate insulating film, the difference in refractive index between the silicon nitride film and the silicon oxide film causes a problem in which the chromaticity of the transparent display becomes large.

[0043] In one embodiment of the present invention, a nitride insulating film 201 (also called the first nitride insulating film) that functions as a base film is laminated with a first titanium layer 202a-1, an aluminum layer 202b-1, and a second titanium layer 202c-1 as a conductive layer 202-1 (gate electrode). In this case, it is preferable that the film thickness of the second titanium layer 202c-1 be greater than the film thickness of the first titanium layer 202a-1.

[0044] By laminating a first titanium layer 202a-1, an aluminum layer 202b-1, and a second titanium layer 202c-1 on a nitride insulating film 201, surface irregularities of the gate electrode can be reduced. In this case, the thickness of the second titanium layer 202c-1 is preferably 5 to 10 times the thickness of the first titanium layer 202a-1. The thickness of the first titanium layer 202a-1 is, for example, 10 nm to 25 nm. The thickness of the second titanium layer 202c-1 is, for example, 50 nm to 250 nm, preferably 50 nm to 150 nm, and more preferably 50 nm to 100 nm. The thickness of the aluminum layer 202b-1 is, for example, 100 nm to 700 nm.

[0045] Furthermore, it is preferable that the first titanium layer 202a-1 is in contact with the nitride insulating film 201. When an oxide insulating film is used as the underlayer, the surface irregularities of the gate electrode are not improved.

[0046] In contrast, by providing the first titanium layer 202a-1 in contact with the nitride insulating film 201, surface irregularities of the gate electrode (conductive layer 202) can be reduced. Furthermore, the nitride insulating film 201 is preferable because it can block impurities from the array substrate 150.

[0047] The nitride insulating film 201 is in contact with the nitride insulating film 203a (also called the second nitride insulating film), and the total film thickness of nitride insulating film 201 and nitride insulating film 203a is between 600 nm and 1000 nm. By setting the film thickness of nitride insulating film 201 and nitride insulating film 203a in this way, variations in the chromaticity of the display device 10 can be suppressed.

[0048] Since the nitride insulating film 203a is used as part of the gate insulating film 203, there are limitations on the range of its film thickness. For example, the film thickness of the nitride insulating film 203a is preferably 200 nm or more and 400 nm or less. In this case, the film thickness of the nitride insulating film 201 is 200 nm or more and 800 nm or less. Since the nitride insulating film 201 is provided below the conductive layer 202-1 (gate electrode), it does not affect the characteristics of the transistor Tr. Therefore, the film thickness of the nitride insulating film 201 can be set appropriately according to the film thickness of the nitride insulating film 203a. The film thickness of the nitride insulating film 201 may be greater than or less than the film thickness of the nitride insulating film 203a.

[0049] The nitride insulating film 203a and the oxide insulating film 203b function as the gate insulating film 203. In this case, the thickness of the gate insulating film 203 is preferably, for example, 300 nm or more and 700 nm or less.

[0050] An insulating film 205 is provided on top of the transistor Tr. The insulating film 205 functions as a passivation film. The insulating film 205 has an oxide insulating film 205a and a nitride insulating film 205b. By sandwiching the oxide semiconductor layer 204-1 between the oxide insulating film 205a and the oxide insulating film 203b, oxygen is released from the oxide insulating film 203b and the oxide insulating film 205a during the process. This is preferable because it can repair oxygen vacancies in the oxide semiconductor layer 204-1. In addition, a conductive layer 208-1 is provided on top of the insulating film 205 at a position opposite to the oxide semiconductor layer 204-1. The conductive layer 208-1 functions as a back gate electrode. In this embodiment, the transistor Tr is described as a bottom gate driven transistor, but it is not limited to this, and may be a top gate driven transistor or a dual gate driven transistor.

[0051] A planarization film 207 is provided on the conductive layer 208-1 and the insulating film 205. The planarization film 207 is provided to alleviate the irregularities of the various wirings that constitute the transistor Tr. When the display device 10 is applied to a transparent display, it is preferable to remove the planarization film 207 in the aperture region of the pixel PIX. This makes it possible to suppress light absorption by the planarization film 207 in the aperture region.

[0052] A transparent conductive layer 212 is provided on the planarization film 207 and the insulating film 205. A conductive layer 214 is provided on the transparent conductive layer 212. The transparent conductive layer 212 and the conductive layer 214 function as capacitive wiring. An insulating film 209 is provided on the transparent conductive layer 212 and the conductive layer 214. A pixel electrode 216 is provided on the insulating film 209. The pixel electrode 216 is connected to the conductive layer 206-3 through openings provided in the insulating films 205 and 209.

[0053] A counter substrate 152 is provided opposite the array substrate 150. The counter substrate 152 is provided with a light-shielding layer 219 and a common electrode 218. The light-shielding layer 219 functions as a black matrix. In the structure shown in Figure 4, the light-shielding layer 219 is provided in the region overlapping with the conductive layer 206-4. The light-shielding layer 219 is arranged in a grid pattern so as to cover the gate wiring GL and the source wiring SL1 to SL4 shown in Figure 7. The common electrode 218 is large enough to cover the entire surface of the display area 12. The light-shielding layer 219 may be formed of a metal film and functions as an auxiliary electrode by being provided in contact with the common electrode 218 which is formed of a transparent conductive film. A liquid crystal layer 210 is provided between the array substrate 150 and the counter substrate 152 and is sealed with a sealing material 154 (see Figure 1). The pixel electrode 216, the liquid crystal layer 210, and the common electrode 218 constitute the liquid crystal element LE.

[0054] <Materials of each component of the display device 10> As the array substrate 150 and the counter substrate 152, rigid substrates having light transmittance and no flexibility, such as glass substrates, quartz substrates, and sapphire substrates, can be used. On the other hand, when the array substrate 150 and the counter substrate 152 need to have flexibility, flexible substrates containing resin and having flexibility, such as polyimide substrates, acrylic substrates, siloxane substrates, or fluororesin substrates, can be used as the array substrate 150 and the counter substrate 152. In order to improve the heat resistance of the array substrate 150 and the counter substrate 152, impurities may be introduced into the above resin. Further, when the display device 10 is applied to a transparent display, a large-sized or high-definition display, it is preferable to use a glass substrate as the array substrate 150 and the counter substrate 152. Further, the first transparent substrate 151A and the second transparent substrate 151B are provided to protect the array substrate 150 and the counter substrate 152. Therefore, for example, it is preferable to use a glass substrate, a plastic substrate, or the like having light transmittance.

[0055] As the nitride insulating films 201, 203a, 205b and the insulating film 209, silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), aluminum nitride (AlN x ), aluminum oxynitride (AlN x O y ) are used. In the present embodiment, silicon nitride is used as the nitride insulating films 201, 203a, 205b and the insulating film 209. The silicon nitride film is formed, for example, by a CVD (Chemical Vapor Deposition) method.

[0056] As the oxide insulating films 203b, 205a, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ) are used. In the present embodiment, silicon oxide is used as the oxide insulating films 203b, 205a. The silicon oxide film is formed, for example, by a CVD method.

[0057] The above SiO x N y and AlO x N y These are silicon compounds and aluminum compounds that contain nitrogen (N) in a smaller proportion (x>y) than oxygen (O). x O y and AlN x O y These are silicon compounds and aluminum compounds that contain oxygen in a smaller proportion (x > y) than nitrogen.

[0058] As the planarization film 207, organic insulating materials such as polyimide resin, acrylic resin, epoxy resin, silicone resin, fluororesin, or siloxane resin can be used.

[0059] As described above, a configuration in which a low-resistance wiring material is sandwiched between wiring materials with a high melting point is preferred for the conductive layer 202. Examples of low-resistance wiring materials include aluminum or copper. Examples of high-melting-point wiring materials include titanium, molybdenum, or tungsten. Similarly, for the conductive layer 206, a configuration in which a low-resistance wiring material is sandwiched between wiring materials with a high melting point is preferred. The conductive layer 206 may have a structure in which a first titanium layer 202a, an aluminum layer 202b, and a second titanium layer 202c are laminated in that order, similar to the conductive layer 202.

[0060] Common metallic materials can be used as conductive layers 208 and 214. For example, these materials may include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), and alloys or compounds thereof. The above materials may be used as single layers or in laminated layers.

[0061] As the oxide semiconductor layer 204, an oxide semiconductor having semiconductor properties can be used. The oxide semiconductor layer 204 is translucent. For example, as the oxide semiconductor layer 204, an oxide semiconductor containing two or more metals including indium (In) can be used. As the oxide semiconductor layer 204, for example, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) may be used. In particular, an oxide semiconductor having a composition ratio of In:Ga:Zn:O = 1:1:1:4 may be used. However, the oxide semiconductor layer 204 used in this embodiment is not limited to the above composition, and an oxide semiconductor with a different composition may be used. For example, the ratio of In may be increased to improve mobility. Also, the ratio of Ga may be increased to increase the band gap and reduce the effect of light irradiation. The oxide semiconductor layer 204 may be amorphous or polycrystalline. The oxide semiconductor layer 204 may be a mixed phase of amorphous and crystalline material.

[0062] A mixture of indium oxide and tin oxide (ITO) and a mixture of indium oxide and zinc oxide (IZO) can be used as the transparent conductive layer 212, the pixel electrode 216, and the common electrode 218. Other materials may be used for the transparent conductive layer. The light-shielding layer 219 used for the black matrix BM can be formed from a black resin or metal material. The black matrix BM is formed in contact with the common electrode 218 (see Figure 4). By forming the black matrix BM from a metal material relative to the common electrode 218, which is formed from a transparent conductive film, it can function as an auxiliary electrode to reduce resistance loss. As the metal material for forming the black matrix BM, chromium, molybdenum, titanium, etc., which have a relatively low reflectivity compared to aluminum, may be used as a single layer or in a laminated form. In the case of laminated formation, aluminum may be used.

[0063] When the display device 10 is applied to a transparent display, it is preferable to use a polymer-dispersed liquid crystal as the liquid crystal layer 210. The polymer-dispersed liquid crystal includes bulk and fine particles. The orientation of the fine particles changes in the bulk according to the potential difference between the pixel electrode 216 and the common electrode 218. By individually controlling the potential of the pixel electrode 216 for each pixel PIX, at least the degree of light transmission and dispersion is controlled for each pixel PIX. The degree of scattering of the liquid crystal layer (fine particles) is controlled according to the voltage of each pixel electrode 216 and the voltage of the common electrode 218. For example, the liquid crystal layer may use a polymer-dispersed liquid crystal such that the degree of scattering increases as the voltage between the voltage of each pixel PIX and the common electrode 218 increases, or it may use a polymer-dispersed liquid crystal such that the degree of scattering increases as the voltage between the voltage of each pixel electrode 216 and the common electrode 218 decreases.

[0064] In the liquid crystal layer 210, the ordinary refractive indices of the bulk and fine particles are equal to each other. When no voltage is applied between the pixel electrode 216 and the common electrode 218, the refractive index difference between the bulk and fine particles is zero in all directions. The liquid crystal layer 210 is in a non-scattering state and does not scatter the light emitted from the light source. As shown in Figure 2, the light emitted from the light source propagates away from the light source 104 (light-emitting part) while being reflected by the second plane 15B of the second transparent substrate 151B and the first plane 15A of the first transparent substrate 151A. When the liquid crystal layer 210 is in a non-scattering state and does not scatter the light L emitted from the light source, the background of the opposing substrate 152 is visible from the array substrate 150, and the background of the array substrate 150 is visible from the opposing substrate 152.

[0065] Between the pixel electrode 216 to which a voltage is applied and the common electrode 218, the optical axis of the microparticle is tilted by the electric field generated between the pixel electrode 216 and the common electrode 218. Since the optical axis of the bulk does not change due to the electric field, the orientation of the optical axis of the bulk and the optical axis of the microparticle are different from each other. In a pixel PIX where the pixel electrode 216 to which a voltage is applied, light emitted from the light source is scattered. As described above, a portion of the scattered light emitted from the light source is radiated outward from the first plane of the first transparent substrate 151A or the second plane of the second transparent substrate 151B and is observed by the observer.

[0066] In pixels PIX where no voltage is applied to the pixel electrode 216, the background on the first main surface side of the opposing substrate 152 is visible from the first main surface of the array substrate 150, and the background on the first main surface 10A side of the array substrate 150 is visible from the first main surface 20A of the opposing substrate 152. When a video signal is input to the display device 10 of this embodiment, a voltage is applied to the pixel electrode 216 of the pixel PIX on which the image is displayed, and the image based on the video signal is visible along with the background. In this way, when the polymer-dispersed liquid crystal is in a scattering state, an image is displayed in the display area.

[0067] In this embodiment, a case is described in which a nitride insulating film 201 is provided between the array substrate 150 and the gate electrode (conductive layer 202-1) provided on the array substrate 150, but the embodiment of the present invention is not limited thereto. For example, a nitride insulating film may be provided between the opposing substrate 152 and a light-shielding layer 219 provided on the opposing substrate 152 (in Figure 4, the light-shielding layer 219 is provided below the opposing substrate 152). In this case, the laminated structure of the light-shielding layer 219 may be the same as the laminated structure of the gate electrode. That is, the light-shielding layer 219 may be, for example, a laminated structure of a first titanium layer, aluminum, and a second titanium layer. In this case, the first titanium layer is provided in contact with the nitride insulating film, and the second titanium layer is provided in contact with the common electrode 218. Furthermore, it is preferable that the film thickness of the second titanium layer is greater than the film thickness of the first titanium layer, and it is preferable that the film thickness of the second titanium layer is 5 times or more and 10 times or less the film thickness of the first titanium layer.

[0068] The light-shielding layer 219 is formed on a nitride insulating film formed on the opposing substrate 152. By making the light-shielding layer 219 have the same laminated structure as the conductive layer 202 (gate electrode), it is possible to suppress the formation of irregularities on the surface of the light-shielding layer 219 and the formation of etching residue on the side surface of the light-shielding layer 219.

[0069] <Pixel Circuit> Figure 5 is a diagram illustrating the pixel circuit of a pixel PIX in a display device 10 according to one embodiment of the present invention. In this embodiment, a display device 10 is described that can simultaneously supply an ON voltage to four gate wires and simultaneously charge four pixels arranged in the column direction by four source wires. This makes it possible to make one horizontal period longer than the horizontal period of line sequential charging. In other words, the time required to scan all pixel lines arranged in the display area 12 can be reduced to one-quarter. Therefore, a sufficient charging period for pixels can be ensured in high-speed drive panels such as transparent displays, and in large or high-resolution panels. The pixel configuration in this embodiment will be described in detail below.

[0070] In Figure 5, four pixels PIX1 to PIX4 are arranged in the column direction (D2 direction). Each of the four pixels PIX1 to PIX4 is electrically connected to each of the four gate wirings GL1 to GL4. Also, each of the four pixels PIX1 to PIX4 is electrically connected to each of the four source wirings SL1 to SL4. Each of the four pixels PIX1 to PIX4 is connected to the capacitive wiring CW. In the display area 12, the conductive layer 214 and transparent conductive layer 212 shown in Figure 4 correspond to the capacitive wiring CW. In the following explanation, when pixels PIX1 to PIX4 are not distinguished, they will be referred to as pixel PIX. Similarly, when gate wirings GL1 to GL4 and source wirings SL1 to SL4 are not distinguished, they will be referred to as gate wiring GL and source wiring SL.

[0071] Each pixel PIX comprises a transistor Tr, a liquid crystal element LE, and a retaining capacitor C. The gate of the transistor Tr is connected to the gate wiring GL, the source of the transistor Tr is connected to the source wiring SL, and the drain of the transistor Tr is connected to one electrode of the liquid crystal element LE and one electrode of the retaining capacitor C. The other electrode of the liquid crystal element LE is connected to the common wiring CL. The other electrode of the retaining capacitor C is connected to the capacitance wiring CW.

[0072] The transistor Tr has the function of controlling the writing time of the video signal supplied from the source wiring to the pixels by switching between an on state and an off state. By turning the transistor Tr on, the potential corresponding to the video signal supplied from the source wiring can be written to the retaining capacitor C electrically connected to the transistor Tr. Conversely, by turning the transistor Tr off, the potential held in the retaining capacitor C can be retained.

[0073] Figure 6 is a timing chart of a display device 10 according to one embodiment of the present invention. Normally, gate wiring GL is supplied with an ON voltage one row at a time, sequentially charging the pixel rows aligned in the D2 direction with the same source wiring. In contrast, in this embodiment, an ON voltage is supplied to four gate wirings GL simultaneously, causing each of the four pixel transistors Tr to be turned ON at the same time. In this state, video signals are supplied simultaneously to different source wirings SL1 to SL4. This makes it possible to drive four pixels aligned in the D2 direction simultaneously.

[0074] As shown in Figure 5, source wirings SL1 and SL3, and source wirings SL2 and SL4 are provided so as to flank each row of pixels. In other words, four source wirings SL1 to SL4 are arranged between each row of pixels.

[0075] Source wiring SL1 and source wiring SL3 have an intersecting region. Similarly, source wiring SL2 and source wiring SL4 also have an intersecting region. In other words, source wiring SL1 and source wiring SL3 are swapped, and source wiring SL2 and source wiring SL4 are swapped. This allows for uniformity of the resistance and capacitance of source wiring SL1 to SL4. Furthermore, it helps suppress defects caused by static electricity during the manufacturing of the display panel. The reason for this will be explained with reference to Figures 7 to 11.

[0076] <Pixel Planar Layout> Referring to Figures 7 to 11, the planar layout of pixels PIX in a display device 10 according to one embodiment of the present invention will be described. Figures 7 to 11 show the configuration of PIX-A1, PIX-A2, PIX-B1, and PIX-B2 in a planar view.

[0077] As shown in Figure 7, gate wirings GLn-1 to GLn+1 are arranged along the D1 direction. Source wirings S1 to S4 are arranged along the D2 direction. Here, the aperture region of pixel PIX-B1 is the region enclosed by the adjacent gate wiring GLn-1, gate wiring GLn, source wiring S3, and source wiring S4. Pixel PIX-B1 is controlled by transistor Tr located in region 250.

[0078] Figures 8 to 11 describe in detail the configuration of the region where source wiring SL1 and source wiring SL3 intersect, and the region 250 where source wiring SL2 and source wiring SL4 intersect.

[0079] Figure 8 shows the planar layout of conductive layers 202-1 to 202-9, oxide semiconductor layers 204-1 to 204-5, and conductive layers 206-1 to 206-11 in region 250. Conductive layers 202-1 to 202-9 are provided on top of the nitride insulating film 201. Conductive layer 202-1 extends in the D1 direction but has a region that branches in the D2 direction. Conductive layers 202-2 to 202-9 also extend in the D2 direction. Oxide semiconductor layers 204-1 to 204-5 are provided on top of conductive layer 202-1 via the gate insulating film 203 (see Figure 4). Oxide semiconductor layers 204-1 to 204-5 are arranged side by side in the D2 direction. In this embodiment, an example is shown in which five oxide semiconductor layers 204-1 to 204-5 are used to construct a transistor Tr. The effect of heat generation can be reduced by providing the oxide semiconductor layers in separate layers. The number of oxide semiconductor layers is not particularly limited. The oxide semiconductor layers 204-1 to 204-5 are made less prone to light leakage because the conductive layer 202-1 reflects the light that has been guided through the glass substrate (array substrate 150) from the conductive layer 202-1 side toward the oxide semiconductor layers 204-1 to 204-5. The conductive layers 206-1 to 206-11 are provided on the gate insulating film 203 and the oxide semiconductor layers 204-1 to 204-5. Conductive layers 206-1, 206-2, and 206-11 extend in the D1 direction, and conductive layers 206-3 to 206-10 extend in the D2 direction.

[0080] The conductive layer 202-1 is superimposed on conductive layers 206-1, 206-2, and 206-11. Conductive layer 202-1 is connected to conductive layer 206-1 via an opening 213-1 provided in the gate insulating film 203, and is connected to conductive layer 206-2 via an opening 213-2 provided in the gate insulating film 203. Of conductive layer 202-1, the region extending in the D1 direction functions as a gate wire. Also, of conductive layer 202-1, the region extending in the D2 direction functions as a gate electrode. As explained in Figure 4, conductive layer 202 is composed of a laminate of a first titanium layer 202a, an aluminum layer 202b, and a second titanium layer 202c, with the film thickness of the second titanium layer 202c being greater than the film thickness of the first titanium layer 202a. Therefore, when forming the opening 213 in the gate insulating film 203, it is possible to suppress the etching of the second titanium layer 202c and the exposure of the aluminum layer 202b.

[0081] Conductive layers 202-2 and 202-3 overlap with conductive layer 206-4. Conductive layer 202-2 is connected to conductive layer 206-4 via an opening 213-3 provided in the gate insulating film 203, and conductive layer 202-3 is connected to conductive layer 206-4 via an opening 213-4 provided in the gate insulating film 203. Conductive layer 206-4 intersects with conductive layer 202-1. Conductive layer 206-4 functions as the first source wiring SL1. In addition, the region of conductive layer 206-4 that does not overlap with conductive layers 202-2 and 202-3 functions as the source electrode of transistor Tr. Conductive layer 206-3 functions as the drain electrode of transistor Tr.

[0082] Conductive layer 202-4 is superimposed on conductive layer 206-5 and connected to conductive layer 206-5 via an opening 213-5 provided in the gate insulating film 203. Conductive layer 202-5 is superimposed on conductive layer 206-6 and connected to conductive layer 206-6 via an opening 213-6 provided in the gate insulating film 203. Conductive layer 206-5 is connected to conductive layer 206-6 via conductive layer 208-2 (see Figure 9). As a result, conductive layers 206-5, 206-6, and 208-2 function as the third source wiring SL3.

[0083] Conductive layer 202-6 is superimposed on conductive layer 206-7 and connected to conductive layer 206-7 via an opening 213-7 provided in the gate insulating film 203. Conductive layer 202-7 is superimposed on conductive layer 206-8 and connected to conductive layer 206-8 via an opening 213-8 provided in the gate insulating film 203. Conductive layer 206-7 is connected to conductive layer 206-8 via conductive layer 208-3 (see Figure 9). Conductive layers 206-7, 206-8, and 208-3 function as the second source wiring SL2.

[0084] Conductive layer 202-8 is superimposed on conductive layer 206-9 and connected to conductive layer 206-9 via an opening 213-9 provided in the gate insulating film 203. Conductive layer 202-9 is superimposed on conductive layers 206-9 and conductive layer 206-10. Conductive layer 202-9 is connected to conductive layer 206-9 via an opening 213-10 provided in the gate insulating film 203. Conductive layer 202-9 is connected to conductive layer 206-10 via an opening 213-11 provided in the gate insulating film 203. Conductive layer 206-9 has a region that intersects with conductive layer 202-1. Conductive layers 206-9 and conductive layers 206-10 function as the fourth source wiring SL4.

[0085] Furthermore, the conductive layer 202-1 is superimposed on the conductive layer 206-11 and is connected to the conductive layer 206-11 through an opening 213-12 provided in the gate insulating film 203.

[0086] Conductive layers 202-9 and 206-8 have bent regions. Conductive layer 202-9 has a region where it overlaps with and intersects with conductive layer 206-8. In other words, it has a region where the second source wiring SL2 and the fourth source wiring SL4 intersect.

[0087] Although not shown in the diagram, conductive layers 202-2 and 206-5 have bent regions. Conductive layer 202-2 overlaps with conductive layer 206-5 and has a region where they intersect. In other words, the first source wiring SL1 has a region where it intersects with the third source wiring SL3.

[0088] As shown in Figure 7, the gate wiring GL is constructed by laminating conductive layer 202-1 and conductive layers 206-1 and 206-2. Conductive layer 202-1 extends along the D1 direction. In the region where the gate wiring GL intersects with source wirings SL1 to SL4, only conductive layer 202-1 is provided, and conductive layers 206-1 and 206-2 are spaced apart. Also, as shown in Figure 8, source wiring SL1 is constructed by laminating conductive layers 202-2 and 202-3 and conductive layer 206-4. In the region where source wiring SL1 intersects with the gate wiring GL, only conductive layer 206-4 is provided, and conductive layers 202-2 and 202-3 are spaced apart. As a result, even if static electricity is generated during the manufacturing process of the display area 12 and peripheral area 14 of the array substrate 150, the static electricity can be dissipated, thereby suppressing the occurrence of defects caused by static electricity.

[0089] Figure 9 shows the planar layout of conductive layers 206-1 to 206-11 and conductive layers 208-1 to 208-3 in region 250. Conductive layers 206-1 to 206-11 are as described in Figure 8. Conductive layers 208-1 to 208-3 are provided on the insulating film 205 (see Figure 4). Conductive layer 208-1 has a region extending in the D2 direction and a region extending in the D1 direction. The region extending in the D2 direction overlaps with oxide semiconductor layers 204-1 to 204-5. The region extending in the D1 direction overlaps with conductive layer 206-11 and is connected to conductive layer 206-11 via an opening 215-1 provided in the insulating film 205. Conductive layer 208-2 extends in the D2 direction. The conductive layer 208-2 is superimposed on conductive layers 206-5 and 206-6 and is connected to conductive layers 206-5 and 206-6 via openings 215-2 and 215-3 provided in the insulating film 205. The conductive layer 208-3 extends in the D2 direction. The conductive layer 208-3 is superimposed on conductive layers 206-7 and 206-8 and is connected to conductive layers 206-7 and 206-8 via openings 215-4 and 215-5 provided in the insulating film 205.

[0090] Figure 10 shows the planar layout of the planarization film 207, transparent conductive layer 212, and conductive layer 214 in region 250. The planarization film 207 is removed in the aperture region of pixels PIX1 to PIX4, as shown in Figure 4. In other words, the planarization film 207 is provided on top of the wiring region. The transparent conductive layer 212 is provided on top of the planarization film 207. The conductive layer 214 is provided on top of the transparent conductive layer 212. The transparent conductive layer 212 and the conductive layer 214 function as capacitive wiring. The transparent conductive layer 212 is provided on conductive layers 206-1 to 206-11 via the planarization film 207. Therefore, the source wiring SL1 to SL4 and the capacitive wiring CW are spaced apart, making them less susceptible to the potential influence from the capacitive wiring CW. Also, the electrical resistance of the conductive layer 214 is smaller than that of the transparent conductive layer 212. Therefore, within the display area 12, variations in the potential of the capacitive wiring CW depending on the position of the pixel PIX are suppressed. The transparent conductive layer 212 has an opening 223, and the conductive layer 214 has an opening 225. The openings 223 and 225 are provided so as to overlap.

[0091] The transparent conductive layer 212 and the conductive layer 214 are arranged in a grid pattern so as to cover the gate wiring GL and source wiring SL1 to SL4. This reduces the retention capacitance C between the region where the transparent conductive layer 212 is not provided and the pixel electrode 216. The retention capacitance C is adjusted by the size of the region where the transparent conductive layer 212 is not provided. Note that the transparent conductive layer 212 may be provided over the entire surface instead of in a grid pattern. The conductive layer 214 is provided so as to cover the transistor Tr. This suppresses light leakage from the transistor Tr.

[0092] The conductive layer 214 is shown as being provided on top of the transparent conductive layer 212, but it may also be provided below the transparent conductive layer 212. The conductive layer 214 only needs to be laminated with the transparent conductive layer 212. The conductive layer 214 has light-shielding properties. Therefore, it can shield the wiring area from light. The width of the conductive layer 214 is set to be greater than the combined width of the source wirings SL1 to SL4 in a plan view. Also, the width of the conductive layer 214 is set to be greater than the width of the gate wiring GL in a plan view. This makes it possible to suppress the emission of reflected light reflected from the edges of the source wirings SL1 to SL4 by the display panel 11. Note that the width of the conductive layer 214 and the combined width of the source wirings SL1 to SL4 refer to the length in the direction (D2 direction) that intersects the direction in which the source wirings SL1 to SL4 extend. Also, the width of the gate wiring GL refers to the length in the direction (D2 direction) that intersects the direction in which the gate wiring GL extends.

[0093] Figure 11 shows the planar layout of the conductive layers 206-1 to 206-11 and the pixel electrodes 216-1 to 216-4 in region 250. The conductive layers 206-1 to 206-11 are as described in Figure 8. The pixel electrodes 216-1 to 216-4 are provided on the insulating film 209. The pixel electrodes 216-1 to 216-4 are provided in the aperture region of the pixel PIX. Pixel electrode 216-1 is connected to conductive layer 206-3 via an aperture 217-1 provided in the insulating film 209 and an aperture 215-6 provided in the insulating film 205 (see Figure 9). The insulating film 209 has an aperture 217-2. Aperture 217-2 is provided so as to overlap with apertures 223 and 225. By arranging the openings 223, 225, and 217-2 to overlap on the planarized film 207, moisture contained in the planarized film 207 can be released through the openings 223, 225, and 217-2.

[0094] As explained above, in the display area 12, the conductive layers 202 and 206 are arranged to extend in a stacked manner, serving as gate wirings GL1 to GL4 and source wirings SL1 to SL4. By arranging the source wirings SL1 to SL4 in a stacked manner, the resistance of the source wirings SL1 to SL4 and the wiring capacitance can be made uniform. Furthermore, source wirings SL1 and SL3 can be arranged to cross each other, and source wirings SL2 and SL4 can be arranged to cross each other. [Examples]

[0095] In this embodiment, we will explain the results of our investigation into the surface irregularities and end shape of the gate electrode in relation to the surface forming the gate electrode and the laminated structure of the gate electrode.

[0096] First, we will describe a sample used when forming a gate electrode on a glass substrate.

[0097] (Sample A) A 240 nm aluminum layer and a 150 nm titanium layer were laminated onto a glass substrate. Subsequently, the aluminum and titanium layers were patterned using an inductively coupled plasma method with a mixed gas of Cl2, BCl3, and N2. All subsequent samples were also patterned using the same etching conditions.

[0098] (Sample B) A 240nm aluminum layer and a 50nm titanium layer were laminated onto a glass substrate. Subsequently, the aluminum and titanium layers were processed into a pattern.

[0099] (Sample C) A 10nm titanium layer, a 240nm aluminum layer, and a 50nm titanium layer were layered on a glass substrate. Subsequently, the titanium layer, aluminum layer, and titanium layer were processed into a pattern.

[0100] Next, we will describe a sample in which a gate electrode is formed on a 50 nm silicon oxide film provided on a glass substrate.

[0101] (Sample D) A 240 nm aluminum layer and a 150 nm titanium layer were laminated onto a silicon oxide film. Subsequently, the aluminum and titanium layers were processed into a pattern.

[0102] (Sample E) A 240 nm aluminum layer and a 50 nm titanium layer were laminated onto a silicon oxide film. Subsequently, the aluminum and titanium layers were processed into a pattern.

[0103] (Sample F) A 10nm titanium layer, a 240nm aluminum layer, and a 50nm titanium layer were layered on a silicon oxide film. Subsequently, the titanium layer, aluminum layer, and titanium layer were processed into a pattern.

[0104] Next, we will describe a sample in which a gate electrode is formed on a 50 nm silicon nitride film provided on a glass substrate.

[0105] (Sample G) A silicon nitride film was formed by laminating a 240 nm aluminum layer and a 150 nm titanium layer. Subsequently, the aluminum and titanium layers were processed into a pattern.

[0106] (Sample H) A 240 nm aluminum layer and a 50 nm titanium layer were laminated onto a silicon nitride film. Subsequently, the aluminum and titanium layers were processed into a pattern.

[0107] (Sample I) A silicon nitride film was formed by laminating a 10 nm titanium layer, a 240 nm aluminum layer, and a 50 nm titanium layer. Subsequently, the titanium layer, aluminum layer, and titanium layer were processed into a pattern.

[0108] For each of the patterned samples, scanning electron microscope (SEM) images were acquired. Figure 12 shows SEM images of the surface irregularities and edge shape of the gate electrode for each of samples A to I.

[0109] Samples A, D, and G, which were formed by laminating a 240nm aluminum layer and a 50nm titanium layer, all exhibited surface irregularities, including pincushion-like irregularities at the edges of the patterns. Samples B, E, and H, which were formed by laminating a 240nm aluminum layer and a 50nm titanium layer, all exhibited surface irregularities, but the pincushion-like residue at the pattern edges was improved. In particular, the pattern edges of sample H, which was formed on a silicon nitride film, were very smooth. Samples C, F, and I, which were formed by laminating a 10nm titanium layer, a 240nm aluminum layer, and a 50nm titanium layer, all exhibited pincushion-like irregularities at the pattern edges, but the surface irregularities of the patterns improved in sample C, which was formed on a glass substrate, and sample I, which was formed on a silicon nitride film. [Examples]

[0110] In this example, we will describe the results of verifying the surface irregularities and end shape by changing the conditions of the gate electrode's laminated structure.

[0111] (Sample J) A 240nm aluminum layer (Al) and a 150nm titanium layer (T-Ti) were laminated onto a glass substrate. Subsequently, the aluminum and titanium layers were processed into a pattern.

[0112] (Sample K) A 10nm titanium layer (B-Ti), a 240nm aluminum layer (Al), and a 150nm titanium layer (T-Ti) were layered on a glass substrate. Subsequently, the titanium layer, aluminum layer, and titanium layer were processed into a pattern.

[0113] (Sample L) A 240nm aluminum layer (Al) and a 50nm titanium layer (T-Ti) were laminated onto a glass substrate. Subsequently, the aluminum and titanium layers were processed into a pattern.

[0114] (Sample M) A 10nm titanium layer (B-Ti), a 240nm aluminum layer (Al), and a 50nm titanium layer (T-Ti) were layered on a glass substrate. Subsequently, the aluminum and titanium layers were processed into a pattern.

[0115] For each of the patterned samples, scanning electron microscope (SEM) images were acquired. Figure 13 shows SEM images of the surface irregularities and edge shapes of the gate electrodes for each of samples J to M. SEM observations were performed on both the center and edges of the substrate for each of samples J to M.

[0116] For sample J, surface irregularities appeared on the pattern, and the etching residue at the edges of the pattern did not improve. For sample K, surface irregularities improved, but the etching residue at the edges of the pattern did not improve. For sample L, surface irregularities appeared on the pattern, but the etching residue at the edges of the pattern improved. Furthermore, for sample M, both surface irregularities and etching residue at the edges of the pattern improved. [Examples]

[0117] Next, in this embodiment, we will explain the results of optical simulations performed on chromaticity variation by varying the conditions on the insulating film thickness.

[0118] First, the optical simulation model used in this embodiment will be described. Figure 14 is a diagram of the optical simulation model. As shown in Figure 14, silicon nitride 304, silicon oxide 306, silicon oxide 308, silicon nitride 310, silicon nitride 312, ITO 314, liquid crystal 316, ITO 318, and glass 320 are stacked on top of glass 302 in that order. Here, silicon nitride 304 and silicon oxide 306 correspond to the gate insulating film 203, silicon oxide 308 and silicon nitride 310 correspond to the insulating film 205, silicon nitride 312 corresponds to the insulating film 209, ITO 314 corresponds to the pixel electrode 216, liquid crystal 316 corresponds to the liquid crystal, ITO 318 corresponds to the common electrode 218, and glass 320 corresponds to the opposing substrate.

[0119] The film thicknesses of each layer used in the simulation were as follows: silicon oxide 306: 200 nm, silicon oxide 308: 300 nm, silicon nitride 310: 100 nm, silicon nitride 312: 220 nm, ITO 314: 50 nm, liquid crystal 316: 3150 nm, and ITO 318: 35 nm. Here, the film thickness of silicon nitride 304 was varied to 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 800 nm, and 1000 nm. The calculations were performed assuming that the film thickness of silicon nitride 304 varied within the plane by ±10%.

[0120] To examine the variation in chromaticity across the aperture region of multiple pixels (PIX), an optical simulation was performed using the transfer matrix method to calculate chromaticity.

[0121] Figures 15 to 22 are xy chromaticity diagrams obtained by optical simulation. Figures 15, 16, 17, 18, 19, 20, 21, and 22 are xy chromaticity diagrams for silicon nitride 304 film thicknesses of 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 800 nm, and 1000 nm, respectively. Figures 15 to 22 are enlarged views of the region in the CIE1931 color space where x is between 0.315 and 0.35 and y is between 0.32 and 0.355. The region where x is between 0.315 and 0.35 and y is between 0.32 and 0.355 is near the white point (0.33, 0.33). The number of plots is 500.

[0122] As shown in Figures 16 to 19, it was demonstrated that chromaticity varies when the silicon nitride film thickness is in the range of 200 nm to 500 nm. In contrast, it was shown that chromaticity variation is suppressed when the silicon nitride film thickness of the gate insulating film is between 600 nm and 1000 nm.

[0123] As described in the first embodiment, there are limitations on the thickness of the nitride insulating film used as part of the gate insulating film. When the thickness of the nitride insulating film used as part of the gate insulating film is 200 nm or more and 400 nm or less, it is suggested that the variation in chromaticity in the display device can be reduced by setting the nitride insulating film that functions as the underlayer to 200 nm or more and 800 nm or less.

[0124] For comparison, in Figure 14, the gate insulating film thickness was set to 300 nm, and the total film thickness of silicon nitride 310 and silicon nitride 312 was varied to 320 nm, 500 nm, and 700 nm. To confirm the variation in chromaticity in the aperture region of multiple pixels PIX according to the total film thickness of silicon nitride 310 and silicon nitride 312, optical simulations were performed to calculate chromaticity using the transfer matrix method.

[0125] Figures 23 to 25 are xy chromaticity diagrams obtained by optical simulation. Figures 23, 24, and 25 are xy chromaticity diagrams when the total film thickness of silicon nitride 310 and silicon nitride 312 is 320 nm, 500 nm, and 700 nm, respectively. Figures 23 to 25 are enlarged views of the region in the CIE1931 color space where x is between 0.315 and 0.35 and y is between 0.32 and 0.355. The region where x is between 0.315 and 0.35 and y is between 0.32 and 0.355 is near the white point (0.33, 0.33). The number of plots is 500.

[0126] As shown in Figures 23 to 25, the variation in chromaticity did not improve even when the total film thickness of silicon nitride 310 and silicon nitride 312 was varied.

[0127] While preferred embodiments have been described above, this disclosure is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications are possible without departing from the spirit of this disclosure. Any modifications made without departing from the spirit of this disclosure will naturally fall within the technical scope of this disclosure. [Explanation of Symbols]

[0128] 10: Display device, 11: Display panel, 12: Display area, 14: Peripheral area, 16: Common wiring, 18: Common wiring, 22: Common wiring area, 24: Flexible printed circuit, 26: Terminal section, 28: Gate drive circuit, 32: Gate wiring area, 34: Flexible printed circuit, 36: Terminal section, 38: Source drive circuit, 42: Source wiring area, 46: ESD protection circuit, 48: Gate inspection circuit, 52: Source inspection circuit, 54: Inspection line, 56: QD pad, 58: ESD protection circuit, 59: ESD protection circuit, 62: Area, 64: Area, 66: Area, 71: Area, 72: Area Area, 102: Display panel, 104: Light source, 105: Insulating layer, 150: Array substrate, 152: Opposing substrate, 202: Conductive layer, 203: Gate insulating film, 204: Oxide semiconductor layer, 205: Insulating film, 206: Conductive layer, 207: Planarization film, 208: Conductive layer, 209: Insulating film, 210: Liquid crystal layer, 212: Transparent conductive layer, 213: Aperture, 214: Conductive layer, 215: Aperture, 216: Pixel electrode, 217: Aperture, 218: Common electrode, 219: Light-shielding layer, 220: Encapacitor, GL: Gate wiring, SL: Source wiring, CL: Common wiring, CW: Capacitance wiring, C: Holding capacitance, LE: Liquid crystal element, PIX: Pixel

Claims

1. A display area comprising a plurality of pixels, Each of the aforementioned plurality of pixels is A first nitride insulating film provided on the first substrate, A gate electrode provided on the first nitride insulating film along a first direction, A second nitride insulating film is provided on the gate electrode, The first oxide insulating film is provided on the second nitride insulating film, An oxide semiconductor layer provided on the first oxide insulating film, Source electrode and drain electrode provided on the oxide semiconductor layer, A planarized film is disposed on the gate electrode, the oxide semiconductor layer, and the source electrode, and includes an aperture region that exposes a region that does not overlap with the gate electrode, the oxide semiconductor layer, the source electrode, and the drain electrode, Includes a pixel electrode disposed on the source electrode and the drain electrode and electrically connected to the drain electrode, The gate electrode has a first titanium layer, an aluminum layer, and a second titanium layer stacked in order from the first nitride insulating film side. The thickness of the second titanium layer is greater than the thickness of the first titanium layer. The pixel electrodes are arranged in the aperture region of the display device.

2. The display device according to claim 1, wherein the thickness of the second titanium layer is 5 times or more and 10 times or less the thickness of the first titanium layer.

3. The display device according to claim 1, wherein the first titanium layer is in contact with the first nitride insulating film.

4. The first nitride insulating film is in contact with the second nitride insulating film, The display device according to claim 1, wherein the total thickness of the first nitride insulating film and the second nitride insulating film is 600 nm or more and 1000 nm or less.

5. The display device according to claim 2, wherein the thickness of the first nitride insulating film is greater than the thickness of the second nitride insulating film.

6. The display device according to claim 3, wherein the film thickness of the second nitride insulating film is 200 nm or more and 400 nm or less.

7. The display device according to claim 3, wherein the second nitride insulating film and the first oxide insulating film function as a gate insulating film.

8. A second substrate is provided opposite to the first substrate, A liquid crystal layer provided between the first substrate and the second substrate, The display device according to claim 1, further comprising: a light source arranged so as to enter toward the side surface of the first substrate or toward the side surface with the second substrate.

9. The aforementioned liquid crystal layer is a polymer-dispersed liquid crystal, When the polymer-dispersed liquid crystal is in a scattering state, an image is displayed in the display area. The display device according to claim 8, wherein when the polymer-dispersed liquid crystal is in a non-scattering state, the background of the second substrate is visible from the first substrate in the display area, and the background of the first substrate is visible from the second substrate.

Images