Semiconductor equipment

Abstract

To provide a semiconductor device that can reduce forward voltage degradation and turn-on loss.SOLUTION: A vertical MOSFET includes: a first conductive type semiconductor substrate 2; a first conductive type first semiconductor layer 1; a second conductive type second semiconductor layer 16; a first conductive type first semiconductor region 17; a first trench 31 and a second trench 32; a gate electrode 20 provided inside the first trench 31 via a gate insulating film 19; and a Schottky electrode 29 provided inside the second trench 32. The first trench 31 is provided in a striped pattern in a plan view, and the second trench 32 surrounds the first trench 31.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, in power semiconductor devices, vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) with a trench structure have been manufactured to reduce the on-resistance of the device. In vertical MOSFETs, a trench structure in which the channel is formed perpendicular to the substrate surface can increase the cell density per unit area compared to a planar structure in which the channel is formed parallel to the substrate surface, thus increasing the current density per unit area and offering cost advantages.

[0003] Vertical MOSFETs incorporate a parasitic pn diode formed from a p-type base layer and an n-type drift layer as a body diode between the source and drain. This eliminates the need for a freewheeling diode (FWD) used in inverters, contributing to cost reduction and miniaturization. However, when using a silicon carbide substrate as the semiconductor substrate, the parasitic pn diode has a higher built-in potential compared to when using a silicon (Si) substrate, resulting in higher on-resistance of the parasitic pn diode and increased losses. Furthermore, when the parasitic pn diode is turned on and current is supplied, its bipolar operation causes its characteristics to change over time (aging degradation), leading to forward degradation and increased turn-on losses.

[0004] To address this problem, a Schottky barrier diode (SBD) can be connected in parallel with the MOSFET in the circuit. During freewheeling, current flows through the SBD, preventing current from flowing through the parasitic pn diode. However, this requires approximately the same number of SBD chips as MOSFETs, increasing costs.

[0005] Therefore, a technique has been proposed in which a contact trench penetrating the p-type channel portion is formed on the substrate surface, an SBD is incorporated in the trench inner wall, and the current during reflux is made to flow through the built-in SBD instead of the PiN diode (see, for example, Patent Document 1 below).

[0006] FIG. 24 is a top view showing the structure of a conventional silicon carbide semiconductor device incorporating an SBD. FIG. 25 is a cross-sectional view of the C-C' portion of FIG. 24 showing the structure of a conventional silicon carbide semiconductor device incorporating an SBD. As shown in FIG. 24, a silicon carbide semiconductor device 150 incorporating an SBD includes an active region 140 through which current flows when the element structure is formed and in the on state, an edge region 142 surrounding the periphery of the active region 140 and holding the breakdown voltage, and a connecting region 141 between the active region 140 and the edge region 142. The active region 140 is the region surrounded by the broken line in FIG. 24.

[0007] Also, as shown in FIG. 25, a MOS gate having a general trench gate structure is provided on the front surface (the surface on the p-type base layer 116 side described later) side of a semiconductor substrate made of silicon carbide (hereinafter referred to as a silicon carbide substrate). The silicon carbide substrate (semiconductor chip) is formed by epitaxially growing an n-type drift layer 101, an n-type region 115 which is a current diffusion region, and each silicon carbide layer serving as a p-type base layer 116 in this order on an n-type silicon carbide substrate (hereinafter referred to as an n-type silicon carbide substrate) 102.[[ID=!0]] + type silicon carbide substrate (hereinafter referred to as an n-type silicon carbide substrate) 102, an n-type drift layer 101, an n-type region 115 which is a current diffusion region, and each silicon carbide layer serving as a p-type base layer 116 are epitaxially grown in this order. + type silicon carbide substrate) 102, an n-type drift layer 101, an n-type region 115 which is a current diffusion region, and each silicon carbide layer serving as a p-type base layer 116 are epitaxially grown in this order. - type drift layer 101, an n-type region 115 which is a current diffusion region, and each silicon carbide layer serving as a p-type base layer 116 are epitaxially grown in this order.

[0008] n + type silicon carbide substrate 102, an n-type drift layer 101, an n-type region 115 which is a current diffusion region, and each silicon carbide layer serving as a p-type base layer 116 are epitaxially grown in this order. - type drift layer 101, an n-type region 115 which is a current diffusion region, and each silicon carbide layer serving as a p-type base layer 116 are epitaxially grown in this order. - type layer is epitaxially grown to form an n-type drift layer 101 on the front surface (the surface on the n-type drift layer 101 side) side of the n-type silicon carbide substrate 102, and a MOS gate structure including a p-type base layer 116, an n-type source region 117, a trench gate 131, a gate insulating film 119, and a gate electrode 120 is provided. + type silicon carbide substrate 102, an n-type drift layer 101, an n-type region 115 which is a current diffusion region, and each silicon carbide layer serving as a p-type base layer 116 are epitaxially grown in this order. - type drift layer 101 side) side of the n-type silicon carbide substrate 102, a MOS gate structure including a p-type base layer 11, an n-type source region 117, a trench gate 131, a gate insulating film 119, and a gate electrode 120 is provided. + type source region 117, a trench gate 131, a gate insulating film 119, and a gate electrode 120 is provided. Also, reference numerals 118, 121, and 122 denote p-type regions, respectively. ++These are the type contact region, the interlayer insulating film, and the source electrode.

[0009] In the n-type region 115, the first p is positioned to cover the entire bottom surface of the trench gate 131. + Type region 103 is selectively provided. In addition, the n-type region 115 is provided so as to cover the entire bottom surface of the trench SBD 132. + Type region 103 is selectively provided. 1p + Type region 103 is n - It is provided at a depth that does not reach the drift layer 101. Also, in the edge region 142, the first p + The second p is placed on the entire surface of type region 103. + A mold region 104 is provided.

[0010] Furthermore, the trench SBD 132 is a trench in which the inner wall is covered with Schottky metal 129 connected to the source electrode 122, and a Schottky bond is formed between the semiconductor region exposed on the inner wall and the Schottky metal 129. Thus, in Figure 24, a parasitic Schottky diode (built-in SBD) is provided in parallel with a parasitic pn diode between the source and drain.

[0011] As shown in Figure 24, in conventional silicon carbide semiconductor devices with built-in SBDs, the trench gate 131 is longer than the trench SBD 132 in order to facilitate connection of the trench gate 131 to the gate runner (not shown) provided in the edge region 142.

[0012] A positive voltage is applied to the source electrode 122, n + When a negative voltage is applied to the drain electrode (not shown) provided on the back surface of the silicon carbide substrate 102 (when the MOSFET is off), the p-type base layer 116 and n - The pn junction between the MOSFET and the drift layer 101 is forward-biased. In Figure 24, by designing the parasitic Schottky diode to turn on before the parasitic pn diode turns on when the MOSFET is off, the bipolar operation of the parasitic pn diode can be suppressed, and degradation due to bipolar operation over time can be prevented.

[0013] Furthermore, a known configuration is one in which multiple rings made of p-type layers, each formed by arranging an epitaxial film within a linear, frame-shaped trench surrounding the cell portion, are provided, and a Schottky electrode is positioned to cover a portion of the inner circumference of these rings (see, for example, Patent Document 2 below). [Prior art documents] [Patent Documents]

[0014] [Patent Document 1] Japanese Patent Application Publication No. 8-204179 [Patent Document 2] Japanese Patent Publication No. 2018-006630 [Overview of the Initiative] [Problems that the invention aims to solve]

[0015] Here, Figure 26 is a cross-sectional view of the A-A' portion of Figure 24, showing the structure of a conventional silicon carbide semiconductor device with an integrated SBD. Also, Figure 27 is a cross-sectional view of the B-B' portion of Figure 24, showing the structure of a conventional silicon carbide semiconductor device with an integrated SBD. As shown in Figures 26 and 27, in the connecting region 141, the first p + The second p is located on type region 103. + A mold region 104 is provided. In addition, the surface layer of the p-type base layer 116 is in contact with the trench SBD 132. ++ A type contact region 118 is provided. Therefore, in the connecting region 141, the trench SBD 132 is surrounded by a p-type region (p-type base layer 116, p ++ Type contact area 118, 1p + Type region 103 and 2p + It has a structure enclosed by type region 104).

[0016] As a result, in the junction region 141, the trench SBD 132 does not function as a parasitic Schottky diode and cannot suppress the bipolar operation of the parasitic pn diode. When the parasitic pn diode is turned on and current is supplied, the bipolar operation of the parasitic pn diode causes a Hall current to flow as shown in path D in Figures 26 and 27, and the energy generated by the recombination of the Hall current and electron current causes stacking faults to occur and expand.

[0017] Therefore, the bridging region 141 experiences changes in characteristics over time (aging degradation) due to the bipolar operation of the parasitic pn diode, resulting in issues such as forward degradation and increased turn-on losses, compared to the interior of the active region 140.

[0018] This invention aims to provide a semiconductor device that can reduce forward voltage degradation and turn-on losses in order to overcome the problems of the conventional technology described above. [Means for solving the problem]

[0019] To solve the above-mentioned problems and achieve the objectives of the present invention, the semiconductor device according to this invention has the following features: A first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate is provided on the front surface of a semiconductor substrate of a first conductivity type. A second semiconductor layer of a second conductivity type is provided on the side of the first semiconductor layer opposite to the semiconductor substrate side. A first semiconductor region of a first conductivity type having a higher impurity concentration than the semiconductor substrate is selectively provided inside the second semiconductor layer. A second semiconductor region of a second conductivity type is provided inside the first semiconductor layer. A third semiconductor region of a second conductivity type is provided on the surface layer of the first semiconductor layer, with its bottom surface in contact with the second semiconductor region. A first trench and a second trench are provided that penetrate the first semiconductor region and the second semiconductor layer and reach the first semiconductor layer. A gate electrode is provided inside the first trench via a gate insulating film. A Schottky electrode is provided inside the second trench. The first trench is provided in a striped shape with ends in a plan view, and the second trench has a striped portion parallel to the first trench in a plan view, and an outer peripheral portion connecting the striped portions and surrounding each end of the first trench, and the second trench surrounds each of the first trenches. The semiconductor device has, in plan view, an active region in which an element structure is formed and current flows when it is in the ON state, an edge region surrounding the active region and maintaining breakdown voltage, and a connecting region between the active region and the edge region. The end of the first trench is located in the edge region. In the connecting region, the side wall of the Schottky electrode is in contact with the first semiconductor layer and functions as a parasitic Schottky diode.

[0020] Furthermore, the semiconductor device according to this invention, in the invention described above, The aforementioned The edge region is provided with a joint termination structure for improving pressure resistance, the distance between the end of the first trench and the outer peripheral portion of the second trench is greater than or equal to the distance between the first trench and the second trench, and the end of the first trench is provided on the active region side of the joint termination structure.

[0021] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, the second trench is composed of a heterojunction with polysilicon.

[0022] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, a part of the second trench is provided at a position opposite in the depth direction to the gate contact region that connects the gate electrode and the gate runner.

[0023] According to the invention described above, the trench gate (first trench) is surrounded by the trench SBD (second trench). As a result, the part of the trench gate that contacts the source electrode is inside the region surrounded by the trench SBD. Jumpsuit Outside the region, when a negative bias is applied to the drain side of a silicon carbide semiconductor device with a built-in SBD, the parasitic pn diode no longer operates bipolar, thereby suppressing forward degradation and increased turn-on losses. [Effects of the Invention]

[0024] The semiconductor device according to the present invention has the effect of reducing the degradation of the forward voltage and the losses during turn-on. [Brief explanation of the drawing]

[0025] [Figure 1] This is a top view showing the structure of a silicon carbide semiconductor device according to an embodiment. [Figure 2] This is a cross-sectional view of the A-A' portion of Figure 1, showing the structure of a silicon carbide semiconductor device according to an embodiment. [Figure 3] This is a cross-sectional view of the B-B' portion of Figure 1, showing the structure of a silicon carbide semiconductor device according to an embodiment. [Figure 4] This is a cross-sectional view of the C-C' portion of Figure 1, showing the structure of a silicon carbide semiconductor device according to an embodiment. [Figure 5] This is a cross-sectional view of the D-D' portion of Figure 1, showing the structure of a silicon carbide semiconductor device according to an embodiment. [Figure 6] This is a top view showing the external appearance of a silicon carbide semiconductor device according to an embodiment. [Figure 7] This is a cross-sectional view (part 1) showing the state of a silicon carbide semiconductor device during the manufacturing process according to the embodiment. [Figure 8] This is a cross-sectional view (part 2) showing the silicon carbide semiconductor device in the process of being manufactured according to the embodiment. [Figure 9] This is a cross-sectional view (part 3) showing the silicon carbide semiconductor device in the process of being manufactured according to the embodiment. [Figure 10] This is a cross-sectional view (part 4) showing the state of a silicon carbide semiconductor device during the manufacturing process according to the embodiment. [Figure 11] This is a cross-sectional view (part 5) showing the state of a silicon carbide semiconductor device during the manufacturing process according to the embodiment. [Figure 12] This is a top view (part 1) showing the state of a silicon carbide semiconductor device during the manufacturing process according to the embodiment. [Figure 13] This is a cross-sectional view of the A-A' portion of Figure 12, showing the silicon carbide semiconductor device in the process of being manufactured according to the embodiment (part 1). [Figure 14] This is a top view (part 2) showing the state of the silicon carbide semiconductor device during the manufacturing process according to the embodiment. [Figure 15] This is a cross-sectional view of the A-A' portion of Figure 12, showing the silicon carbide semiconductor device in the process of being manufactured according to the embodiment (part 2). [Figure 16] This is a top view (part 3) showing the state of the silicon carbide semiconductor device during the manufacturing process according to the embodiment. [Figure 17] This is a cross-sectional view of section A-A' in Figure 12, showing the silicon carbide semiconductor device according to the embodiment during the manufacturing process (part 3). [Figure 18] This is a top view (part 4) showing the state of the silicon carbide semiconductor device during the manufacturing process according to the embodiment. [Figure 19] This is a cross-sectional view of the A-A' portion of Figure 12, showing the silicon carbide semiconductor device in the process of being manufactured according to the embodiment (part 4). [Figure 20] This is a top view (part 5) showing the state of the silicon carbide semiconductor device during the manufacturing process according to the embodiment. [Figure 21] This is a cross-sectional view of section A-A' in Figure 12, showing the silicon carbide semiconductor device according to the embodiment during the manufacturing process (part 5). [Figure 22] This is a top view (part 6) showing the state of a silicon carbide semiconductor device during the manufacturing process according to the embodiment. [Figure 23] This is a cross-sectional view of section A-A' in Figure 12, showing the silicon carbide semiconductor device according to the embodiment during the manufacturing process (part 6). [Figure 24] This is a top view showing the structure of a conventional silicon carbide semiconductor device with a built-in SBD. [Figure 25] This is a cross-sectional view of the C-C' portion of Figure 24, which shows the structure of a conventional silicon carbide semiconductor device with a built-in SBD. [Figure 26] This is a cross-sectional view of section A-A' in Figure 24, which shows the structure of a conventional silicon carbide semiconductor device with a built-in SBD. [Figure 27] This is a cross-sectional view of the B-B' portion of Figure 24, which shows the structure of a conventional silicon carbide semiconductor device with a built-in SBD. [Modes for carrying out the invention]

[0026] Preferred embodiments of the semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these signs. In the following description of embodiments and the accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted. In this specification, in the notation of Miller indices, "-" indicates a bar attached to the exponent immediately following it, and a "-" before the exponent indicates a negative exponent.

[0027] (Embodiment) The semiconductor device according to the present invention is constructed using a semiconductor with a wider bandgap than silicon (hereinafter referred to as a wide-bandgap semiconductor). Here, the structure of a semiconductor device using silicon carbide (SiC) as the wide-bandgap semiconductor (silicon carbide semiconductor device) will be described as an example. Figure 1 is a top view showing the structure of a silicon carbide semiconductor device according to an embodiment. Figure 2 is a cross-sectional view of the A-A' portion of Figure 1 showing the structure of a silicon carbide semiconductor device according to an embodiment. Figure 3 is a cross-sectional view of the B-B' portion of Figure 1 showing the structure of a silicon carbide semiconductor device according to an embodiment. Figure 4 is a cross-sectional view of the C-C' portion of Figure 1 showing the structure of a silicon carbide semiconductor device according to an embodiment. Here, Figure 5 is a cross-sectional view of the D-D' portion of Figure 1 showing the structure of a silicon carbide semiconductor device according to an embodiment. Figure 4 is a cross-sectional view of the C-C' portion of the connecting region 41, and Figure 5 is a cross-sectional view of the D-D' portion of the active region where the main current flows in the thickness direction of the substrate when the element structure is formed and the device is in the ON state.

[0028] As shown in Figure 1, the silicon carbide semiconductor device 50 with a built-in SBD consists of an active region 40 through which the main current flows in the thickness direction of the substrate when the element structure is formed and the device is in the ON state, an edge region 42 surrounding the active region 40 and maintaining the breakdown voltage, and a connecting region 41 between the active region 40 and the edge region 42. The active region 40 is the region enclosed by the dashed line in Figure 1. The connecting region 41 is the region where the side surface of the trench gate 31, which will be described later, is covered by a p-type region and does not function as a MOS, as shown in Figure 4. The silicon carbide semiconductor device according to the embodiment shown in Figures 1 to 4 is a silicon carbide semiconductor device 50 with a built-in SBD that has a MOS gate on the front side (the side facing the p-type base layer 16, which will be described later) of a semiconductor substrate (silicon carbide substrate: semiconductor chip) made of silicon carbide.

[0029] The silicon carbide substrate is made of n + n on a silicon carbide substrate (first conductivity type semiconductor substrate) 2 - Each silicon carbide layer, which becomes a p-type drift layer (first semiconductor layer of the first conductivity type) 1 and a p-type base layer (second semiconductor layer of the second conductivity type) 16, is epitaxially grown in sequence. In the active region 40, the MOS gate consists of a p-type base layer 16 and n+ It consists of a type source region (first semiconductor region of the first conductivity type) 17, a gate insulating film 19, and a gate electrode 20. Specifically, n - An n-type region 15 may be provided on the source side (source electrode 22 side, described later) of the p-type drift layer 1 so as to be in contact with the p-type base layer 16. The n-type region 15 is a so-called current spreading layer (CSL) that reduces the carrier spreading resistance. This n-type region 15 is provided uniformly in a direction parallel to the substrate surface (the surface of the silicon carbide substrate), for example.

[0030] n-type region 15 (If n-type region 15 is not provided, n - Inside the drift layer 1 (hereinafter referred to as (1)), the first p + A type region (second semiconductor region of the second conductivity type) 3 is selectively provided. 1p + The n-type region 3 is provided so as to be in contact with the bottom surface of the trench gate (first trench) 31, which will be described later, and the bottom surface of the trench SBD (second trench) 32, which will be described later. In addition, the surface layer of the n-type region 15(1) has a second p + A type region (third semiconductor region of the second conductivity type) 4 is selectively provided. + Type region 4 has a base that is the first p + It is provided so as to be in contact with type region 3.

[0031] If an n-type region 15 is provided, the first p + Type region 3 is located deeper on the drain side than the interface between the p-type base layer 16 and the n-type region 15, and is connected to the n-type region 15 and n - It is provided at a depth that does not reach the interface with the mold drift layer 1. 1p + By providing mold region 3, the first p is located near the bottom surface of the trench gate 31 and trench SBD 32. + A pn junction can be formed between the n-type region 3 and the n-type region 15(1). + Type region 3 and 2p + Type region 4 has a higher impurity concentration than the p-type base layer 16.

[0032] Furthermore, inside the p-type base layer 16, n + A type source region 17 is selectively provided. n are arranged so as to be in contact with each other. + Type source region 17 and p ++ Type contact regions (fifth semiconductor region of the second conductivity type) (not shown) may be selectively provided. In this case, p ++ The depth of the contact region is, for example, n + It may be the same depth as the type source area 17, or n + The type source area may be deeper than 17.

[0033] The trench gate 31 is located from the front surface of the substrate n + The n-type region 15(1) is reached by penetrating the type source region 17 and the p-type base layer 16. Inside the trench gate 31, a gate insulating film 19 is provided along the side wall of the trench gate 31, and a gate electrode 20 is provided inside the gate insulating film 19. The source-side end of the gate electrode 20 may or may not protrude outward from the surface of the substrate. The gate electrode 20 is electrically connected to a gate electrode pad (not shown). The interlayer insulating film 21 is provided on the surface of the substrate so as to cover the gate electrode 20 embedded in the trench gate 31. The interlayer insulating film 21 is opened at a connecting region 41, and the gate electrode 20 is connected to the gate runner 27 at the opening via the gate contact region 26 of the polysilicon layer.

[0034] Trench SBD32 is located from the front surface of the substrate n + The n-type region 15(1) is reached by penetrating the p-type source region 17 and the p-type base layer 16. Inside the trench SBD 32, along the side walls of the trench SBD 32, there is a Schottky metal 29 that connects to the source electrode 22, forming a Schottky junction between the semiconductor region exposed on the inner wall and the Schottky metal 29. An oxide film, such as silicon dioxide (SiO2), may also be provided on the inside of the Schottky metal 29.

[0035] As shown in Figure 1, in this embodiment, the trench gate 31 is surrounded by the trench SBD 32. As shown in Figure 6, which will be described later, surrounding means that in order to reach the edge region 42 from any point on the trench gate 31 in a plan view, it is necessary to cross the trench SBD 32. For example, the trench gate 31 is provided in a stripe shape in a plan view, and the trench SBD 32 is provided parallel to the trench gate 31 and has a stripe-shaped portion P1 that is longer than the trench gate 31 and an outer peripheral portion P2 that connects the stripe-shaped portion. As a result, the part of the trench gate 31 that contacts the source electrode 22 is inside the region surrounded by the trench SBD 32. Therefore, outside the region surrounded by the trench SBD 32, when a negative bias is applied to the drain side of the silicon carbide semiconductor device with the SBD built in, the parasitic pn diode will not operate bipolar, and forward degradation and increased turn-on loss can be suppressed.

[0036] Furthermore, as shown in Figure 4, in the connecting region 41, the side wall of the trench SBD 32 is the second p + It is not in contact with type region 4. In other words, in conventional silicon carbide semiconductor devices with built-in SBDs, the p-type regions (first and second p) that fill the periphery of the trench SBD 132 + By opening up a portion of the type regions 103 and 104), the trench SBD32 of this embodiment has a side wall that is in contact with the n-type region 15(1). This allows the trench SBD32 to function as a parasitic Schottky diode even in the bridging region 41. Therefore, when a negative bias is applied to the drain side of the silicon carbide semiconductor device with the SBD built in, the parasitic Schottky diode can be operated in the bridging region 41 as well, thereby suppressing the bipolar operation of the parasitic pn diode and preventing forward degradation and increased turn-on losses.

[0037] Figure 6 is a top view showing the external appearance of a silicon carbide semiconductor device according to an embodiment. As shown in Figure 6, the trench gate 31 is n +The silicon carbide substrate 1 is arranged in stripes in the direction of the crystal orientation <11-20>. In the edge region 42 surrounding the active region 40 and maintaining the breakdown voltage, a JTE region 43 is provided as a junction termination extension (JTE) structure to improve the breakdown voltage of the entire high-voltage semiconductor device by relaxing or dispersing the electric field. Outside the JTE region 43, n is provided which functions as a channel stopper. + A semiconductor region (not shown) is provided.

[0038] In this embodiment, the distance W1 between the end T of the trench gate 31 and the outer peripheral portion P2 of the trench SBD 32 is preferably greater than or equal to the distance W2 between the trench gate 31 and the trench SBD 32. Short And, in the current path of the trench SBD32, there is resistance. decrease This is because the tolerance may decrease. Furthermore, it is preferable that the end T of the trench gate 31 is located inside the JTE region 43 (on the active region 40 side). For this reason, the outer peripheral portion P2 of the trench SBD 32 is located opposite the gate contact region 26 in the depth direction.

[0039] The source electrode 22 is connected to the interlayer insulating film 21 via a contact hole opened in the interlayer insulating film 21. + It is in contact with the type source region 17 and is electrically insulated from the gate electrode 20 by the interlayer insulating film 21. ++ If a type contact region is provided, the source electrode 22 is p ++ It also contacts the type contact region. A barrier metal may be provided between the source electrode 22 and the interlayer insulating film 21 to prevent the diffusion of metal atoms from the source electrode 22 to the gate electrode 20 side. A source electrode pad (not shown) is provided on the source electrode 22. The back surface (n + n becomes the type drain region + A drain electrode (not shown) is provided on the back surface of the silicon carbide substrate 1.

[0040] (Method for manufacturing a semiconductor device according to an embodiment) Next, a method for manufacturing a semiconductor device according to the embodiment will be described. Figures 7 to 11 are cross-sectional views showing the silicon carbide semiconductor device in the process of manufacturing according to the embodiment. Figures 12, 14, 16, 18, 20, and 22 are top views showing the silicon carbide semiconductor device in the process of manufacturing according to the embodiment. Figures 13, 15, 17, 19, 21, and 23 are cross-sectional views of the A-A' portion of Figure 12, showing the silicon carbide semiconductor device in the process of manufacturing according to the embodiment.

[0041] First, n + n becomes the type drain region + Prepare a silicon carbide substrate 2. Next, n + On the front surface of the silicon carbide substrate 2, the above-mentioned n - Type drift layer 1 is epitaxially grown. For example, n - The conditions for epitaxial growth to form type drift layer 1 are n - The impurity concentration in the drift layer 1 is 3 × 10 15 / cm 3 You may set it to a certain degree. The state up to this point is shown in Figure 7.

[0042] Next, n - On top of the drift layer 1, the lower n-type region 15a (if n-type region 15 is not formed, n - An n-type layer (hereinafter abbreviated as the n-type layer) with impurities of a similar degree to that of the drift layer 1 is epitaxially grown. For example, the conditions for epitaxial growth to form the lower n-type region 15a are such that the impurity concentration of the lower n-type region 15a is 1 × 10⁻⁶. 17 / cm 3 It may be set to the extent that this is the case. This lower n-type region 15a is part of the n-type region 15. Next, by photolithography and ion implantation of p-type impurities, the surface layer of the lower n-type region 15a (n-type layer) is implanted with the first p + Selectively forms type region 3. For example, the first p + The dose of ion implantation required to form type region 3 is determined when the impurity concentration is 5 × 10⁻⁶. 18 / cm 3You may set it to a certain degree. The state up to this point is shown in Figure 8.

[0043] Next, the lower n-type region 15a (n-type layer), the first p + An upper n-type region 15b (n-type layer) is epitaxially grown on top of the n-type region 3. For example, the conditions for epitaxial growth to form the upper n-type region 15b may be set to be approximately the same as the impurity concentration of the lower n-type region 15a. This upper n-type region 15b is part of the n-type region 15, and together with the lower n-type region 15a, the upper n-type region 15b forms the n-type region 15. Next, by photolithography and ion implantation of p-type impurities, a second p-type impurity is implanted in the surface layer of the upper n-type region 15b (n-type layer). + Selectively forms type region 4. For example, 2p + The dose amount during ion implantation to form type region 4 is determined when the impurity concentration is 1p + It may be set to be similar to type region 3. (1st p) + Type region 3 and 2p + The region formed by combining type region 4 and the other region is designated as the 1st and 2nd p. + These are referred to as type regions 3 and 4. Here, 2p + When forming the mold region 4, the side wall of the trench SBD 32 in the connecting region 41 is the second p + Form it so that it does not come into contact with mold region 4. The state up to this point is shown in Figure 9.

[0044] Next, the upper n-type region 15b and the second p + A p-type base layer 16 is epitaxially grown on the type region 4. For example, the conditions for epitaxial growth to form the p-type base layer 16 are such that the impurity concentration of the p-type base layer 16 is 4 × 10⁻⁶. 17 / cm 3 You may set it to a certain degree.

[0045] Next, photolithography and ion implantation of n-type impurities are performed on the surface layer of the p-type base layer 16. + A type source region 17 is selectively formed. For example, n + The dose amount for ion implantation to form the type source region 17 is determined when the impurity concentration is 3 × 10⁻⁶.20 / cm 3 It may be set to reach a certain level.

[0046] Next, by photolithography and ion implantation of p-type impurities, a p-type contact region is selectively formed on the surface layer of the p-type base layer 16 so as to be in contact with the n-type source region 17. For example, the dose amount during ion implantation for forming the p-type contact region may be set so that the impurity concentration is about 3×10 + / cm. The formation order of the n-type source region 17 and the p-type contact region may be swapped. Next, by photolithography and ion implantation of p-type impurities, a JTE region 43 is formed in the edge region 42. After all the ion implantations are completed, activation annealing is performed. The state up to this point is described in FIG. 10. ++ 型コンタクト領域を選択的に形成してもよい。例えば、p ++ 型コンタクト領域を形成するためのイオン注入時のドーズ量を、不純物濃度が3×10 20 / cm 3 程度となるように設定してもよい。n + 型ソース領域17とp ++ 型コンタクト領域との形成順序を入れ替えてもよい。次に、フォトリソグラフィおよびp型不純物のイオン注入により、エッジ領域42にJTE領域43を形成する。イオン注入が全て終わった後に、活性化アニールを施す。ここまでの状態が図10に記載される。

[0047] Next, by photolithography and etching, a trench gate 31 is formed that penetrates the n-type source region 17 and the p-type base layer 16 and reaches the n-type region 15(1). The bottom of the trench gate 31 may reach the first p-type region 3, or may be located within the n-type region 15(1) sandwiched between the p-type base layer 16 and the first p-type region 3. Subsequently, the mask used to form the trench gate 31 is removed. Also, an oxide film is used as the mask for trench formation. Also, after trench etching, isotropic etching for removing the damage of the trench gate 31 or hydrogen annealing for rounding the corners of the bottom and the opening of the trench gate 31 may be performed. Either isotropic etching or hydrogen annealing may be performed alone. Also, hydrogen annealing may be performed after isotropic etching. + 型ソース領域17およびp型ベース層16を貫通して、n型領域15(1)に達するトレンチゲート31を形成する。トレンチゲート31の底部は、第1p + 型領域3に達してもよいし、p型ベース層16と第1p + 型領域3に挟まれたn型領域15(1)内に位置していてもよい。続いて、トレンチゲート31を形成するために用いたマスクを除去する。また、トレンチ形成時のマスクには酸化膜を用いる。また、トレンチエッチング後に、トレンチゲート31のダメージを除去するための等方性エッチングや、トレンチゲート31の底部およびトレンチゲート31の開口部の角を丸めるための水素アニールを施してもよい。等方性エッチングと水素アニールはどちらか一方のみを行ってもよい。また、等方性エッチングを行った後に水素アニールを行ってもよい。

[0048] Next, by photolithography and etching, an n +A trench SBD32 is formed that penetrates the p-type source region 17 and the p-type base layer 16 and reaches the n-type region 15(1). The bottom of the trench SBD32 is the first p + It may reach type region 3, or the p-type base layer 16 and the first p + It may be located within the n-type region 15(1) sandwiched between the type regions 3. Next, the mask used to form the trench SBD 32 is removed. At this time, the distance W1 between the end T of the trench gate 31 and the outer peripheral portion P2 of the trench SBD 32 is greater than or equal to the distance W2 between the trench gate 31 and the trench SBD 32, and the end of the trench gate 31 is formed to be on the active region 40 side of the JTE region 42. The state up to this point is shown in Figure 11.

[0049] Next, a gate insulating film 19 is formed along the surface of the silicon carbide substrate and the inner wall of the trench gate 31. Then, a metal film is formed along the inner wall of the trench SBD 32, for example, made of titanium (Ti). Next, a Schottky junction is formed between the metal film and the semiconductor region on the inner wall of the trench SBD 32 by heat treatment (annealing) in a nitrogen (N2) atmosphere at a temperature of approximately 500°C or less.

[0050] Next, polysilicon is deposited and etched into the trench gate 31 and trench SBD 32, leaving polysilicon inside the trench gate 31 to form the gate electrode 20 and polysilicon inside the trench SBD 32. In this case, etching back may be performed to leave the polysilicon inside the substrate surface. By embedding polysilicon in the trench SBD 32 in this way, the trench SBD 32 is formed by a heterojunction between the metal film and polysilicon. A top view of the state up to this point is shown in Figure 12, and a cross-section A-A' in Figure 12 is shown in Figure 13.

[0051] Next, an interlayer insulating film 21 is formed on the entire surface of the silicon carbide substrate so as to cover the gate electrode 20. The interlayer insulating film 21 is formed from, for example, NSG (None-doped Silicate Glass), PSG (Phospho Silicate Glass), BPSG (Boro Phospho Silicate Glass), HTO (High Temperature Oxide), or a combination thereof. Next, the interlayer insulating film 21 and the gate insulating film 19 are patterned to form a contact hole, n + Expose the type source region 17. ++ When a type contact region is formed, n + Type source region 17 and p ++ The mold contact area is exposed. The trench gate 31 opens the interlayer insulating film 21 only in the connecting area 41. A top view of this state is shown in Figure 14, and a cross section A-A' in Figure 12 at this state is shown in Figure 15.

[0052] Next, a barrier metal is formed and patterned to cover the interlayer insulating film 21, n + Type source region 17 and p ++ Re-expose the contact area. Next, n + The source electrode 22 is formed so as to be in contact with the polysilicon embedded in the mold source region 17 and the trench SBD 32. The source electrode 22 may be formed to cover the barrier metal or it may be left only within the contact hole.

[0053] Next, polysilicon (Poly-Si) is deposited over the entire surface of the silicon carbide substrate. A top view of the state up to this point is shown in Figure 16, and the A-A' cross section in Figure 12 at this point is shown in Figure 17. Next, the polysilicon is patterned by etching, leaving it only in the direction of the gate runner, thereby forming the gate contact region 26. A top view of the state up to this point is shown in Figure 18, and the A-A' cross section in Figure 12 at this point is shown in Figure 19. In this way, by dividing the deposition of polysilicon into two stages—filling the trench SBD32 and forming the gate contact region 26—a wide gate contact region 26 can be formed on the upper part of the trench SBD32.

[0054] Next, an interlayer insulating film 21 is formed on the entire surface of the silicon carbide substrate. The interlayer insulating film 21 is formed from, for example, NSG, PSG, HTO, or a combination thereof. A top view of the state up to this point is shown in Figure 20, and a cross section A-A' in Figure 12 at this state is shown in Figure 21. Next, the interlayer insulating film 21 is patterned to form contact holes and expose the gate contact region 26.

[0055] Next, the source electrode pad 28 and gate runner 27 are formed to fill the contact hole. A portion of the metal layer deposited to form the source electrode pad 28 may also be used as the gate electrode pad. A top view of this state is shown in Figure 22, and a cross-section of A-A' in Figure 12 at this state is shown in Figure 23. + On the back surface of the silicon carbide substrate 2, a metal film such as a nickel (Ni) film or a titanium (Ti) film is formed in the contact area of ​​the drain electrode using sputter deposition or the like. This metal film may be a combination of multiple Ni and Ti films stacked together. Subsequently, annealing such as rapid thermal annealing (RTA) is performed so that the metal film silicides and forms an ohmic contact. After that, a thick film, such as a multilayer film in which a Ti film, Ni film, and gold (Au) are stacked in order, is formed by electron beam (EB) deposition or the like to form the drain electrode.

[0056] In the epitaxial growth and ion implantation described above, n-type impurities (n-type dopants) can be, for example, nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb), which are n-type relative to silicon carbide. For p-type impurities (p-type dopants), for example, boron (B), aluminum (Al), gallium (Ga), indium (In), or thallium (Tl), which are p-type relative to silicon carbide, can be used. In this way, the MOSFETs shown in Figures 1 to 4 are completed.

[0057] As described above, according to this embodiment, the trench gate is surrounded by a trench SBD. As a result, the portion of the trench gate that contacts the source electrode is located inside the region surrounded by the trench SBD. Therefore, outside the region surrounded by the trench SBD, when a negative bias is applied to the drain side of the silicon carbide semiconductor device with a built-in SBD, the parasitic pn diode will not operate bipolar, thereby suppressing forward degradation and increased turn-on loss.

[0058] As described above, the present invention can be modified in various ways without departing from the spirit of the invention, and in each of the embodiments described above, for example, the dimensions of each part, the impurity concentration, etc. can be set in various ways according to the required specifications. Furthermore, although the embodiments described above use MOSFETs as examples, the present invention is not limited to MOSFETs and can be broadly applied to various silicon carbide semiconductor devices that conduct and interrupt current by gate drive control based on a predetermined gate threshold voltage. Examples of silicon carbide semiconductor devices that are gate drive controlled include IGBTs (Insulated Gate Bipolar Transistors). Furthermore, although the embodiments described above use silicon carbide as the wide-bandgap semiconductor as an example, the present invention can also be applied to wide-bandgap semiconductors other than silicon carbide, such as gallium nitride (GaN). Furthermore, although the first conductivity type is n-type and the second conductivity type is p-type in each embodiment, the present invention can be similarly applied even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial applicability]

[0059] As described above, the semiconductor device according to the present invention is useful as a power semiconductor device used in power conversion devices and power supply devices for various industrial machines, and is particularly suitable as a silicon carbide semiconductor device with a trench gate structure. [Explanation of Symbols]

[0060] 1, 101 n - Type drift layer 2, 102 n + Silicon carbide substrate 3, 103 1st p. + type area 4, 104 2nd p. + type area 5, 105 p + type area 15, 115 n-type region 15a Lower n-type region 15b Upper n-type region 16, 116 p-type base layer 17, 117 n + Type source area pp. 18, 118 ++ Type Contact Area 19, 119 Gate insulating film 20, 120 gates 21, 121 Interlayer insulating film 22, 122 Source electrodes 25 Interlayer insulating film 26 Gate Contact Region 27 Gate Runner 28 Source electrode pads 29, 129 Schottky metal 31, 131 Trench Gate 32, 132 Trench SBD 40, 140 active area 41, 141 Transition Area 42, 142 edge regions 43 JTE area Silicon carbide semiconductor device with 50 and 150 SBDs

Claims

1. A first-type conductive semiconductor substrate and A first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate is provided on the front surface of the semiconductor substrate, A second semiconductor layer of a second conductivity type is provided on the side of the first semiconductor layer opposite to the semiconductor substrate side, A first semiconductor region of a first conductivity type having a higher impurity concentration than the semiconductor substrate is selectively provided inside the second semiconductor layer, A first trench and a second trench that penetrate the first semiconductor region and the second semiconductor layer and reach the first semiconductor layer, A gate electrode is provided inside the first trench via a gate insulating film, A Schottky electrode provided inside the second trench, A semiconductor device equipped with, The first trench is provided in a stripe shape with ends in a plan view, The second trench has a striped portion parallel to the first trench in a plan view, and an outer peripheral portion that connects the striped portion and surrounds each end of the first trench. The second trench surrounds each of the first trenches, The semiconductor device has, in plan view, an active region in which an element structure is formed and current flows when it is in the ON state, an edge region surrounding the active region and maintaining voltage resistance, and a connecting region between the active region and the edge region. The end of the first trench is located in the edge region, A semiconductor device characterized in that, in the bridging region, the side wall of the Schottky electrode is in contact with the first semiconductor layer and functions as a parasitic Schottky diode.

2. The edge region is provided with a joint termination structure for improving pressure resistance, The semiconductor device according to claim 1, characterized in that the distance between the end of the first trench and the outer peripheral portion of the second trench is greater than or equal to the distance between the first trench and the second trench, and the end of the first trench is provided on the active region side of the junction termination structure.

3. The semiconductor device according to claim 1 or 2, characterized in that the second trench is formed by a heterojunction with polysilicon.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that a portion of the second trench is provided at a position opposite in the depth direction to the gate contact region connecting the gate electrode and the gate runner.

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