Phase adjustment method and system

Abstract

To provide a phase adjustment method and system that effectively adjust a clock signal.SOLUTION: A phase adjustment method in a phase adjustment circuit 100 includes the steps of receiving a serial clock signal, receiving a serial data signal, sweeping a plurality of phase codes that can transition the phase of the serial clock signal, identifying a first phase code, a second phase code, a third phase code, and a fourth phase code from among the plurality of phase codes, determining the average phase code on the basis of the first phase code, the second phase code, the third phase code, and the fourth phase code, and applying the average phase code to a phase interpolator to transition the phase of the serial clock signal.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a phase adjustment method and system, and more particularly to a phase adjustment method and system having a serial interface.

[0002] This application claims priority to U.S. Patent Application No. 63 / 135,434, filed with the United States Patent and Trademark Office on January 8, 2021, the entire contents of which are hereby incorporated by reference into this application.

Background Art

[0003] Data transfer via a high-speed serial interface is affected by a clock signal adjusted according to the data sent through the interface. Unadjusted clock signals may occasionally produce data that contains errors and is not reliable.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to present a method for effectively adjusting a clock signal.

Means for Solving the Problems

[0005] A phase adjustment method according to one embodiment of the present invention may include the steps of: receiving a series clock signal; receiving a series data signal; sweeping a plurality of phase codes that can be applied to the series clock signal to shift the phase of the series clock signal; identifying a first phase code from the plurality of phase codes; identifying a second phase code from the plurality of phase codes; identifying a third phase code from the plurality of phase codes; identifying a fourth phase code from the plurality of phase codes; determining an average phase code based on the first phase code, the second phase code, the third phase code, and the fourth phase code; and applying the average phase code to a phase interpolator to shift the phase of the series clock signal. In this case, the first phase code may be identified such that the specific value is the number of bits obtained by adding the first threshold bit number extracted from the serial data signal to 0; the second phase code may be identified such that the specific value is the number of bits obtained by subtracting the second threshold bit number extracted from the serial data signal from the total number of extracted bits; the third phase code may be identified such that the specific value is the number of bits obtained by subtracting the third threshold bit number extracted from the serial data signal from the total number of extracted bits; and the fourth phase code may be identified such that the specific value is the number of bits obtained by adding the fourth threshold bit number extracted from the serial data signal to 0.

[0006] The serial data signal includes the same training pattern as the serial clock signal, and the number of first, second, third, and fourth threshold bits may be 0% to 5% of the total number of extracted bits.

[0007] The specified value is 1 or 0, where 1 includes bits extracted from the serial data signal at an earlier time than the scheduled time, and 0 includes bits extracted from the serial data signal at a later time than the scheduled time.

[0008] The step of sweeping the plurality of phase codes may include the step of sweeping three unit intervals of the serial data signal.

[0009] The step of applying the average phase code to the phase interpolator to transition the phase of the serial clock signal may include the step of transitioning the serial clock signal so that the edges of the serial clock signal align with the center of the data eye of the serial data signal.

[0010] The bits extracted from the serial data signal may include a first bit corresponding to the rising edge of the serial clock signal and a second bit corresponding to the falling edge of the serial clock signal.

[0011] The phase adjustment method further includes the steps of: sweeping a first window of phase codes to identify an updated first phase code and an updated second phase code; sweeping a second window of phase codes to identify an updated third phase code and an updated fourth phase code; determining an updated average phase code based on the updated first phase code, the updated second phase code, the updated third phase code, and the updated fourth phase code; and applying the updated average phase code to the phase interpolator to further shift the phase of the series clock signal, wherein the first window may start from a point obtained by subtracting a constant from the first phase code and end at a point obtained by adding the constant to the second phase code, and the second window may start from a point obtained by subtracting a constant from the third phase code and end at a point obtained by adding the constant to the fourth phase code.

[0012] The constant may be a programmable predetermined value.

[0013] The updated first phase code may differ from the updated second phase code, and the updated third phase code may differ from the updated fourth phase code.

[0014] A system according to one embodiment of the present invention includes a memory for storing computer-executable instructions and a processor for executing the instructions, wherein when the processor executes the instructions, the system may include receiving a serial clock signal, receiving a serial data signal, sweeping a plurality of phase codes that can be applied to the serial clock signal to shift the phase of the serial clock signal, identifying a first phase code from the plurality of phase codes, identifying a second phase code from the plurality of phase codes, identifying a third phase code from the plurality of phase codes, identifying a fourth phase code from the plurality of phase codes, determining an average phase code based on the first phase code, the second phase code, the third phase code and the fourth phase code, and applying the average phase code to a phase interpolator to shift the phase of the serial clock signal. In this case, the first phase code may be identified such that the specific value is the number of bits obtained by adding the first threshold bit number extracted from the serial data signal to 0; the second phase code may be identified such that the specific value is the number of bits obtained by subtracting the second threshold bit number extracted from the serial data signal from the total number of extracted bits; the third phase code may be identified such that the specific value is the number of bits obtained by subtracting the third threshold bit number extracted from the serial data signal from the total number of extracted bits; and the fourth phase code may be identified such that the specific value is the number of bits obtained by adding the fourth threshold bit number extracted from the serial data signal to 0.

[0015] The serial data signal includes the same training pattern as the serial clock signal, and the number of first, second, third, and fourth threshold bits may be 0% to 5% of the total number of extracted bits.

[0016] The specified value is 1 or 0, where 1 includes bits extracted from the serial data signal at an earlier time than the scheduled time, and 0 includes bits extracted from the serial data signal at a later time than the scheduled time.

[0017] The sweeping of the multiple phase codes can sweep three unit intervals of the serial data signal.

[0018] Applying the average phase code to the phase interpolator to transition the phase of the serial clock signal may include transitioning the serial clock signal so that the edges of the serial clock signal align with the center of the data eye of the serial data signal.

[0019] The bits extracted from the serial data signal may include a first bit corresponding to the rising edge of the serial clock signal and a second bit corresponding to the falling edge of the serial clock signal.

[0020] When the processor executes the instruction, the system may further include sweeping a first window of phase codes to identify updated first and updated second phase codes, sweeping a second window of phase codes to identify updated third and updated fourth phase codes, determining an updated average phase code based on the updated first phase code, updated second phase code, updated third phase code, and updated fourth phase code, and applying the updated average phase code to the phase interpolator to further transition the phase of the series clock signal. In this case, the first window may start from a point obtained by subtracting a constant from the first phase code and end at a point obtained by adding the constant to the second phase code, and the second window may start from a point obtained by subtracting a constant from the third phase code and end at a point obtained by adding the constant to the fourth phase code.

[0021] The constant may be a programmable predetermined value.

[0022] The updated first phase code may differ from the updated second phase code, and the updated third phase code may differ from the updated fourth phase code.

[0023] A phase adjustment method according to one embodiment of the present invention may include the steps of: receiving a series clock signal; receiving a series data signal; sweeping a first window of phase codes that can be applied to the series clock signal to shift the phase of the series clock signal; identifying an updated first phase code from the first window of phase codes; identifying an updated second phase code from the first window of phase codes; sweeping a second window of phase codes that can be applied to the series clock signal to shift the phase of the series clock signal; identifying an updated third phase code from the second window of phase codes; identifying an updated fourth phase code from the second window of phase codes; determining an average phase code based on the updated first phase code, the updated second phase code, the updated third phase code, and the updated fourth phase code; and applying the average phase code to a phase interpolator to shift the phase of the series clock signal. In this case, the first window may start from a point obtained by subtracting a constant from a predetermined first phase code and end at a point obtained by adding the constant to a predetermined second phase code, wherein the updated first phase code is identified such that the number of bits obtained by adding the number of first threshold bits extracted from the serial data signal to 0 is the specific value, the updated second phase code is identified such that the number of bits obtained by subtracting the number of second threshold bits extracted from the serial data signal from the total number of extracted bits is the specific value, the second window may start from a point obtained by subtracting the constant from a predetermined third phase code and end at a point obtained by adding the constant to a predetermined fourth phase code, wherein the updated third phase code is identified such that the number of bits obtained by subtracting the number of third threshold bits extracted from the serial data signal from the total number of extracted bits is the specific value, and the updated fourth phase code is identified such that the number of bits obtained by adding the number of fourth threshold bits extracted from the serial data signal to 0 is the specific value.

[0024] The first, second, third, and fourth threshold bit numbers are 0% to 5% of the total number of extracted bits, the specific value is 1 or 0, 1 includes bits extracted from the serial data signal at a time point earlier than the scheduled time point, and 0 can include bits extracted from the serial data signal at a time point later than the scheduled time point.

Effect of the Invention

[0025] By doing so, the clock signal can be effectively adjusted.

Brief Description of the Drawings

[0026] [Figure 1] It is a block diagram of a phase adjustment circuit in an electronic device having a serial interface according to an embodiment of the present invention. [Figure 2A] It shows a serial clock signal and a serial data signal according to an embodiment of the present invention, and is a diagram showing that data is sampled at the rising edge of the clock signal. [Figure 2B] It shows a serial clock signal and a serial data signal according to an embodiment of the present invention, and is a diagram showing that data is sampled at the rising edge of the clock signal. [Figure 3A] It shows a serial clock signal and a serial data signal according to an embodiment of the present invention, and is a diagram showing that data is sampled at both the rising edge and the falling edge of the clock signal. [Figure 3B] It shows a serial clock signal and a serial data signal according to an embodiment of the present invention, and is a diagram showing that data is sampled at both the rising edge and the falling edge of the clock signal. [Figure 4] It is a diagram showing a graph of phase code sweep showing the percentage of 1s of the extracted bits of data according to an embodiment of the present invention. [Figure 5]This figure shows a phase code sweep graph representing the percentage of 1s in the extracted bits of data with errors from a jittery clock according to one embodiment of the present invention. [Figure 6] This figure shows a phase code sweep graph representing the percentage of 1s in the extracted data bits according to one embodiment of the present invention. [Figure 7] This figure shows a phase code sweep graph representing the percentage of 1s in the extracted data bits according to one embodiment of the present invention. [Figure 8] This is a flowchart of a phase adjustment method according to one embodiment of the present invention. [Modes for carrying out the invention]

[0027] Embodiments of the present invention and their advantages can be best understood through the following detailed description. Unless otherwise specified, the same reference numerals in the drawings and throughout the specification refer to the same components, and therefore, the description will not be repeated. In addition, in the drawings, parts, layers, regions, etc., may be exaggerated for clarity.

[0028] Embodiments of the present invention will be described in detail below with reference to the attached drawings. However, the present invention can be realized in various different forms and is not limited to the embodiments described herein. Providing such embodiments will make the detailed description of the invention complete and comprehensive and will fully demonstrate the diverse aspects and features of the invention to those skilled in the art. Therefore, processes, apparatus, techniques, etc. that are not necessary for those skilled in the art to fully understand the diverse aspects and features of the present invention will be omitted from the description.

[0029] Embodiments of the present invention relate to a device that transfers data from one device to another using a high-speed serial data interface. An example of a high-speed serial data interface is a mobile display device interface such as MIPI D-PHY, which transfers video and / or audio data from one device to another. Other examples of high-speed serial data interfaces include DDR interfaces or other high-speed serial data interfaces known to those skilled in the art. More generally, one embodiment of the present invention relates to a phase adjustment method for adjusting the phase of a clock transferred by a forwarded-clock PHY protocol so that data is accurately sampled.

[0030] Figure 1 shows an electronic device having a series interface according to one embodiment of the present invention, and is a block diagram of the phase adjustment circuit 100.

[0031] According to one embodiment of the present invention, a transmitter 102 transmits data to a receiver 108, which is coupled together with a high-speed serial data interface such as MIPI D-PHY. For example, the transmitter 102 may be a computer tablet, and the receiver 108 may be a display device, or the computer tablet may send video data to the display device for display. According to one embodiment of the present invention, the transmitter 102 includes at least a clock transmitter 104 and a data transmitter 106, and the receiver 108 includes at least a clock receiver 110 and a data receiver 112. The clock transmitter 104 transmits a serial clock signal, which the clock receiver 110 receives, and the data transmitter 106 transmits serial data, which the data receiver 112 receives. Thus, a slicer [or sampler] 118 coupled with the receiver 108 samples the received serial data signal based on the received clock signal, for example, at each rising edge of the clock signal.

[0032] According to one embodiment of the present invention, the transmitter 102 and the receiver 108 may be part of the same electronic device or system, but for example, the transmitter 102 and the receiver 108 can be connected via a high-speed serial interface within a display device. According to another embodiment of the present invention, the transmitter 102 and the receiver 108 can be connected via a high-speed serial interface within a single computer, and data can be transferred from one area of ​​that computer to another.

[0033] In the embodiment shown in Figure 1, the clock transmitter 104 transmits a periodic square wave clock signal, and the data transmitter 106 transmits a data signal. Here, as shown in Figure 122, the clock signal and data signal are transmitted such that the edges of the clock signal (e.g., rising edge or falling edge) are aligned in the middle of the data eye. Such alignment is desirable because the slicer 118 samples the data signal using the edge of the clock signal, for example, the rising edge of the clock signal. Aligning the edge of the clock signal in the middle of the data eye ensures that accurate data is sampled. That is, since the clock edge is in the middle of the data eye, where the data does not change from 1 to 0 or from 0 to 1, if the data is logical 1, logical 1 is sampled, and if the data is logical 0, logical 0 is sampled.

[0034] While the clock signal and data signal are transmitted to the receiver via a high-speed serial interface, the phase of the clock signal transitions (for example, relative to the data signal). In some cases, as shown in Figure 124, the phase of the clock signal transitions so that the edges of the clock signal align with, or nearly align with, the edges of the data signal. Then, the slicer 118 samples the data signal, for example, at the rising edge of the clock signal, but because the clock signal and data signal are not further aligned, the slicer 118 may not be able to extract an accurate sample of the data. In other words, depending on whether the data signal is sampled slightly ahead or slightly behind, the sampled data may be extracted as a logical 1 or a logical 0. Therefore, it is preferable to adjust the phase transition by providing a phase calibration process so that the edges of the received clock signal align with the middle of the data eye of the data signal, as initially transmitted by the transmitter 102. Thus, by performing phase calibration, the clock signal and data signal can be properly aligned as shown in Figure 126. According to one embodiment of the present invention, initial phase calibration can be performed when the system or device is turned on. According to another embodiment of the present invention, phase adjustment can be performed periodically or at some regular intervals by transmitting adjustment data or training data during operation [for example, when there is a pause in data transmission]. According to another embodiment of the present invention, a well-adjusted serial interface can be further enhanced by combining initial phase adjustment and periodic phase adjustment.

[0035] According to one embodiment of the present invention, a phase interpolator 116 is connected to a clock receiver 110 and receives a phase-shifted clock signal. A slicer 118 is connected to a data receiver 112 and receives a data signal. The phase-shifted clock signal is transmitted from the phase interpolator 116 to the slicer 118, and the slicer 118 samples the received serial data based on this phase-shifted clock signal. Thus, one embodiment of the present invention presents a method for phase-adjusting a phase-shifted clock signal so that the phase interpolator 116 provides the slicer 118 with a phase-adjusted or calibrated clock signal so that the slicer 118 can correctly sample the data. According to one embodiment of the present invention, phase adjustment can be performed by supplying the slicer 118 with a training data signal that is identical or substantially identical to the serial clock signal containing alternating 0s and 1s.

[0036] According to one embodiment of the present invention, sampled data from slicer 118 is supplied to deserializer 120, which deserializes the serial data signal and supplies the deserialized data to phase calibrator 114. According to one embodiment of the present invention, the deserialized data may be a 16-bit data block, and according to another embodiment of the present invention, the deserialized data may be a 32, 64, or predetermined bit data block. The phase calibrator 114 takes the deserialized data and performs a phase adjustment process to determine the phase code, which is supplied to phase interpolator 116, which is used to adjust the phase transition clock signal.

[0037] Figures 2A and 2B illustrate the case where the clock signal shifts or transitions due to external factors such as interference occurring in cables, connections, etc. In particular, Figure 2A shows a serial clock signal and a serial data signal, and the serial clock signal has shifted to the right compared to a properly adjusted clock signal. Here, a properly adjusted clock signal has its rising edge aligned with the center of the data eye of the data signal (e.g., the center of 0), as shown in 122 of Figure 1. The clock signal shown in Figure 2A has shifted to the right because its rising edge has moved away from the center of 0 of the data signal and closer to the rising edge of the data signal. As a result, the data signal lags behind the clock signal, and the slicer 118 samples the data signal at a later time than intended with a properly adjusted clock signal, which is referred to as "late bits". In other words, during the rising edge of the clock signal, the data signal is sampled closer to the rising edge of the data signal than the center of the data eye of the data signal.

[0038] Figure 2B shows a series clock signal and a series data signal, but the series clock signal is shifted to the left compared to a properly adjusted clock signal. Here, a properly adjusted clock signal has its rising edge aligned with the center of the data eye of the data signal (e.g., the center of 1), as shown in 122 of Figure 1. In the clock signal shown in Figure 2B, the rising edge has shifted from the center of 1 in the data signal and moved closer to the rising edge of the data signal, thus shifting to the left. As a result, the data signal precedes the clock signal, and the slicer 118 samples the data signal earlier than intended with a properly adjusted clock signal, which we will call "early bits". In other words, during the rising edges of the clock signal, the data signal is sampled closer to the rising edge of the data signal than the center of the data eye of the data signal. A slow or delayed data signal, as shown in Figure 2A, and a fast or leading data signal, as shown in Figure 2B, cause the slicer 118 to generate incorrect data, especially when the data is sampled too close to the edge of the data signal. Therefore, the clock signal in Figure 2A can be phase-aligned by shifting it to the left so that its edge aligns with the center of the data eye of the data signal, and the clock signal in Figure 2B can be phase-aligned by shifting it to the right so that its edge aligns with the center of the data eye of the data signal.

[0039] According to one embodiment of the present invention, data is sampled on the rising edge of the clock signal, and as shown in Figure 2A, if all or most of the sampled data is 0, the phase adjuster 114 determines that the data signal lags behind the clock signal and is sampled at a later time than intended. Conversely, as shown in Figure 2B, if all or most of the sampled data is 1, the phase adjuster 114 determines that the data signal precedes the clock signal and is sampled at an earlier time than intended. Furthermore, according to one embodiment of the present invention, if all or most of the sampled data is 0, it can also mean that the data signal is sampled at an earlier time (rather than a later time), which may be due to using different data signal patterns, sampling the data on the falling edge of the clock signal, or both. Similarly, if all or most of the sampled data is 1, it can also mean that the data signal is sampled at a later time (rather than an earlier time), for the same reasons explained above. This allows the phase adjuster 114 to look for all or most zeros or all or most ones, and apply the appropriate phase code to the clock signal to move the edges so that the edges of the clock signal align with the center of the data eye of the data signal.

[0040] Similar to Figure 2A, Figure 3A shows a series clock signal and a series data signal, but the clock signal is shifted to the right compared to a properly adjusted clock signal. Here, a properly adjusted clock signal has its rising edge aligned with the center of the data eye of data signal 0, and its falling edge aligned with the center of the data eye of data signal 1. In the clock signal shown in Figure 3A, the rising edge is shifted from the center of the data eye of data signal 0 and closer to the rising edge of the data signal, and the falling edge is shifted from the center of the data eye of data signal 1 and closer to the falling edge of the data signal, so it has shifted to the right. As a result, the data signal lags behind the clock signal, and the slicer 118 samples the data signal at a later time than intended with a properly adjusted clock signal.

[0041] Similar to Figure 2B, Figure 3B shows a series clock signal and a series data signal, but the clock signal is shifted to the left compared to a properly adjusted clock signal. Here, a properly adjusted clock signal has its rising edge aligned with the center of the data eye of data signal 1, and its falling edge aligned with the center of the data eye of data signal 0. In the clock signal shown in Figure 3B, the rising edge is shifted from the center of the data eye of data signal 1 and closer to the rising edge of the data signal, and the falling edge is shifted from the center of the data eye of data signal 0 and closer to the falling edge of the data signal, so it has shifted to the left. As a result, the data signal precedes the clock signal, and the slicer 118 samples the data signal earlier than intended with a properly adjusted clock signal. However, unlike Figures 2A and 2B, Figures 3A and 3B show a data sampling method in which data is sampled on both the rising and falling edges of the series clock signal. For example, referring to Figure 3A, if all even-numbered bits of the sampled data are 0 and all odd-numbered bits are 1, then according to one embodiment of the present invention, the phase adjuster 114 can determine that the data signal is lagging behind the clock signal. Conversely, if all even-numbered bits of the sampled data are 1 and all odd-numbered bits are 0, then according to one embodiment of the present invention, the phase adjuster 114 can determine that the data signal is leading the clock signal.

[0042] According to one embodiment of the present invention, the phase adjuster 114 can set a phase code depending on whether the data is sampled at an earlier or later time, and can adjust the phase transition of the clock signal so that the edge of the clock signal aligns with the center of the data eye of the data signal. The phase code is, for example, an 8-bit number, e.g., 0 to 255, which corresponds to 256 different incremental transitions to the clock signal. Thus, by applying a phase code to the phase interpolator 116, the phase interpolator 116 can shift the phase of the clock signal by an amount corresponding to the given phase code. For example, phase code 1 corresponds to a 1.4-degree phase transition of the clock signal. Therefore, by applying phase code 1 to the phase interpolator 116, the phase interpolator 116 can shift or move the clock signal by 1.4 degrees. To give another example, for example, phase code 37 corresponds to a 52-degree phase transition of the clock signal. Therefore, by applying phase code 37 to the phase interpolator 116, the phase interpolator 116 can shift or move the clock signal by 52 degrees. Therefore, the phase interpolator 116 can be adjusted by shifting the phase of the clock signal based on the phase code provided to the phase interpolator 116. This allows the slicer 118 to use the phase-adjusted clock signal to sample the serial data signal, deseries the sampled data (120), and analyze it in the phase adjuster 114 to determine if the clock signal has been adjusted as desired. According to one embodiment of the present invention, the desired result is achieved when the clock signal is adjusted so that the rising edge of the clock signal aligns with the center of the data eye of the data signal. Therefore, trial and error can be performed by applying different phase codes to the phase interpolator 116 until the phase-shifted clock signal is as desired.

[0043] For example, if one clock cycle is two unit intervals in the same DDR-based serial link, sampling all data on both the rising and falling edges of the clock signal allows for faster sampling of the data signal than sampling data at only one of the rising or falling edges (i.e., twice as fast). (For example, sampling a given number of bits in the data signal can be done in half the number of clock cycles compared to sampling at only one of the rising or falling edges.) Since phase adjustment algorithms are associated with sampling a specific number of bits, sampling data at a faster rate allows for faster determination and setting of the phase code, enabling faster adjustment of the phase transition clock signal and thus improving the overall speed of the phase adjustment process.

[0044] Figure 4 is a graph showing the percentage of data bits ("leading bits") that are sampled ahead of each phase code by the clock signal during a phase code sweep. For example, an 8-bit phase code has 256 distinct codes, and these 256 distinct codes cause the clock signal to transition by 256 distinct increments. If we graph the percentage of 1s obtained as a result of each phase code, we can obtain a graph of phase codes versus percentages of 1s, as shown in Figure 4. In other words, the percentage of 1s for each phase code among the multiple phase codes being swept is plotted in this graph. The lower region of the graph corresponds to phase codes where there are almost no data bits that are 1 (e.g., 0-5%) extracted from the phase code sweep. In other words, almost all (e.g., 95-100%) of the data bits extracted by the clock signal are sampled with a delay. In contrast, the upper region of the graph corresponds to phase codes where almost all (e.g., 95-100%) of the data bits extracted from the phase code sweep are 1. The intermediate region of the graph corresponds to the phase code when approximately half of the extracted data bits are 1 and the other half are 0. Thus, this 50% threshold corresponds to the case where the edges of the serial clock signal align with the edges of the serial data signal. Therefore, by determining the phase code corresponding to the 50% threshold, the clock signal can be shifted far away from the 50% threshold point, and the clock signal can be adjusted so that the edges of the clock signal align with the center of the data eye.

[0045] According to one embodiment of the present invention, as shown in Figure 4, the phase codes corresponding to points 1 and 2 are stored and averaged to determine the average phase code, which is then applied to the clock signal to align the edges of the clock signal with the center of the data eye of the data signal. In other words, when sweeping the phase code, multiple (e.g., 64, 128, 256, etc.) different phase-adjusted clock signals are generated by the interpolator 116, and when the percentage of 1s increases from approximately 0 to approximately 50% (i.e., approximately 50% of the bits are leading and the remaining approximately 50% are not), the corresponding phase code can be stored as point 1. The phase code continues sweeping, and the percentage of 1s increases to almost 100% before starting to decrease again. When the percentage of 1s decreases again to approximately 50%, the corresponding phase code can be stored as point 2. However, this method of setting the phase code is very slow and prone to errors. For example, if the edges of the clock signal and the edges of the data are aligned, jitter occurs in the data sample, which can result in incorrect detection of the phase code, as shown in the graph in Figure 5. Figure 5 does not reflect the phase code corresponding to 1, where the average of point 1 and point 2 is 50%.

[0046] Similar to Figure 4, Figure 6 is a graph showing the percentage of 1 during the phase code sweep. However, unlike Figure 4, Figure 6 shows a 4-point detection method for determining the correct phase code. This method stores different points in the phase code sweep graph to eliminate or reduce errors due to jitter. This allows for a more accurate determination of the phase code.

[0047] According to one embodiment of the present invention, a percentage of 1s is determined by sweeping a plurality of phase codes. For example, the phase code may consist of any number of bits, but for example, if it consists of 8 bits, 256 different phase bits are applied to the phase interpolator 116 to generate 256 different phase adjustment clock signals, which are used to sample the data signal, and the percentage of 1s is determined from the sampled bits. In order to determine whether the phase code produces about 50% 1s and 50% 0s, two phase codes corresponding to cases where there are virtually no 1s (e.g., in addition to cases where there are no 1s, a predetermined threshold, e.g., 1s are within a range of about 0-5%) are stored, and two phase codes corresponding to cases where there are virtually all 1s (e.g., in addition to cases where there are all 1s, a predetermined threshold, e.g., 1s are within a range of 95-100%) are stored.

[0048] In particular, when performing a phase code sweep, as shown in Figure 6, when the percentage of 1 increases from 0% to approximately 0% (e.g., about 5%), the corresponding phase code is stored as point 1. If the phase code sweep continues, the percentage of 1 increases toward 100%. The phase code corresponding to approximately 100% (e.g., about 95%) to 100% is stored as point 2, as shown in Figure 6. According to one embodiment of the present invention, if the phase code sweep continues, eventually the percentage of 1 will begin to decrease again. Here, when the percentage of 1 begins to decrease from 100% to approximately 100% (e.g., about 95%), the corresponding phase code is stored as point 3, as shown in Figure 6. Finally, the phase code sweep is continued to decrease, and the phase code corresponding to approximately 0% (e.g., about 5%) to 0% is stored as point 4.

[0049] According to one embodiment of the present invention, the average of these four phase codes, namely points 1, 2, 3, and 4, is calculated to determine the final phase code corresponding to approximately 50% of 1s. For example, if there are 256 phase codes and the phase codes corresponding to points 1, 2, 3, and 4 are 40, 60, 200, and 215 respectively, the average phase code would be (40 + 50 + 200 + 215) / 4 = 126.25. According to one embodiment of the present invention, after calculating the phase code corresponding to 50% of 1s using the average of the four stored points, the final average phase code is applied to the phase interpolator 116 to adjust the clock phase so that the edges of the clock signal align with the center of the data eye of the data signal. Also, the phase code is circular and therefore "wraps around". For example, for phase codes from 0 to 255, the phase codes corresponding to points 1, 2, 3, and 4 are 190, 192, 64, and 66, respectively. Therefore, the "circular" average is (190 + 192 + (64 + 256) + (66 + 256) / 4 = 256 = 0.

[0050] Another embodiment of the present invention, a fast calibration technique, is described below. The fast calibration technique begins after the initial execution of the 4-point detection technique, but can be used to perform phase calibration on the system during system use or during downtime between operations. Figure 7 is a graph of the phase code sweep versus 1 percentage using the fast calibration technique. Unlike the 4-point detection technique shown in Figure 6, the fast calibration technique performs the phase code sweep over a smaller range, but the time required to sweep the phase code is reduced by, for example, performing a first window of the phase code sweep on one small range of the phase code and a second window of the phase code sweep on another small range of the phase code.

[0051] According to one embodiment of the present invention, the first window of the phase code sweep may begin N phase codes before point 1 and end N phase codes after point 2, where N is a predetermined or programmable constant. In other words, similar to Figure 6, in Figure 7, point 1 may be a phase code corresponding to the case where 1 is substantially 0 (e.g., about 5%), and point 2 may be a phase code corresponding to the case where 1 is almost entirely (e.g., about 95%) 1 or all 1, and the phase code sweep begins N phase codes before point 1 (i.e., point 1-N) and ends N phase codes after point 2 (i.e., point 2+N). Thus, the first window of the phase code sweep is substantially smaller than the full phase code sweep described with reference to Figure 6.

[0052] According to one embodiment of the present invention, N can be selected as a value of 4 (out of 256 phase codes). Thus, the first window of the phase code sweep should start 4 phase codes before point 1 and end 4 phase codes after point 2. This allows the programmable N value to vary the trade-off between adjustment speed and phase-drift tolerance for the end user. That is, a larger N value means that sweeping takes longer and adjustment is slower, but it should be able to withstand larger phase code shifts from the last adjustment to N codes. Conversely, a smaller N value means that sweeping takes less time and adjustment is faster, but the phase code shift that can be withstood is smaller.

[0053] According to one embodiment of the present invention, the second window of the phase code sweep may begin N phase codes before point 3 and end N phase codes after point 4. In other words, similar to Figure 6, in Figure 7, point 3 may be a phase code corresponding to the case where almost all (e.g., about 95%) are 1 or all are 1, and point 4 may be a phase code corresponding to the case where 1 is substantially 0 from 0 (e.g., about 5%), and the phase code sweep may begin N phase codes before point 3 (i.e., point 3-N) and end N phase codes after point 4 (i.e., point 4+N). Thus, the second window of the phase code sweep is substantially smaller than the full phase code sweep described with reference to Figure 6. In other words, the first window and the second window of the phase code sweep are swept, but the phase codes between point 2+N and point 3-N are not swept. Also, the phase codes before point 1-N and the phase codes after point 4+N are not swept. Therefore, the time required to sweep the phase code is reduced, and points 1, 2, 3, and 4 can be determined quickly.

[0054] Next, the average phase code for points 1, 2, 3, and 4 can be calculated to determine the final phase code corresponding to approximately 50% of 1s. According to one embodiment of the present invention, after calculating the phase code corresponding to 50% of 1s using the average of the four stored points, the final average phase code is applied to the phase interpolator 116 to adjust the clock phase so that the edges of the clock signal align with the center of the data eye of the data signal. Thus, this method allows for faster acquisition of results similar to those described with reference to Figure 6 by utilizing the previously obtained phase code information. That is, for example, points 1-N can be determined using the phase code corresponding to point 1 from the previous adjustment cycle, and the region prior to points 1-N can be omitted, allowing the phase code sweep to begin from point 1-N. Similarly, the region between points 2+N and points 3-N can be omitted, and since the phase code corresponding to point 3 is already known from the previous adjustment cycle, the second window of the phase code sweep can begin from point 3-N.

[0055] Figure 8 is a flowchart of the four-point detection method and the rapid adjustment method. According to one embodiment of the present invention, the phase adjuster 114 receives a phase adjustment request and adjusts the series clock signal to the series data signal. During initial adjustment, an initial adjustment method 804 using the four-point detection method can be performed. Alternatively, during periodic adjustment, a periodic adjustment method 816 using rapid mode adjustment may be performed. According to one embodiment of the present invention, the initial adjustment method 804 can also be performed when periodic adjustment is desired, but the initial adjustment method 804 takes longer to execute than the periodic adjustment method 816.

[0056] First, by selecting the initial adjustment method 804, the phase code sweeping process can be started. As previously described, the phase code sweep includes phase codes, and the number of phase codes can be any number, for example, 256. Each phase code corresponds to a clock signal that has transitioned by a small amount (e.g., 1 / 256 of the clock period). According to one embodiment of the present invention, first, the phase code is set to 0 (806), which corresponds to the first phase code (e.g., the first phase code among the multiple phase codes used in the phase code sweep). According to one embodiment of the present invention, the phase code may be a 6-bit phase code containing 64 phase codes for the phase code sweep. According to another embodiment of the present invention, the phase code may be a 7-bit phase code containing 128 phase codes for the phase code sweep. In this specification, only the case where the phase code is 8 bits is assumed and described, but this is only an example.

[0057] Next, the phase codes are swept by applying multiple phase codes to the phase interpolator (808). Performing the phase code sweep adjusts the phase of the clock and determines the percentage of 1s from the sampled and deserialized data, ranging from none to all 1s. As illustrated with reference to Figure 6, if 0% to approximately 0% (e.g., about 5%) of the bits are 1, the corresponding phase code is stored as point 1 (810). According to one embodiment of the present invention, the phase code sweep is performed between three unit intervals (UIs) (e.g., between one bit of serial clock) to obtain points 1, 2, 3, and 4, as illustrated with reference to Figure 6. For example, point 2 is stored when the percentage of 1s is approximately 100% (e.g., about 95%) to 100%, point 3 is stored when the percentage of 1s is approximately 100% (e.g., about 95%) to 100%, and point 4 is stored when the percentage of 1s is approximately 0% (e.g., about 5%) to 0%. After storing the four points (812), the final phase code is calculated by averaging the phase codes corresponding to points 1 to 4 (838), and the calculated phase code is applied to the phase interpolator 116 (840). If the phase code sweep has not been performed for three UIs (812), the phase code is advanced to the next phase code, for example, by incrementing from phase code 1 to phase code 2. Steps 808-812 are repeated until three UIs have been performed.

[0058] According to one embodiment of the present invention, a periodic adjustment method using a rapid adjustment method is performed (816). First, the phase code is set to points 1-N (818), where N is a predetermined or programmable constant. The phase code for point 1 is determined in a previous phase code sweep, e.g., in an initial adjustment mode. Next, a first window of phase codes is swept by applying multiple phase codes to the phase interpolator (820). When the first window of the phase code sweep is performed, the phase of the clock is adjusted and the percentage of 1s is determined from the sampled and deserialized data, ranging from none to all 1s. If 0% to approximately 0% (e.g., about 5%) of the bits are 1, the phase code is stored as point 1, as described with reference to Figure 7 (822). When the first window of the phase code sweep is continued and the phase code becomes the same as that of point 2+N, the first window of the phase code sweep has been performed for the first two points (824). If the phase code is not the same as point 2+N, the phase code is incremented, and steps 820-824 are repeated until both point 1 and point 2 are stored (826). Once point 1 and point 2 are stored, the phase code is set to point 3-N (828), the second window of the phase code sweep is executed, and it is applied to the phase interpolator (830). If the percentage of 1 is determined to be approximately 100% (e.g., about 95%) to 100%, the phase code is stored as point 3 (832), as explained with reference to Figure 7, and it is checked whether the phase code is the same as point 4+N, which means that the phase code sweep has been completed for the third and fourth points (834). If the phase code is not the same as point 4+N, the phase code is incremented (836), and steps 830-834 are repeated until both point 3 and point 4 are stored (836). Once two points, namely points 3 and 4, are stored, the final phase code is calculated by averaging the phase codes corresponding to points 1, 2, 3, and 4 (838), and the calculated phase code is applied to the phase interpolator (840). Once the adjustment cycle is complete, the phase adjuster enters an idle state and waits until it receives another adjustment request (842).

[0059] According to one embodiment of the present invention, when the phase interpolator 116 is updated with the calculated final phase code, the phase interpolator 116 adjusts the clock signal and provides this adjusted clock signal to the slicer 118, which uses this adjusted clock signal to sample the input serial data. As a result, the edges of the adjusted clock signal are aligned with the center of the data eye of the input serial data signal.

[0060] In the method described above, we referred to the percentage of 1 (e.g., early bit), but according to other embodiments of the present invention, the bit may be 0 (e.g., late bit) instead of 1. Therefore, the four-point detection method or rapid adjustment method can be applied similarly using the percentage of 0 instead of the percentage of 1.

[0061] According to one embodiment of the present invention, the adjustment results can be improved by using multiple adjustment methods together. For example, the four-point detection method described with reference to Figure 6 can be applied together with the two-edge sampling method (sampling data on both the rising and falling edges of the clock signal) described with reference to Figures 3A and 3B. Furthermore, according to another embodiment of the present invention, the rapid adjustment method described earlier with reference to Figure 7 may be used together with the two-edge sampling method described with reference to Figures 3A and 3B.

[0062] Terms such as "first," "second," and "third" are used for various elements, components, regions, layers, and parts, but these are not limited by such modifiers. Such terms are used to distinguish one element, component, region, layer, or part from other elements, components, regions, layers, and parts. Therefore, the first element, component, region, layer, or part can also be the second element, component, region, layer, or part without departing from the spirit and scope of the present invention.

[0063] For the sake of clarity, spatial relation terms such as “below,” “downward,” “below,” “directly below,” “above,” and “above” may be used to indicate the relationship between one part or feature and another part or feature shown in the drawing. Such spatial relation terms are intended to indicate the different positions and / or orientations of the device being used or operating as shown in the drawing. For example, a part shown in the drawing as “below” or “below” a part will be “above” the device if it is turned upside down. Therefore, for example, “below” and “below” can refer to both up and down. The device may be rotated, for example, by 90 degrees or oriented in another direction, in which case the spatial relation terms must be interpreted accordingly.

[0064] When describing an ingredient or layer as being "on top of" or "connected to" another ingredient or layer, this includes not only cases where it is "directly" on top of or "directly connected," but also cases where other ingredients or layers are sandwiched in between. However, describing it as being "directly on top of" or "directly connected" means that there are no other parts in between. Also, when describing an ingredient or layer as being "between" two other ingredients or layers, the two ingredients or layers may consist only of that ingredient or layer, but may also have one or more other ingredients or layers in between.

[0065] The terms used herein are for the purpose of describing specific embodiments and are not intended to limit the invention. Unless otherwise specified, numbers here include both singular and plural cases. The expression "includes" a certain feature, integer, stage, operation, part, component, etc., means that it may also include other features, integers, stages, operations, parts, components, etc., in addition to the part in question. The expression "and / or" includes all combinations of one or more of the listed items. Expressions such as "at least one" preceding a list modify the entire list, not each individual item within it.

[0066] Here, "substantially," "about," "approximately," and similar expressions are merely approximations and do not indicate "degree," but are used to indicate the inherent error of measured or calculated values ​​that are well known to those skilled in the art. Furthermore, the expression "may be" used when describing embodiments of the present invention means that it is applicable to "one or more embodiments of the present invention." The term "exemplary" refers to examples or drawings. "Use," "utilize," etc., are used with similar meanings along with other similar expressions.

[0067] The electronic devices, electrical devices, and / or other related devices or their components described in the embodiments of the present invention can be realized using appropriate hardware, firmware [e.g., application-specific integrated circuit (ASIC), field-programmable gate array (FPGA)], software, or a combination thereof. For example, the diverse components of these devices may be formed on a single integrated circuit chip, or they may be realized on different integrated circuit chips. Furthermore, the diverse components of these devices can be realized on flexible printed circuit film, tape carrier packages (TCP), printed circuit boards, etc., or formed on a single substrate. Moreover, the diverse components of these devices may be processes or threads executable by one or more processors within one or more computer devices that execute computer program instructions and interact with other system elements to perform the diverse functions described herein. Computer program instructions can be stored in memory implemented in a computer device using standard memory devices such as RAM (random access memory). In addition, those skilled in the art can combine or integrate the functions of diverse computer devices into a single computer device, or distribute the functions of a particular computer device across one or more other computer devices, without departing from the concepts and scope of the embodiments of the present invention.

[0068] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as those generally known to those skilled in the art in the field to which this invention pertains. Terms such as those defined in commonly used dictionaries should be construed to have the meaning consistent with their meaning in the relevant art and / or herein, and should not be construed in an ideal or overly strict sense unless expressly stated herein.

[0069] The embodiments described above are merely examples. Those skilled in the art will be able to learn of a variety of alternative embodiments from those described herein. Such alternative embodiments are within the scope of the present invention. Thus, the embodiments are limited only by the following claims and their equivalents. [Explanation of Symbols]

[0070] 100: Phase adjustment circuit 102: Transmitter 104: Clock Transmitter 106: Data Transmitter 108: Receiver 110: Clock receiver 112: Data receiver 114: Phase adjuster 116: Phase Interpolator 118: Slicer 120: Inverse series converter

Claims

1. The stage of receiving a serial clock signal, The stage of receiving serial data signals, A step of sweeping a plurality of phase codes that can be applied to the series clock signal to shift the phase of the series clock signal, A step of identifying a first phase code among the plurality of phase codes, A step of identifying the second phase code among the plurality of phase codes, A step of identifying a third phase code among the plurality of phase codes, A step of identifying the fourth phase code among the aforementioned plurality of phase codes, A step of determining the average phase code based on the first phase code, the second phase code, the third phase code, and the fourth phase code, The steps include applying the average phase code to a phase interpolator to transition the phase of the series clock signal. Includes, The first phase code is set such that, with respect to the total number of bits, which is the total number of bit values ​​extracted when the serial data signal is sampled based on the edge of the serial clock signal to which the first phase code is applied, the percentage of the number of bits that are specific values ​​among those bit values ​​falls within the range of a first threshold. The second phase code is set such that, with respect to the total number of bits, which is the total number of bit values ​​extracted when the serial data signal is sampled based on the edge of the serial clock signal to which the second phase code is applied, the percentage of the number of bits that are specific values ​​among those bit values ​​falls within the range of a second threshold. The third phase code is set such that, with respect to the total number of bits, which is the total number of bit values ​​extracted when the serial data signal is sampled based on the edge of the serial clock signal to which the third phase code is applied, the percentage of the number of bits that are specific values ​​among those bit values ​​falls within the range of a third threshold. The fourth phase code is set such that, with respect to the total number of bits, which is the total number of bit values ​​extracted when the serial data signal is sampled based on the edge of the serial clock signal to which the fourth phase code is applied, the percentage of the number of bits that are specific values ​​among those bit values ​​falls within the range of the fourth threshold. Phase adjustment method.

2. The serial data signal includes the same training pattern as the serial clock signal. The first, second, third, and fourth phase codes are set such that the percentages indicated by the first, second, third, and fourth thresholds are between 0% and 5%. The phase adjustment method according to claim 1.

3. The first phase code is set in response to the case where the percentage indicated by the first threshold increases from 0% to 5%, The second phase code is set in response to the case where the percentage indicated by the second threshold increases from 95% to 100%. The third phase code is set in response to the case where the percentage indicated by the third threshold decreases from 100% to 95%. The fourth phase code is set in accordance with the case where the percentage indicated by the fourth threshold decreases from 5% to 0%. The phase adjustment method according to claim 2.

4. The phase adjustment method according to claim 1, wherein the step of sweeping the plurality of phase codes includes the step of sweeping three unit intervals of the serial data signal.

5. The phase adjustment method according to claim 1, wherein the step of applying the average phase code to the phase interpolator to transition the phase of the series clock signal includes the step of transitioning the series clock signal so that the edge of the series clock signal aligns with the center of the data eye of the series data signal.

6. The phase adjustment method according to claim 1, wherein the bit value extracted from the serial data signal includes a first bit value corresponding to the rising edge of the serial clock signal and a second bit value corresponding to the falling edge of the serial clock signal.

7. A step of sweeping the first window of phase codes to identify the updated first phase code and the updated second phase code, A step of sweeping the second window of phase codes to identify the updated third phase code and the updated fourth phase code, A step of determining an updated average phase code based on the updated first phase code, the updated second phase code, the updated third phase code, and the updated fourth phase code, The steps include applying the updated average phase code to the phase interpolator to further transition the phase of the serial clock signal. It further includes, The first window begins at the point obtained by subtracting a constant from the first phase code and ends at the point obtained by adding the constant to the second phase code. The second window begins at the point obtained by subtracting the constant from the third phase code and ends at the point obtained by adding the constant to the fourth phase code. The phase adjustment method according to claim 1.

8. The phase adjustment method according to claim 7, wherein the constant is a programmable predetermined value.

9. The phase adjustment method according to claim 8, wherein the updated first phase code is different from the updated second phase code, and the updated third phase code is different from the updated fourth phase code.

10. Memory for storing computer-executable instructions, A processor that executes the aforementioned instructions A system including, When the processor executes the instruction, the system Receive a serial clock signal, Receives serial data signals, Multiple phase codes that can be applied to the series clock signal to shift the phase of the series clock signal are swept, Identify the first phase code among the plurality of phase codes, Identify the second phase code among the aforementioned plurality of phase codes, Identify the third phase code among the aforementioned multiple phase codes, Identify the fourth phase code among the aforementioned plurality of phase codes, The average phase code is determined based on the first phase code, the second phase code, the third phase code, and the fourth phase code. This includes applying the average phase code to a phase interpolator to transition the phase of the series clock signal, The first phase code is set such that, with respect to the total number of bits, which is the total number of bit values ​​extracted when the serial data signal is sampled based on the edge of the serial clock signal to which the first phase code is applied, the percentage of the number of bits that are specific values ​​among those bit values ​​falls within the range of a first threshold. The second phase code is set such that, with respect to the total number of bits, which is the total number of bit values ​​extracted when the serial data signal is sampled based on the edge of the serial clock signal to which the second phase code is applied, the percentage of the number of bits that are specific values ​​among those bit values ​​falls within the range of a second threshold. The third phase code is set such that, with respect to the total number of bits, which is the total number of bit values ​​extracted when the serial data signal is sampled based on the edge of the serial clock signal to which the third phase code is applied, the percentage of the number of bits that are specific values ​​among those bit values ​​falls within the range of a third threshold. The fourth phase code is set such that, with respect to the total number of bits, which is the total number of bit values ​​extracted when the serial data signal is sampled based on the edge of the serial clock signal to which the fourth phase code is applied, the percentage of the number of bits that are specific values ​​among those bit values ​​falls within the range of the fourth threshold. system.

11. The serial data signal includes the same training pattern as the serial clock signal. The first, second, third, and fourth phase codes are set such that the percentages indicated by the first, second, third, and fourth thresholds are between 0% and 5%. The system according to claim 10.

12. The first phase code is set in response to the case where the percentage indicated by the first threshold increases from 0% to 5%, The second phase code is set in response to the case where the percentage indicated by the second threshold increases from 95% to 100%. The third phase code is set in response to the case where the percentage indicated by the third threshold decreases from 100% to 95%. The fourth phase code is set in accordance with the case where the percentage indicated by the fourth threshold decreases from 5% to 0%. The system according to claim 11.

13. The system according to claim 10, wherein the sweeping of the plurality of phase codes sweeps three unit intervals of the serial data signal.

14. The system according to claim 10, wherein applying the average phase code to the phase interpolator to transition the phase of the serial clock signal includes transitioning the serial clock signal such that the edges of the serial clock signal align with the center of the data eye of the serial data signal.

15. The system according to claim 10, wherein the bit value extracted from the serial data signal includes a first bit value corresponding to the rising edge of the serial clock signal and a second bit value corresponding to the falling edge of the serial clock signal.

16. When the processor executes the instruction, the system further: Sweep the first window of phase codes to identify the updated first phase code and the updated second phase code. Sweep the second window of the phase code to identify the updated third phase code and the updated fourth phase code. Based on the updated first phase code, the updated second phase code, the updated third phase code, and the updated fourth phase code, the updated average phase code is determined. This includes applying the updated average phase code to the phase interpolator to further transition the phase of the series clock signal, The first window begins at the point obtained by subtracting a constant from the first phase code and ends at the point obtained by adding the constant to the second phase code. The second window begins at the point obtained by subtracting the constant from the third phase code and ends at the point obtained by adding the constant to the fourth phase code. The system according to claim 10.

17. The system according to claim 16, wherein the constant is a programmable predetermined value.

18. The system according to claim 17, wherein the updated first phase code is different from the updated second phase code, and the updated third phase code is different from the updated fourth phase code.

19. The stage of receiving a serial clock signal, The stage of receiving serial data signals, A step of sweeping a phase code within a first window that can be applied to the series clock signal to shift the phase of the series clock signal, A step of identifying the updated first phase code from the first window of the phase code, A step of identifying the updated second phase code from the first window of the phase code, A step of sweeping a phase code that can be applied to the series clock signal to shift the phase of the series clock signal within a second window, A step of identifying the updated third phase code from the second window of the phase code, A step of identifying the updated fourth phase code from the second window of the phase code, The updated first phase code, the updated second phase code, the updated third A step of determining the average phase code based on the phase code and the updated fourth phase code, The steps include applying the average phase code to a phase interpolator to transition the phase of the series clock signal. Includes, The first window begins at a point obtained by subtracting a constant from a predetermined first phase code and ends at a point obtained by adding the constant to a predetermined second phase code. The updated first phase code is set such that, with respect to the total number of bits, which is the total number of bit values ​​extracted when the serial data signal is sampled based on the edge of the serial clock signal to which the updated first phase code is applied, the percentage of the number of bits that are specific values ​​among those bit values ​​falls within the range of a first threshold. The updated second phase code is set such that, with respect to the total number of bits, which is the total number of bit values ​​extracted when the serial data signal is sampled based on the edge of the serial clock signal to which the updated second phase code is applied, the percentage of the number of bits that are specific values ​​among those bit values ​​falls within the range of a second threshold. The second window begins at a point obtained by subtracting the constant from a predetermined third phase code and ends at a point obtained by adding the constant to a predetermined fourth phase code. The updated third phase code is set such that, with respect to the total number of bits, which is the total number of bit values ​​extracted when the serial data signal is sampled based on the edge of the serial clock signal to which the updated third phase code is applied, the percentage of the number of bits that are specific values ​​among those bit values ​​falls within the range of the third threshold. The updated fourth phase code is set such that, with respect to the total number of bits, which is the total number of bit values ​​extracted when the serial data signal is sampled based on the edge of the serial clock signal to which the updated fourth phase code is applied, the percentage of the number of bits that are specific values ​​among those bit values ​​falls within the range of the fourth threshold. Phase adjustment method.

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